1module AND2(A, B, O); 2 input A; 3 input B; 4 output O; 5endmodule 6 7module CEMux(I, O); 8 input I; 9 output O; 10endmodule 11 12module CascadeBuf(I, O); 13 input I; 14 output O; 15endmodule 16 17module CascadeMux(I, O); 18 input I; 19 output O; 20endmodule 21 22module ClkMux(I, O); 23 input I; 24 output O; 25endmodule 26 27module ColCtrlBuf(I, O); 28 input I; 29 output O; 30endmodule 31 32module DummyBuf(I, O); 33 input I; 34 output O; 35endmodule 36 37module Glb2LocalMux(I, O); 38 input I; 39 output O; 40endmodule 41 42module GlobalMux(I, O); 43 input I; 44 output O; 45endmodule 46 47module ICE_CARRY_IN_MUX(carryinitout, carryinitin); 48 input carryinitin; 49 output carryinitout; 50endmodule 51 52module ICE_GB(GLOBALBUFFEROUTPUT, USERSIGNALTOGLOBALBUFFER); 53 output GLOBALBUFFEROUTPUT; 54 input USERSIGNALTOGLOBALBUFFER; 55endmodule 56 57module ICE_GB_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, GLOBALBUFFEROUTPUT); 58 input CLOCKENABLE; 59 output DIN0; 60 output DIN1; 61 input DOUT0; 62 input DOUT1; 63 output GLOBALBUFFEROUTPUT; 64 input INPUTCLK; 65 input LATCHINPUTVALUE; 66 input OUTPUTCLK; 67 input OUTPUTENABLE; 68 inout PACKAGEPIN; 69endmodule 70 71module ICE_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); 72 input CLOCKENABLE; 73 output DIN0; 74 output DIN1; 75 input DOUT0; 76 input DOUT1; 77 input INPUTCLK; 78 input LATCHINPUTVALUE; 79 input OUTPUTCLK; 80 input OUTPUTENABLE; 81 inout PACKAGEPIN; 82endmodule 83 84module ICE_IO_DLY(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, SCLK, SDI, CRSEL, SDO); 85 input CLOCKENABLE; 86 input CRSEL; 87 output DIN0; 88 output DIN1; 89 input DOUT0; 90 input DOUT1; 91 input INPUTCLK; 92 input LATCHINPUTVALUE; 93 input OUTPUTCLK; 94 input OUTPUTENABLE; 95 inout PACKAGEPIN; 96 input SCLK; 97 input SDI; 98 output SDO; 99endmodule 100 101module ICE_IO_DS(PACKAGEPIN, PACKAGEPINB, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); 102 input CLOCKENABLE; 103 output DIN0; 104 output DIN1; 105 input DOUT0; 106 input DOUT1; 107 input INPUTCLK; 108 input LATCHINPUTVALUE; 109 input OUTPUTCLK; 110 input OUTPUTENABLE; 111 inout PACKAGEPIN; 112 inout PACKAGEPINB; 113endmodule 114 115module ICE_IO_OD(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); 116 input CLOCKENABLE; 117 output DIN0; 118 output DIN1; 119 input DOUT0; 120 input DOUT1; 121 input INPUTCLK; 122 input LATCHINPUTVALUE; 123 input OUTPUTCLK; 124 input OUTPUTENABLE; 125 inout PACKAGEPIN; 126endmodule 127 128module ICE_IR500_DRV(IRLEDEN, IRPWM, CURREN, IRLEDEN2, IRPWM2, IRLED1, IRLED2); 129 input CURREN; 130 output IRLED1; 131 output IRLED2; 132 input IRLEDEN; 133 input IRLEDEN2; 134 input IRPWM; 135 input IRPWM2; 136endmodule 137 138module INV(I, O); 139 input I; 140 output O; 141endmodule 142 143module IO_PAD(PACKAGEPIN, DOUT, DIN, OE); 144 input DIN; 145 output DOUT; 146 input OE; 147 inout PACKAGEPIN; 148endmodule 149 150module InMux(I, O); 151 input I; 152 output O; 153endmodule 154 155module IoInMux(I, O); 156 input I; 157 output O; 158endmodule 159 160module IoSpan4Mux(I, O); 161 input I; 162 output O; 163endmodule 164 165module IpInMux(I, O); 166 input I; 167 output O; 168endmodule 169 170module IpOutMux(I, O); 171 input I; 172 output O; 173endmodule 174 175module LocalMux(I, O); 176 input I; 177 output O; 178endmodule 179 180module LogicCell(carryout, lcout, carryin, clk, clkb, in0, in1, in2, in3, sr); 181 input carryin; 182 output carryout; 183 input clk; 184 input clkb; 185 input in0; 186 input in1; 187 input in2; 188 input in3; 189 output lcout; 190 input sr; 191endmodule 192 193module LogicCell2(carryout, lcout, carryin, clk, in0, in1, in2, in3, sr, ce); 194 input carryin; 195 output carryout; 196 input ce; 197 input clk; 198 input in0; 199 input in1; 200 input in2; 201 input in3; 202 output lcout; 203 input sr; 204endmodule 205 206module LogicCell40(carryout, lcout, ltout, carryin, clk, in0, in1, in2, in3, sr, ce); 207 input carryin; 208 output carryout; 209 input ce; 210 input clk; 211 input in0; 212 input in1; 213 input in2; 214 input in3; 215 output lcout; 216 output ltout; 217 input sr; 218endmodule 219 220module Odrv12(I, O); 221 input I; 222 output O; 223endmodule 224 225module Odrv4(I, O); 226 input I; 227 output O; 228endmodule 229 230module PAD_BANK0(PAD, PADIN, PADOUT, PADOEN); 231 inout PAD; 232 output PADIN; 233 input PADOEN; 234 input PADOUT; 235endmodule 236 237module PAD_BANK1(PAD, PADIN, PADOUT, PADOEN); 238 inout PAD; 239 output PADIN; 240 input PADOEN; 241 input PADOUT; 242endmodule 243 244module PAD_BANK2(PAD, PADIN, PADOUT, PADOEN); 245 inout PAD; 246 output PADIN; 247 input PADOEN; 248 input PADOUT; 249endmodule 250 251module PAD_BANK3(PAD, PADIN, PADOUT, PADOEN); 252 inout PAD; 253 output PADIN; 254 input PADOEN; 255 input PADOUT; 256endmodule 257 258module PLL40(PLLIN, PLLOUTCORE, PLLOUTGLOBAL, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); 259 input BYPASS; 260 input [7:0] DYNAMICDELAY; 261 input EXTFEEDBACK; 262 input LATCHINPUTVALUE; 263 output LOCK; 264 input PLLIN; 265 output PLLOUTCORE; 266 output PLLOUTGLOBAL; 267 input RESETB; 268 input SCLK; 269 input SDI; 270 output SDO; 271endmodule 272 273module PLL40_2(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); 274 input BYPASS; 275 input [7:0] DYNAMICDELAY; 276 input EXTFEEDBACK; 277 input LATCHINPUTVALUE; 278 output LOCK; 279 input PLLIN; 280 output PLLOUTCOREA; 281 output PLLOUTCOREB; 282 output PLLOUTGLOBALA; 283 output PLLOUTGLOBALB; 284 input RESETB; 285 input SCLK; 286 input SDI; 287 output SDO; 288endmodule 289 290module PLL40_2F(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); 291 input BYPASS; 292 input [7:0] DYNAMICDELAY; 293 input EXTFEEDBACK; 294 input LATCHINPUTVALUE; 295 output LOCK; 296 input PLLIN; 297 output PLLOUTCOREA; 298 output PLLOUTCOREB; 299 output PLLOUTGLOBALA; 300 output PLLOUTGLOBALB; 301 input RESETB; 302 input SCLK; 303 input SDI; 304 output SDO; 305endmodule 306 307module PREIO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); 308 input CLOCKENABLE; 309 output DIN0; 310 output DIN1; 311 input DOUT0; 312 input DOUT1; 313 input INPUTCLK; 314 input LATCHINPUTVALUE; 315 input OUTPUTCLK; 316 input OUTPUTENABLE; 317 input PADIN; 318 output PADOEN; 319 output PADOUT; 320endmodule 321 322module PRE_IO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); 323 input CLOCKENABLE; 324 output DIN0; 325 output DIN1; 326 input DOUT0; 327 input DOUT1; 328 input INPUTCLK; 329 input LATCHINPUTVALUE; 330 input OUTPUTCLK; 331 input OUTPUTENABLE; 332 input PADIN; 333 output PADOEN; 334 output PADOUT; 335endmodule 336 337module PRE_IO_GBUF(GLOBALBUFFEROUTPUT, PADSIGNALTOGLOBALBUFFER); 338 output GLOBALBUFFEROUTPUT; 339 input PADSIGNALTOGLOBALBUFFER; 340endmodule 341 342module QuadClkMux(I, O); 343 input I; 344 output O; 345endmodule 346 347module SB_G2TBuf(I, O); 348 input I; 349 output O; 350endmodule 351 352module SMCCLK(CLK); 353 output CLK; 354endmodule 355 356module SRMux(I, O); 357 input I; 358 output O; 359endmodule 360 361module Sp12to4(I, O); 362 input I; 363 output O; 364endmodule 365 366module Span12Mux(I, O); 367 input I; 368 output O; 369endmodule 370 371module Span12Mux_h(I, O); 372 input I; 373 output O; 374endmodule 375 376module Span12Mux_s0_h(I, O); 377 input I; 378 output O; 379endmodule 380 381module Span12Mux_s0_v(I, O); 382 input I; 383 output O; 384endmodule 385 386module Span12Mux_s10_h(I, O); 387 input I; 388 output O; 389endmodule 390 391module Span12Mux_s10_v(I, O); 392 input I; 393 output O; 394endmodule 395 396module Span12Mux_s11_h(I, O); 397 input I; 398 output O; 399endmodule 400 401module Span12Mux_s11_v(I, O); 402 input I; 403 output O; 404endmodule 405 406module Span12Mux_s1_h(I, O); 407 input I; 408 output O; 409endmodule 410 411module Span12Mux_s1_v(I, O); 412 input I; 413 output O; 414endmodule 415 416module Span12Mux_s2_h(I, O); 417 input I; 418 output O; 419endmodule 420 421module Span12Mux_s2_v(I, O); 422 input I; 423 output O; 424endmodule 425 426module Span12Mux_s3_h(I, O); 427 input I; 428 output O; 429endmodule 430 431module Span12Mux_s3_v(I, O); 432 input I; 433 output O; 434endmodule 435 436module Span12Mux_s4_h(I, O); 437 input I; 438 output O; 439endmodule 440 441module Span12Mux_s4_v(I, O); 442 input I; 443 output O; 444endmodule 445 446module Span12Mux_s5_h(I, O); 447 input I; 448 output O; 449endmodule 450 451module Span12Mux_s5_v(I, O); 452 input I; 453 output O; 454endmodule 455 456module Span12Mux_s6_h(I, O); 457 input I; 458 output O; 459endmodule 460 461module Span12Mux_s6_v(I, O); 462 input I; 463 output O; 464endmodule 465 466module Span12Mux_s7_h(I, O); 467 input I; 468 output O; 469endmodule 470 471module Span12Mux_s7_v(I, O); 472 input I; 473 output O; 474endmodule 475 476module Span12Mux_s8_h(I, O); 477 input I; 478 output O; 479endmodule 480 481module Span12Mux_s8_v(I, O); 482 input I; 483 output O; 484endmodule 485 486module Span12Mux_s9_h(I, O); 487 input I; 488 output O; 489endmodule 490 491module Span12Mux_s9_v(I, O); 492 input I; 493 output O; 494endmodule 495 496module Span12Mux_v(I, O); 497 input I; 498 output O; 499endmodule 500 501module Span4Mux(I, O); 502 input I; 503 output O; 504endmodule 505 506module Span4Mux_h(I, O); 507 input I; 508 output O; 509endmodule 510 511module Span4Mux_s0_h(I, O); 512 input I; 513 output O; 514endmodule 515 516module Span4Mux_s0_v(I, O); 517 input I; 518 output O; 519endmodule 520 521module Span4Mux_s1_h(I, O); 522 input I; 523 output O; 524endmodule 525 526module Span4Mux_s1_v(I, O); 527 input I; 528 output O; 529endmodule 530 531module Span4Mux_s2_h(I, O); 532 input I; 533 output O; 534endmodule 535 536module Span4Mux_s2_v(I, O); 537 input I; 538 output O; 539endmodule 540 541module Span4Mux_s3_h(I, O); 542 input I; 543 output O; 544endmodule 545 546module Span4Mux_s3_v(I, O); 547 input I; 548 output O; 549endmodule 550 551module Span4Mux_v(I, O); 552 input I; 553 output O; 554endmodule 555 556module carry_logic(cout, carry_in, a, a_bar, b, b_bar, vg_en); 557 input a; 558 input a_bar; 559 input b; 560 input b_bar; 561 input carry_in; 562 output cout; 563 input vg_en; 564endmodule 565 566module clut4(lut4, in0, in1, in2, in3, in0b, in1b, in2b, in3b, cbit); 567 input [15:0] cbit; 568 input in0; 569 input in0b; 570 input in1; 571 input in1b; 572 input in2; 573 input in2b; 574 input in3; 575 input in3b; 576 output lut4; 577endmodule 578 579module coredffr(q, d, purst, S_R, cbit, clk, clkb); 580 input S_R; 581 input [1:0] cbit; 582 input clk; 583 input clkb; 584 input d; 585 input purst; 586 output q; 587endmodule 588 589module coredffr2(q, d, purst, S_R, cbit, clk, clkb, ce); 590 input S_R; 591 input [1:0] cbit; 592 input ce; 593 input clk; 594 input clkb; 595 input d; 596 input purst; 597 output q; 598endmodule 599 600module gio2CtrlBuf(I, O); 601 input I; 602 output O; 603endmodule 604 605module inv_hvt(Y, A); 606 input A; 607 output Y; 608endmodule 609 610module logic_cell(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r); 611 input carry_in; 612 output carry_out; 613 input [20:0] cbit; 614 input clk; 615 input clkb; 616 input in0; 617 input in1; 618 input in2; 619 input in3; 620 output lc_out; 621 input prog; 622 input purst; 623 input s_r; 624endmodule 625 626module logic_cell2(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce); 627 input carry_in; 628 output carry_out; 629 input [20:0] cbit; 630 input ce; 631 input clk; 632 input clkb; 633 input in0; 634 input in1; 635 input in2; 636 input in3; 637 output lc_out; 638 input prog; 639 input purst; 640 input s_r; 641endmodule 642 643module logic_cell40(carry_out, lc_out, lt_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce); 644 input carry_in; 645 output carry_out; 646 input [20:0] cbit; 647 input ce; 648 input clk; 649 input clkb; 650 input in0; 651 input in1; 652 input in2; 653 input in3; 654 output lc_out; 655 output lt_out; 656 input prog; 657 input purst; 658 input s_r; 659endmodule 660 661module o_mux(O, in0, in1, cbit, prog); 662 output O; 663 input cbit; 664 input in0; 665 input in1; 666 input prog; 667endmodule 668 669module sync_clk_enable(D, NC, Q); 670 input D; 671 input NC; 672 output Q; 673endmodule 674 675module Span4Mux_h0(I, O); 676 input I; 677 output O; 678endmodule 679 680module Span4Mux_h1(I, O); 681 input I; 682 output O; 683endmodule 684 685module Span4Mux_h2(I, O); 686 input I; 687 output O; 688endmodule 689 690module Span4Mux_h3(I, O); 691 input I; 692 output O; 693endmodule 694 695module Span4Mux_h4(I, O); 696 input I; 697 output O; 698endmodule 699 700module Span4Mux_v0(I, O); 701 input I; 702 output O; 703endmodule 704 705module Span4Mux_v1(I, O); 706 input I; 707 output O; 708endmodule 709 710module Span4Mux_v2(I, O); 711 input I; 712 output O; 713endmodule 714 715module Span4Mux_v3(I, O); 716 input I; 717 output O; 718endmodule 719 720module Span4Mux_v4(I, O); 721 input I; 722 output O; 723endmodule 724 725module Span12Mux_h0(I, O); 726 input I; 727 output O; 728endmodule 729 730module Span12Mux_h1(I, O); 731 input I; 732 output O; 733endmodule 734 735module Span12Mux_h2(I, O); 736 input I; 737 output O; 738endmodule 739 740module Span12Mux_h3(I, O); 741 input I; 742 output O; 743endmodule 744 745module Span12Mux_h4(I, O); 746 input I; 747 output O; 748endmodule 749 750module Span12Mux_h5(I, O); 751 input I; 752 output O; 753endmodule 754 755module Span12Mux_h6(I, O); 756 input I; 757 output O; 758endmodule 759 760module Span12Mux_h7(I, O); 761 input I; 762 output O; 763endmodule 764 765module Span12Mux_h8(I, O); 766 input I; 767 output O; 768endmodule 769 770module Span12Mux_h9(I, O); 771 input I; 772 output O; 773endmodule 774 775module Span12Mux_h10(I, O); 776 input I; 777 output O; 778endmodule 779 780module Span12Mux_h11(I, O); 781 input I; 782 output O; 783endmodule 784 785module Span12Mux_h12(I, O); 786 input I; 787 output O; 788endmodule 789 790module Span12Mux_v0(I, O); 791 input I; 792 output O; 793endmodule 794 795module Span12Mux_v1(I, O); 796 input I; 797 output O; 798endmodule 799 800module Span12Mux_v2(I, O); 801 input I; 802 output O; 803endmodule 804 805module Span12Mux_v3(I, O); 806 input I; 807 output O; 808endmodule 809 810module Span12Mux_v4(I, O); 811 input I; 812 output O; 813endmodule 814 815module Span12Mux_v5(I, O); 816 input I; 817 output O; 818endmodule 819 820module Span12Mux_v6(I, O); 821 input I; 822 output O; 823endmodule 824 825module Span12Mux_v7(I, O); 826 input I; 827 output O; 828endmodule 829 830module Span12Mux_v8(I, O); 831 input I; 832 output O; 833endmodule 834 835module Span12Mux_v9(I, O); 836 input I; 837 output O; 838endmodule 839 840module Span12Mux_v10(I, O); 841 input I; 842 output O; 843endmodule 844 845module Span12Mux_v11(I, O); 846 input I; 847 output O; 848endmodule 849 850module Span12Mux_v12(I, O); 851 input I; 852 output O; 853endmodule 854 855module GND(Y); 856 output Y; 857endmodule 858 859module VCC(Y); 860 output Y; 861endmodule 862 863module INTERCONN(I, O); 864 input I; 865 output O; 866endmodule 867 868module SB_RAM40_4K(RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); 869 output [15:0] RDATA; 870 input RCLK, RCLKE, RE; 871 input [10:0] RADDR; 872 input WCLK, WCLKE, WE; 873 input [10:0] WADDR; 874 input [15:0] MASK, WDATA; 875endmodule 876