1 /*------------------------------------------------------------------------- 2 mcs51reg.h - Register Declarations for the mcs51 compatible 3 microcontrollers 4 5 Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch 6 7 This library is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by the 9 Free Software Foundation; either version 2, or (at your option) any 10 later version. 11 12 This library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this library; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20 MA 02110-1301, USA. 21 22 As a special exception, if you link this library with other files, 23 some of which are compiled with SDCC, to produce an executable, 24 this library does not by itself cause the resulting executable to 25 be covered by the GNU General Public License. This exception does 26 not however invalidate any other reasons why the executable file 27 might be covered by the GNU General Public License. 28 -------------------------------------------------------------------------*/ 29 30 /*------------------------------------------------------------------------- 31 History: 32 -------- 33 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch 34 Initial release, supported microcontrollers: 35 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051, 36 Infineon / Siemens SAB80515, SAB80535, SAB80515A 37 38 Version 1.0.1 (Nov 3, 2000) 39 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de 40 41 Version 1.0.2 (Nov 6, 2000) 42 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs 43 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55 44 Support for the Dallas DS80C320 and DS80C323 45 B. Torok / bela.torok@kssg.ch 46 47 Version 1.0.3 (Nov 7, 2000) 48 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de 49 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch 50 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch 51 52 Version 1.0.4 (Nov 9, 2000) 53 To simplify the identication of registers, a large number of definitios 54 were renamed. Long register names now (hopefully) clearly define the 55 function of the registers. 56 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch 57 58 Version 1.0.5 (Dec 15, 2000) 59 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM 60 #ifdef MCS51REG_EXTERNAL_RAM 61 #ifndef MCS51REG_DISABLE_WARNINGS 62 63 64 Version 1.0.6 (March 10, 2001) 65 Support for the Dallas DS5000 & DS2250 66 Support for the Dallas DS5001 & DS2251 67 Support for the Dallas DS80C390 68 microcontrollers - B. Torok / bela.torok@kssg.ch 69 70 Version 1.0.7 (June 7, 2001) 71 #ifndef MCS51REG_DISABLE_WARNINGS removed 72 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch 73 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de 74 75 Version 1.0.8 (Feb 28, 2002) 76 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch 77 Revised by lanius@ewetel.net 78 79 Version 1.0.9 (Sept 9, 2002) 80 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de 81 82 Version 1.0.10 (Sept 19, 2002) 83 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net 84 85 Version 1.0.11 (Sept 19, 2004) 86 Dallas DS5000 MCON Register declarations corrected by Radek Zadera / a2i@swipnet.se 87 88 Version 1.0.12 (March 2, 2005) 89 Infineon SAB80C509 Register declarations added Thomas Boje / thomas@boje.name 90 91 Adding support for additional microcontrollers: 92 ----------------------------------------------- 93 94 1. Don't modify this file!!! 95 96 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include 97 this after the #define HEADER_MCS51REG statement in this file 98 99 3. The mcs51reg_update.h file should contain following definitions: 100 101 a. An entry with the inventory of the register set of the 102 microcontroller in the "Describe microcontrollers" section. 103 104 b. If necessary add entry(s) for registers not defined in this file 105 106 c. Define interrupt vectors 107 108 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:, 109 sdcc -E test.c > t.txt 110 and check definitions for validity in the t.txt file. 111 112 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch 113 I'm going to resolve conflicts & verify/merge new definitions to this file. 114 115 116 Microcontroller support: 117 118 Use one of the following options: 119 120 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile. 121 122 2. use following definitions prior the 123 #include <mcs51reg.h> line in your program: 124 e.g.: 125 #define MICROCONTROLLER_8052 -> 8052 type microcontroller 126 or 127 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers 128 129 130 Use only one of the following definitions!!! 131 132 Supported Microcontrollers: 133 134 No definition 8051 135 MICROCONTROLLER_8051 8051 136 MICROCONTROLLER_8052 8052 137 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051 138 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller 139 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers 140 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers 141 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller 142 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller 143 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers 144 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller 145 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller 146 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers 147 MICROCONTROLLER_P80C552 Philips P80C552 148 MICROCONTROLLER_P89C668 Philips P89C668 149 MICROCONTROLLER_SAB80C509 Infineon / Siemens SAB80C509 150 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535 151 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A 152 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517 153 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2 154 155 Additional definitions (use them prior the #include mcs51reg.h statement): 156 157 Ports P0 & P2 are not available if external ROM used. 158 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2. 159 160 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used. 161 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2, 162 P3_6, WR, P3_7 & RD. 163 164 #define MCS51REG_ENABLE_WARNINGS -> enable warnings 165 166 -----------------------------------------------------------------------*/ 167 168 169 #ifndef HEADER_MCS51REG 170 #define HEADER_MCS51REG 171 172 /////////////////////////////////////////////////////// 173 /// Insert header here (for developers only) /// 174 /// remove "//" from the begining of the next line /// 175 //#include "mcs51reg_update.h" /// 176 /////////////////////////////////////////////////////// 177 178 ////////////////////////////////// 179 /// Describe microcontrollers /// 180 /// (inventory of registers) /// 181 ////////////////////////////////// 182 183 // definitions for the 8051 184 #ifdef MICROCONTROLLER_8051 185 #ifdef MICROCONTROLLER_DEFINED 186 #define MCS51REG_ERROR 187 #endif 188 #ifndef MICROCONTROLLER_DEFINED 189 #define MICROCONTROLLER_DEFINED 190 #endif 191 #ifdef MCS51REG_ENABLE_WARNINGS 192 #warning Selected HW: 8051 193 #endif 194 #define P0 195 #define SP 196 #define DPL 197 #define DPH 198 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 199 #define TCON 200 #define TMOD 201 #define TL0 202 #define TL1 203 #define TH0 204 #define TH1 205 #define P1 206 #define SCON 207 #define SBUF 208 #define P2 209 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 210 #define P3 211 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0 212 #define PSW 213 #define ACC 214 #define B 215 #endif 216 // end of definitions for the 8051 217 218 219 // definitions for the 8052 microcontroller 220 #ifdef MICROCONTROLLER_8052 221 #ifdef MICROCONTROLLER_DEFINED 222 #define MCS51REG_ERROR 223 #endif 224 #ifndef MICROCONTROLLER_DEFINED 225 #define MICROCONTROLLER_DEFINED 226 #endif 227 #ifdef MCS51REG_ENABLE_WARNINGS 228 #warning Selected HW: 8052 229 #endif 230 // 8051 register set 231 #define P0 232 #define SP 233 #define DPL 234 #define DPH 235 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 236 #define TCON 237 #define TMOD 238 #define TL0 239 #define TL1 240 #define TH0 241 #define TH1 242 #define P1 243 #define SCON 244 #define SBUF 245 #define P2 246 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 247 #define P3 248 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 249 #define PSW 250 #define ACC 251 #define B 252 // 8052 specific registers 253 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 254 #define RCAP2L 255 #define RCAP2H 256 #define TL2 257 #define TH2 258 #endif 259 // end of definitions for the 8052 microcontroller 260 261 262 // definitionsons for the Atmel 263 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers 264 #ifdef MICROCONTROLLER_AT89CX051 265 #ifdef MICROCONTROLLER_DEFINED 266 #define MCS51REG_ERROR 267 #endif 268 #ifndef MICROCONTROLLER_DEFINED 269 #define MICROCONTROLLER_DEFINED 270 #endif 271 #ifdef MCS51REG_ENABLE_WARNINGS 272 #warning Selected HW: Atmel AT89Cx051 273 #endif 274 // 8051 register set without P0 & P2 275 #define SP 276 #define DPL 277 #define DPH 278 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 279 #define TCON 280 #define TMOD 281 #define TL0 282 #define TL1 283 #define TH0 284 #define TH1 285 #define P1 286 #define SCON 287 #define SBUF 288 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 289 #define P3 290 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0 291 #define PSW 292 #define ACC 293 #define B 294 #endif 295 // end of definitionsons for the Atmel 296 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers 297 298 299 // definitions for the Atmel AT89S53 300 #ifdef MICROCONTROLLER_AT89S53 301 #ifdef MICROCONTROLLER_DEFINED 302 #define MCS51REG_ERROR 303 #endif 304 #ifndef MICROCONTROLLER_DEFINED 305 #define MICROCONTROLLER_DEFINED 306 #endif 307 #ifdef MCS51REG_ENABLE_WARNINGS 308 #warning Selected HW: AT89S53 309 #endif 310 // 8051 register set 311 #define P0 312 #define SP 313 #define DPL 314 #define DPH 315 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 316 #define TCON 317 #define TMOD 318 #define TL0 319 #define TL1 320 #define TH0 321 #define TH1 322 #define P1 323 #define SCON 324 #define SBUF 325 #define P2 326 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 327 #define P3 328 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 329 #define PSW 330 #define ACC 331 #define B 332 // 8052 specific registers 333 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 334 #define RCAP2L 335 #define RCAP2H 336 #define TL2 337 #define TH2 338 // AT89S53 specific register 339 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 340 #define P1_EXT__x__x__x__x__x__x__T2EX__T2 341 #define SPCR 342 #define SPDR 343 #define SPSR 344 #define WCOM 345 #define DPL1 346 #define DPH1 347 #endif 348 // end of definitions for the Atmel AT89S53 microcontroller 349 350 351 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers 352 #ifdef MICROCONTROLLER_AT89X52 353 #ifdef MICROCONTROLLER_DEFINED 354 #define MCS51REG_ERROR 355 #endif 356 #ifndef MICROCONTROLLER_DEFINED 357 #define MICROCONTROLLER_DEFINED 358 #endif 359 #ifdef MCS51REG_ENABLE_WARNINGS 360 #warning Selected HW: AT89C52 or AT89LV52 361 #endif 362 // 8051 register set 363 #define P0 364 #define SP 365 #define DPL 366 #define DPH 367 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 368 #define TCON 369 #define TMOD 370 #define TL0 371 #define TL1 372 #define TH0 373 #define TH1 374 #define P1 375 #define SCON 376 #define SBUF 377 #define P2 378 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 379 #define P3 380 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 381 #define PSW 382 #define ACC 383 #define B 384 // 8052 specific registers 385 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 386 #define RCAP2L 387 #define RCAP2H 388 #define TL2 389 #define TH2 390 // AT89X55 specific register 391 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 392 #define P1_EXT__x__x__x__x__x__x__T2EX__T2 393 #endif 394 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers 395 396 397 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers 398 #ifdef MICROCONTROLLER_AT89X55 399 #ifdef MICROCONTROLLER_DEFINED 400 #define MCS51REG_ERROR 401 #endif 402 #ifndef MICROCONTROLLER_DEFINED 403 #define MICROCONTROLLER_DEFINED 404 #endif 405 #ifdef MCS51REG_ENABLE_WARNINGS 406 #warning Selected HW: AT89C55 or AT89LV55 407 #endif 408 // 8051 register set 409 #define P0 410 #define SP 411 #define DPL 412 #define DPH 413 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 414 #define TCON 415 #define TMOD 416 #define TL0 417 #define TL1 418 #define TH0 419 #define TH1 420 #define P1 421 #define SCON 422 #define SBUF 423 #define P2 424 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 425 #define P3 426 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 427 #define PSW 428 #define ACC 429 #define B 430 // 8052 specific registers 431 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 432 #define RCAP2L 433 #define RCAP2H 434 #define TL2 435 #define TH2 436 // AT89X55 specific register 437 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 438 #define P1_EXT__x__x__x__x__x__x__T2EX__T2 439 #endif 440 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers 441 442 443 // definitions for the Dallas DS5000 444 #ifdef MICROCONTROLLER_DS5000 445 #ifdef MICROCONTROLLER_DEFINED 446 #define MCS51REG_ERROR 447 #endif 448 #ifndef MICROCONTROLLER_DEFINED 449 #define MICROCONTROLLER_DEFINED 450 #endif 451 #ifdef MCS51REG_ENABLE_WARNINGS 452 #warning Selected HW: DS5000 453 #endif 454 #define P0 455 #define SP 456 #define DPL 457 #define DPH 458 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL 459 #define TCON 460 #define TMOD 461 #define TL0 462 #define TL1 463 #define TH0 464 #define TH1 465 #define P1 466 #define SCON 467 #define SBUF 468 #define P2 469 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 470 #define P3 471 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 472 #define MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL 473 #define TA 474 #define PSW 475 #define ACC 476 #define B 477 #endif 478 // end of definitions for the Dallas DS5000 479 480 481 // definitions for the Dallas DS5001 482 #ifdef MICROCONTROLLER_DS5001 483 #ifdef MICROCONTROLLER_DEFINED 484 #define MCS51REG_ERROR 485 #endif 486 #ifndef MICROCONTROLLER_DEFINED 487 #define MICROCONTROLLER_DEFINED 488 #endif 489 #ifdef MCS51REG_ENABLE_WARNINGS 490 #warning Selected HW: DS5001 491 #endif 492 #define P0 493 #define SP 494 #define DPL 495 #define DPH 496 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL 497 #define TCON 498 #define TMOD 499 #define TL0 500 #define TL1 501 #define TH0 502 #define TH1 503 #define P1 504 #define SCON 505 #define SBUF 506 #define P2 507 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 508 #define P3 509 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 510 #define CRC 511 #define CRCLOW 512 #define CRCHIGH 513 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL 514 #define TA 515 #define RNR 516 #define PSW 517 #define RPCTL 518 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF 519 #define ACC 520 #define B 521 #endif 522 // end of definitions for the Dallas DS5001 523 524 525 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers 526 #ifdef MICROCONTROLLER_DS80C32X 527 #ifdef MICROCONTROLLER_DEFINED 528 #define MCS51REG_ERROR 529 #endif 530 #ifndef MICROCONTROLLER_DEFINED 531 #define MICROCONTROLLER_DEFINED 532 #endif 533 #ifdef MCS51REG_ENABLE_WARNINGS 534 #warning Selected HW: Dallas DS80C320 or DS80C323 535 #endif 536 // 8051 register set 537 #define P0 538 #define SP 539 #define DPL 540 #define DPH 541 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE 542 #define TCON 543 #define TMOD 544 #define TL0 545 #define TL1 546 #define TH0 547 #define TH1 548 #define P1 549 #define SCON 550 #define SCON0 551 #define SBUF 552 #define P2 553 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 554 #define P3 555 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 556 #define PSW 557 #define ACC 558 #define B 559 // 8052 specific registers 560 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 561 #define RCAP2L 562 #define RCAP2H 563 #define TL2 564 #define TH2 565 // DS80C320 specific register 566 #define DPL1 567 #define DPH1 568 #define DPS__x__x__x__x__x__x__x__SEL 569 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 570 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS 571 #define SADDR0 572 #define SADDR1 573 #define SADEN0 574 #define SADEN1 575 #define SCON1 576 #define SBUF1 577 #define STATUS__PIP__HIP__LIP__x__x__x__x__x 578 #define TA 579 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 580 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 581 #define WDCON 582 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 583 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 584 #endif 585 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers 586 587 588 // definitions for the Dallas DS80C390 589 #ifdef MICROCONTROLLER_DS80C390 590 #ifdef MICROCONTROLLER_DEFINED 591 #define MCS51REG_ERROR 592 #endif 593 #ifndef MICROCONTROLLER_DEFINED 594 #define MICROCONTROLLER_DEFINED 595 #endif 596 #ifdef MCS51REG_ENABLE_WARNINGS 597 #warning Selected HW: Dallas DS80C390 598 #endif 599 // 8051 register set 600 #define P0 601 #define SP 602 #define DPL 603 #define DPH 604 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE 605 #define TCON 606 #define TMOD 607 #define TL0 608 #define TL1 609 #define TH0 610 #define TH1 611 #define P1 612 #define SCON 613 #define SCON0 614 #define SBUF 615 #define P2 616 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 617 #define P3 618 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 619 #define PSW 620 #define ACC 621 #define B 622 // 8052 specific registers 623 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 624 #define RCAP2L 625 #define RCAP2H 626 #define TL2 627 #define TH2 628 // DS80C390 specific register 629 #define P4_AT_0X80 630 #define DPL1 631 #define DPH1 632 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL 633 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 634 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS 635 #define P4CNT 636 #define DPX 637 #define DPX1 638 #define C0RMS0 639 #define C0RMS1 640 #define ESP 641 #define AP 642 #define ACON__x__x__x__x__x__SA__AM1__AM0 643 #define C0TMA0 644 #define C0TMA1 645 #define P5_AT_0XA1 646 #define P5CNT 647 #define C0C 648 #define C0S 649 #define C0IR 650 #define C0TE 651 #define C0RE 652 #define SADDR0 653 #define SADDR1 654 #define C0M1C 655 #define C0M2C 656 #define C0M3C 657 #define C0M4C 658 #define C0M5C 659 #define C0M6C 660 #define C0M7C 661 #define C0M8C 662 #define C0M9C 663 #define C0M10C 664 #define SADEN0 665 #define SADEN1 666 #define C0M11C 667 #define C0M12C 668 #define C0M13C 669 #define C0M14C 670 #define C0M15C 671 #define SCON1 672 #define SBUF1 673 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x 674 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 675 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 676 #define TA 677 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN 678 #define COR 679 #define MCNT0 680 #define MCNT1 681 #define MA 682 #define MB 683 #define MC 684 #define C1RSM0 685 #define C1RSM1 686 #define WDCON 687 #define C1TMA0 688 #define C1TMA1 689 #define C1C 690 #define C1S 691 #define C1IR 692 #define C1TE 693 #define C1RE 694 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 695 #define MXMAX 696 #define C1M1C 697 #define C1M2C 698 #define C1M3C 699 #define C1M4C 700 #define C1M5C 701 #define C1M6C 702 #define C1M7C 703 #define C1M8C 704 #define C1M9C 705 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 706 #define C1M10C 707 #define C1M11C 708 #define C1M12C 709 #define C1M13C 710 #define C1M14C 711 #define C1M15C 712 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 713 #endif 714 // end of definitions for the Dallas DS80C390 715 716 // definitions for the Dallas DS89C420 microcontroller 717 #ifdef MICROCONTROLLER_DS89C420 718 #ifdef MICROCONTROLLER_DEFINED 719 #define MCS51REG_ERROR 720 #endif 721 #ifndef MICROCONTROLLER_DEFINED 722 #define MICROCONTROLLER_DEFINED 723 #endif 724 #ifdef MCS51REG_ENABLE_WARNINGS 725 #warning Selected HW: Dallas DS89C420 726 #endif 727 // 8051 register set 728 #define P0 729 #define SP 730 #define DPL 731 #define DPH 732 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE 733 #define TCON 734 #define TMOD 735 #define TL0 736 #define TL1 737 #define TH0 738 #define TH1 739 #define P1 740 #define SCON 741 #define SCON0 742 #define SBUF 743 #define P2 744 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 745 #define P3 746 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 747 #define PSW 748 #define ACC 749 #define B 750 // 8052 specific registers 751 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 752 #define RCAP2L 753 #define RCAP2H 754 #define TL2 755 #define TH2 756 // DS8XC420 specific registers 757 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x 758 #define DPL1 759 #define DPH1 760 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL 761 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 762 #define CKMOD 763 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 764 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 765 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS 766 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 767 #define SADDR0 768 #define SADDR1 769 #define SADEN0 770 #define SADEN1 771 #define SCON1 772 #define SBUF1 773 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 774 #define TA 775 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 776 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 777 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 778 #define WDCON 779 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 780 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 781 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 782 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 783 #endif 784 // end of definitions for the Dallas DS89C420 microcontroller 785 786 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers 787 #ifdef MICROCONTROLLER_DS8XC520 788 #ifdef MICROCONTROLLER_DEFINED 789 #define MCS51REG_ERROR 790 #endif 791 #ifndef MICROCONTROLLER_DEFINED 792 #define MICROCONTROLLER_DEFINED 793 #endif 794 #ifdef MCS51REG_ENABLE_WARNINGS 795 #warning Selected HW: Dallas DS87C520 or DS85C520 796 #endif 797 // 8051 register set 798 #define P0 799 #define SP 800 #define DPL 801 #define DPH 802 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE 803 #define TCON 804 #define TMOD 805 #define TL0 806 #define TL1 807 #define TH0 808 #define TH1 809 #define P1 810 #define SCON 811 #define SCON0 812 #define SBUF 813 #define P2 814 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 815 #define P3 816 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 817 #define PSW 818 #define ACC 819 #define B 820 // 8052 specific registers 821 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 822 #define RCAP2L 823 #define RCAP2H 824 #define TL2 825 #define TH2 826 // DS8XC520 specific registers 827 #define DPL1 828 #define DPH1 829 #define DPS__x__x__x__x__x__x__x__SEL 830 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 831 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS 832 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 833 #define SADDR0 834 #define SADDR1 835 #define SADEN0 836 #define SADEN1 837 #define SCON1 838 #define SBUF1 839 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 840 #define TA 841 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 842 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 843 #define WDCON 844 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 845 #define BP2 846 #define WDCON 847 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 848 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 849 #endif 850 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers 851 852 853 // definitions for the Philips P80C552 microcontroller 854 #ifdef MICROCONTROLLER_P80C552 855 #ifdef MICROCONTROLLER_DEFINED 856 #define MCS51REG_ERROR 857 #endif 858 #ifndef MICROCONTROLLER_DEFINED 859 #define MICROCONTROLLER_DEFINED 860 #endif 861 #ifdef MCS51REG_ENABLE_WARNINGS 862 #warning Selected HW: Philips P80C552 863 #endif 864 // 8051 register set 865 #define P0 866 #define SP 867 #define DPL 868 #define DPH 869 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL 870 #define TCON 871 #define TMOD 872 #define TL0 873 #define TL1 874 #define TH0 875 #define TH1 876 #define P1 877 #define SCON 878 #define SBUF 879 #define P2 880 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 881 #define P3 882 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 883 #define PSW 884 #define ACC 885 #define B 886 // P80C552 specific register-names 887 #define S0BUF // same as SBUF, set in mcs51reg.h 888 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI 889 // P80C552 specific registers 890 #define ADCH_AT_0XC6 891 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 892 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 893 #define CTH0_AT_0XCC 894 #define CTH1_AT_0XCD 895 #define CTH2_AT_0XCE 896 #define CTH3_AT_0XCF 897 #define CMH0_AT_0XC9 898 #define CMH1_AT_0XCA 899 #define CMH2_AT_0XCB 900 #define CTL0_AT_0XAC 901 #define CTL1_AT_0XAD 902 #define CTL2_AT_0XAE 903 #define CTL3_AT_0XAF 904 #define CML0_AT_0XA9 905 #define CML1_AT_0XAA 906 #define CML2_AT_0XAB 907 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 908 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 909 #define PWM0_AT_0XFC 910 #define PWM1_AT_0XFD 911 #define PWMP_AT_0XFE 912 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I 913 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 914 #define P5_AT_0XC4 915 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 916 #define S1ADR__x__x__x__x__x__x__x__GC 917 #define S1DAT_AT_0XDA 918 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x 919 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 920 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 921 #define TMH2_AT_0XED 922 #define TML2_AT_0XEC 923 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 924 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 925 #define T3_AT_0XFF 926 #endif 927 // end of definitions for the Philips P80C552 microcontroller 928 929 930 // definitions for the Philips P89C668 931 #ifdef MICROCONTROLLER_P89C668 932 #ifdef MICROCONTROLLER_DEFINED 933 #define MCS51REG_ERROR 934 #endif 935 #ifndef MICROCONTROLLER_DEFINED 936 #define MICROCONTROLLER_DEFINED 937 #endif 938 #ifdef MCS51REG_ENABLE_WARNINGS 939 #warning Selected HW: P89C668 940 #endif 941 #define P0 942 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 943 #define P1 944 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 945 #define P2 946 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 947 #define P3 948 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x 949 #define SP 950 #define DPL 951 #define DPH 952 #define TCON 953 #define TMOD 954 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL 955 #define TL0 956 #define TL1 957 #define TH0 958 #define TH1 959 #define SCON 960 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI 961 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 962 #define SBUF 963 #define S0BUF SBUF 964 #define PSW 965 #define ACC 966 #define B 967 #define SADR_AT_0XA9 968 #define SADEN_AT_0XB9 969 #define S1IST_AT_0XDC 970 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x 971 #define S1DAT_AT_0XDA 972 #define S1ADR__x__x__x__x__x__x__x__GC 973 #define SBUF 974 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 975 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN 976 #define RCAP2L 977 #define RCAP2H 978 #define TL2 979 #define TH2 980 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 981 #define IEN1__x__x__x__x__x__x__x__ET2 982 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 983 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H 984 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 985 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 986 #define AUXR__x__x__x__x__x__x__EXTRAM__A0 987 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS 988 #define WDTRST_AT_0XA6 989 #define CCAPM0_AT_0XC2 990 #define CCAPM1_AT_0XC3 991 #define CCAPM2_AT_0XC4 992 #define CCAPM3_AT_0XC5 993 #define CCAPM4_AT_0XC6 994 #define CCAP0L_AT_0XEA 995 #define CCAP1L_AT_0XEB 996 #define CCAP2L_AT_0XEC 997 #define CCAP3L_AT_0XED 998 #define CCAP4L_AT_0XEE 999 #define CH_AT_0XF9 1000 #define CL_AT_0XE9 1001 #define CCAP0H_AT_0XFA 1002 #define CCAP1H_AT_0XFB 1003 #define CCAP2H_AT_0XFC 1004 #define CCAP3H_AT_0XFD 1005 #define CCAP4H_AT_0XFE 1006 #endif 1007 // end of definitions for the Philips P89C668 1008 1009 1010 // definitions for the Infineon / Siemens SAB80509 1011 #ifdef MICROCONTROLLER_SAB80509 1012 #ifdef MICROCONTROLLER_DEFINED 1013 #define MCS51REG_ERROR 1014 #endif 1015 #ifndef MICROCONTROLLER_DEFINED 1016 #define MICROCONTROLLER_DEFINED 1017 #endif 1018 #ifdef MCS51REG_ENABLE_WARNINGS 1019 #warning Selected HW: Infineon / Siemens SAB80509 1020 #endif 1021 // 8051 register set without IP 1022 #define P0 1023 #define SP 1024 #define DPL 1025 #define DPH 1026 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL 1027 #define TCON 1028 #define TMOD 1029 #define TL0 1030 #define TL1 1031 #define TH0 1032 #define TH1 1033 #define WDTREL 1034 #define P1 1035 #define XPAGE 1036 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 1037 #define IEN2__SAB80517 1038 1039 #define P2 1040 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 1041 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 1042 1043 #define P3 1044 #define SYSCON 1045 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 1046 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 1047 1048 #define IRCON 1049 #define CCEN 1050 #define CCL1 1051 #define CCH1 1052 #define CCL2 1053 #define CCH2 1054 #define CCL3 1055 #define CCH3 1056 #define CCL4 1057 #define CCH4 1058 #define CC4EN 1059 #define S0RELH 1060 #define S0RELL 1061 #define S1BUF 1062 #define S1CON_AT_0X9B 1063 #define S1RELH 1064 #define S1RELL 1065 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 1066 1067 #define PSW 1068 #define CMEN 1069 #define CMH0 1070 #define CML0 1071 #define CMH1 1072 #define CML1 1073 #define CMH2 1074 #define CML2 1075 #define CMH3 1076 #define CML3 1077 #define CMH4 1078 #define CML4 1079 #define CMH5 1080 #define CML5 1081 #define CMH6 1082 #define CML6 1083 #define CMH7 1084 #define CML7 1085 #define CMSEL 1086 #define CRCL 1087 #define CRCH 1088 #define CTCOM_AT_0XE1 1089 #define CTRELH 1090 #define CTRELL 1091 #define TL2 1092 #define TH2 1093 #define ADCON0 1094 #define ADCON1 1095 #define ADDATH 1096 #define ADDATL 1097 1098 #define P4_AT_0XE8 1099 #define DPSEL 1100 #define ARCON 1101 #define MD0 1102 #define MD1 1103 #define MD2 1104 #define MD3 1105 #define MD4 1106 #define MD5 1107 #define S0BUF 1108 1109 #define ACC 1110 1111 #define B 1112 1113 #define P5_AT_0XF8 1114 #define P6_AT_0XFA 1115 #define P7 1116 #define P8 1117 1118 #define COMSETL 1119 #define COMSETH 1120 #define COMCLRL 1121 #define COMCLRH 1122 #define SETMSK 1123 #define CLRMSK 1124 #define SYSCON1 1125 #define FMODE 1126 #define PRSC 1127 #define CT1COM 1128 #define IEN3 1129 #define IRCON2 1130 #define EICC1 1131 #define CC1 1132 #define CC2 1133 #define CC3 1134 #define CC4 1135 #define CCR 1136 #define T2 1137 #define P9_AT_0XF9 1138 #endif 1139 // end of definitions for the Infineon / Siemens SAB80509 1140 1141 1142 // definitions for the Infineon / Siemens SAB80515 & SAB80535 1143 #ifdef MICROCONTROLLER_SAB80515 1144 #ifdef MICROCONTROLLER_DEFINED 1145 #define MCS51REG_ERROR 1146 #endif 1147 #ifndef MICROCONTROLLER_DEFINED 1148 #define MICROCONTROLLER_DEFINED 1149 #endif 1150 #ifdef MCS51REG_ENABLE_WARNINGS 1151 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535 1152 #endif 1153 // 8051 register set without IP 1154 #define P0 1155 #define SP 1156 #define DPL 1157 #define DPH 1158 #define PCON__SMOD__x__x__x__x__x__x__x 1159 #define TCON 1160 #define TMOD 1161 #define TL0 1162 #define TL1 1163 #define TH0 1164 #define TH1 1165 #define P1 1166 #define SCON 1167 #define SBUF 1168 #define P2 1169 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 1170 #define P3 1171 #define PSW 1172 #define ACC 1173 #define B 1174 // SAB80515 specific registers 1175 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 1176 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 1177 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 1178 #define IRCON 1179 #define CCEN 1180 #define CCL1 1181 #define CCH1 1182 #define CCL2 1183 #define CCH2 1184 #define CCL3 1185 #define CCH3 1186 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 1187 #define CRCL 1188 #define CRCH 1189 #define TL2 1190 #define TH2 1191 #define ADCON 1192 #define ADDAT 1193 #define DAPR__SAB80515 1194 #define P4_AT_0XE8 1195 #define P5_AT_0XF8 1196 #define P6_AT_0XDB 1197 #endif 1198 // end of definitions for the Infineon / Siemens SAB80515 1199 1200 1201 // definitions for the Infineon / Siemens SAB80515A 1202 #ifdef MICROCONTROLLER_SAB80515A 1203 #ifdef MICROCONTROLLER_DEFINED 1204 #define MCS51REG_ERROR 1205 #endif 1206 #ifndef MICROCONTROLLER_DEFINED 1207 #define MICROCONTROLLER_DEFINED 1208 #endif 1209 #ifdef MCS51REG_ENABLE_WARNINGS 1210 #warning Selected HW: Infineon / Siemens SAB80515A 1211 #endif 1212 // 8051 register set without IP 1213 #define P0 1214 #define SP 1215 #define DPL 1216 #define DPH 1217 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL 1218 #define TCON 1219 #define TMOD 1220 #define TL0 1221 #define TL1 1222 #define TH0 1223 #define TH1 1224 #define P1 1225 #define SCON 1226 #define SBUF 1227 #define P2 1228 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 1229 #define P3 1230 #define PSW 1231 #define ACC 1232 #define B 1233 // SAB80515A specific registers 1234 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 1235 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 1236 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 1237 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 1238 #define IRCON 1239 #define CCEN 1240 #define CCL1 1241 #define CCH1 1242 #define CCL2 1243 #define CCH2 1244 #define CCL3 1245 #define CCH3 1246 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 1247 #define CRCL 1248 #define CRCH 1249 #define TL2 1250 #define TH2 1251 #define ADCON0 1252 #define ADDATH 1253 #define ADDATL 1254 #define ADCON1 1255 #define SRELL 1256 #define SYSCON 1257 #define SRELH 1258 #define P4_AT_0XE8 1259 #define P5_AT_0XF8 1260 #define P6_AT_0XDB 1261 #define XPAGE 1262 #endif 1263 // end of definitions for the Infineon / Siemens SAB80515A 1264 1265 1266 // definitions for the Infineon / Siemens SAB80517 1267 #ifdef MICROCONTROLLER_SAB80517 1268 #ifdef MICROCONTROLLER_DEFINED 1269 #define MCS51REG_ERROR 1270 #endif 1271 #ifndef MICROCONTROLLER_DEFINED 1272 #define MICROCONTROLLER_DEFINED 1273 #endif 1274 #ifdef MCS51REG_ENABLE_WARNINGS 1275 #warning Selected HW: Infineon / Siemens SAB80517 1276 #endif 1277 // 8051 register set without IP, SCON & SBUF 1278 #define P0 1279 #define SP 1280 #define DPL 1281 #define DPH 1282 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL 1283 #define TCON 1284 #define TMOD 1285 #define TL0 1286 #define TL1 1287 #define TH0 1288 #define TH1 1289 #define P1 1290 // #define SCON 1291 // #define SBUF 1292 #define P2 1293 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 1294 #define P3 1295 #define PSW 1296 #define ACC 1297 #define B 1298 // SAB80517 specific registers 1299 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 1300 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 1301 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 1302 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 1303 #define IEN2__SAB80517 1304 #define IRCON 1305 #define CCEN 1306 #define CCL1 1307 #define CCH1 1308 #define CCL2 1309 #define CCH2 1310 #define CCL3 1311 #define CCH3 1312 #define CCL4 1313 #define CCH4 1314 #define CC4EN 1315 #define CMEN 1316 #define CMH0 1317 #define CML0 1318 #define CMH1 1319 #define CML1 1320 #define CMH2 1321 #define CML2 1322 #define CMH3 1323 #define CML3 1324 #define CMH4 1325 #define CML4 1326 #define CMH5 1327 #define CML5 1328 #define CMH6 1329 #define CML6 1330 #define CMH7 1331 #define CML7 1332 #define CMSEL 1333 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 1334 #define CRCL 1335 #define CRCH 1336 #define CTCOM_AT_0XE1 1337 #define CTRELH 1338 #define CTRELL 1339 #define TL2 1340 #define TH2 1341 #define ADCON0 1342 #define ADCON1 1343 #define ADDAT 1344 #define DAPR__SAB80517 1345 #define P4_AT_0XE8 1346 #define P5_AT_0XF8 1347 #define P6_AT_0XFA 1348 #define P7_AT_0XDB 1349 #define P8_AT_0XDD 1350 #define DPSEL 1351 #define ARCON 1352 #define MD0 1353 #define MD1 1354 #define MD2 1355 #define MD3 1356 #define MD4 1357 #define MD5 1358 #define S0BUF 1359 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 1360 #define S0RELH 1361 #define S0RELL 1362 #define S1BUF 1363 #define S1CON_AT_0X9B 1364 #define S1RELH 1365 #define S1RELL 1366 #define WDTH 1367 #define WDTL 1368 #define WDTREL 1369 #endif 1370 // end of definitions for the Infineon / Siemens SAB80517 1371 1372 1373 // definitions for the Atmel T89C51RD2 1374 #ifdef MICROCONTROLLER_T89C51RD2 1375 #ifdef MICROCONTROLLER_DEFINED 1376 #define MCS51REG_ERROR 1377 #endif 1378 #ifndef MICROCONTROLLER_DEFINED 1379 #define MICROCONTROLLER_DEFINED 1380 #endif 1381 #ifdef MCS51REG_ENABLE_WARNINGS 1382 #warning Selected HW: T89C51RD2 1383 #endif 1384 1385 // 8051 register set 1386 #define P0 1387 #define SP 1388 #define DPL 1389 #define DPH 1390 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL 1391 #define TCON 1392 #define TMOD 1393 #define TL0 1394 #define TL1 1395 #define TH0 1396 #define TH1 1397 #define P1 1398 #define SCON 1399 #define SBUF 1400 #define P2 1401 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 1402 #define SADDR 1403 #define P3 1404 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 1405 #define PSW 1406 #define ACC 1407 #define B 1408 1409 // 8052 register set 1410 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 1411 #define RCAP2L 1412 #define RCAP2H 1413 #define TL2 1414 #define TH2 1415 1416 // T89C51RD2 register set 1417 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 1418 #define P5_AT_0XE8 1419 #define SADEN0 1420 1421 #define AUXR1__x__x__x__x__GF3__x__x__DPS 1422 #define WDTRST_AT_0XA6 1423 #define WDTPRG_AT_0XA7 1424 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 1425 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H 1426 #define FCON 1427 #define EECON 1428 #define EETIM 1429 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x 1430 #define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 1431 #define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 1432 #define CCAPM0_AT_0XDA 1433 #define CCAPM1_AT_0XDB 1434 #define CCAPM2_AT_0XDC 1435 #define CCAPM3_AT_0XDD 1436 #define CCAPM4_AT_0XDE 1437 #define CL_AT_0XE9 1438 #define CCAP0L_AT_0XEA 1439 #define CCAP1L_AT_0XEB 1440 #define CCAP2L_AT_0XEC 1441 #define CCAP3L_AT_0XED 1442 #define CCAP4L_AT_0XEE 1443 #define CH_AT_0XF9 1444 #define CCAP0H_AT_0XFA 1445 #define CCAP1H_AT_0XFB 1446 #define CCAP2H_AT_0XFC 1447 #define CCAP3H_AT_0XFD 1448 #define CCAP4H_AT_0XFE 1449 #endif /* MICROCONTROLLER_T89C51RD2 */ 1450 /* end of definition for the Atmel T89C51RD2 */ 1451 1452 1453 ///////////////////////////////////////////////////////// 1454 /// don't specify microcontrollers below this line! /// 1455 ///////////////////////////////////////////////////////// 1456 1457 1458 // default microcontroller -> 8051 1459 // use default if no microcontroller specified 1460 #ifndef MICROCONTROLLER_DEFINED 1461 #define MICROCONTROLLER_DEFINED 1462 #ifdef MCS51REG_ENABLE_WARNINGS 1463 #warning No microcontroller defined! 1464 #warning Code generated for the 8051 1465 #endif 1466 // 8051 register set 1467 #define P0 1468 #define SP 1469 #define DPL 1470 #define DPH 1471 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 1472 #define TCON 1473 #define TMOD 1474 #define TL0 1475 #define TL1 1476 #define TH0 1477 #define TH1 1478 #define P1 1479 #define SCON 1480 #define SBUF 1481 #define P2 1482 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 1483 #define P3 1484 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0 1485 #define PSW 1486 #define ACC 1487 #define B 1488 #endif 1489 // end of definitions for the default microcontroller 1490 1491 1492 #ifdef MCS51REG_ERROR 1493 #error Two or more microcontrollers defined! 1494 #endif 1495 1496 #ifdef MCS51REG_EXTERNAL_ROM 1497 #ifndef MCS51REG_UNDEFINE_P0 1498 #define MCS51REG_UNDEFINE_P0 1499 #endif 1500 #ifndef MCS51REG_UNDEFINE_P2 1501 #define MCS51REG_UNDEFINE_P2 1502 #endif 1503 #endif 1504 1505 #ifdef MCS51REG_EXTERNAL_RAM 1506 #ifndef MCS51REG_UNDEFINE_P0 1507 #define MCS51REG_UNDEFINE_P0 1508 #endif 1509 #ifndef MCS51REG_UNDEFINE_P2 1510 #define MCS51REG_UNDEFINE_P2 1511 #endif 1512 #endif 1513 1514 #ifdef MCS51REG_UNDEFINE_P0 1515 #undef P0 1516 #endif 1517 1518 #ifdef MCS51REG_UNDEFINE_P2 1519 #undef P2 1520 #endif 1521 1522 //////////////////////////////// 1523 /// Register definitions /// 1524 /// (In alphabetical order) /// 1525 //////////////////////////////// 1526 1527 #ifdef ACC 1528 #undef ACC 1529 __sfr __at 0xE0 ACC ; 1530 #endif 1531 1532 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x 1533 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x 1534 __sfr __at 0x9D ACON ; // DS89C420 specific 1535 // Not directly accessible bits 1536 #define PAGES0 0x20 1537 #define PAGES1 0x40 1538 #define PAGEE 0x80 1539 #endif 1540 1541 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0 1542 #undef ACON__x__x__x__x__x__SA__AM1__AM0 1543 __sfr __at 0x9D ACON ; // DS89C390 specific 1544 // Not directly accessible bits 1545 #define AM0 0x01 1546 #define AM1 0x02 1547 #define SA 0x04 1548 #endif 1549 1550 #ifdef ADCH_AT_0XC6 1551 #undef ADCH_AT_0XC6 1552 __sfr __at 0xC6 ADCH ; // A/D converter high 1553 #endif 1554 1555 #ifdef ADCON 1556 #undef ADCON 1557 __sfr __at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific 1558 // Bit registers 1559 __sbit __at 0xD8 MX0 ; 1560 __sbit __at 0xD9 MX1 ; 1561 __sbit __at 0xDA MX2 ; 1562 __sbit __at 0xDB ADM ; 1563 __sbit __at 0xDC BSY ; 1564 __sbit __at 0xDE CLK ; 1565 __sbit __at 0xDF BD ; 1566 #endif 1567 1568 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual 1569 #ifdef ADCON0 1570 #undef ADCON0 1571 __sfr __at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A & 1572 // Bit registers // SAB80517 specific 1573 __sbit __at 0xD8 MX0 ; 1574 __sbit __at 0xD9 MX1 ; 1575 __sbit __at 0xDA MX2 ; 1576 __sbit __at 0xDB ADM ; 1577 __sbit __at 0xDC BSY ; 1578 __sbit __at 0xDD ADEX ; 1579 __sbit __at 0xDE CLK ; 1580 __sbit __at 0xDF BD ; 1581 // Not directly accessible ADCON0 1582 #define ADCON0_MX0 0x01 1583 #define ADCON0_MX1 0x02 1584 #define ADCON0_MX2 0x04 1585 #define ADCON0_ADM 0x08 1586 #define ADCON0_BSY 0x10 1587 #define ADCON0_ADEX 0x20 1588 #define ADCON0_CLK 0x40 1589 #define ADCON0_BD 0x80 1590 #endif 1591 1592 #ifdef ADCON1 1593 #undef ADCON1 1594 __sfr __at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific 1595 // Not directly accessible ADCON1 1596 #define ADCON1_MX0 0x01 1597 #define ADCON1_MX1 0x02 1598 #define ADCON1_MX2 0x04 1599 #define ADCON1_ADCL 0x80 1600 #endif 1601 1602 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 1603 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 1604 __sfr __at 0xC5 ADCON ; // A/D control, P80C552 specific 1605 // Not directly accessible Bits. 1606 #define AADR0 0x01 1607 #define AADR1 0x02 1608 #define AADR2 0x04 1609 #define ADCS 0x08 1610 #define ADCI 0x10 1611 #define ADEX 0x20 1612 #define ADC_0 0x40 // different name as ADC0 in P5 1613 #define ADC_1 0x80 // different name as ADC1 in P5 1614 #endif 1615 1616 #ifdef ADDAT 1617 #undef ADDAT 1618 __sfr __at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific 1619 #endif 1620 1621 #ifdef ADDATH 1622 #undef ADDATH 1623 __sfr __at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific 1624 #endif 1625 1626 #ifdef ADDATL 1627 #undef ADDATL 1628 __sfr __at 0xDA ADDATL ; // A/D data low byte SAB80515A specific 1629 #endif 1630 1631 #ifdef ARCON 1632 #undef ARCON 1633 __sfr __at 0xEF ARCON ; // arithmetic control register SAB80517 1634 #endif 1635 1636 #ifdef AP 1637 #undef AP 1638 __sfr __at 0x9C AP ; // DS80C390 1639 #endif 1640 1641 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0 1642 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0 1643 // P89C668 specific, Auxilary 1644 __sfr __at 0x8E AUXR ; 1645 // not bit addressable: 1646 #define EXTRAM 0x02 1647 #define A0 0x01 1648 #endif 1649 1650 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 1651 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 1652 __sfr __at 0x8E AUXR ; 1653 #define AO 0x01 1654 #define EXTRAM 0x02 1655 #define XRS0 0x04 1656 #define XRS1 0x08 1657 #define M0 0x20 1658 #endif 1659 #ifdef B 1660 #undef B 1661 __sfr __at 0xF0 B ; 1662 // Bit registers 1663 __sbit __at 0xF0 BREG_F0 ; 1664 __sbit __at 0xF1 BREG_F1 ; 1665 __sbit __at 0xF2 BREG_F2 ; 1666 __sbit __at 0xF3 BREG_F3 ; 1667 __sbit __at 0xF4 BREG_F4 ; 1668 __sbit __at 0xF5 BREG_F5 ; 1669 __sbit __at 0xF6 BREG_F6 ; 1670 __sbit __at 0xF7 BREG_F7 ; 1671 #endif 1672 1673 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS 1674 #undef AUXR1__x__x__x__x__GF3__x__x__DPS 1675 __sfr __at 0xA2 AUXR1 ; 1676 #define DPS 0x01 1677 #define GF3 0x08 1678 #endif 1679 1680 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS 1681 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS 1682 // P89C668 specific, Auxilary 1 1683 __sfr __at 0xA2 AUXR1 ; 1684 #define ENBOOT 0x20 1685 #define GF2 0x08 1686 #define ALWAYS_ZERO 0x04 1687 #define DPS 0x01 1688 #endif 1689 1690 #ifdef BP2 1691 #undef BP2 1692 __sfr __at 0xC3 BP2 ; 1693 // Not directly accessible bits 1694 #define MS0 0x01 1695 #define MS1 0x02 1696 #define MS2 0x04 1697 #define LB1 0x08 1698 #define LB2 0x10 1699 #define LB3 0x20 1700 #endif 1701 1702 #ifdef C0C 1703 #undef C0C 1704 __sfr __at 0xA3 C0C ; // DS80C390 specific 1705 // Not directly accessible bits 1706 #define SWINT 0x01 1707 #define ERCS 0x02 1708 #define AUTOB 0x04 1709 #define CRST 0x08 1710 #define SIESTA 0x10 1711 #define PDE 0x20 1712 #define STIE 0x40 1713 #define ERIE 0x80 1714 #endif 1715 1716 #ifdef C0IR 1717 #undef C0IR 1718 __sfr __at 0xA5 C0IR ; // DS80C390 specific 1719 // Not directly accessible bits 1720 #define INTIN0 0x01 1721 #define INTIN1 0x02 1722 #define INTIN2 0x04 1723 #define INTIN3 0x08 1724 #define INTIN4 0x10 1725 #define INTIN5 0x20 1726 #define INTIN6 0x40 1727 #define INTIN7 0x80 1728 #endif 1729 1730 #ifdef C0M1C 1731 #undef C0M1C 1732 __sfr __at 0xAB C0M1C ; // DS80C390 specific 1733 // Not directly accessible bits 1734 #define DTUP 0x01 1735 #define ROW_TIH 0x02 1736 #define MTRQ 0x04 1737 #define EXTRQ 0x08 1738 #define INTRQ 0x10 1739 #define ERI 0x20 1740 #define ETI 0x40 1741 #define MSRDY 0x80 1742 #endif 1743 1744 #ifdef C0M2C 1745 #undef C0M2C 1746 __sfr __at 0xAC C0M2C ; // DS80C390 specific 1747 #endif 1748 1749 #ifdef C0M3C 1750 #undef C0M3C 1751 __sfr __at 0xAD C0M3C ; // DS80C390 specific 1752 #endif 1753 1754 #ifdef C0M4C 1755 #undef C0M4C 1756 __sfr __at 0xAE C0M4C ; // DS80C390 specific 1757 #endif 1758 1759 #ifdef C0M5C 1760 #undef C0M5C 1761 __sfr __at 0xAF C0M5C ; // DS80C390 specific 1762 #endif 1763 1764 #ifdef C0M6C 1765 #undef C0M6C 1766 __sfr __at 0xB3 C0M6C ; // DS80C390 specific 1767 #endif 1768 1769 #ifdef C0M7C 1770 #undef C0M7C 1771 __sfr __at 0xB4 C0M7C ; // DS80C390 specific 1772 #endif 1773 1774 #ifdef C0M8C 1775 #undef C0M8C 1776 __sfr __at 0xB5 C0M8C ; // DS80C390 specific 1777 #endif 1778 1779 #ifdef C0M9C 1780 #undef C0M9C 1781 __sfr __at 0xB6 C0M9C ; // DS80C390 specific 1782 #endif 1783 1784 #ifdef C0M10C 1785 #undef C0M10C 1786 __sfr __at 0xB7 C0M10C ; // DS80C390 specific 1787 #endif 1788 1789 #ifdef C0M11C 1790 #undef C0M11C 1791 __sfr __at 0xBB C0M11C ; // DS80C390 specific 1792 #endif 1793 1794 #ifdef C0M12C 1795 #undef C0M12C 1796 __sfr __at 0xBC C0M12C ; // DS80C390 specific 1797 #endif 1798 1799 #ifdef C0M13C 1800 #undef C0M13C 1801 __sfr __at 0xBD C0M13C ; // DS80C390 specific 1802 #endif 1803 1804 #ifdef C0M14C 1805 #undef C0M14C 1806 __sfr __at 0xBE C0M14C ; // DS80C390 specific 1807 #endif 1808 1809 #ifdef C0M15C 1810 #undef C0M15C 1811 __sfr __at 0xBF C0M15C ; // DS80C390 specific 1812 #endif 1813 1814 #ifdef C0RE 1815 #undef C0RE 1816 __sfr __at 0xA7 C0RE ; // DS80C390 specific 1817 #endif 1818 1819 #ifdef C0RMS0 1820 #undef C0RMS0 1821 __sfr __at 0x96 C0RMS0 ; // DS80C390 specific 1822 #endif 1823 1824 #ifdef C0RMS1 1825 #undef C0RMS1 1826 __sfr __at 0x97 C0RMS1 ; // DS80C390 specific 1827 #endif 1828 1829 #ifdef C0S 1830 #undef C0S 1831 __sfr __at 0xA4 C0S ; // DS80C390 specific 1832 // Not directly accessible bits 1833 #define ER0 0x01 1834 #define ER1 0x02 1835 #define ER2 0x04 1836 #define TXS 0x08 1837 #define RXS 0x10 1838 #define WKS 0x20 1839 #define EC96_128 0x40 1840 #define BSS 0x80 1841 #endif 1842 1843 #ifdef C0TE 1844 #undef C0TE 1845 __sfr __at 0xA6 C0TE ; // DS80C390 specific 1846 #endif 1847 1848 #ifdef C0TMA0 1849 #undef C0TMA0 1850 __sfr __at 0x9E C0TMA0 ; // DS80C390 specific 1851 #endif 1852 1853 #ifdef C0TMA1 1854 #undef C0TMA1 1855 __sfr __at 0x9F C0TMA1 ; // DS80C390 specific 1856 #endif 1857 1858 #ifdef C1C 1859 #undef C1C 1860 __sfr __at 0xE3 C1C ; // DS80C390 specific 1861 // Not directly accessible bits 1862 #define SWINT 0x01 1863 #define ERCS 0x02 1864 #define AUTOB 0x04 1865 #define CRST 0x08 1866 #define SIESTA 0x10 1867 #define PDE 0x20 1868 #define STIE 0x40 1869 #define ERIE 0x80 1870 #endif 1871 1872 #ifdef C1IR 1873 #undef C1IR 1874 __sfr __at 0xE5 C1IR ; // DS80C390 specific 1875 // Not directly accessible bits 1876 #define INTIN0 0x01 1877 #define INTIN1 0x02 1878 #define INTIN2 0x04 1879 #define INTIN3 0x08 1880 #define INTIN4 0x10 1881 #define INTIN5 0x20 1882 #define INTIN6 0x40 1883 #define INTIN7 0x80 1884 #endif 1885 1886 #ifdef C1IRE 1887 #undef C1IRE 1888 __sfr __at 0xE7 C1RE ; // DS80C390 specific 1889 #endif 1890 1891 #ifdef C1M1C 1892 #undef C1M1C 1893 __sfr __at 0xEB C1M1C ; // DS80C390 specific 1894 #endif 1895 1896 #ifdef C1M2C 1897 #undef C1M2C 1898 __sfr __at 0xEC C1M2C ; // DS80C390 specific 1899 #endif 1900 1901 #ifdef C1M3C 1902 #undef C1M3C 1903 __sfr __at 0xED C1M3C ; // DS80C390 specific 1904 #endif 1905 1906 #ifdef C1M4C 1907 #undef C1M4C 1908 __sfr __at 0xEE C1M4C ; // DS80C390 specific 1909 #endif 1910 1911 #ifdef C1M5C 1912 #undef C1M5C 1913 __sfr __at 0xEF C1M5C ; // DS80C390 specific 1914 #endif 1915 1916 #ifdef C1M6C 1917 #undef C1M6C 1918 __sfr __at 0xF3 C1M6C ; // DS80C390 specific 1919 #endif 1920 1921 #ifdef C1M7C 1922 #undef C1M7C 1923 __sfr __at 0xF4 C1M7C ; // DS80C390 specific 1924 #endif 1925 1926 #ifdef C1M8C 1927 #undef C1M8C 1928 __sfr __at 0xF5 C1M8C ; // DS80C390 specific 1929 #endif 1930 1931 #ifdef C1M9C 1932 #undef C1M9C 1933 __sfr __at 0xF6 C1M9C ; // DS80C390 specific 1934 #endif 1935 1936 #ifdef C1M10C 1937 #undef C1M10C 1938 __sfr __at 0xF7 C1M10C ; // DS80C390 specific 1939 #endif 1940 1941 #ifdef C1M11C 1942 #undef C1M11C 1943 __sfr __at 0xFB C1M11C ; // DS80C390 specific 1944 #endif 1945 1946 #ifdef C1M12C 1947 #undef C1M12C 1948 __sfr __at 0xFC C1M12C ; // DS80C390 specific 1949 #endif 1950 1951 #ifdef C1M13C 1952 #undef C1M13C 1953 __sfr __at 0xFD C1M13C ; // DS80C390 specific 1954 #endif 1955 1956 #ifdef C1M14C 1957 #undef C1M14C 1958 __sfr __at 0xFE C1M14C ; // DS80C390 specific 1959 #endif 1960 1961 #ifdef C1M15C 1962 #undef C1M15C 1963 __sfr __at 0xFF C1M15C ; // DS80C390 specific 1964 #endif 1965 1966 #ifdef C1S 1967 #undef C1S 1968 __sfr __at 0xE4 C1S ; // DS80C390 specific 1969 // Not directly accessible bits 1970 #define ER0 0x01 1971 #define ER1 0x02 1972 #define ER2 0x04 1973 #define TXS 0x08 1974 #define RXS 0x10 1975 #define WKS 0x20 1976 #define CECE 0x40 1977 #define BSS 0x80 1978 #endif 1979 1980 #ifdef C1ITE 1981 #undef C1ITE 1982 __sfr __at 0xE6 C1TE ; // DS80C390 specific 1983 #endif 1984 1985 #ifdef C1RSM0 1986 #undef C1RSM0 1987 __sfr __at 0xD6 C1RSM0 ; // DS80C390 specific 1988 #endif 1989 1990 #ifdef C1RSM1 1991 #undef C1RSM1 1992 __sfr __at 0xD7 C1RSM1 ; // DS80C390 specific 1993 #endif 1994 1995 #ifdef C1TMA0 1996 #undef C1TMA0 1997 __sfr __at 0xDE C1TMA0 ; // DS80C390 specific 1998 #endif 1999 2000 #ifdef C1TMA1 2001 #undef C1TMA1 2002 __sfr __at 0xDF C1TMA1 ; // DS80C390 specific 2003 #endif 2004 2005 #ifdef CC1 2006 #undef CC1 2007 __sfr __at 0xC2 CC1; 2008 #endif 2009 2010 #ifdef CC2 2011 #undef CC2 2012 __sfr __at 0xC4 CC2; 2013 #endif 2014 2015 #ifdef CC3 2016 #undef CC3 2017 __sfr __at 0xC6 CC3; 2018 #endif 2019 2020 #ifdef CC4 2021 #undef CC4 2022 __sfr __at 0xCE CC4; 2023 #endif 2024 2025 #ifdef CC4EN 2026 #undef CC4EN 2027 __sfr __at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific 2028 #endif 2029 2030 #ifdef CCAP0H_AT_0XFA 2031 #undef CCAP0H_AT_0XFA 2032 __sfr __at 0xFA CCAP0H ; 2033 #endif 2034 2035 #ifdef CCAP1H_AT_0XFB 2036 #undef CCAP1H_AT_0XFB 2037 __sfr __at 0xFB CCAP1H ; 2038 #endif 2039 2040 #ifdef CCAP2H_AT_0XFC 2041 #undef CCAP2H_AT_0XFC 2042 __sfr __at 0xFC CCAP2H ; 2043 #endif 2044 2045 #ifdef CCAP3H_AT_0XFD 2046 #undef CCAP3H_AT_0XFD 2047 __sfr __at 0xFD CCAP3H ; 2048 #endif 2049 2050 #ifdef CCAP4H_AT_0XFE 2051 #undef CCAP4H_AT_0XFE 2052 __sfr __at 0xFE CCAP4H ; 2053 #endif 2054 2055 #ifdef CCAP0L_AT_0XEA 2056 #undef CCAP0L_AT_0XEA 2057 __sfr __at 0xEA CCAP0L ; 2058 #endif 2059 2060 #ifdef CCAP1L_AT_0XEB 2061 #undef CCAP1L_AT_0XEB 2062 __sfr __at 0xEB CCAP1L ; 2063 #endif 2064 2065 #ifdef CCAP2L_AT_0XEC 2066 #undef CCAP2L_AT_0XEC 2067 __sfr __at 0xEC CCAP2L ; 2068 #endif 2069 2070 #ifdef CCAP3L_AT_0XED 2071 #undef CCAP3L_AT_0XED 2072 __sfr __at 0xED CCAP3L ; 2073 #endif 2074 2075 #ifdef CCAP4L_AT_0XEE 2076 #undef CCAP4L_AT_0XEE 2077 __sfr __at 0xEE CCAP4L ; 2078 #endif 2079 2080 #ifdef CCAPM0_AT_0XC2 2081 #undef CCAPM0_AT_0XC2 2082 // P89C668 specific, Capture module: 2083 __sfr __at 0xC2 CCAPM0 ; 2084 #endif 2085 2086 #ifdef CCAPM0_AT_0XDA 2087 #undef CCAPM0_AT_0XDA 2088 __sfr __at 0xDA CCAPM0 ; 2089 #define ECCF 0x01 2090 #define PWM 0x02 2091 #define TOG 0x04 2092 #define MAT 0x08 2093 #define CAPN 0x10 2094 #define CAPP 0x20 2095 #define ECOM 0x40 2096 #endif 2097 2098 #ifdef CCAPM1_AT_0XC3 2099 #undef CCAPM1_AT_0XC3 2100 __sfr __at 0xC3 CCAPM1 ; 2101 #endif 2102 2103 #ifdef CCAPM1_AT_0XDB 2104 #undef CCAPM1_AT_0XDB 2105 __sfr __at 0xDB CCAPM1 ; 2106 #endif 2107 2108 #ifdef CCAPM2_AT_0XC4 2109 #undef CCAPM2_AT_0XC4 2110 __sfr __at 0xC4 CCAPM2 ; 2111 #endif 2112 2113 #ifdef CCAPM2_AT_0XDC 2114 #undef CCAPM2_AT_0XDC 2115 __sfr __at 0x0DC CCAPM2 ; 2116 #endif 2117 2118 #ifdef CCAPM3_AT_0XC5 2119 #undef CCAPM3_AT_0XC5 2120 __sfr __at 0xC5 CCAPM3 ; 2121 #endif 2122 2123 #ifdef CCAPM3_AT_0XDD 2124 #undef CCAPM3_AT_0XDD 2125 __sfr __at 0x0DD CCAPM3 ; 2126 #endif 2127 2128 #ifdef CCAPM4_AT_0XDE 2129 #undef CCAPM4_AT_0XDE 2130 __sfr __at 0x0DE CCAPM4 ; 2131 #endif 2132 2133 #ifdef CCAPM4_AT_0XC6 2134 #undef CCAPM4_AT_0XC6 2135 __sfr __at 0xC6 CCAPM4 ; 2136 #endif 2137 2138 #ifdef CCEN 2139 #undef CCEN 2140 __sfr __at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific 2141 #endif 2142 2143 #ifdef CCH1 2144 #undef CCH1 2145 __sfr __at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific 2146 #endif 2147 2148 #ifdef CCH2 2149 #undef CCH2 2150 __sfr __at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific 2151 #endif 2152 2153 #ifdef CCH3 2154 #undef CCH3 2155 __sfr __at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific 2156 #endif 2157 2158 #ifdef CCH4 2159 #undef CCH4 2160 __sfr __at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific 2161 #endif 2162 2163 #ifdef CCL1 2164 #undef CCL1 2165 __sfr __at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific 2166 #endif 2167 2168 #ifdef CCL2 2169 #undef CCL2 2170 __sfr __at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific 2171 #endif 2172 2173 #ifdef CCL3 2174 #undef CCL3 2175 __sfr __at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific 2176 #endif 2177 2178 #ifdef CCL4 2179 #undef CCL4 2180 __sfr __at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific 2181 #endif 2182 2183 #ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 2184 #undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 2185 __sfr __at 0xD8 CCON ; // T89C51RD2 specific register 2186 // Bit registers 2187 __sbit __at 0xD8 CCF0 ; 2188 __sbit __at 0xD9 CCF1 ; 2189 __sbit __at 0xDA CCF2 ; 2190 __sbit __at 0xDB CCF3 ; 2191 __sbit __at 0xDC CCF4 ; 2192 __sbit __at 0xDE CR ; 2193 __sbit __at 0xDF CF ; 2194 #endif 2195 2196 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 2197 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 2198 // P89C668 specific, PCA Counter control: 2199 __sfr __at 0xC0 CCON ; 2200 // Bit registers 2201 __sbit __at 0xC0 CCF0 ; 2202 __sbit __at 0xC1 CCF1 ; 2203 __sbit __at 0xC2 CCF2 ; 2204 __sbit __at 0xC3 CCF3 ; 2205 __sbit __at 0xC4 CCF4 ; 2206 //__sbit __at 0xC5 - 2207 __sbit __at 0xC6 CR ; 2208 __sbit __at 0xC7 CF ; 2209 #endif 2210 2211 #ifdef CCR 2212 #undef CCR 2213 __sfr __at 0xCA CCR; 2214 #endif 2215 2216 #ifdef CH_AT_0XF9 2217 #undef CH_AT_0XF9 2218 __sfr __at 0xF9 CH ; 2219 #endif 2220 2221 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 2222 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 2223 // P89C668 specific, PCA Counter mode: 2224 __sfr __at 0xC1 CMOD ; 2225 // not bit addressable: 2226 #define CIDL 0x80 2227 #define WDTE 0x40 2228 #define CPS1 0x04 2229 #define CPS0 0x02 2230 #define ECF 0x01 2231 #endif 2232 2233 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 2234 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 2235 __sfr __at 0x8E CKCON ; // DS80C320 & DS80C390 specific 2236 // Not directly accessible Bits. 2237 #define MD0 0x01 2238 #define MD1 0x02 2239 #define MD2 0x04 2240 #define T0M 0x08 2241 #define T1M 0x10 2242 #define T2M 0x20 2243 #define WD0 0x40 2244 #define WD1 0x80 2245 #endif 2246 2247 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x 2248 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x 2249 __sfr __at 0x8F CKCON ; 2250 #define X2 0x01 2251 #define T0X2 0x02 2252 #define T1X2 0x04 2253 #define T2X2 0x08 2254 #define SiX2 0x10 2255 #define PcaX2 0x20 2256 #define WdX2 0x40 2257 #endif 2258 2259 #ifdef CKMOD 2260 #undef CKMOD 2261 __sfr __at 0x96 CKMOD ; // DS89C420 specific 2262 // Not directly accessible Bits. 2263 #define T0MH 0x08 2264 #define T1MH 0x10 2265 #define T2MH 0x20 2266 #endif 2267 2268 #ifdef CL_AT_0XE9 2269 #undef CL_AT_0XE9 2270 __sfr __at 0xE9 CL ; 2271 #endif 2272 2273 #ifdef CLRMSK 2274 #undef CLRMSK 2275 __sfr __at 0xA6 CLRMSK; 2276 #endif 2277 2278 #ifdef CMEN 2279 #undef CMEN 2280 __sfr __at 0xF6 CMEN ; // compare enable register SAB80517 specific 2281 #endif 2282 2283 #ifdef CMH0 2284 #undef CMH0 2285 __sfr __at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific 2286 #endif 2287 2288 #ifdef CMH1 2289 #undef CMH1 2290 __sfr __at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific 2291 #endif 2292 2293 #ifdef CMH2 2294 #undef CMH2 2295 __sfr __at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific 2296 #endif 2297 2298 #ifdef CMH3 2299 #undef CMH3 2300 __sfr __at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific 2301 #endif 2302 2303 #ifdef CMH4 2304 #undef CMH4 2305 __sfr __at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific 2306 #endif 2307 2308 #ifdef CMH5 2309 #undef CMH5 2310 __sfr __at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific 2311 #endif 2312 2313 #ifdef CMH6 2314 #undef CMH6 2315 __sfr __at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific 2316 #endif 2317 2318 #ifdef CMH7 2319 #undef CMH7 2320 __sfr __at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific 2321 #endif 2322 2323 #ifdef CMH0_AT_0XC9 2324 #undef CMH0_AT_0XC9 2325 __sfr __at 0xC9 CMH0 ; // Compare high 0, P80C552 specific 2326 #endif 2327 2328 #ifdef CMH1_AT_0XCA 2329 #undef CMH1_AT_0XCA 2330 __sfr __at 0xCA CMH1 ; // Compare high 1, P80C552 specific 2331 #endif 2332 2333 #ifdef CMH2_AT_0XCB 2334 #undef CMH2_AT_0XCB 2335 __sfr __at 0xCB CMH2 ; // Compare high 2, P80C552 specific 2336 #endif 2337 2338 #ifdef CML0 2339 #undef CML0 2340 __sfr __at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific 2341 #endif 2342 2343 #ifdef CML1 2344 #undef CML1 2345 __sfr __at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific 2346 #endif 2347 2348 #ifdef CML2 2349 #undef CML2 2350 __sfr __at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific 2351 #endif 2352 2353 #ifdef CML3 2354 #undef CML3 2355 __sfr __at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific 2356 #endif 2357 2358 #ifdef CML4 2359 #undef CML4 2360 __sfr __at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific 2361 #endif 2362 2363 #ifdef CML5 2364 #undef CML5 2365 __sfr __at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific 2366 #endif 2367 2368 #ifdef CML6 2369 #undef CML6 2370 __sfr __at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific 2371 #endif 2372 2373 #ifdef CML7 2374 #undef CML7 2375 __sfr __at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific 2376 #endif 2377 2378 #ifdef CML0_AT_0XA9 2379 #undef CML0_AT_0XA9 2380 __sfr __at 0xA9 CML0 ; // Compare low 0, P80C552 specific 2381 #endif 2382 2383 #ifdef CML1_AT_0XAA 2384 #undef CML1_AT_0XAA 2385 __sfr __at 0xAA CML1 ; // Compare low 1, P80C552 specific 2386 #endif 2387 2388 #ifdef CML2_AT_0XAB 2389 #undef CML2_AT_0XAB 2390 __sfr __at 0xAB CML2 ; // Compare low 2, P80C552 specific 2391 #endif 2392 2393 #ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 2394 #undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF 2395 __sfr __at 0xD9 CMOD ; 2396 #define ECF 0x01 2397 #define CPS0 0x02 2398 #define CPS1 0x04 2399 #define WDTE 0x40 2400 #define CIDL 0x80 2401 #endif 2402 2403 #ifdef CMSEL 2404 #undef CMSEL 2405 __sfr __at 0xF7 CMSEL ; // compare input select SAB80517 2406 #endif 2407 2408 #ifdef COMCLRH 2409 #undef COMCLRH 2410 __sfr __at 0xA4 COMCLRH; 2411 #endif 2412 2413 #ifdef COMCLRL 2414 #undef COMCLRL 2415 __sfr __at 0xA3 COMCLRL; 2416 #endif 2417 2418 #ifdef COMSETH 2419 #undef COMSETH 2420 __sfr __at 0xA2 COMSETH; 2421 #endif 2422 2423 #ifdef COMSETL 2424 #undef COMSETL 2425 __sfr __at 0xA1 COMSETL; 2426 #endif 2427 2428 #ifdef COR 2429 #undef COR 2430 __sfr __at 0xCE COR ; // Dallas DS80C390 specific 2431 #define CLKOE 0x01 2432 #define COD0 0x02 2433 #define COD1 0x04 2434 #define C0BPR6 0x08 2435 #define C0BPR7 0x10 2436 #define C1BPR6 0x20 2437 #define C1BPR7 0x40 2438 #define IRDACK 0x80 2439 #endif 2440 2441 #ifdef CRC 2442 #undef CRC 2443 __sfr __at 0xC1 CRC ; // Dallas DS5001 specific 2444 #define CRC_ 0x01 2445 #define MDM 0x02 2446 #define RNGE0 0x10 2447 #define RNGE1 0x20 2448 #define RNGE2 0x40 2449 #define RNGE3 0x80 2450 #endif 2451 2452 #ifdef CRCH 2453 #undef CRCH 2454 __sfr __at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific 2455 #endif 2456 2457 #ifdef CRCHIGH 2458 #undef CRCHIGH 2459 __sfr __at 0xC3 CRCHIGH ; // DS5001 specific 2460 #endif 2461 2462 #ifdef CRCL 2463 #undef CRCL 2464 __sfr __at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific 2465 #endif 2466 2467 #ifdef CRCLOW 2468 #undef CRCLOW 2469 __sfr __at 0xC2 CRCLOW ; // DS5001 specific 2470 #endif 2471 2472 #ifdef CT1COM 2473 #undef CT1COM 2474 __sfr __at 0xBC CT1COM; 2475 #endif 2476 2477 #ifdef CTCOM_AT_0XE1 2478 #undef CTCOM_AT_0XE1 2479 __sfr __at 0xE1 CTCON ; // com.timer control register SAB80517 2480 #endif 2481 2482 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 2483 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 2484 __sfr __at 0xEB CTCON ; // Capture control, P80C552 specific 2485 // Not directly accessible Bits. 2486 #define CTP0 0x01 2487 #define CTN0 0x02 2488 #define CTP1 0x04 2489 #define CTN1 0x08 2490 #define CTP2 0x10 2491 #define CTN2 0x20 2492 #define CTP3 0x40 2493 #define CTN3 0x80 2494 #endif 2495 2496 #ifdef CTH0_AT_0XCC 2497 #undef CTH0_AT_0XCC 2498 __sfr __at 0xCC CTH0 ; // Capture high 0, P80C552 specific 2499 #endif 2500 2501 #ifdef CTH1_AT_0XCD 2502 #undef CTH1_AT_0XCD 2503 __sfr __at 0xCD CTH1 ; // Capture high 1, P80C552 specific 2504 #endif 2505 2506 #ifdef CTH2_AT_0XCE 2507 #undef CTH2_AT_0XCE 2508 __sfr __at 0xCE CTH2 ; // Capture high 2, P80C552 specific 2509 #endif 2510 2511 #ifdef CTH3_AT_0XCF 2512 #undef CTH3_AT_0XCF 2513 __sfr __at 0xCF CTH3 ; // Capture high 3, P80C552 specific 2514 #endif 2515 2516 #ifdef CTL0_AT_0XAC 2517 #undef CTL0_AT_0XAC 2518 __sfr __at 0xAC CTL0 ; // Capture low 0, P80C552 specific 2519 #endif 2520 2521 #ifdef CTL1_AT_0XAD 2522 #undef CTL1_AT_0XAD 2523 __sfr __at 0xAD CTL1 ; // Capture low 1, P80C552 specific 2524 #endif 2525 2526 #ifdef CTL2_AT_0XAE 2527 #undef CTL2_AT_0XAE 2528 __sfr __at 0xAE CTL2 ; // Capture low 2, P80C552 specific 2529 #endif 2530 2531 #ifdef CTL3_AT_0XAF 2532 #undef CTL3_AT_0XAF 2533 __sfr __at 0xAF CTL3 ; // Capture low 3, P80C552 specific 2534 #endif 2535 2536 #ifdef CTRELH 2537 #undef CTRELH 2538 __sfr __at 0xDF CTRELH ; // com.timer rel register high byte SAB80517 2539 #endif 2540 2541 #ifdef CTRELL 2542 #undef CTRELL 2543 __sfr __at 0xDE CTRELL ; // com.timer rel register low byte SAB80517 2544 #endif 2545 2546 #ifdef DAPR__SAB80515 2547 #undef DAPR__SAB80515 2548 __sfr __at 0xDA DAPR ; // D/A-converter program register SAB80515 specific 2549 #endif 2550 2551 #ifdef DAPR__SAB80517 2552 #undef DAPR__SAB80517 2553 __sfr __at 0xDA DAPR ; // D/A-converter program register SAB80517 specific 2554 #endif 2555 2556 #ifdef DPH 2557 #undef DPH 2558 __sfr __at 0x83 DPH ; 2559 __sfr __at 0x83 DP0H ; // Alternate name for AT89S53 2560 #endif 2561 2562 #ifdef DPH1 2563 #undef DPH1 2564 __sfr __at 0x85 DPH1 ; // DS80C320 specific 2565 __sfr __at 0x85 DP1H ; // Alternate name for AT89S53 2566 #endif 2567 2568 #ifdef DPL 2569 #undef DPL 2570 __sfr __at 0x82 DPL ; // Alternate name for AT89S53 2571 __sfr __at 0x82 DP0L ; 2572 #endif 2573 2574 #ifdef DPL1 2575 #undef DPL1 2576 __sfr __at 0x84 DPL1 ; // DS80C320 specific 2577 __sfr __at 0x84 DP1L ; // Alternate name for AT89S53 2578 #endif 2579 2580 #ifdef DPS__x__x__x__x__x__x__x__SEL 2581 #undef DPS__x__x__x__x__x__x__x__SEL 2582 __sfr __at 0x86 DPS ; 2583 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific 2584 #define SEL 0x01 2585 #endif 2586 2587 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL 2588 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL 2589 __sfr __at 0x86 DPS ; 2590 // Not directly accessible DPS Bit. DS89C390 specific 2591 #define SEL 0x01 2592 #define TSL 0x20 2593 #define ID0 0x40 2594 #define ID1 0x80 2595 #endif 2596 2597 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL 2598 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL 2599 __sfr __at 0x86 DPS ; 2600 // Not directly accessible DPS Bit. DS89C420 specific 2601 #define SEL 0x01 2602 #define AID 0x10 2603 #define TSL 0x20 2604 #define ID0 0x40 2605 #define ID1 0x80 2606 #endif 2607 2608 #ifdef DPSEL 2609 #undef DPSEL 2610 __sfr __at 0x92 DPSEL ; // data pointer select register SAB80517 2611 #endif 2612 2613 #ifdef DPX 2614 #undef DPX 2615 __sfr __at 0x93 DPX1 ; // DS80C390 specific 2616 #endif 2617 2618 #ifdef DPX1 2619 #undef DPX1 2620 __sfr __at 0x95 DPX1 ; // DS80C390 specific 2621 #endif 2622 2623 #ifdef EECON 2624 #undef EECON 2625 __sfr __at 0xD2 EECON ; 2626 #define EEBUSY 0x01 2627 #define EEE 0x02 2628 #define EEPL0 0x10 2629 #define EEPL1 0x20 2630 #define EEPL2 0x40 2631 #define EEPL3 0x80 2632 #define EEPL 0xF0 2633 #endif 2634 2635 #ifdef EETIM 2636 #undef EETIM 2637 __sfr __at 0xD3 EETIM ; 2638 #endif 2639 2640 #ifdef EICC1 2641 #undef EICC1 2642 __sfr __at 0xBF EICC1; 2643 #endif 2644 2645 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 2646 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 2647 __sfr __at 0xE8 EIE ; 2648 // Bit registers DS80C320 specific 2649 __sbit __at 0xE8 EX2 ; 2650 __sbit __at 0xE9 EX3 ; 2651 __sbit __at 0xEA EX4 ; 2652 __sbit __at 0xEB EX5 ; 2653 __sbit __at 0xEC EWDI ; 2654 #endif 2655 2656 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 2657 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 2658 __sfr __at 0xE8 EIE ; 2659 // Bit registers DS80C390 specific 2660 __sbit __at 0xE8 EX2 ; 2661 __sbit __at 0xE9 EX3 ; 2662 __sbit __at 0xEA EX4 ; 2663 __sbit __at 0xEB EX5 ; 2664 __sbit __at 0xEC EWDI ; 2665 __sbit __at 0xED C1IE ; 2666 __sbit __at 0xEE C0IE ; 2667 __sbit __at 0xEF CANBIE ; 2668 #endif 2669 2670 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 2671 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 2672 __sfr __at 0xF8 EIP ; 2673 // Bit registers DS80C320 specific 2674 __sbit __at 0xF8 PX2 ; 2675 __sbit __at 0xF9 PX3 ; 2676 __sbit __at 0xFA PX4 ; 2677 __sbit __at 0xFB PX5 ; 2678 __sbit __at 0xFC PWDI ; 2679 #endif 2680 2681 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 2682 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 2683 __sfr __at 0xF8 EIP ; 2684 // Bit registers DS80C320 specific 2685 __sbit __at 0xF8 PX2 ; 2686 __sbit __at 0xF9 PX3 ; 2687 __sbit __at 0xFA PX4 ; 2688 __sbit __at 0xFB PX5 ; 2689 __sbit __at 0xFC PWDI ; 2690 __sbit __at 0xFD C1IP ; 2691 __sbit __at 0xFE C0IP ; 2692 __sbit __at 0xFF CANBIP ; 2693 #endif 2694 2695 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 2696 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 2697 __sfr __at 0xF8 EIP0 ; 2698 // Bit registers DS89C420 specific 2699 __sbit __at 0xF8 LPX2 ; 2700 __sbit __at 0xF9 LPX3 ; 2701 __sbit __at 0xFA LPX4 ; 2702 __sbit __at 0xFB LPX5 ; 2703 __sbit __at 0xFC LPWDI ; 2704 #endif 2705 2706 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 2707 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 2708 __sfr __at 0xF1 EIP1 ; 2709 // Not directly accessible Bits DS89C420 specific 2710 #define MPX2 0x01 2711 #define MPX3 0x02 2712 #define MPX4 0x04 2713 #define MPX5 0x08 2714 #define MPWDI 0x10 2715 #endif 2716 2717 #ifdef ESP 2718 #undef ESP 2719 __sfr __at 0x9B ESP ; 2720 // Not directly accessible Bits DS80C390 specific 2721 #define ESP_0 0x01 2722 #define ESP_1 0x02 2723 #endif 2724 2725 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS 2726 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS 2727 __sfr __at 0x91 EXIF ; 2728 // Not directly accessible EXIF Bits DS80C320 specific 2729 #define BGS 0x01 2730 #define RGSL 0x02 2731 #define RGMD 0x04 2732 #define IE2 0x10 2733 #define IE3 0x20 2734 #define IE4 0x40 2735 #define IE5 0x80 2736 #endif 2737 2738 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS 2739 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS 2740 __sfr __at 0x91 EXIF ; 2741 // Not directly accessible EXIF Bits DS87C520 specific 2742 #define BGS 0x01 2743 #define RGSL 0x02 2744 #define RGMD 0x04 2745 #define XT_RG 0x08 2746 #define IE2 0x10 2747 #define IE3 0x20 2748 #define IE4 0x40 2749 #define IE5 0x80 2750 #endif 2751 2752 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS 2753 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS 2754 __sfr __at 0x91 EXIF ; 2755 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific 2756 #define BGS 0x01 2757 #define RGSL 0x02 2758 #define RGMD 0x04 2759 #define CKRY 0x08 2760 #define IE2 0x10 2761 #define IE3 0x20 2762 #define IE4 0x40 2763 #define IE5 0x80 2764 #endif 2765 2766 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 2767 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 2768 __sfr __at 0xD5 FCNTL ; 2769 // Not directly accessible DS89C420 specific 2770 #define FC0 0x01 2771 #define FC1 0x02 2772 #define FC2 0x04 2773 #define FC3 0x08 2774 #define FERR 0x40 2775 #define FBUSY 0x80 2776 #endif 2777 2778 #ifdef FCON 2779 #undef FCON 2780 __sfr __at 0xD1 FCON ; 2781 #define FBUSY 0x01 2782 #define FMOD0 0x02 2783 #define FMOD1 0x04 2784 #define FPS 0x08 2785 #define FPL0 0x10 2786 #define FPL1 0x20 2787 #define FPL2 0x40 2788 #define FPL3 0x80 2789 #define FPL 0xF0 2790 #endif 2791 2792 #ifdef FDATA 2793 #undef FDATA 2794 __sfr __at 0xD6 FDATA ; 2795 #endif 2796 2797 #ifdef FMODE 2798 #undef FMODE 2799 __sfr __at 0xB3 FMODE; 2800 #endif 2801 2802 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0 2803 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0 2804 __sfr __at 0xA8 IE ; 2805 // Bit registers 2806 __sbit __at 0xA8 EX0 ; 2807 __sbit __at 0xA9 ET0 ; 2808 __sbit __at 0xAA EX1 ; 2809 __sbit __at 0xAB ET1 ; 2810 __sbit __at 0xAC ES ; 2811 __sbit __at 0xAF EA ; 2812 #endif 2813 2814 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 2815 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 2816 __sfr __at 0xA8 IE ; 2817 // Bit registers 2818 __sbit __at 0xA8 EX0 ; 2819 __sbit __at 0xA9 ET0 ; 2820 __sbit __at 0xAA EX1 ; 2821 __sbit __at 0xAB ET1 ; 2822 __sbit __at 0xAC ES ; 2823 __sbit __at 0xAD ET2 ; // Enable timer2 interrupt 2824 __sbit __at 0xAF EA ; 2825 #endif // IE 2826 2827 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 2828 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 2829 __sfr __at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific 2830 __sfr __at 0xA8 IEN0 ; // alternate name 2831 // Bit registers 2832 __sbit __at 0xA8 EX0 ; 2833 __sbit __at 0xA9 ET0 ; 2834 __sbit __at 0xAA EX1 ; 2835 __sbit __at 0xAB ET1 ; 2836 __sbit __at 0xAC ES0 ; 2837 __sbit __at 0xAD ES1 ; 2838 __sbit __at 0xAE EAD ; 2839 __sbit __at 0xAF EEA ; 2840 #endif 2841 2842 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 2843 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 2844 __sfr __at 0xA8 IE ; 2845 __sbit __at 0xA8 EX0 ; 2846 __sbit __at 0xA9 ET0 ; 2847 __sbit __at 0xAA EX1 ; 2848 __sbit __at 0xAB ET1 ; 2849 __sbit __at 0xAC ES ; 2850 __sbit __at 0xAD ET2 ; 2851 __sbit __at 0xAE EC ; 2852 __sbit __at 0xAF EA ; 2853 #endif 2854 2855 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 2856 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 2857 __sfr __at 0xA8 IE ; 2858 // Bit registers 2859 __sbit __at 0xA8 EX0 ; 2860 __sbit __at 0xA9 ET0 ; 2861 __sbit __at 0xAA EX1 ; 2862 __sbit __at 0xAB ET1 ; 2863 __sbit __at 0xAC ES ; 2864 __sbit __at 0xAC ES0 ; // Alternate name 2865 __sbit __at 0xAD ET2 ; // Enable timer2 interrupt 2866 __sbit __at 0xAE ES1 ; 2867 __sbit __at 0xAF EA ; 2868 #endif // IE 2869 2870 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 2871 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 2872 __sfr __at 0xA8 IE ; 2873 __sfr __at 0xA8 IEN0 ; // Alternate name 2874 // Bit registers for the SAB80515 and compatible IE 2875 __sbit __at 0xA8 EX0 ; 2876 __sbit __at 0xA9 ET0 ; 2877 __sbit __at 0xAA EX1 ; 2878 __sbit __at 0xAB ET1 ; 2879 __sbit __at 0xAC ES ; 2880 __sbit __at 0xAC ES0 ; 2881 __sbit __at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific 2882 __sbit __at 0xAE WDT ; // watchdog timer reset - SAB80515 specific 2883 __sbit __at 0xAF EA ; 2884 __sbit __at 0xAF EAL ; // EA as called by Infineon / Siemens 2885 #endif 2886 2887 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 2888 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 2889 // P89C668 specific 2890 __sfr __at 0xA8 IEN0 ; 2891 // Bit registers 2892 __sbit __at 0xA8 EX0 ; 2893 __sbit __at 0xA9 ET0 ; 2894 __sbit __at 0xAA EX1 ; 2895 __sbit __at 0xAB ET1 ; 2896 __sbit __at 0xAC ES0 ; 2897 __sbit __at 0xAD ES1 ; 2898 __sbit __at 0xAE EC ; 2899 __sbit __at 0xAF EA ; 2900 #endif 2901 2902 #ifdef IEN1__x__x__x__x__x__x__x__ET2 2903 #undef IEN1__x__x__x__x__x__x__x__ET2 2904 // P89C668 specific bit registers 2905 __sfr __at 0xE8 IEN1 ; 2906 // Bit registers 2907 __sbit __at 0xE8 ET2 ; 2908 #endif 2909 2910 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 2911 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 2912 __sfr __at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific 2913 // Bit registers 2914 __sbit __at 0xE8 ECT0 ; 2915 __sbit __at 0xE9 ECT1 ; 2916 __sbit __at 0xEA ECT2 ; 2917 __sbit __at 0xEB ECT3 ; 2918 __sbit __at 0xEC ECM0 ; 2919 __sbit __at 0xED ECM1 ; 2920 __sbit __at 0xEE ECM2 ; 2921 __sbit __at 0xEF ET2 ; 2922 #endif 2923 2924 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 2925 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC 2926 __sfr __at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific 2927 // Bit registers 2928 __sbit __at 0xB8 EADC ; // A/D converter interrupt enable 2929 __sbit __at 0xB9 EX2 ; 2930 __sbit __at 0xBA EX3 ; 2931 __sbit __at 0xBB EX4 ; 2932 __sbit __at 0xBC EX5 ; 2933 __sbit __at 0xBD EX6 ; 2934 __sbit __at 0xBE SWDT ; // watchdog timer start/reset 2935 __sbit __at 0xBF EXEN2 ; // timer2 external reload interrupt enable 2936 #endif 2937 2938 #ifdef IEN2__SAB80517 2939 #undef IEN2__SAB80517 2940 __sfr __at 0x9A IEN2 ; // interrupt enable register 2 SAB80517 2941 #endif 2942 2943 #ifdef IEN3 2944 #undef IEN3 2945 __sfr __at 0xBE IEN3; 2946 #endif 2947 2948 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0 2949 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0 2950 __sfr __at 0xB8 IP ; 2951 // Bit registers 2952 __sbit __at 0xB8 PX0 ; 2953 __sbit __at 0xB9 PT0 ; 2954 __sbit __at 0xBA PX1 ; 2955 __sbit __at 0xBB PT1 ; 2956 __sbit __at 0xBC PS ; 2957 #endif 2958 2959 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 2960 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 2961 __sfr __at 0xB8 IP ; 2962 // Bit registers 2963 __sbit __at 0xB8 PX0 ; 2964 __sbit __at 0xB9 PT0 ; 2965 __sbit __at 0xBA PX1 ; 2966 __sbit __at 0xBB PT1 ; 2967 __sbit __at 0xBC PS ; 2968 __sbit __at 0xBC PS0 ; // alternate name 2969 __sbit __at 0xBD PT2 ; 2970 #endif 2971 2972 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 2973 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 2974 __sfr __at 0xB8 IP ; // Interrupt priority 0, P80C552 specific 2975 __sfr __at 0xB8 IP0 ; // alternate name 2976 // Bit registers 2977 __sbit __at 0xB8 PX0 ; 2978 __sbit __at 0xB9 PT0 ; 2979 __sbit __at 0xBA PX1 ; 2980 __sbit __at 0xBB PT1 ; 2981 __sbit __at 0xBC PS0 ; 2982 __sbit __at 0xBD PS1 ; 2983 __sbit __at 0xBE PAD ; 2984 #endif 2985 2986 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 2987 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 2988 __sfr __at 0xB8 IP ; 2989 // Bit registers 2990 __sbit __at 0xB8 PX0 ; 2991 __sbit __at 0xB9 PT0 ; 2992 __sbit __at 0xBA PX1 ; 2993 __sbit __at 0xBB PT1 ; 2994 __sbit __at 0xBC PS ; 2995 __sbit __at 0xBD PT2 ; 2996 __sbit __at 0xBE PPC ; 2997 #endif 2998 2999 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 3000 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 3001 __sfr __at 0xB8 IP ; 3002 // Bit registers 3003 __sbit __at 0xB8 PX0 ; 3004 __sbit __at 0xB9 PT0 ; 3005 __sbit __at 0xBA PX1 ; 3006 __sbit __at 0xBB PT1 ; 3007 __sbit __at 0xBC PS ; 3008 __sbit __at 0xBD PT2 ; 3009 __sbit __at 0xBE PS1 ; 3010 #endif 3011 3012 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 3013 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 3014 // P89C668 specific: 3015 __sfr __at 0xB8 IP ; 3016 // Bit registers 3017 __sbit __at 0xB8 PX0 ; 3018 __sbit __at 0xB9 PT0 ; 3019 __sbit __at 0xBA PX1 ; 3020 __sbit __at 0xBB PT1 ; 3021 __sbit __at 0xBC PS0 ; 3022 __sbit __at 0xBD PS1 ; 3023 __sbit __at 0xBE PPC ; 3024 __sbit __at 0xBF PT2 ; 3025 #endif 3026 3027 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 3028 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 3029 __sfr __at 0xB8 IP ; 3030 // Bit registers 3031 __sbit __at 0xB8 PX0 ; 3032 __sbit __at 0xB9 PT0 ; 3033 __sbit __at 0xBA PX1 ; 3034 __sbit __at 0xBB PT1 ; 3035 __sbit __at 0xBC PS ; 3036 __sbit __at 0xBF RWT ; 3037 #endif 3038 3039 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 3040 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 3041 __sfr __at 0xA9 IP0 ; // interrupt priority register SAB80515 specific 3042 // Not directly accessible IP0 bits 3043 #define IP0_0 0x01 3044 #define IP0_1 0x02 3045 #define IP0_2 0x04 3046 #define IP0_3 0x08 3047 #define IP0_4 0x10 3048 #define IP0_5 0x20 3049 #define WDTS 0x40 3050 #endif 3051 3052 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 3053 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 3054 __sfr __at 0xB8 IP0 ; // interrupt priority register DS89C420 specific 3055 // Bit registers 3056 __sbit __at 0xB8 LPX0 ; 3057 __sbit __at 0xB9 LPT0 ; 3058 __sbit __at 0xBA LPX1 ; 3059 __sbit __at 0xBB LPT1 ; 3060 __sbit __at 0xBC LPS0 ; 3061 __sbit __at 0xBD LPT2 ; 3062 __sbit __at 0xBE LPS1 ; 3063 #endif 3064 3065 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 3066 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 3067 __sfr __at 0xB9 IP1 ; // interrupt priority register SAB80515 specific 3068 // Not directly accessible IP1 bits 3069 #define IP1_0 0x01 3070 #define IP1_1 0x02 3071 #define IP1_2 0x04 3072 #define IP1_3 0x08 3073 #define IP1_4 0x10 3074 #define IP1_5 0x20 3075 #endif 3076 3077 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 3078 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 3079 __sfr __at 0xB1 IP1 ; // interrupt priority register DS89C420 specific 3080 // Not directly accessible IP1 bits 3081 #define MPX0 0x01 3082 #define MPT0 0x02 3083 #define MPX1 0x04 3084 #define MPT1 0x08 3085 #define MPS0 0x10 3086 #define MPT2 0x20 3087 #define MPS1 0x40 3088 #endif 3089 3090 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 3091 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 3092 __sfr __at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific 3093 // Bit registers 3094 __sbit __at 0xF8 PCT0 ; 3095 __sbit __at 0xF9 PCT1 ; 3096 __sbit __at 0xFA PCT2 ; 3097 __sbit __at 0xFB PCT3 ; 3098 __sbit __at 0xFC PCM0 ; 3099 __sbit __at 0xFD PCM1 ; 3100 __sbit __at 0xFE PCM2 ; 3101 __sbit __at 0xFF PT2 ; 3102 #endif 3103 3104 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H 3105 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H 3106 __sfr __at 0xB7 IPH ; 3107 #define PX0H 0x01 3108 #define PT0H 0x02 3109 #define PX1H 0x04 3110 #define PT1H 0x08 3111 #define PSH 0x10 3112 #define PT2H 0x20 3113 #define PPCH 0x40 3114 #endif 3115 3116 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H 3117 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H 3118 // P89C668 specific: 3119 __sfr __at 0xB7 IPH ; 3120 // not bit addressable: 3121 #define PX0H 0x01 3122 #define PT0H 0x02 3123 #define PX1H 0x04 3124 #define PT1H 0x08 3125 #define PS0H 0x10 3126 #define PS1H 0x20 3127 #define PPCH 0x40 3128 #define PT2H 0x80 3129 #endif 3130 3131 #ifdef IRCON 3132 #undef IRCON 3133 __sfr __at 0xC0 IRCON ; // interrupt control register - SAB80515 specific 3134 // Bit registers 3135 __sbit __at 0xC0 IADC ; // A/D converter irq flag 3136 __sbit __at 0xC1 IEX2 ; // external interrupt edge detect flag 3137 __sbit __at 0xC2 IEX3 ; 3138 __sbit __at 0xC3 IEX4 ; 3139 __sbit __at 0xC4 IEX5 ; 3140 __sbit __at 0xC5 IEX6 ; 3141 __sbit __at 0xC6 TF2 ; // timer 2 owerflow flag 3142 __sbit __at 0xC7 EXF2 ; // timer2 reload flag 3143 #endif 3144 3145 #ifdef IRCON0 3146 #undef IRCON0 3147 __sfr __at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific 3148 // Bit registers 3149 __sbit __at 0xC0 IADC ; // A/D converter irq flag 3150 __sbit __at 0xC1 IEX2 ; // external interrupt edge detect flag 3151 __sbit __at 0xC2 IEX3 ; 3152 __sbit __at 0xC3 IEX4 ; 3153 __sbit __at 0xC4 IEX5 ; 3154 __sbit __at 0xC5 IEX6 ; 3155 __sbit __at 0xC6 TF2 ; // timer 2 owerflow flag 3156 __sbit __at 0xC7 EXF2 ; // timer2 reload flag 3157 #endif 3158 3159 #ifdef IRCON1 3160 #undef IRCON1 3161 __sfr __at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific 3162 #endif 3163 3164 #ifdef IRCON2 3165 #undef IRCON2 3166 __sfr __at 0xBF IRCON2; 3167 #endif 3168 3169 #ifdef MA 3170 #undef MA 3171 __sfr __at 0xD3 MA ; // DS80C390 3172 #endif 3173 3174 #ifdef MB 3175 #undef MB 3176 __sfr __at 0xD4 MB ; // DS80C390 3177 #endif 3178 3179 #ifdef MC 3180 #undef MC 3181 __sfr __at 0xD5 MC ; // DS80C390 3182 #endif 3183 3184 #ifdef MCNT0 3185 #undef MCNT0 3186 __sfr __at 0xD1 MCNT0 ; // DS80C390 3187 #define MAS0 0x01 3188 #define MAS1 0x02 3189 #define MAS2 0x04 3190 #define MAS3 0x08 3191 #define MAS4 0x10 3192 #define SCB 0x20 3193 #define CSE 0x40 3194 #define LSHIFT 0x80 3195 #endif 3196 3197 #ifdef MCNT1 3198 #undef MCNT1 3199 __sfr __at 0xD2 MCNT1 ; // DS80C390 3200 #define CLM 0x10 3201 #define MOF 0x40 3202 #define MST 0x80 3203 #endif 3204 3205 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 3206 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 3207 __sfr __at 0xC6 MCON ; // DS80C390 3208 #define PDCE0 0x01 3209 #define PDCE1 0x02 3210 #define PDCE2 0x04 3211 #define PDCE3 0x08 3212 #define CMA 0x20 3213 #define IDM0 0x40 3214 #define IDM1 0x80 3215 #endif 3216 3217 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL 3218 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL 3219 __sfr __at 0xC6 MCON ; // DS5000 3220 #define SL 0x01 3221 #define PAA 0x02 3222 #define ECE2 0x04 3223 #define RA32_8 0x08 3224 #define PA0 0x10 3225 #define PA1 0x20 3226 #define PA2 0x40 3227 #define PA3 0x80 3228 #endif 3229 3230 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL 3231 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL 3232 __sfr __at 0xC6 MCON ; // DS5001 3233 #define SL 0x01 3234 #define PM 0x02 3235 #define PES 0x04 3236 #define RG1 0x08 3237 #define PA0 0x10 3238 #define PA1 0x20 3239 #define PA2 0x40 3240 #define PA3 0x80 3241 #endif 3242 3243 #ifdef MD0 3244 #undef MD0 3245 __sfr __at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517 3246 #endif 3247 3248 #ifdef MD1 3249 #undef MD1 3250 __sfr __at 0xEA MD1 ; // MUL / DIV register 1 SAB80517 3251 #endif 3252 3253 #ifdef MD2 3254 #undef MD2 3255 __sfr __at 0xEB MD2 ; // MUL / DIV register 2 SAB80517 3256 #endif 3257 3258 #ifdef MD3 3259 #undef MD3 3260 __sfr __at 0xEC MD3 ; // MUL / DIV register 3 SAB80517 3261 #endif 3262 3263 #ifdef MD4 3264 #undef MD4 3265 __sfr __at 0xED MD4 ; // MUL / DIV register 4 SAB80517 3266 #endif 3267 3268 #ifdef MD5 3269 #undef MD5 3270 __sfr __at 0xEE MD5 ; // MUL / DIV register 5 SAB80517 3271 #endif 3272 3273 #ifdef MXAX 3274 #undef MXAX 3275 __sfr __at 0xEA MXAX ; // Dallas DS80C390 3276 #endif 3277 3278 #ifdef P0 3279 #undef P0 3280 __sfr __at 0x80 P0 ; 3281 // Bit Registers 3282 __sbit __at 0x80 P0_0 ; 3283 __sbit __at 0x81 P0_1 ; 3284 __sbit __at 0x82 P0_2 ; 3285 __sbit __at 0x83 P0_3 ; 3286 __sbit __at 0x84 P0_4 ; 3287 __sbit __at 0x85 P0_5 ; 3288 __sbit __at 0x86 P0_6 ; 3289 __sbit __at 0x87 P0_7 ; 3290 #endif 3291 3292 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 3293 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 3294 // P89C668 alternate names for bits in P0 3295 __sbit __at 0x80 AD0 ; 3296 __sbit __at 0x81 AD1 ; 3297 __sbit __at 0x82 AD2 ; 3298 __sbit __at 0x83 AD3 ; 3299 __sbit __at 0x84 AD4 ; 3300 __sbit __at 0x85 AD5 ; 3301 __sbit __at 0x86 AD6 ; 3302 __sbit __at 0x87 AD7 ; 3303 #endif 3304 3305 #ifdef P1 3306 #undef P1 3307 __sfr __at 0x90 P1 ; 3308 // Bit registers 3309 __sbit __at 0x90 P1_0 ; 3310 __sbit __at 0x91 P1_1 ; 3311 __sbit __at 0x92 P1_2 ; 3312 __sbit __at 0x93 P1_3 ; 3313 __sbit __at 0x94 P1_4 ; 3314 __sbit __at 0x95 P1_5 ; 3315 __sbit __at 0x96 P1_6 ; 3316 __sbit __at 0x97 P1_7 ; 3317 #endif 3318 3319 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 3320 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 3321 // P1 alternate functions 3322 __sbit __at 0x90 T2 ; 3323 __sbit __at 0x91 T2EX ; 3324 __sbit __at 0x92 RXD1 ; 3325 __sbit __at 0x93 TXD1 ; 3326 __sbit __at 0x94 INT2 ; 3327 __sbit __at 0x95 INT3 ; 3328 __sbit __at 0x96 INT4 ; 3329 __sbit __at 0x97 INT5 ; 3330 #endif 3331 3332 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 3333 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 3334 // P89C669 alternate names for bits __at P1 3335 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 3336 __sbit __at 0x90 T2 ; 3337 __sbit __at 0x91 T2EX ; 3338 __sbit __at 0x92 ECI ; 3339 __sbit __at 0x93 CEX0 ; 3340 __sbit __at 0x94 CEX1 ; 3341 __sbit __at 0x95 CEX2 ; 3342 __sbit __at 0x96 SCL ; 3343 __sbit __at 0x97 SDA ; 3344 #endif 3345 3346 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 3347 __sbit __at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific 3348 __sbit __at 0x91 INT4_CC1 ; 3349 __sbit __at 0x92 INT5_CC2 ; 3350 __sbit __at 0x93 INT6_CC3 ; 3351 __sbit __at 0x94 INT2 ; 3352 __sbit __at 0x95 T2EX ; 3353 __sbit __at 0x96 CLKOUT ; 3354 __sbit __at 0x97 T2 ; 3355 #endif 3356 3357 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA 3358 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA 3359 // Bit registers 3360 __sbit __at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific 3361 __sbit __at 0x91 CT1I ; 3362 __sbit __at 0x92 CT2I ; 3363 __sbit __at 0x93 CT3I ; 3364 __sbit __at 0x94 T2 ; 3365 __sbit __at 0x95 RT2 ; 3366 __sbit __at 0x96 SCL ; 3367 __sbit __at 0x97 SDA ; 3368 #endif 3369 3370 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2 3371 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2 3372 // P1 alternate functions 3373 __sbit __at 0x90 T2 ; 3374 __sbit __at 0x91 T2EX ; 3375 #endif 3376 3377 #ifdef P2 3378 #undef P2 3379 __sfr __at 0xA0 P2 ; 3380 // Bit registers 3381 __sbit __at 0xA0 P2_0 ; 3382 __sbit __at 0xA1 P2_1 ; 3383 __sbit __at 0xA2 P2_2 ; 3384 __sbit __at 0xA3 P2_3 ; 3385 __sbit __at 0xA4 P2_4 ; 3386 __sbit __at 0xA5 P2_5 ; 3387 __sbit __at 0xA6 P2_6 ; 3388 __sbit __at 0xA7 P2_7 ; 3389 #endif 3390 3391 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 3392 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 3393 // P89C668 specific bit registers __at P2: 3394 __sbit __at 0xA0 AD8 ; 3395 __sbit __at 0xA1 AD9 ; 3396 __sbit __at 0xA2 AD10 ; 3397 __sbit __at 0xA3 AD11 ; 3398 __sbit __at 0xA4 AD12 ; 3399 __sbit __at 0xA5 AD13 ; 3400 __sbit __at 0xA6 AD14 ; 3401 __sbit __at 0xA7 AD15 ; 3402 #endif 3403 3404 #ifdef P3 3405 #undef P3 3406 __sfr __at 0xB0 P3 ; 3407 // Bit registers 3408 __sbit __at 0xB0 P3_0 ; 3409 __sbit __at 0xB1 P3_1 ; 3410 __sbit __at 0xB2 P3_2 ; 3411 __sbit __at 0xB3 P3_3 ; 3412 __sbit __at 0xB4 P3_4 ; 3413 __sbit __at 0xB5 P3_5 ; 3414 #ifndef MCS51REG_EXTERNAL_RAM 3415 __sbit __at 0xB6 P3_6 ; 3416 __sbit __at 0xB7 P3_7 ; 3417 #endif 3418 // alternate names 3419 __sbit __at 0xB0 RXD ; 3420 __sbit __at 0xB0 RXD0 ; 3421 __sbit __at 0xB1 TXD ; 3422 __sbit __at 0xB1 TXD0 ; 3423 __sbit __at 0xB2 INT0 ; 3424 __sbit __at 0xB3 INT1 ; 3425 __sbit __at 0xB4 T0 ; 3426 __sbit __at 0xB5 T1 ; 3427 #ifndef MCS51REG_EXTERNAL_RAM 3428 __sbit __at 0xB6 WR ; 3429 __sbit __at 0xB7 RD ; 3430 #endif 3431 #endif 3432 3433 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x 3434 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x 3435 // P89C668 specific bit registers __at P3 (alternate names) 3436 __sbit __at 0xB5 CEX4 ; 3437 __sbit __at 0xB4 CEX3 ; 3438 #endif 3439 3440 #ifdef P4_AT_0X80 3441 #undef P4_AT_0X80 3442 __sfr __at 0x80 P4 ; // Port 4 - DS80C390 3443 // Bit registers 3444 __sbit __at 0x80 P4_0 ; 3445 __sbit __at 0x81 P4_1 ; 3446 __sbit __at 0x82 P4_2 ; 3447 __sbit __at 0x83 P4_3 ; 3448 __sbit __at 0x84 P4_4 ; 3449 __sbit __at 0x85 P4_5 ; 3450 __sbit __at 0x86 P4_6 ; 3451 __sbit __at 0x87 P4_7 ; 3452 #endif 3453 3454 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 3455 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 3456 __sfr __at 0xC0 P4 ; // Port 4, P80C552 specific 3457 // Bit registers 3458 __sbit __at 0xC0 CMSR0 ; 3459 __sbit __at 0xC1 CMSR1 ; 3460 __sbit __at 0xC2 CMSR2 ; 3461 __sbit __at 0xC3 CMSR3 ; 3462 __sbit __at 0xC4 CMSR4 ; 3463 __sbit __at 0xC5 CMSR5 ; 3464 __sbit __at 0xC6 CMT0 ; 3465 __sbit __at 0xC7 CMT1 ; 3466 #endif 3467 3468 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 3469 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 3470 __sfr __at 0xC0 P4 ; // Port 4, T89C51 specific 3471 // Bit registers 3472 __sbit __at 0xC0 P4_0 ; 3473 __sbit __at 0xC1 P4_1 ; 3474 __sbit __at 0xC2 P4_2 ; 3475 __sbit __at 0xC3 P4_3 ; 3476 __sbit __at 0xC4 P4_4 ; 3477 __sbit __at 0xC5 P4_5 ; 3478 __sbit __at 0xC6 P4_6 ; 3479 __sbit __at 0xC7 P4_7 ; 3480 #endif 3481 3482 #ifdef P4_AT_0XE8 3483 #undef P4_AT_0XE8 3484 __sfr __at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers 3485 // Bit registers 3486 __sbit __at 0xE8 P4_0 ; 3487 __sbit __at 0xE9 P4_1 ; 3488 __sbit __at 0xEA P4_2 ; 3489 __sbit __at 0xEB P4_3 ; 3490 __sbit __at 0xEC P4_4 ; 3491 __sbit __at 0xED P4_5 ; 3492 __sbit __at 0xEE P4_6 ; 3493 __sbit __at 0xEF P4_7 ; 3494 #endif 3495 3496 #ifdef P4CNT 3497 #undef P4CNT 3498 __sfr __at 0x92 P4CNT ; // DS80C390 3499 // Not directly accessible bits 3500 #define P4CNT_0 0x01 3501 #define P4CNT_1 0x02 3502 #define P4CNT_2 0x04 3503 #define P4CNT_3 0x08 3504 #define P4CNT_4 0x10 3505 #define P4CNT_5 0x20 3506 #define SBCAN 0x40 3507 #endif 3508 3509 #ifdef P5_AT_0XA1 3510 #undef P5_AT_0XA1 3511 __sfr __at 0xA1 P5 ; // Port 5 - DS80C390 3512 #endif 3513 3514 #ifdef P5_AT_0XE8 3515 #undef P5_AT_0XE8 3516 __sfr __at 0xE8 P5 ; // Port 5 - T89C51RD2 3517 // Bit registers 3518 __sbit __at 0xE8 P5_0 ; 3519 __sbit __at 0xE9 P5_1 ; 3520 __sbit __at 0xEA P5_2 ; 3521 __sbit __at 0xEB P5_3 ; 3522 __sbit __at 0xEC P5_4 ; 3523 __sbit __at 0xED P5_5 ; 3524 __sbit __at 0xEE P5_6 ; 3525 __sbit __at 0xEF P5_7 ; 3526 #endif 3527 3528 #ifdef P5CNT 3529 #undef P5CNT 3530 __sfr __at 0xA2 P5CNT ; // DS80C390 3531 // Not directly accessible bits 3532 #define P5CNT_0 0x01 3533 #define P5CNT_1 0x02 3534 #define P5CNT_2 0x04 3535 #define C0_I_O 0x08 3536 #define C1_I_O 0x10 3537 #define SP1EC 0x20 3538 #define SBCAN0BA 0x40 3539 #define SBCAN1BA 0x80 3540 #endif 3541 3542 #ifdef P5_AT_0XC4 3543 #undef P5_AT_0XC4 3544 __sfr __at 0xC4 P5 ; // Port 5, P80C552 specific 3545 // Not directly accessible Bits. 3546 #define ADC0 0x01 3547 #define ADC1 0x02 3548 #define ADC2 0x04 3549 #define ADC3 0x08 3550 #define ADC4 0x10 3551 #define ADC5 0x20 3552 #define ADC6 0x40 3553 #define ADC7 0x80 3554 #endif 3555 3556 #ifdef P5_AT_0XF8 3557 #undef P5_AT_0XF8 3558 __sfr __at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers 3559 // Bit registers 3560 __sbit __at 0xF8 P5_0 ; 3561 __sbit __at 0xF9 P5_1 ; 3562 __sbit __at 0xFA P5_2 ; 3563 __sbit __at 0xFB P5_3 ; 3564 __sbit __at 0xFC P5_4 ; 3565 __sbit __at 0xFD P5_5 ; 3566 __sbit __at 0xFE P5_6 ; 3567 __sbit __at 0xFF P5_7 ; 3568 #endif 3569 3570 #ifdef P6_AT_0XDB 3571 #undef P6_AT_0XDB 3572 __sfr __at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers 3573 #endif 3574 3575 #ifdef P6_AT_0XFA 3576 #undef P6_AT_0XFA 3577 __sfr __at 0xFA P6 ; // Port 6 - SAB80517 specific 3578 #endif 3579 3580 #ifdef P7_AT_0XDB 3581 #undef P7_AT_0XDB 3582 __sfr __at 0xDB P7 ; // Port 7 - SAB80517 specific 3583 #endif 3584 3585 #ifdef P8_AT_0XDD 3586 #undef P8_AT_0XDD 3587 __sfr __at 0xDD P8 ; // Port 6 - SAB80517 specific 3588 #endif 3589 3590 #ifdef P9_AT_0XF9 3591 #undef P9_AT_0XF9 3592 __sfr __at 0xF9 P9; 3593 #endif 3594 3595 #ifdef PCON__SMOD__x__x__x__x__x__x__x 3596 #undef PCON__SMOD__x__x__x__x__x__x__x 3597 __sfr __at 0x87 PCON ; 3598 // Not directly accessible PCON bits 3599 #define SMOD 0x80 3600 #endif 3601 3602 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 3603 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL 3604 __sfr __at 0x87 PCON ; 3605 // Not directly accessible PCON bits 3606 #define IDL 0x01 3607 #define PD 0x02 3608 #define GF0 0x04 3609 #define GF1 0x08 3610 #define SMOD 0x80 3611 #endif 3612 3613 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL 3614 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL 3615 __sfr __at 0x87 PCON ; // PCON, P80C552 specific 3616 // Not directly accessible Bits. 3617 #define IDL 0x01 3618 #define IDLE 0x01 /* same as IDL */ 3619 #define PD 0x02 3620 #define GF0 0x04 3621 #define GF1 0x08 3622 #define WLE 0x10 3623 #define SMOD 0x80 3624 #endif 3625 3626 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL 3627 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL 3628 __sfr __at 0x87 PCON ; 3629 // Not directly accessible PCON bits 3630 #define IDL 0x01 3631 #define IDLE 0x01 /* same as IDL */ 3632 #define PD 0x02 3633 #define PDE 0x02 /* same as PD */ 3634 #define IDLS 0x20 3635 #define PDS 0x40 3636 #define SMOD 0x80 3637 // alternate names 3638 #define PCON_IDLE 0x01 3639 #define PCON_PDE 0x02 3640 #define PCON_GF0 0x04 3641 #define PCON_GF1 0x08 3642 #define PCON_IDLS 0x20 3643 #define PCON_PDS 0x40 3644 #define PCON_SMOD 0x80 3645 #endif 3646 3647 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL 3648 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL 3649 __sfr __at 0x87 PCON ; 3650 // Not directly accessible PCON bits 3651 #define IDL 0x01 3652 #define IDLE 0x01 /* same as IDL */ 3653 #define STOP 0x02 3654 #define EWT 0x04 3655 #define EPFW 0x08 3656 #define WTR 0x10 3657 #define PFW 0x20 3658 #define POR 0x40 3659 #define SMOD 0x80 3660 #endif 3661 3662 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE 3663 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE 3664 __sfr __at 0x87 PCON ; 3665 // Not directly accessible PCON bits 3666 #define IDL 0x01 3667 #define IDLE 0x01 /* same as IDL */ 3668 #define STOP 0x02 3669 #define GF0 0x04 3670 #define GF1 0x08 3671 #define SMOD0 0x40 3672 #define SMOD 0x80 3673 #endif 3674 3675 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE 3676 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE 3677 __sfr __at 0x87 PCON ; 3678 // Not directly accessible PCON bits 3679 #define IDL 0x01 3680 #define IDLE 0x01 /* same as IDL */ 3681 #define STOP 0x02 3682 #define GF0 0x04 3683 #define GF1 0x08 3684 #define OFDE 0x10 3685 #define OFDF 0x20 3686 #define SMOD0 0x40 3687 #define SMOD 0x80 3688 #define SMOD_0 0x80 /* same as SMOD */ 3689 #endif 3690 3691 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL 3692 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL 3693 __sfr __at 0x87 PCON ; 3694 #define IDL 0x01 3695 #define PD 0x02 3696 #define GF0 0x04 3697 #define GF1 0x08 3698 #define POF 0x10 3699 #define SMOD0 0x40 3700 #define SMOD1 0x80 3701 #endif 3702 3703 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 3704 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 3705 __sfr __at 0xC4 PMR ; // DS87C520, DS83C520 3706 // Not directly accessible bits 3707 #define DME0 0x01 3708 #define DME1 0x02 3709 #define ALEOFF 0x04 3710 #define XTOFF 0x08 3711 #define SWB 0x20 3712 #define CD0 0x40 3713 #define CD1 0x80 3714 #endif 3715 3716 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x 3717 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x 3718 __sfr __at 0xC4 PMR ; // DS80C390 3719 // Not directly accessible bits 3720 #define ALEOFF 0x04 3721 #define XTOFF 0x08 3722 #define _4X_2X 0x10 3723 #define SWB 0x20 3724 #define CD0 0x40 3725 #define CD1 0x80 3726 #endif 3727 3728 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 3729 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 3730 __sfr __at 0xC4 PMR ; // DS89C420 3731 // Not directly accessible bits 3732 #define DME0 0x01 3733 #define DME1 0x02 3734 #define ALEON 0x04 3735 #define _4X_2X 0x08 3736 #define CTM 0x10 3737 #define SWB 0x20 3738 #define CD0 0x40 3739 #define CD1 0x80 3740 #endif 3741 3742 #ifdef PRSC 3743 #undef PRSC 3744 __sfr __at 0xB4 PRSC; 3745 #endif 3746 3747 #ifdef PSW 3748 #undef PSW 3749 __sfr __at 0xD0 PSW ; 3750 // Bit registers 3751 __sbit __at 0xD0 P ; 3752 __sbit __at 0xD1 F1 ; 3753 __sbit __at 0xD2 OV ; 3754 __sbit __at 0xD3 RS0 ; 3755 __sbit __at 0xD4 RS1 ; 3756 __sbit __at 0xD5 F0 ; 3757 __sbit __at 0xD6 AC ; 3758 __sbit __at 0xD7 CY ; 3759 #endif 3760 3761 #ifdef PWM0_AT_0XFC 3762 #undef PWM0_AT_0XFC 3763 __sfr __at 0xFC PWM0 ; // PWM register 0, P80C552 specific 3764 #endif 3765 3766 #ifdef PWM1_AT_0XFD 3767 #undef PWM1_AT_0XFD 3768 __sfr __at 0xFD PWM1 ; // PWM register 1, P80C552 specific 3769 #endif 3770 3771 #ifdef PWMP_AT_0XFE 3772 #undef PWMP_AT_0XFE 3773 __sfr __at 0xFE PWMP ; // PWM prescaler, P80C552 specific 3774 #endif 3775 3776 #ifdef RCAP2H 3777 #undef RCAP2H 3778 __sfr __at 0xCB RCAP2H ; 3779 #endif 3780 3781 #ifdef RCAP2L 3782 #undef RCAP2L 3783 __sfr __at 0xCA RCAP2L ; 3784 #endif 3785 3786 #ifdef RNR 3787 #undef RNR 3788 __sfr __at 0xCF RNR ; 3789 #endif 3790 3791 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 3792 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 3793 __sfr __at 0xC2 ROMSIZE ; // DS87C520, DS83C520 3794 // Not directly accessible bits 3795 #define RSM0 0x01 3796 #define RSM1 0x02 3797 #define RSM2 0x04 3798 #endif 3799 3800 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 3801 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 3802 __sfr __at 0xC2 ROMSIZE ; // DS89C420 3803 // Not directly accessible bits 3804 #define RSM0 0x01 3805 #define RSM1 0x02 3806 #define RSM2 0x04 3807 #define PRAME 0x08 3808 #endif 3809 3810 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0 3811 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0 3812 __sfr __at 0xC2 ROMSIZE ; // DS87C520, DS83C520 3813 // Not directly accessible bits 3814 #define RSM0 0x01 3815 #define RSM1 0x02 3816 #define RSM2 0x04 3817 #define PRAME 0x08 3818 #define MOVCX 0x10 3819 #define TE 0x20 3820 #define BPF 0x40 3821 #define HBPF 0x80 3822 #endif 3823 3824 #ifdef RPCTL 3825 #undef RPCTL 3826 __sfr __at 0xD8 RPCTL ; // Dallas DS5001 specific 3827 __sbit __at 0xD8 RG0 ; 3828 __sbit __at 0xD9 RPCON ; 3829 __sbit __at 0xDA DMA ; 3830 __sbit __at 0xDB IBI ; 3831 __sbit __at 0xDC AE ; 3832 __sbit __at 0xDD EXBS ; 3833 __sbit __at 0xDF RNR_FLAG ; 3834 #endif 3835 3836 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 3837 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 3838 __sfr __at 0xEF RTE ; // Reset/toggle enable, P80C552 specific 3839 // Not directly accessible Bits. 3840 #define RP40 0x01 3841 #define RP41 0x02 3842 #define RP42 0x04 3843 #define RP43 0x08 3844 #define RP44 0x10 3845 #define RP45 0x20 3846 #define TP46 0x40 3847 #define TP47 0x80 3848 #endif 3849 3850 #ifdef S0BUF 3851 #undef S0BUF 3852 __sfr __at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific 3853 #endif 3854 3855 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI 3856 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI 3857 __sfr __at 0x98 S0CON ; // serial channel 0 control register P80C552 specific 3858 // Bit registers 3859 // Already defined in SCON 3860 //__sbit __at 0x98 RI0 ; 3861 //__sbit __at 0x99 TI0 ; 3862 //__sbit __at 0x9A RB8 ; 3863 //__sbit __at 0x9B TB8 ; 3864 //__sbit __at 0x9C REN ; 3865 //__sbit __at 0x9D SM2 ; 3866 //__sbit __at 0x9E SM1 ; 3867 //__sbit __at 0x9F SM0 ; 3868 #endif 3869 3870 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 3871 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 3872 // serial channel 0 buffer register SAB80517 specific(same as stock SCON) 3873 __sfr __at 0x98 S0CON ; 3874 __sbit __at 0x98 RI0 ; 3875 __sbit __at 0x99 TI0 ; 3876 __sbit __at 0x9A RB80 ; 3877 __sbit __at 0x9B TB80 ; 3878 __sbit __at 0x9C REN0 ; 3879 __sbit __at 0x9D SM20 ; 3880 __sbit __at 0x9E SM1 ; 3881 __sbit __at 0x9F SM0 ; 3882 #endif 3883 3884 #ifdef S0RELL 3885 #undef S0RELL 3886 __sfr __at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific 3887 #endif 3888 3889 #ifdef S0RELH 3890 #undef S0RELH 3891 __sfr __at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific 3892 #endif 3893 3894 #ifdef S1ADR__x__x__x__x__x__x__x__GC 3895 #undef S1ADR__x__x__x__x__x__x__x__GC 3896 __sfr __at 0xDB S1ADR ; // Serial 1 address, P80C552 specific 3897 // Not directly accessible Bits. 3898 #define GC 0x01 3899 #endif 3900 3901 #ifdef S1BUF 3902 #undef S1BUF 3903 __sfr __at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific 3904 #endif 3905 3906 #ifdef S1CON_AT_0X9B 3907 #undef S1CON_AT_0X9B 3908 __sfr __at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific 3909 #endif 3910 3911 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 3912 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 3913 __sfr __at 0xD8 S1CON ; // Serial 1 control, P80C552 specific 3914 __sfr __at 0xD8 SICON ; // sometimes called SICON 3915 // Bit register 3916 __sbit __at 0xD8 CR0 ; 3917 __sbit __at 0xD9 CR1 ; 3918 __sbit __at 0xDA AA ; 3919 __sbit __at 0xDB SI ; 3920 __sbit __at 0xDC ST0 ; 3921 __sbit __at 0xDD STA ; 3922 __sbit __at 0xDE ENS1 ; 3923 __sbit __at 0xDF CR2 ; 3924 #endif 3925 3926 #ifdef S1DAT_AT_0XDA 3927 #undef S1DAT_AT_0XDA 3928 __sfr __at 0xDA S1DAT ; // Serial 1 data, P80C552 specific 3929 __sfr __at 0xDA SIDAT ; // sometimes called SIDAT 3930 #endif 3931 3932 #ifdef S1IST_AT_0XDC 3933 #undef S1IST_AT_0XDC 3934 // P89C668 specific 3935 __sfr __at 0xDC S1IST ; 3936 #endif 3937 3938 #ifdef S1RELL 3939 #undef S1RELL 3940 __sfr __at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific 3941 #endif 3942 3943 #ifdef S1RELH 3944 #undef S1RELH 3945 __sfr __at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific 3946 #endif 3947 3948 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x 3949 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x 3950 __sfr __at 0xD9 S1STA ; // Serial 1 status, P80C552 specific 3951 // Not directly accessible Bits. 3952 #define SC0 0x08 3953 #define SC1 0x10 3954 #define SC2 0x20 3955 #define SC3 0x40 3956 #define SC4 0x80 3957 #endif 3958 3959 #ifdef SADR_AT_0XA9 3960 #undef SADR_AT_0XA9 3961 __sfr __at 0xA9 SADDR ; 3962 #endif 3963 3964 #ifdef SADDR0 3965 #undef SADDR0 3966 // DS80C320 specific 3967 __sfr __at 0xA9 SADDR0 ; 3968 #endif 3969 3970 #ifdef SADDR1 3971 #undef SADDR1 3972 // DS80C320 specific 3973 __sfr __at 0xAA SADDR1 ; 3974 #endif 3975 3976 #ifdef SADEN_AT_0XB9 3977 #undef SADEN_AT_0XB9 3978 __sfr __at 0xB9 SADEN ; 3979 #endif 3980 3981 #ifdef SADEN0 3982 #undef SADEN0 3983 // DS80C320 & DS80C390 specific 3984 __sfr __at 0xB9 SADEN0 ; 3985 #endif 3986 3987 #ifdef SADEN1 3988 #undef SADEN1 3989 // DS80C320 & DS80C390 specific 3990 __sfr __at 0xBA SADEN1 ; 3991 #endif 3992 3993 #ifdef SBUF 3994 #undef SBUF 3995 __sfr __at 0x99 SBUF ; 3996 __sfr __at 0x99 SBUF0 ; 3997 #endif 3998 3999 #ifdef SBUF1 4000 #undef SBUF1 4001 // DS80C320 & DS80C390 specific 4002 __sfr __at 0xC1 SBUF1 ; 4003 #endif 4004 4005 #ifdef SCON 4006 #undef SCON 4007 __sfr __at 0x98 SCON ; 4008 // Bit registers 4009 __sbit __at 0x98 RI ; 4010 __sbit __at 0x99 TI ; 4011 __sbit __at 0x9A RB8 ; 4012 __sbit __at 0x9B TB8 ; 4013 __sbit __at 0x9C REN ; 4014 __sbit __at 0x9D SM2 ; 4015 __sbit __at 0x9E SM1 ; 4016 __sbit __at 0x9F SM0 ; 4017 #endif 4018 4019 #ifdef SCON0 4020 #undef SCON0 4021 __sfr __at 0x98 SCON0 ; 4022 // Bit registers 4023 __sbit __at 0x98 RI_0 ; 4024 __sbit __at 0x99 TI_0 ; 4025 __sbit __at 0x9A RB8_0 ; 4026 __sbit __at 0x9B TB8_0 ; 4027 __sbit __at 0x9C REN_0 ; 4028 __sbit __at 0x9D SM2_0 ; 4029 __sbit __at 0x9E SM1_0 ; 4030 __sbit __at 0x9F SM0_0 ; 4031 __sbit __at 0x9F FE_0 ; 4032 __sbit __at 0x9F SM0_FE_0 ; 4033 #endif 4034 4035 #ifdef SCON1 4036 #undef SCON1 4037 // DS80C320 - 80C390 specific 4038 __sfr __at 0xC0 SCON1 ; 4039 // Bit registers 4040 __sbit __at 0xC0 RI_1 ; 4041 __sbit __at 0xC1 TI_1 ; 4042 __sbit __at 0xC2 RB8_1 ; 4043 __sbit __at 0xC3 TB8_1 ; 4044 __sbit __at 0xC4 REN_1 ; 4045 __sbit __at 0xC5 SM2_1 ; 4046 __sbit __at 0xC6 SM1_1 ; 4047 __sbit __at 0xC7 SM0_1 ; 4048 __sbit __at 0xC7 FE_1 ; 4049 __sbit __at 0xC7 SM0_FE_1 ; 4050 #endif 4051 4052 #ifdef SETMSK 4053 #undef SETMSK 4054 __sfr __at 0xA5 SETMSK; 4055 #endif 4056 4057 #ifdef SP 4058 #undef SP 4059 __sfr __at 0x81 SP ; 4060 #endif 4061 4062 #ifdef SPCR 4063 #undef SPCR 4064 __sfr __at 0xD5 SPCR ; // AT89S53 specific 4065 // Not directly accesible bits 4066 #define SPR0 0x01 4067 #define SPR1 0x02 4068 #define CPHA 0x04 4069 #define CPOL 0x08 4070 #define MSTR 0x10 4071 #define DORD 0x20 4072 #define SPE 0x40 4073 #define SPIE 0x80 4074 #endif 4075 4076 #ifdef SPDR 4077 #undef SPDR 4078 __sfr __at 0x86 SPDR ; // AT89S53 specific 4079 // Not directly accesible bits 4080 #define SPD_0 0x01 4081 #define SPD_1 0x02 4082 #define SPD_2 0x04 4083 #define SPD_3 0x08 4084 #define SPD_4 0x10 4085 #define SPD_5 0x20 4086 #define SPD_6 0x40 4087 #define SPD_7 0x80 4088 #endif 4089 4090 #ifdef SPSR 4091 #undef SPSR 4092 __sfr __at 0xAA SPSR ; // AT89S53 specific 4093 // Not directly accesible bits 4094 #define SPIF 0x40 4095 #define WCOL 0x80 4096 #endif 4097 4098 #ifdef SRELH 4099 #undef SRELH 4100 __sfr __at 0xBA SRELH ; // Baudrate generator reload high 4101 #endif 4102 4103 #ifdef SRELL 4104 #undef SRELL 4105 __sfr __at 0xAA SRELL ; // Baudrate generator reload low 4106 #endif 4107 4108 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x 4109 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x 4110 // DS80C320 specific 4111 __sfr __at 0xC5 STATUS ; 4112 // Not directly accessible Bits. DS80C320 specific 4113 #define LIP 0x20 4114 #define HIP 0x40 4115 #define PIP 0x80 4116 #endif 4117 4118 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 4119 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 4120 __sfr __at 0xC5 STATUS ; // DS80C390 specific 4121 // Not directly accessible Bits. 4122 #define SPRA0 0x01 4123 #define SPTA0 0x02 4124 #define SPRA1 0x04 4125 #define SPTA1 0x08 4126 #define LIP 0x20 4127 #define HIP 0x40 4128 #define PIP 0x80 4129 #endif 4130 4131 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 4132 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 4133 __sfr __at 0xC5 STATUS ; // DS89C420 specific 4134 // Not directly accessible Bits. 4135 #define SPRA0 0x01 4136 #define SPTA0 0x02 4137 #define SPRA1 0x04 4138 #define SPTA1 0x08 4139 #define PIS0 0x20 4140 #define PIS1 0x40 4141 #define PIS2 0x80 4142 #endif 4143 4144 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 4145 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 4146 __sfr __at 0xC5 STATUS ; // DS80C390 specific 4147 // Not directly accessible Bits. 4148 #define SPRA0 0x01 4149 #define SPTA0 0x02 4150 #define SPRA1 0x04 4151 #define SPTA1 0x08 4152 #define LIP 0x20 4153 #define HIP 0x40 4154 #define PIP 0x80 4155 #endif 4156 4157 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 4158 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 4159 __sfr __at 0xC5 STATUS ; // DS87C520 & DS83520specific 4160 // Not directly accessible Bits. 4161 #define SPRA0 0x01 4162 #define SPTA0 0x02 4163 #define SPTA1 0x04 4164 #define SPTA2 0x08 4165 #define XTUP 0x10 4166 #define LIP 0x20 4167 #define HIP 0x40 4168 #define PIP 0x80 4169 #endif 4170 4171 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF 4172 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF 4173 __sfr __at 0xDA STATUS ; // DS5001specific 4174 // Not directly accessible Bits. 4175 #define OBF 0x01 4176 #define IBF 0x02 4177 #define F0 0x04 4178 #define IA0 0x08 4179 #define ST4 0x10 4180 #define ST5 0x20 4181 #define ST6 0x40 4182 #define ST7 0x80 4183 #endif 4184 4185 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 4186 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 4187 __sfr __at 0xEE STE ; // Set enable, P80C552 specific 4188 // Not directly accessible Bits. 4189 #define SP40 0x01 4190 #define SP41 0x02 4191 #define SP42 0x04 4192 #define SP43 0x08 4193 #define SP44 0x10 4194 #define SP45 0x20 4195 #define TG46 0x40 4196 #define TG47 0x80 4197 #endif 4198 4199 #ifdef SYSCON 4200 #undef SYSCON 4201 __sfr __at 0xB1 SYSCON ; // XRAM Controller Access Control 4202 // SYSCON bits 4203 #define SYSCON_XMAP0 0x01 4204 #define SYSCON_XMAP1 0x02 4205 #define SYSCON_RMAP 0x10 4206 #define SYSCON_EALE 0x20 4207 #endif 4208 4209 #ifdef SYSCON1 4210 #undef SYSCON1 4211 __sfr __at 0xB2 SYSCON1; 4212 #endif 4213 4214 #ifdef T2 4215 #undef T2 4216 __sfr __at 0xCC T2; 4217 #endif 4218 4219 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 4220 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 4221 __sfr __at 0xC8 T2CON ; 4222 // Definitions for the 8052 compatible microcontrollers. 4223 // Bit registers 4224 __sbit __at 0xC8 CP_RL2 ; 4225 __sbit __at 0xC9 C_T2 ; 4226 __sbit __at 0xCA TR2 ; 4227 __sbit __at 0xCB EXEN2 ; 4228 __sbit __at 0xCC TCLK ; 4229 __sbit __at 0xCD RCLK ; 4230 __sbit __at 0xCE EXF2 ; 4231 __sbit __at 0xCF TF2 ; 4232 // alternate names 4233 __sbit __at 0xC8 T2CON_0 ; 4234 __sbit __at 0xC9 T2CON_1 ; 4235 __sbit __at 0xCA T2CON_2 ; 4236 __sbit __at 0xCB T2CON_3 ; 4237 __sbit __at 0xCC T2CON_4 ; 4238 __sbit __at 0xCD T2CON_5 ; 4239 __sbit __at 0xCE T2CON_6 ; 4240 __sbit __at 0xCF T2CON_7 ; 4241 #endif 4242 4243 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 4244 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 4245 __sfr __at 0xC8 T2CON ; 4246 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517 4247 // Bit registers 4248 __sbit __at 0xC8 T2I0 ; 4249 __sbit __at 0xC9 T2I1 ; 4250 __sbit __at 0xCA T2CM ; 4251 __sbit __at 0xCB T2R0 ; 4252 __sbit __at 0xCC T2R1 ; 4253 __sbit __at 0xCD I2FR ; 4254 __sbit __at 0xCE I3FR ; 4255 __sbit __at 0xCF T2PS ; 4256 // alternate names 4257 __sbit __at 0xC8 T2CON_0 ; 4258 __sbit __at 0xC9 T2CON_1 ; 4259 __sbit __at 0xCA T2CON_2 ; 4260 __sbit __at 0xCB T2CON_3 ; 4261 __sbit __at 0xCC T2CON_4 ; 4262 __sbit __at 0xCD T2CON_5 ; 4263 __sbit __at 0xCE T2CON_6 ; 4264 __sbit __at 0xCF T2CON_7 ; 4265 #endif 4266 4267 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN 4268 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN 4269 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers 4270 __sfr __at 0xC9 T2MOD ; 4271 // Not not directly accessible T2MOD bits 4272 #define DCEN 0x01 4273 #define T2OE 0x02 4274 #define D13T2 0x08 4275 #define D13T1 0x10 4276 #endif 4277 4278 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN 4279 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN 4280 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller 4281 __sfr __at 0xC9 T2MOD ; 4282 // Not not directly accessible T2MOD bits 4283 #define DCEN 0x01 4284 #define T2OE 0x02 4285 // Alternate names 4286 #define DCEN_ 0x01 4287 #define T2OE_ 0x02 4288 #endif 4289 4290 #ifdef T3_AT_0XFF 4291 #undef T3_AT_0XFF 4292 __sfr __at 0xFF T3 ; // Timer 3, P80C552 specific 4293 #endif 4294 4295 #ifdef TA 4296 #undef TA 4297 // DS500x, DS80C320 & DS80C390 specific 4298 __sfr __at 0xC7 TA ; 4299 #endif 4300 4301 #ifdef TCON 4302 #undef TCON 4303 __sfr __at 0x88 TCON ; 4304 // Bit registers 4305 __sbit __at 0x88 IT0 ; 4306 __sbit __at 0x89 IE0 ; 4307 __sbit __at 0x8A IT1 ; 4308 __sbit __at 0x8B IE1 ; 4309 __sbit __at 0x8C TR0 ; 4310 __sbit __at 0x8D TF0 ; 4311 __sbit __at 0x8E TR1 ; 4312 __sbit __at 0x8F TF1 ; 4313 #endif 4314 4315 #ifdef TH0 4316 #undef TH0 4317 __sfr __at 0x8C TH0 ; 4318 #endif 4319 4320 #ifdef TH1 4321 #undef TH1 4322 __sfr __at 0x8D TH1 ; 4323 #endif 4324 4325 #ifdef TH2 4326 #undef TH2 4327 __sfr __at 0xCD TH2 ; 4328 #endif 4329 4330 #ifdef TL0 4331 #undef TL0 4332 __sfr __at 0x8A TL0 ; 4333 #endif 4334 4335 #ifdef TL1 4336 #undef TL1 4337 __sfr __at 0x8B TL1 ; 4338 #endif 4339 4340 #ifdef TL2 4341 #undef TL2 4342 __sfr __at 0xCC TL2 ; 4343 #endif 4344 4345 #ifdef TMOD 4346 #undef TMOD 4347 __sfr __at 0x89 TMOD ; 4348 // Not directly accessible TMOD bits 4349 #define T0_M0 0x01 4350 #define T0_M1 0x02 4351 #define T0_CT 0x04 4352 #define T0_GATE 0x08 4353 #define T1_M0 0x10 4354 #define T1_M1 0x20 4355 #define T1_CT 0x40 4356 #define T1_GATE 0x80 4357 4358 #define T0_MASK 0x0F 4359 #define T1_MASK 0xF0 4360 #endif 4361 4362 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 4363 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 4364 __sfr __at 0xEA TM2CON ; // Timer 2 control, P80C552 specific 4365 // Not directly accessible Bits. 4366 #define T2MS0 0x01 4367 #define T2MS1 0x02 4368 #define T2P0 0x04 4369 #define T2P1 0x08 4370 #define T2B0 0x10 4371 #define T2ER 0x20 4372 #define T2IS0 0x40 4373 #define T2IS1 0x80 4374 #endif 4375 4376 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 4377 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 4378 __sfr __at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific 4379 // Bit register 4380 __sbit __at 0xC8 CTI0 ; 4381 __sbit __at 0xC9 CTI1 ; 4382 __sbit __at 0xCA CTI2 ; 4383 __sbit __at 0xCB CTI3 ; 4384 __sbit __at 0xCC CMI0 ; 4385 __sbit __at 0xCD CMI1 ; 4386 __sbit __at 0xCE CMI2 ; 4387 __sbit __at 0xCF T20V ; 4388 #endif 4389 4390 #ifdef TMH2_AT_0XED 4391 #undef TMH2_AT_0XED 4392 __sfr __at 0xED TMH2 ; // Timer high 2, P80C552 specific 4393 #endif 4394 4395 #ifdef TML2_AT_0XEC 4396 #undef TML2_AT_0XEC 4397 __sfr __at 0xEC TML2 ; // Timer low 2, P80C552 specific 4398 #endif 4399 4400 #ifdef WCON 4401 #undef WCON 4402 __sfr __at 0x96 WCON ; // AT89S53 specific 4403 // Not directly accesible bits 4404 #define WDTEN 0x01 4405 #define WDTRST 0x02 4406 #define DPS 0x04 4407 #define PS0 0x20 4408 #define PS1 0x40 4409 #define PS2 0x80 4410 #endif 4411 4412 #ifdef WDCON 4413 #undef WDCON 4414 // DS80C320 - 390, DS89C420, etc. specific 4415 __sfr __at 0xD8 WDCON ; 4416 // Bit registers 4417 __sbit __at 0xD8 RWT ; 4418 __sbit __at 0xD9 EWT ; 4419 __sbit __at 0xDA WTRF ; 4420 __sbit __at 0xDB WDIF ; 4421 __sbit __at 0xDC PFI ; 4422 __sbit __at 0xDD EPFI ; 4423 __sbit __at 0xDE POR ; 4424 __sbit __at 0xDF SMOD_1 ; 4425 #endif 4426 4427 #ifdef WDTPRG_AT_0XA7 4428 #undef WDTPRG_AT_0XA7 4429 __sfr __at 0xA7 WDTPRG ; 4430 #define WDTRPRG_S0 0x01 4431 #define WDTRPRG_S1 0x02 4432 #define WDTRPRG_S2 0x04 4433 #endif 4434 4435 #ifdef WDTREL 4436 #undef WDTREL 4437 __sfr __at 0x86 WDTREL ; // Watchdof Timer reload register 4438 #endif 4439 4440 #ifdef WDTRST_AT_0XA6 4441 #undef WDTRST_AT_0XA6 4442 __sfr __at 0xA6 WDTRST ; 4443 #endif 4444 4445 #ifdef XPAGE 4446 #undef XPAGE 4447 __sfr __at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific 4448 #endif 4449 4450 ///////////////////////// 4451 /// Interrupt vectors /// 4452 ///////////////////////// 4453 4454 // Interrupt numbers: address = (number * 8) + 3 4455 #define IE0_VECTOR 0 // 0x03 external interrupt 0 4456 #define TF0_VECTOR 1 // 0x0b timer 0 4457 #define IE1_VECTOR 2 // 0x13 external interrupt 1 4458 #define TF1_VECTOR 3 // 0x1b timer 1 4459 #define SI0_VECTOR 4 // 0x23 serial port 0 4460 4461 #ifdef MICROCONTROLLER_AT89S53 4462 #define TF2_VECTOR 5 /* 0x2B timer 2 */ 4463 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ 4464 #endif 4465 4466 #ifdef MICROCONTROLLER_AT89X52 4467 #define TF2_VECTOR 5 /* 0x2B timer 2 */ 4468 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ 4469 #endif 4470 4471 #ifdef MICROCONTROLLER_AT89X55 4472 #define TF2_VECTOR 5 /* 0x2B timer 2 */ 4473 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ 4474 #endif 4475 4476 #ifdef MICROCONTROLLER_DS5000 4477 #define PFW_VECTOR 5 /* 0x2B */ 4478 #endif 4479 4480 #ifdef MICROCONTROLLER_DS5001 4481 #define PFW_VECTOR 5 /* 0x2B */ 4482 #endif 4483 4484 #ifdef MICROCONTROLLER_DS80C32X 4485 #define TF2_VECTOR 5 /* 0x2B */ 4486 #define PFI_VECTOR 6 /* 0x33 */ 4487 #define SIO1_VECTOR 7 /* 0x3B */ 4488 #define IE2_VECTOR 8 /* 0x43 */ 4489 #define IE3_VECTOR 9 /* 0x4B */ 4490 #define IE4_VECTOR 10 /* 0x53 */ 4491 #define IE5_VECTOR 11 /* 0x5B */ 4492 #define WDI_VECTOR 12 /* 0x63 */ 4493 #endif 4494 4495 #ifdef MICROCONTROLLER_DS89C420 4496 #define TF2_VECTOR 5 /* 0x2B */ 4497 #define PFI_VECTOR 6 /* 0x33 */ 4498 #define SIO1_VECTOR 7 /* 0x3B */ 4499 #define IE2_VECTOR 8 /* 0x43 */ 4500 #define IE3_VECTOR 9 /* 0x4B */ 4501 #define IE4_VECTOR 10 /* 0x53 */ 4502 #define IE5_VECTOR 11 /* 0x5B */ 4503 #define WDI_VECTOR 12 /* 0x63 */ 4504 #endif 4505 4506 #ifdef MICROCONTROLLER_DS8XC520 4507 #define TF2_VECTOR 5 /* 0x2B */ 4508 #define PFI_VECTOR 6 /* 0x33 */ 4509 #define SIO1_VECTOR 7 /* 0x3B */ 4510 #define IE2_VECTOR 8 /* 0x43 */ 4511 #define IE3_VECTOR 9 /* 0x4B */ 4512 #define IE4_VECTOR 10 /* 0x53 */ 4513 #define IE5_VECTOR 11 /* 0x5B */ 4514 #define WDI_VECTOR 12 /* 0x63 */ 4515 #endif 4516 4517 #ifdef MICROCONTROLLER_P80C552 4518 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C) 4519 #define CT0_VECTOR 6 // 0x33 T2 capture 0 4520 #define CT1_VECTOR 7 // 0x3B T2 capture 1 4521 #define CT2_VECTOR 8 // 0x43 T2 capture 2 4522 #define CT3_VECTOR 9 // 0x4B T2 capture 3 4523 #define ADC_VECTOR 10 // 0x53 ADC completion 4524 #define CM0_VECTOR 11 // 0x5B T2 compare 0 4525 #define CM1_VECTOR 12 // 0x63 T2 compare 1 4526 #define CM2_VECTOR 13 // 0x6B T2 compare 2 4527 #define TF2_VECTOR 14 // 0x73 T2 overflow 4528 #endif 4529 4530 #ifdef MICROCONTROLLER_P89C668 4531 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c) 4532 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array) 4533 #define TF2_VECTOR 7 // 0x3B (Timer 2) 4534 #endif 4535 4536 #ifdef MICROCONTROLLER_SAB80509 4537 #define RI0_VECTOR 4 // 0x23 serial port 0 4538 #define TI0_VECTOR 4 // 0x23 serial port 0 4539 #define TF2_VECTOR 5 // 0x2B timer 2 4540 #define EX2_VECTOR 5 // 0x2B external interrupt 2 4541 // 0x33 4542 // 0x3B 4543 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt 4544 #define IEX2_VECTOR 9 // 0x4B external interrupt 2 4545 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 4546 #define IEX4_VECTOR 11 // 0x5B external interrupt 4 4547 #define IEX5_VECTOR 12 // 0x63 external interrupt 5 4548 #define IEX6_VECTOR 13 // 0x6B external interrupt 6 4549 // 0x73 not used 4550 // 0x7B not used 4551 #define SI1_VECTOR 16 // 0x83 serial port 1 4552 #define RI1_VECTOR 16 // 0x83 serial port 1 4553 #define TI1_VECTOR 16 // 0x83 serial port 1 4554 // 0x8B not used 4555 #define ICM_VECTOR 18 // 0x93 compare registers CM0-CM7 4556 #define CTF_VECTOR 19 // 0x9B compare time overflow 4557 #define ICS_VECTOR 20 // 0xA3 compare register COMSET 4558 #define ICR_VECTOR 21 // 0xAB compare register COMCLR 4559 #define ICC_VECTOR 26 // 0xD3 compare event interrupt ICC10-ICC17 4560 #define CT1_VECTOR 27 // 0xDB compare timer 1 oveflow 4561 #endif 4562 4563 #ifdef MICROCONTROLLER_SAB80515 4564 #define TF2_VECTOR 5 // 0x2B timer 2 4565 #define EX2_VECTOR 5 // 0x2B external interrupt 2 4566 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt 4567 #define IEX2_VECTOR 9 // 0x4B external interrupt 2 4568 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 4569 #define IEX4_VECTOR 11 // 0x5B external interrupt 4 4570 #define IEX5_VECTOR 12 // 0x63 external interrupt 5 4571 #define IEX6_VECTOR 13 // 0x6B external interrupt 6 4572 #endif 4573 4574 #ifdef MICROCONTROLLER_SAB80515A 4575 #define TF2_VECTOR 5 // 0x2B timer 2 4576 #define EX2_VECTOR 5 // 0x2B external interrupt 2 4577 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt 4578 #define IEX2_VECTOR 9 // 0x4B external interrupt 2 4579 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 4580 #define IEX4_VECTOR 11 // 0x5B external interrupt 4 4581 #define IEX5_VECTOR 12 // 0x63 external interrupt 5 4582 #define IEX6_VECTOR 13 // 0x6B external interrupt 6 4583 #endif 4584 4585 #ifdef MICROCONTROLLER_SAB80517 4586 #define TF2_VECTOR 5 // 0x2B timer 2 4587 #define EX2_VECTOR 5 // 0x2B external interrupt 2 4588 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt 4589 #define IEX2_VECTOR 9 // 0x4B external interrupt 2 4590 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 4591 #define IEX4_VECTOR 11 // 0x5B external interrupt 4 4592 #define IEX5_VECTOR 12 // 0x63 external interrupt 5 4593 #define IEX6_VECTOR 13 // 0x6B external interrupt 6 4594 // 0x73 not used 4595 // 0x7B not used 4596 #define SI1_VECTOR 16 // 0x83 serial port 1 4597 // 0x8B not used 4598 // 0x93 not used 4599 #define COMPARE_VECTOR 19 // 0x9B compare 4600 #endif 4601 4602 #ifdef MICROCONTORLLER_T89C51RD2 4603 #define TF2_VECTOR 5 /* 0x2B timer 2 */ 4604 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */ 4605 #endif /* MICROCONTORLLER_T89C51RD2 */ 4606 4607 #endif // End of the header -> #ifndef MCS51REG_H 4608