1 /* $OpenBSD: if_iwxreg.h,v 1.55 2024/11/08 09:12:46 kettenis Exp $ */
2
3 /*-
4 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
5 * which were used as the reference documentation for this implementation.
6 *
7 ******************************************************************************
8 *
9 * This file is provided under a dual BSD/GPLv2 license. When using or
10 * redistributing this file, you may do so under either license.
11 *
12 * GPL LICENSE SUMMARY
13 *
14 * Copyright(c) 2017 Intel Deutschland GmbH
15 * Copyright(c) 2018 - 2019 Intel Corporation
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of version 2 of the GNU General Public License as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * General Public License for more details.
25 *
26 * BSD LICENSE
27 *
28 * Copyright(c) 2017 Intel Deutschland GmbH
29 * Copyright(c) 2018 - 2019 Intel Corporation
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 *
36 * * Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * * Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in
40 * the documentation and/or other materials provided with the
41 * distribution.
42 * * Neither the name Intel Corporation nor the names of its
43 * contributors may be used to endorse or promote products derived
44 * from this software without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 *
58 *****************************************************************************
59 */
60
61
62 /* maximum number of DRAM map entries supported by FW */
63 #define IWX_MAX_DRAM_ENTRY 64
64 #define IWX_CSR_CTXT_INFO_BA 0x40
65
66 /**
67 * enum iwx_context_info_flags - Context information control flags
68 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
69 * the init done for driver command that configures several system modes
70 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug
71 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump
72 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
73 * exponent, the actual size is 2**value, valid sizes are 8-2048.
74 * The value is four bits long. Maximum valid exponent is 12
75 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
76 * default is short format - not supported by the driver)
77 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position
78 * (values are IWX_CTXT_INFO_RB_SIZE_*K)
79 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
80 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
81 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
82 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
83 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
84 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
85 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
86 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
87 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
88 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
89 */
90 enum iwx_context_info_flags {
91 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0),
92 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1),
93 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2),
94 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4,
95 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8),
96 IWX_CTXT_INFO_RB_SIZE_POS = 9,
97 IWX_CTXT_INFO_RB_SIZE_1K = 0x1,
98 IWX_CTXT_INFO_RB_SIZE_2K = 0x2,
99 IWX_CTXT_INFO_RB_SIZE_4K = 0x4,
100 IWX_CTXT_INFO_RB_SIZE_8K = 0x8,
101 IWX_CTXT_INFO_RB_SIZE_12K = 0x9,
102 IWX_CTXT_INFO_RB_SIZE_16K = 0xa,
103 IWX_CTXT_INFO_RB_SIZE_20K = 0xb,
104 IWX_CTXT_INFO_RB_SIZE_24K = 0xc,
105 IWX_CTXT_INFO_RB_SIZE_28K = 0xd,
106 IWX_CTXT_INFO_RB_SIZE_32K = 0xe,
107 };
108
109 /*
110 * struct iwx_context_info_version - version structure
111 * @mac_id: SKU and revision id
112 * @version: context information version id
113 * @size: the size of the context information in DWs
114 */
115 struct iwx_context_info_version {
116 uint16_t mac_id;
117 uint16_t version;
118 uint16_t size;
119 uint16_t reserved;
120 } __packed;
121
122 /*
123 * struct iwx_context_info_control - version structure
124 * @control_flags: context information flags see &enum iwx_context_info_flags
125 */
126 struct iwx_context_info_control {
127 uint32_t control_flags;
128 uint32_t reserved;
129 } __packed;
130
131 /*
132 * struct iwx_context_info_dram - images DRAM map
133 * each entry in the map represents a DRAM chunk of up to 32 KB
134 * @umac_img: UMAC image DRAM map
135 * @lmac_img: LMAC image DRAM map
136 * @virtual_img: paged image DRAM map
137 */
138 struct iwx_context_info_dram {
139 uint64_t umac_img[IWX_MAX_DRAM_ENTRY];
140 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY];
141 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY];
142 } __packed;
143
144 struct iwx_pnvm_info_dram {
145 uint64_t pnvm_img[IWX_MAX_DRAM_ENTRY];
146 } __packed;
147
148 /*
149 * struct iwx_context_info_rbd_cfg - RBDs configuration
150 * @free_rbd_addr: default queue free RB CB base address
151 * @used_rbd_addr: default queue used RB CB base address
152 * @status_wr_ptr: default queue used RB status write pointer
153 */
154 struct iwx_context_info_rbd_cfg {
155 uint64_t free_rbd_addr;
156 uint64_t used_rbd_addr;
157 uint64_t status_wr_ptr;
158 } __packed;
159
160 /*
161 * struct iwx_context_info_hcmd_cfg - command queue configuration
162 * @cmd_queue_addr: address of command queue
163 * @cmd_queue_size: number of entries
164 */
165 struct iwx_context_info_hcmd_cfg {
166 uint64_t cmd_queue_addr;
167 uint8_t cmd_queue_size;
168 uint8_t reserved[7];
169 } __packed;
170
171 /*
172 * struct iwx_context_info_dump_cfg - Core Dump configuration
173 * @core_dump_addr: core dump (debug DRAM address) start address
174 * @core_dump_size: size, in DWs
175 */
176 struct iwx_context_info_dump_cfg {
177 uint64_t core_dump_addr;
178 uint32_t core_dump_size;
179 uint32_t reserved;
180 } __packed;
181
182 /*
183 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration
184 * @platform_nvm_addr: Platform NVM data start address
185 * @platform_nvm_size: size in DWs
186 */
187 struct iwx_context_info_pnvm_cfg {
188 uint64_t platform_nvm_addr;
189 uint32_t platform_nvm_size;
190 uint32_t reserved;
191 } __packed;
192
193 /*
194 * struct iwx_context_info_early_dbg_cfg - early debug configuration for
195 * dumping DRAM addresses
196 * @early_debug_addr: early debug start address
197 * @early_debug_size: size in DWs
198 */
199 struct iwx_context_info_early_dbg_cfg {
200 uint64_t early_debug_addr;
201 uint32_t early_debug_size;
202 uint32_t reserved;
203 } __packed;
204
205 /*
206 * struct iwx_context_info - device INIT configuration
207 * @version: version information of context info and HW
208 * @control: control flags of FH configurations
209 * @rbd_cfg: default RX queue configuration
210 * @hcmd_cfg: command queue configuration
211 * @dump_cfg: core dump data
212 * @edbg_cfg: early debug configuration
213 * @pnvm_cfg: platform nvm configuration
214 * @dram: firmware image addresses in DRAM
215 */
216 struct iwx_context_info {
217 struct iwx_context_info_version version;
218 struct iwx_context_info_control control;
219 uint64_t reserved0;
220 struct iwx_context_info_rbd_cfg rbd_cfg;
221 struct iwx_context_info_hcmd_cfg hcmd_cfg;
222 uint32_t reserved1[4];
223 struct iwx_context_info_dump_cfg dump_cfg;
224 struct iwx_context_info_early_dbg_cfg edbg_cfg;
225 struct iwx_context_info_pnvm_cfg pnvm_cfg;
226 uint32_t reserved2[16];
227 struct iwx_context_info_dram dram;
228 uint32_t reserved3[16];
229 } __packed;
230
231
232 /*
233 * Context info definitions for AX210 devices.
234 */
235
236 #define IWX_CSR_CTXT_INFO_BOOT_CTRL 0x0
237 #define IWX_CSR_CTXT_INFO_ADDR 0x118
238 #define IWX_CSR_IML_DATA_ADDR 0x120
239 #define IWX_CSR_IML_SIZE_ADDR 0x128
240 #define IWX_CSR_IML_RESP_ADDR 0x12c
241
242 /* Set bit for enabling automatic function boot */
243 #define IWX_CSR_AUTO_FUNC_BOOT_ENA (1 << 1)
244 /* Set bit for initiating function boot */
245 #define IWX_CSR_AUTO_FUNC_INIT (1 << 7)
246
247 /**
248 * iwx_prph_scratch_mtr_format - tfd size configuration
249 * @IWX_PRPH_MTR_FORMAT_16B: 16 bit tfd
250 * @IWX_PRPH_MTR_FORMAT_32B: 32 bit tfd
251 * @IWX_PRPH_MTR_FORMAT_64B: 64 bit tfd
252 * @IWX_PRPH_MTR_FORMAT_256B: 256 bit tfd
253 */
254 #define IWX_PRPH_MTR_FORMAT_16B 0x0
255 #define IWX_PRPH_MTR_FORMAT_32B 0x40000
256 #define IWX_PRPH_MTR_FORMAT_64B 0x80000
257 #define IWX_PRPH_MTR_FORMAT_256B 0xC0000
258
259 /**
260 * iwx_prph_scratch_flags - PRPH scratch control flags
261 * @IWX_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
262 * @IWX_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
263 * @IWX_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
264 * in hwm config.
265 * @IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
266 * @IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
267 * multicomm.
268 * @IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
269 * @IWX_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
270 * @IWX_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
271 * completion descriptor, 1 for responses (legacy)
272 * @IWX_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
273 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
274 * 3: 256 bit.
275 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
276 * by older firmware versions, so set IWX_PRPH_SCRATCH_RB_SIZE_4K
277 * appropriately; use the below values for this.
278 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
279 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
280 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
281 */
282 #define IWX_PRPH_SCRATCH_IMR_DEBUG_EN (1 << 1)
283 #define IWX_PRPH_SCRATCH_EARLY_DEBUG_EN (1 << 4)
284 #define IWX_PRPH_SCRATCH_EDBG_DEST_DRAM (1 << 8)
285 #define IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL (1 << 9)
286 #define IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER (1 << 10)
287 #define IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF (1 << 11)
288 #define IWX_PRPH_SCRATCH_RB_SIZE_4K (1 << 16)
289 #define IWX_PRPH_SCRATCH_MTR_MODE (1 << 17)
290 #define IWX_PRPH_SCRATCH_MTR_FORMAT ((1 << 18) | (1 << 19))
291 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK (0xf << 20)
292 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K (8 << 20)
293 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K (9 << 20)
294 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K (10 << 20)
295
296 /*
297 * struct iwx_prph_scratch_version - version structure
298 * @mac_id: SKU and revision id
299 * @version: prph scratch information version id
300 * @size: the size of the context information in DWs
301 * @reserved: reserved
302 */
303 struct iwx_prph_scratch_version {
304 uint16_t mac_id;
305 uint16_t version;
306 uint16_t size;
307 uint16_t reserved;
308 } __packed; /* PERIPH_SCRATCH_VERSION_S */
309
310 /*
311 * struct iwx_prph_scratch_control - control structure
312 * @control_flags: context information flags see &iwx_prph_scratch_flags
313 * @reserved: reserved
314 */
315 struct iwx_prph_scratch_control {
316 uint32_t control_flags;
317 uint32_t reserved;
318 } __packed; /* PERIPH_SCRATCH_CONTROL_S */
319
320 /*
321 * struct iwx_prph_scratch_pnvm_cfg - ror config
322 * @pnvm_base_addr: PNVM start address
323 * @pnvm_size: PNVM size in DWs
324 * @reserved: reserved
325 */
326 struct iwx_prph_scratch_pnvm_cfg {
327 uint64_t pnvm_base_addr;
328 uint32_t pnvm_size;
329 uint32_t reserved;
330 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
331
332 struct iwx_pnvm_section {
333 uint32_t offset;
334 const uint8_t data[];
335 } __packed;
336
337 /*
338 * struct iwx_prph_scratch_hwm_cfg - hwm config
339 * @hwm_base_addr: hwm start address
340 * @hwm_size: hwm size in DWs
341 * @debug_token_config: debug preset
342 */
343 struct iwx_prph_scratch_hwm_cfg {
344 uint64_t hwm_base_addr;
345 uint32_t hwm_size;
346 uint32_t debug_token_config;
347 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
348
349 /*
350 * struct iwx_prph_scratch_rbd_cfg - RBDs configuration
351 * @free_rbd_addr: default queue free RB CB base address
352 * @reserved: reserved
353 */
354 struct iwx_prph_scratch_rbd_cfg {
355 uint64_t free_rbd_addr;
356 uint32_t reserved;
357 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
358
359 /*
360 * struct iwx_prph_scratch_uefi_cfg - prph scratch reduce power table
361 * @base_addr: reduce power table address
362 * @size: table size in dwords
363 */
364 struct iwx_prph_scratch_uefi_cfg {
365 uint64_t base_addr;
366 uint32_t size;
367 uint32_t reserved;
368 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */
369
370 /*
371 * struct iwx_prph_scratch_ctrl_cfg - prph scratch ctrl and config
372 * @version: version information of context info and HW
373 * @control: control flags of FH configurations
374 * @pnvm_cfg: ror configuration
375 * @hwm_cfg: hwm configuration
376 * @rbd_cfg: default RX queue configuration
377 */
378 struct iwx_prph_scratch_ctrl_cfg {
379 struct iwx_prph_scratch_version version;
380 struct iwx_prph_scratch_control control;
381 struct iwx_prph_scratch_pnvm_cfg pnvm_cfg;
382 struct iwx_prph_scratch_hwm_cfg hwm_cfg;
383 struct iwx_prph_scratch_rbd_cfg rbd_cfg;
384 struct iwx_prph_scratch_uefi_cfg reduce_power_cfg;
385 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
386
387 /*
388 * struct iwx_prph_scratch - peripheral scratch mapping
389 * @ctrl_cfg: control and configuration of prph scratch
390 * @dram: firmware images addresses in DRAM
391 * @reserved: reserved
392 */
393 struct iwx_prph_scratch {
394 struct iwx_prph_scratch_ctrl_cfg ctrl_cfg;
395 uint32_t reserved[12];
396 struct iwx_context_info_dram dram;
397 } __packed; /* PERIPH_SCRATCH_S */
398
399 /*
400 * struct iwx_prph_info - peripheral information
401 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
402 * @ipc_status_mirror: reflects the value in the IPC Status CSR register
403 * @sleep_notif: indicates the peripheral sleep status
404 * @reserved: reserved
405 */
406 struct iwx_prph_info {
407 uint32_t boot_stage_mirror;
408 uint32_t ipc_status_mirror;
409 uint32_t sleep_notif;
410 uint32_t reserved;
411 } __packed; /* PERIPH_INFO_S */
412
413 /*
414 * struct iwx_context_info_gen3 - device INIT configuration
415 * @version: version of the context information
416 * @size: size of context information in DWs
417 * @config: context in which the peripheral would execute - a subset of
418 * capability csr register published by the peripheral
419 * @prph_info_base_addr: the peripheral information structure start address
420 * @cr_head_idx_arr_base_addr: the completion ring head index array
421 * start address
422 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
423 * start address
424 * @cr_tail_idx_arr_base_addr: the completion ring tail index array
425 * start address
426 * @tr_head_idx_arr_base_addr: the transfer ring head index array
427 * start address
428 * @cr_idx_arr_size: number of entries in the completion ring index array
429 * @tr_idx_arr_size: number of entries in the transfer ring index array
430 * @mtr_base_addr: the message transfer ring start address
431 * @mcr_base_addr: the message completion ring start address
432 * @mtr_size: number of entries which the message transfer ring can hold
433 * @mcr_size: number of entries which the message completion ring can hold
434 * @mtr_doorbell_vec: the doorbell vector associated with the message
435 * transfer ring
436 * @mcr_doorbell_vec: the doorbell vector associated with the message
437 * completion ring
438 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
439 * completing a transfer descriptor in the message transfer ring
440 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
441 * completing a completion descriptor in the message completion ring
442 * @mtr_opt_header_size: the size of the optional header in the transfer
443 * descriptor associated with the message transfer ring in DWs
444 * @mtr_opt_footer_size: the size of the optional footer in the transfer
445 * descriptor associated with the message transfer ring in DWs
446 * @mcr_opt_header_size: the size of the optional header in the completion
447 * descriptor associated with the message completion ring in DWs
448 * @mcr_opt_footer_size: the size of the optional footer in the completion
449 * descriptor associated with the message completion ring in DWs
450 * @msg_rings_ctrl_flags: message rings control flags
451 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
452 * after updating the Peripheral Information structure
453 * @prph_scratch_base_addr: the peripheral scratch structure start address
454 * @prph_scratch_size: the size of the peripheral scratch structure in DWs
455 * @reserved: reserved
456 */
457 struct iwx_context_info_gen3 {
458 uint16_t version;
459 uint16_t size;
460 uint32_t config;
461 uint64_t prph_info_base_addr;
462 uint64_t cr_head_idx_arr_base_addr;
463 uint64_t tr_tail_idx_arr_base_addr;
464 uint64_t cr_tail_idx_arr_base_addr;
465 uint64_t tr_head_idx_arr_base_addr;
466 uint16_t cr_idx_arr_size;
467 uint16_t tr_idx_arr_size;
468 uint64_t mtr_base_addr;
469 uint64_t mcr_base_addr;
470 uint16_t mtr_size;
471 uint16_t mcr_size;
472 uint16_t mtr_doorbell_vec;
473 uint16_t mcr_doorbell_vec;
474 uint16_t mtr_msi_vec;
475 uint16_t mcr_msi_vec;
476 uint8_t mtr_opt_header_size;
477 uint8_t mtr_opt_footer_size;
478 uint8_t mcr_opt_header_size;
479 uint8_t mcr_opt_footer_size;
480 uint16_t msg_rings_ctrl_flags;
481 uint16_t prph_info_msi_vec;
482 uint64_t prph_scratch_base_addr;
483 uint32_t prph_scratch_size;
484 uint32_t reserved;
485 } __packed; /* IPC_CONTEXT_INFO_S */
486
487 #define IWX_MGMT_TID 15
488
489 #define IWX_MQ_RX_TABLE_SIZE 512
490
491 /* cb size is the exponent */
492 #define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1))
493
494 /*
495 * CSR (control and status registers)
496 *
497 * CSR registers are mapped directly into PCI bus space, and are accessible
498 * whenever platform supplies power to device, even when device is in
499 * low power states due to driver-invoked device resets
500 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
501 *
502 * Use iwl_write32() and iwl_read32() family to access these registers;
503 * these provide simple PCI bus access, without waking up the MAC.
504 * Do not use iwl_write_direct32() family for these registers;
505 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
506 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
507 * the CSR registers.
508 *
509 * NOTE: Device does need to be awake in order to read this memory
510 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers
511 */
512 #define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
513 #define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
514 #define IWX_CSR_INT (0x008) /* host interrupt status/ack */
515 #define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */
516 #define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
517 #define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */
518 #define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
519 #define IWX_CSR_GP_CNTRL (0x024)
520
521 /* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */
522 #define IWX_CSR_INT_PERIODIC_REG (0x005)
523
524 /*
525 * Hardware revision info
526 * Bit fields:
527 * 31-16: Reserved
528 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions
529 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
530 * 1-0: "Dash" (-) value, as in A-1, etc.
531 */
532 #define IWX_CSR_HW_REV (0x028)
533
534 /*
535 * RF ID revision info
536 * Bit fields:
537 * 31:24: Reserved (set to 0x0)
538 * 23:12: Type
539 * 11:8: Step (A - 0x0, B - 0x1, etc)
540 * 7:4: Dash
541 * 3:0: Flavor
542 */
543 #define IWX_CSR_HW_RF_ID (0x09c)
544
545
546 #define IWX_CSR_GIO_REG (0x03C)
547
548 /*
549 * UCODE-DRIVER GP (general purpose) mailbox registers.
550 * SET/CLR registers set/clear bit(s) if "1" is written.
551 */
552 #define IWX_CSR_UCODE_DRV_GP1 (0x054)
553 #define IWX_CSR_UCODE_DRV_GP1_SET (0x058)
554 #define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c)
555 #define IWX_CSR_UCODE_DRV_GP2 (0x060)
556
557 #define IWX_CSR_MBOX_SET_REG (0x088)
558 #define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20
559
560 #define IWX_CSR_DRAM_INT_TBL_REG (0x0A0)
561 #define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
562
563 /* LTR control */
564 #define IWX_CSR_LTR_LONG_VAL_AD (0x0d4)
565 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000
566 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_MASK 0x1c000000
567 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_SHIFT 24
568 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_MASK 0x03ff0000
569 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_SHIFT 16
570 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000
571 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_MASK 0x00001c00
572 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_SHIFT 8
573 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff
574 #define IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC 2
575
576 /* GIO Chicken Bits (PCI Express bus link power management) */
577 #define IWX_CSR_GIO_CHICKEN_BITS (0x100)
578
579 #define IWX_CSR_DBG_HPET_MEM_REG (0x240)
580 #define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
581
582 /* Bits for IWX_CSR_HW_IF_CONFIG_REG */
583 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
584 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
585 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
586 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
587 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
588 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
589 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
590 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
591
592 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
593 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
594 #define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
595 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
596 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
597 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
598
599 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
600 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
601 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
602 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
603 #define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
604 #define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
605 #define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
606
607 #define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
608 #define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
609
610 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
611 * acknowledged (reset) by host writing "1" to flagged bits. */
612 #define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
613 #define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
614 #define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
615 #define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
616 #define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
617 #define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
618 #define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
619 #define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
620 #define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
621 #define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
622 #define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
623
624 #define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \
625 IWX_CSR_INT_BIT_HW_ERR | \
626 IWX_CSR_INT_BIT_FH_TX | \
627 IWX_CSR_INT_BIT_SW_ERR | \
628 IWX_CSR_INT_BIT_RF_KILL | \
629 IWX_CSR_INT_BIT_SW_RX | \
630 IWX_CSR_INT_BIT_WAKEUP | \
631 IWX_CSR_INT_BIT_ALIVE | \
632 IWX_CSR_INT_BIT_RX_PERIODIC)
633
634 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
635 #define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */
636 #define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
637 #define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
638 #define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
639 #define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
640 #define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
641
642 #define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \
643 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \
644 IWX_CSR_FH_INT_BIT_RX_CHNL0)
645
646 #define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \
647 IWX_CSR_FH_INT_BIT_TX_CHNL0)
648
649 /**
650 * struct iwx_rx_transfer_desc - transfer descriptor AX210
651 * @addr: ptr to free buffer start address
652 * @rbid: unique tag of the buffer
653 * @reserved: reserved
654 */
655 struct iwx_rx_transfer_desc {
656 uint16_t rbid;
657 uint16_t reserved[3];
658 uint64_t addr;
659 };
660
661 #define IWX_RX_CD_FLAGS_FRAGMENTED (1 << 0)
662
663 /**
664 * struct iwx_rx_completion_desc - completion descriptor AX210
665 * @reserved1: reserved
666 * @rbid: unique tag of the received buffer
667 * @flags: flags (0: fragmented, all others: reserved)
668 * @reserved2: reserved
669 */
670 struct iwx_rx_completion_desc {
671 uint32_t reserved1;
672 uint16_t rbid;
673 uint8_t flags;
674 uint8_t reserved2[25];
675 };
676
677 /* RESET */
678 #define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
679 #define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
680 #define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
681 #define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
682 #define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
683 #define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
684
685 /*
686 * GP (general purpose) CONTROL REGISTER
687 * Bit fields:
688 * 27: HW_RF_KILL_SW
689 * Indicates state of (platform's) hardware RF-Kill switch
690 * 26-24: POWER_SAVE_TYPE
691 * Indicates current power-saving mode:
692 * 000 -- No power saving
693 * 001 -- MAC power-down
694 * 010 -- PHY (radio) power-down
695 * 011 -- Error
696 * 9-6: SYS_CONFIG
697 * Indicates current system configuration, reflecting pins on chip
698 * as forced high/low by device circuit board.
699 * 4: GOING_TO_SLEEP
700 * Indicates MAC is entering a power-saving sleep power-down.
701 * Not a good time to access device-internal resources.
702 * 3: MAC_ACCESS_REQ
703 * Host sets this to request and maintain MAC wakeup, to allow host
704 * access to device-internal resources. Host must wait for
705 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
706 * device registers.
707 * 2: INIT_DONE
708 * Host sets this to put device into fully operational D0 power mode.
709 * Host resets this after SW_RESET to put device into low power mode.
710 * 0: MAC_CLOCK_READY
711 * Indicates MAC (ucode processor, etc.) is powered up and can run.
712 * Internal resources are accessible.
713 * NOTE: This does not indicate that the processor is actually running.
714 * NOTE: This does not indicate that device has completed
715 * init or post-power-down restore of internal SRAM memory.
716 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
717 * SRAM is restored and uCode is in normal operation mode.
718 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
719 * do not need to save/restore it.
720 * NOTE: After device reset, this bit remains "0" until host sets
721 * INIT_DONE
722 */
723 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
724 #define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
725 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
726 #define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
727
728 #define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
729
730 #define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
731 #define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
732 #define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
733
734
735 /* HW REV */
736 #define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
737 #define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
738 #define IWX_CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
739
740 #define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0)
741 #define IWX_CSR_HW_REV_TYPE_QU_B0 (0x0000334)
742 #define IWX_CSR_HW_REV_TYPE_QU_C0 (0x0000338)
743 #define IWX_CSR_HW_REV_TYPE_QUZ (0x0000354)
744 #define IWX_CSR_HW_REV_TYPE_SO (0x0000370)
745 #define IWX_CSR_HW_REV_TYPE_TY (0x0000420)
746
747 /* HW RFID */
748 #define IWX_CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
749 #define IWX_CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
750 #define IWX_CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
751 #define IWX_CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
752 #define IWX_CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28)
753 #define IWX_CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29)
754
755 /* CSR GIO */
756 #define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
757
758 /*
759 * UCODE-DRIVER GP (general purpose) mailbox register 1
760 * Host driver and uCode write and/or read this register to communicate with
761 * each other.
762 * Bit fields:
763 * 4: UCODE_DISABLE
764 * Host sets this to request permanent halt of uCode, same as
765 * sending CARD_STATE command with "halt" bit set.
766 * 3: CT_KILL_EXIT
767 * Host sets this to request exit from CT_KILL state, i.e. host thinks
768 * device temperature is low enough to continue normal operation.
769 * 2: CMD_BLOCKED
770 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
771 * to release uCode to clear all Tx and command queues, enter
772 * unassociated mode, and power down.
773 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
774 * 1: SW_BIT_RFKILL
775 * Host sets this when issuing CARD_STATE command to request
776 * device sleep.
777 * 0: MAC_SLEEP
778 * uCode sets this when preparing a power-saving power-down.
779 * uCode resets this when power-up is complete and SRAM is sane.
780 * NOTE: device saves internal SRAM data to host when powering down,
781 * and must restore this data after powering back up.
782 * MAC_SLEEP is the best indication that restore is complete.
783 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
784 * do not need to save/restore it.
785 */
786 #define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
787 #define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
788 #define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
789 #define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
790 #define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
791
792 /* GIO Chicken Bits (PCI Express bus link power management) */
793 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
794 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
795
796 /* HPET MEM debug */
797 #define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
798
799 /* DRAM INT TABLE */
800 #define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31)
801 #define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
802 #define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
803
804 /* 22000 configuration registers */
805
806 /*
807 * TFH Configuration register.
808 *
809 * BIT fields:
810 *
811 * Bits 3:0:
812 * Define the maximum number of pending read requests.
813 * Maximum configuration value allowed is 0xC
814 * Bits 9:8:
815 * Define the maximum transfer size. (64 / 128 / 256)
816 * Bit 10:
817 * When bit is set and transfer size is set to 128B, the TFH will enable
818 * reading chunks of more than 64B only if the read address is aligned to 128B.
819 * In case of DRAM read address which is not aligned to 128B, the TFH will
820 * enable transfer size which doesn't cross 64B DRAM address boundary.
821 */
822 #define IWX_TFH_TRANSFER_MODE (0x1F40)
823 #define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc
824 #define IWX_TFH_CHUNK_SIZE_128 (1 << 8)
825 #define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10)
826
827 /*
828 * Defines the offset address in dwords referring from the beginning of the
829 * Tx CMD which will be updated in DRAM.
830 * Note that the TFH offset address for Tx CMD update is always referring to
831 * the start of the TFD first TB.
832 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
833 */
834 #define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48)
835
836 /*
837 * Controls TX DMA operation
838 *
839 * BIT fields:
840 *
841 * Bits 31:30: Enable the SRAM DMA channel.
842 * Turning on bit 31 will kick the SRAM2DRAM DMA.
843 * Note that the sram2dram may be enabled only after configuring the DRAM and
844 * SRAM addresses registers and the byte count register.
845 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When
846 * set to 1 - interrupt is sent to the driver
847 * Bit 0: Indicates the snoop configuration
848 */
849 #define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60)
850 #define IWX_TFH_SRV_DMA_SNOOP (1 << 0)
851 #define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24)
852 #define IWX_TFH_SRV_DMA_START (1U << 31)
853
854 /* Defines the DMA SRAM write start address to transfer a data block */
855 #define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64)
856
857 /* Defines the 64bits DRAM start address to read the DMA data block from */
858 #define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68)
859
860 /*
861 * Defines the number of bytes to transfer from DRAM to SRAM.
862 * Note that this register may be configured with non-dword aligned size.
863 */
864 #define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70)
865
866 /* 9000 rx series registers */
867
868 #define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
869 #define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
870 /* Write index table */
871 #define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080
872 #define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4)
873 /* Write index table - shadow registers */
874 #define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
875 #define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
876 /* Read index table */
877 #define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0
878 #define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4)
879 /* Used list table */
880 #define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
881 #define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
882 /* Write index table */
883 #define IWX_RFH_Q0_URBDCB_WIDX 0xA08180
884 #define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4)
885 #define IWX_RFH_Q0_URBDCB_VAID 0xA081C0
886 #define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4)
887 /* stts */
888 #define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
889 #define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
890
891 #define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280
892 #define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8)
893 #define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300
894 #define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8)
895
896 /**
897 * RFH Status Register
898 *
899 * Bit fields:
900 *
901 * Bit 29: RBD_FETCH_IDLE
902 * This status flag is set by the RFH when there is no active RBD fetch from
903 * DRAM.
904 * Once the RFH RBD controller starts fetching (or when there is a pending
905 * RBD read response from DRAM), this flag is immediately turned off.
906 *
907 * Bit 30: SRAM_DMA_IDLE
908 * This status flag is set by the RFH when there is no active transaction from
909 * SRAM to DRAM.
910 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
911 *
912 * Bit 31: RXF_DMA_IDLE
913 * This status flag is set by the RFH when there is no active transaction from
914 * RXF to DRAM.
915 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
916 */
917 #define IWX_RFH_GEN_STATUS 0xA09808
918 #define IWX_RFH_GEN_STATUS_GEN3 0xA07824
919 #define IWX_RBD_FETCH_IDLE (1 << 29)
920 #define IWX_SRAM_DMA_IDLE (1 << 30)
921 #define IWX_RXF_DMA_IDLE (1U << 31)
922
923 /* DMA configuration */
924 #define IWX_RFH_RXF_DMA_CFG 0xA09820
925 #define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880
926 /* RB size */
927 #define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
928 #define IWX_RFH_RXF_DMA_RB_SIZE_POS 16
929 #define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
930 #define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
931 #define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
932 #define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
933 #define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
934 #define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS)
935 #define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS)
936 #define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS)
937 #define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS)
938 #define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS)
939 /* RB Circular Buffer size:defines the table sizes in RBD units */
940 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
941 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20
942 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
943 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
944 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
945 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
946 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
947 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
948 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
949 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
950 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
951 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
952 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24
953 #define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS)
954 #define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
955 #define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
956 #define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
957 #define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31)
958
959 #define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C
960
961 #define IWX_RFH_GEN_CFG 0xA09800
962 #define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)
963 #define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)
964 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
965 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
966 /* the driver assumes everywhere that the default RXQ is 0 */
967 #define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
968
969 /* end of 9000 rx series registers */
970
971 /*
972 * This register is written by driver and is read by uCode during boot flow.
973 * Note this address is cleared after MAC reset.
974 */
975 #define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40)
976 #define IWX_UREG_CPU_INIT_RUN (0xa05c44)
977
978 /*
979 * HBUS (Host-side Bus)
980 *
981 * HBUS registers are mapped directly into PCI bus space, but are used
982 * to indirectly access device's internal memory or registers that
983 * may be powered-down.
984 *
985 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
986 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
987 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
988 * internal resources.
989 *
990 * Do not use iwl_write32()/iwl_read32() family to access these registers;
991 * these provide only simple PCI bus access, without waking up the MAC.
992 */
993 #define IWX_HBUS_BASE (0x400)
994
995 /*
996 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
997 * structures, error log, event log, verifying uCode load).
998 * First write to address register, then read from or write to data register
999 * to complete the job. Once the address register is set up, accesses to
1000 * data registers auto-increment the address by one dword.
1001 * Bit usage for address registers (read or write):
1002 * 0-31: memory address within device
1003 */
1004 #define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c)
1005 #define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010)
1006 #define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018)
1007 #define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c)
1008
1009 /*
1010 * Registers for accessing device's internal peripheral registers
1011 * (e.g. SCD, BSM, etc.). First write to address register,
1012 * then read from or write to data register to complete the job.
1013 * Bit usage for address registers (read or write):
1014 * 0-15: register address (offset) within device
1015 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
1016 */
1017 #define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044)
1018 #define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048)
1019 #define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c)
1020 #define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050)
1021
1022 /* enable the ID buf for read */
1023 #define IWX_WFPM_PS_CTL_CLR 0xa0300c
1024 #define IWX_WFMP_MAC_ADDR_0 0xa03080
1025 #define IWX_WFMP_MAC_ADDR_1 0xa03084
1026 #define IWX_LMPM_PMG_EN 0xa01cec
1027 #define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
1028 #define IWX_RFIC_REG_RD 0xad0470
1029 #define IWX_WFPM_CTRL_REG 0xa03030
1030 #define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
1031 #define IWX_ENABLE_WFPM 0x80000000
1032
1033 #define IWX_AUX_MISC_MASTER1_EN 0xa20818
1034 #define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
1035 #define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
1036 #define IWX_RSA_ENABLE 0xa24b08
1037 #define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0
1038 #define IWX_PREG_PRPH_WPROT_9000 0xa04ce0
1039 #define IWX_PREG_PRPH_WPROT_22000 0xa04d00
1040 #define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78
1041 #define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000
1042 #define IWX_SB_CFG_BASE_OVERRIDE 0xa20000
1043 #define IWX_SB_MODIFY_CFG_FLAG 0xa03088
1044 #define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0
1045 #define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4
1046
1047 #define IWX_UREG_CHICK 0xa05c00
1048 #define IWX_UREG_CHICK_MSI_ENABLE (1 << 24)
1049 #define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25)
1050
1051 #define IWX_HPM_DEBUG 0xa03440
1052 #define IWX_PERSISTENCE_BIT (1 << 12)
1053 #define IWX_PREG_WFPM_ACCESS (1 << 12)
1054
1055 #define IWX_HPM_HIPM_GEN_CFG 0xa03458
1056 #define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0)
1057 #define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1)
1058 #define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10)
1059
1060 #define IWX_UREG_DOORBELL_TO_ISR6 0xa05c04
1061 #define IWX_UREG_DOORBELL_TO_ISR6_NMI_BIT (1 << 0)
1062 #define IWX_UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE ((1 << 0) | (1 << 1))
1063 #define IWX_UREG_DOORBELL_TO_ISR6_SUSPEND (1 << 18)
1064 #define IWX_UREG_DOORBELL_TO_ISR6_RESUME (1 << 19)
1065 #define IWX_UREG_DOORBELL_TO_ISR6_PNVM (1 << 20)
1066
1067 /* LTR control (Qu only) */
1068 #define IWX_HPM_MAC_LTR_CSR 0xa0348c
1069 #define IWX_HPM_MAC_LRT_ENABLE_ALL 0xf
1070 /* also uses CSR_LTR_* for values */
1071 #define IWX_HPM_UMAC_LTR 0xa03480
1072
1073 /*
1074 * Per-Tx-queue write pointer (index, really!)
1075 * Indicates index to next TFD that driver will fill (1 past latest filled).
1076 * Bit usage:
1077 * 0-7: queue write index
1078 * 11-8: queue selector
1079 */
1080 #define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060)
1081
1082 /**********************************************************
1083 * CSR values
1084 **********************************************************/
1085 /*
1086 * host interrupt timeout value
1087 * used with setting interrupt coalescing timer
1088 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1089 *
1090 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1091 */
1092 #define IWX_HOST_INT_TIMEOUT_MAX (0xFF)
1093 #define IWX_HOST_INT_TIMEOUT_DEF (0x40)
1094 #define IWX_HOST_INT_TIMEOUT_MIN (0x0)
1095 #define IWX_HOST_INT_OPER_MODE (1U << 31)
1096
1097 /*****************************************************************************
1098 * MSIX related registers *
1099 *****************************************************************************/
1100
1101 #define IWX_CSR_MSIX_BASE (0x2000)
1102 #define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800)
1103 #define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804)
1104 #define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808)
1105 #define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C)
1106 #define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810)
1107 #define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880)
1108 #define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890)
1109 #define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000)
1110 #define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause))
1111 #define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause))
1112
1113 /*
1114 * Causes for the FH register interrupts
1115 */
1116 enum msix_fh_int_causes {
1117 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0),
1118 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1),
1119 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16),
1120 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17),
1121 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19),
1122 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21),
1123 };
1124
1125 /*
1126 * Causes for the HW register interrupts
1127 */
1128 enum mix_hw_int_causes {
1129 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0),
1130 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1),
1131 IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE = (1 << 2),
1132 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5),
1133 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6),
1134 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7),
1135 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8),
1136 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25),
1137 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26),
1138 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27),
1139 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29),
1140 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30),
1141 };
1142
1143 /*
1144 * Registers to map causes to vectors
1145 */
1146 enum msix_ivar_for_cause {
1147 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0,
1148 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1,
1149 IWX_MSIX_IVAR_CAUSE_S2D = 0x3,
1150 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5,
1151 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10,
1152 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11,
1153 IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE = 0x12,
1154 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16,
1155 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17,
1156 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18,
1157 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29,
1158 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a,
1159 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b,
1160 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d,
1161 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e,
1162 };
1163
1164 #define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7)
1165 #define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)
1166
1167 #define IWX_CSR_ADDR_BASE(sc) ((sc)->mac_addr_from_csr)
1168 #define IWX_CSR_MAC_ADDR0_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x00)
1169 #define IWX_CSR_MAC_ADDR1_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x04)
1170 #define IWX_CSR_MAC_ADDR0_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x08)
1171 #define IWX_CSR_MAC_ADDR1_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x0c)
1172
1173 /**
1174 * uCode API flags
1175 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
1176 * was a separate TLV but moved here to save space.
1177 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
1178 * treats good CRC threshold as a boolean
1179 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
1180 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
1181 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
1182 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
1183 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
1184 * offload profile config command.
1185 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
1186 * (rather than two) IPv6 addresses
1187 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
1188 * from the probe request template.
1189 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
1190 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
1191 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
1192 * single bound interface).
1193 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
1194 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
1195 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
1196 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
1197 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
1198 *
1199 */
1200 #define IWX_UCODE_TLV_FLAGS_PAN (1 << 0)
1201 #define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)
1202 #define IWX_UCODE_TLV_FLAGS_MFP (1 << 2)
1203 #define IWX_UCODE_TLV_FLAGS_P2P (1 << 3)
1204 #define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)
1205 #define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)
1206 #define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)
1207 #define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)
1208 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)
1209 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)
1210 #define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21)
1211 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)
1212 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)
1213 #define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)
1214 #define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)
1215 #define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)
1216 #define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)
1217 #define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)
1218 #define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)
1219
1220 #define IWX_UCODE_TLV_FLAG_BITS \
1221 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
1222
1223 /**
1224 * uCode TLV api
1225 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
1226 * longer than the passive one, which is essential for fragmented scan.
1227 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
1228 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
1229 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
1230 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format
1231 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
1232 * (command version 3) that supports per-chain limits
1233 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
1234 * iteration complete notification, and the timestamp reported for RX
1235 * received during scan, are reported in TSF of the mac specified in the
1236 * scan request.
1237 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
1238 * ADD_MODIFY_STA_KEY_API_S_VER_2.
1239 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment.
1240 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
1241 * instead of 3.
1242 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
1243 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of
1244 * SCAN_CONFIG_DB_CMD_API_S.
1245 *
1246 * @IWX_NUM_UCODE_TLV_API: number of bits used
1247 */
1248 #define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8
1249 #define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9
1250 #define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14
1251 #define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18
1252 #define IWX_UCODE_TLV_API_NEW_VERSION 20
1253 #define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24
1254 #define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27
1255 #define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28
1256 #define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29
1257 #define IWX_UCODE_TLV_API_STA_TYPE 30
1258 #define IWX_UCODE_TLV_API_NAN2_VER2 31
1259 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32
1260 #define IWX_UCODE_TLV_API_NEW_RX_STATS 35
1261 #define IWX_UCODE_TLV_API_WOWLAN_KEY_MATERIAL 36
1262 #define IWX_UCODE_TLV_API_QUOTA_LOW_LATENCY 38
1263 #define IWX_UCODE_TLV_API_DEPRECATE_TTAK 41
1264 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42
1265 #define IWX_UCODE_TLV_API_NAN_NOTIF_V2 43
1266 #define IWX_UCODE_TLV_API_FRAG_EBS 44
1267 #define IWX_UCODE_TLV_API_REDUCE_TX_POWER 45
1268 #define IWX_UCODE_TLV_API_SHORT_BEACON_NOTIF 46
1269 #define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47
1270 #define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48
1271 #define IWX_UCODE_TLV_API_FTM_NEW_RANGE_REQ 49
1272 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56
1273 #define IWX_UCODE_TLV_API_SCAN_OFFLOAD_CHANS 50
1274 #define IWX_UCODE_TLV_API_MBSSID_HE 52
1275 #define IWX_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE 53
1276 #define IWX_UCODE_TLV_API_FTM_RTT_ACCURACY 54
1277 #define IWX_UCODE_TLV_API_SAR_TABLE_VER 55
1278 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56
1279 #define IWX_UCODE_TLV_API_ADWELL_HB_DEF_N_AP 57
1280 #define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58
1281 #define IWX_UCODE_TLV_API_BAND_IN_RX_DATA 59
1282 #define IWX_NUM_UCODE_TLV_API 128
1283
1284 #define IWX_UCODE_TLV_API_BITS \
1285 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"
1286
1287 /**
1288 * uCode capabilities
1289 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
1290 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
1291 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
1292 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
1293 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
1294 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
1295 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
1296 * tx power value into TPC Report action frame and Link Measurement Report
1297 * action frame
1298 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
1299 * channel in DS parameter set element in probe requests.
1300 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
1301 * probe requests.
1302 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
1303 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
1304 * which also implies support for the scheduler configuration command
1305 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
1306 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
1307 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
1308 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
1309 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
1310 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
1311 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
1312 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
1313 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
1314 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
1315 * sources for the MCC. This TLV bit is a future replacement to
1316 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
1317 * is supported.
1318 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
1319 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
1320 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
1321 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
1322 * 0=no support)
1323 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band
1324 * (6 GHz).
1325 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
1326 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
1327 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
1328 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
1329 * antenna the beacon should be transmitted
1330 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
1331 * from AP and will send it upon d0i3 exit.
1332 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
1333 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
1334 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
1335 * thresholds reporting
1336 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
1337 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
1338 * regular image.
1339 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
1340 * memory addresses from the firmware.
1341 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
1342 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
1343 * 0=no support)
1344 *
1345 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used
1346 */
1347 #define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0
1348 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1
1349 #define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2
1350 #define IWX_UCODE_TLV_CAPA_BEAMFORMER 3
1351 #define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5
1352 #define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6
1353 #define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8
1354 #define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9
1355 #define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10
1356 #define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11
1357 #define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12
1358 #define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13
1359 #define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17
1360 #define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18
1361 #define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19
1362 #define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20
1363 #define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21
1364 #define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22
1365 #define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26
1366 #define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28
1367 #define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29
1368 #define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30
1369 #define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31
1370 #define IWX_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG 32
1371 #define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34
1372 #define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35
1373 #define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37
1374 #define IWX_UCODE_TLV_CAPA_STA_PM_NOTIF 38
1375 #define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39
1376 #define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40
1377 #define IWX_UCODE_TLV_CAPA_D0I3_END_FIRST 41
1378 #define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43
1379 #define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44
1380 #define IWX_UCODE_TLV_CAPA_COEX_SCHEMA_2 45
1381 #define IWX_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD 46
1382 #define IWX_UCODE_TLV_CAPA_FTM_CALIBRATED 47
1383 #define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48
1384 #define IWX_UCODE_TLV_CAPA_CS_MODIFY 49
1385 #define IWX_UCODE_TLV_CAPA_SET_LTR_GEN2 50
1386 #define IWX_UCODE_TLV_CAPA_SET_PPAG 52
1387 #define IWX_UCODE_TLV_CAPA_TAS_CFG 53
1388 #define IWX_UCODE_TLV_CAPA_SESSION_PROT_CMD 54
1389 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56
1390 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57
1391 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58
1392 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56
1393 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57
1394 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58
1395 #define IWX_UCODE_TLV_CAPA_BAID_ML_SUPPORT 63
1396 #define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64
1397 #define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65
1398 #define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67
1399 #define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68
1400 #define IWX_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD 70
1401 #define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71
1402 #define IWX_UCODE_TLV_CAPA_BEACON_STORING 72
1403 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V3 73
1404 #define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74
1405 #define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75
1406 #define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76
1407 #define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77
1408 #define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79
1409 #define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80
1410 #define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81
1411 #define IWX_UCODE_TLV_CAPA_TX_POWER_ACK 84
1412 #define IWX_UCODE_TLV_CAPA_D3_DEBUG 87
1413 #define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88
1414 #define IWX_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT 89
1415 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING 90
1416 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING_V2 91
1417 #define IWX_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP 92
1418 #define IWX_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP 93
1419 #define IWX_UCODE_TLV_CAPA_MLME_OFFLOAD 96
1420 #define IWX_UCODE_TLV_CAPA_BIGTK_SUPPORT 100
1421 #define IWX_UCODE_TLV_CAPA_RFIM_SUPPORT 102
1422 #define IWX_UCODE_TLV_CAPA_MLD_API_SUPPORT 110
1423
1424 #define IWX_NUM_UCODE_TLV_CAPA 128
1425
1426 /*
1427 * For 16.0 uCode and above, there is no differentiation between sections,
1428 * just an offset to the HW address.
1429 */
1430 #define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
1431 #define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB
1432
1433 /* uCode version contains 4 values: Major/Minor/API/Serial */
1434 #define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
1435 #define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
1436 #define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
1437 #define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
1438
1439 /*
1440 * Calibration control struct.
1441 * Sent as part of the phy configuration command.
1442 * @flow_trigger: bitmap for which calibrations to perform according to
1443 * flow triggers.
1444 * @event_trigger: bitmap for which calibrations to perform according to
1445 * event triggers.
1446 */
1447 struct iwx_tlv_calib_ctrl {
1448 uint32_t flow_trigger;
1449 uint32_t event_trigger;
1450 } __packed;
1451
1452 #define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0
1453 #define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS)
1454 #define IWX_FW_PHY_CFG_RADIO_STEP_POS 2
1455 #define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS)
1456 #define IWX_FW_PHY_CFG_RADIO_DASH_POS 4
1457 #define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS)
1458 #define IWX_FW_PHY_CFG_TX_CHAIN_POS 16
1459 #define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS)
1460 #define IWX_FW_PHY_CFG_RX_CHAIN_POS 20
1461 #define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS)
1462
1463 /**
1464 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW.
1465 * @cipher: a cipher suite selector
1466 * @flags: cipher scheme flags (currently reserved for a future use)
1467 * @hdr_len: a size of MPDU security header
1468 * @pn_len: a size of PN
1469 * @pn_off: an offset of pn from the beginning of the security header
1470 * @key_idx_off: an offset of key index byte in the security header
1471 * @key_idx_mask: a bit mask of key_idx bits
1472 * @key_idx_shift: bit shift needed to get key_idx
1473 * @mic_len: mic length in bytes
1474 * @hw_cipher: a HW cipher index used in host commands
1475 */
1476 struct iwx_fw_cipher_scheme {
1477 uint32_t cipher;
1478 uint8_t flags;
1479 uint8_t hdr_len;
1480 uint8_t pn_len;
1481 uint8_t pn_off;
1482 uint8_t key_idx_off;
1483 uint8_t key_idx_mask;
1484 uint8_t key_idx_shift;
1485 uint8_t mic_len;
1486 uint8_t hw_cipher;
1487 } __packed;
1488
1489 /**
1490 * struct iwx_fw_cscheme_list - a cipher scheme list
1491 * @size: a number of entries
1492 * @cs: cipher scheme entries
1493 */
1494 struct iwx_fw_cscheme_list {
1495 uint8_t size;
1496 struct iwx_fw_cipher_scheme cs[];
1497 } __packed;
1498
1499 /* v1/v2 uCode file layout */
1500 struct iwx_ucode_header {
1501 uint32_t ver; /* major/minor/API/serial */
1502 union {
1503 struct {
1504 uint32_t inst_size; /* bytes of runtime code */
1505 uint32_t data_size; /* bytes of runtime data */
1506 uint32_t init_size; /* bytes of init code */
1507 uint32_t init_data_size; /* bytes of init data */
1508 uint32_t boot_size; /* bytes of bootstrap code */
1509 uint8_t data[0]; /* in same order as sizes */
1510 } v1;
1511 struct {
1512 uint32_t build; /* build number */
1513 uint32_t inst_size; /* bytes of runtime code */
1514 uint32_t data_size; /* bytes of runtime data */
1515 uint32_t init_size; /* bytes of init code */
1516 uint32_t init_data_size; /* bytes of init data */
1517 uint32_t boot_size; /* bytes of bootstrap code */
1518 uint8_t data[0]; /* in same order as sizes */
1519 } v2;
1520 } u;
1521 };
1522
1523 /*
1524 * new TLV uCode file layout
1525 *
1526 * The new TLV file format contains TLVs, that each specify
1527 * some piece of data.
1528 */
1529
1530 #define IWX_UCODE_TLV_INVALID 0 /* unused */
1531 #define IWX_UCODE_TLV_INST 1
1532 #define IWX_UCODE_TLV_DATA 2
1533 #define IWX_UCODE_TLV_INIT 3
1534 #define IWX_UCODE_TLV_INIT_DATA 4
1535 #define IWX_UCODE_TLV_BOOT 5
1536 #define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */
1537 #define IWX_UCODE_TLV_PAN 7
1538 #define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8
1539 #define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9
1540 #define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10
1541 #define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11
1542 #define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12
1543 #define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13
1544 #define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14
1545 #define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15
1546 #define IWX_UCODE_TLV_WOWLAN_INST 16
1547 #define IWX_UCODE_TLV_WOWLAN_DATA 17
1548 #define IWX_UCODE_TLV_FLAGS 18
1549 #define IWX_UCODE_TLV_SEC_RT 19
1550 #define IWX_UCODE_TLV_SEC_INIT 20
1551 #define IWX_UCODE_TLV_SEC_WOWLAN 21
1552 #define IWX_UCODE_TLV_DEF_CALIB 22
1553 #define IWX_UCODE_TLV_PHY_SKU 23
1554 #define IWX_UCODE_TLV_SECURE_SEC_RT 24
1555 #define IWX_UCODE_TLV_SECURE_SEC_INIT 25
1556 #define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26
1557 #define IWX_UCODE_TLV_NUM_OF_CPU 27
1558 #define IWX_UCODE_TLV_CSCHEME 28
1559 #define IWX_UCODE_TLV_API_CHANGES_SET 29
1560 #define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30
1561 #define IWX_UCODE_TLV_N_SCAN_CHANNELS 31
1562 #define IWX_UCODE_TLV_PAGING 32
1563 #define IWX_UCODE_TLV_SEC_RT_USNIFFER 34
1564 #define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35
1565 #define IWX_UCODE_TLV_FW_VERSION 36
1566 #define IWX_UCODE_TLV_FW_DBG_DEST 38
1567 #define IWX_UCODE_TLV_FW_DBG_CONF 39
1568 #define IWX_UCODE_TLV_FW_DBG_TRIGGER 40
1569 #define IWX_UCODE_TLV_CMD_VERSIONS 48
1570 #define IWX_UCODE_TLV_FW_GSCAN_CAPA 50
1571 #define IWX_UCODE_TLV_FW_MEM_SEG 51
1572 #define IWX_UCODE_TLV_IML 52
1573 #define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53
1574 #define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54
1575 #define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55
1576 #define IWX_UCODE_TLV_FW_RECOVERY_INFO 57
1577 #define IWX_UCODE_TLV_HW_TYPE 58
1578 #define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59
1579 #define IWX_UCODE_TLV_FW_FSEQ_VERSION 60
1580 #define IWX_UCODE_TLV_PHY_INTEGRATION_VERSION 61
1581 #define IWX_UCODE_TLV_PNVM_VERSION 62
1582 #define IWX_UCODE_TLV_PNVM_SKU 64
1583
1584 #define IWX_UCODE_TLV_SEC_TABLE_ADDR 66
1585 #define IWX_UCODE_TLV_D3_KEK_KCK_ADDR 67
1586 #define IWX_UCODE_TLV_CURRENT_PC 68
1587
1588 #define IWX_UCODE_TLV_CONST_BASE 0x100
1589 #define IWX_UCODE_TLV_FW_NUM_STATIONS (IWX_UCODE_TLV_CONST_BASE + 0)
1590 #define IWX_UCODE_TLV_FW_NUM_BEACONS (IWX_UCODE_TLV_CONST_BASE + 2)
1591
1592 #define IWX_UCODE_TLV_DEBUG_BASE 0x1000005
1593 #define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0)
1594 #define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1)
1595 #define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2)
1596 #define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3)
1597 #define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4)
1598 #define IWX_UCODE_TLV_TYPE_CONF_SET (IWX_UCODE_TLV_DEBUG_BASE + 5)
1599 #define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_CONF_SET
1600
1601
1602 struct iwx_ucode_tlv {
1603 uint32_t type; /* see above */
1604 uint32_t length; /* not including type/length fields */
1605 uint8_t data[0];
1606 };
1607
1608 struct iwx_ucode_api {
1609 uint32_t api_index;
1610 uint32_t api_flags;
1611 } __packed;
1612
1613 struct iwx_ucode_capa {
1614 uint32_t api_index;
1615 uint32_t api_capa;
1616 } __packed;
1617
1618 #define IWX_TLV_UCODE_MAGIC 0x0a4c5749
1619
1620 struct iwx_tlv_ucode_header {
1621 /*
1622 * The TLV style ucode header is distinguished from
1623 * the v1/v2 style header by first four bytes being
1624 * zero, as such is an invalid combination of
1625 * major/minor/API/serial versions.
1626 */
1627 uint32_t zero;
1628 uint32_t magic;
1629 uint8_t human_readable[64];
1630 uint32_t ver; /* major/minor/API/serial */
1631 uint32_t build;
1632 uint64_t ignore;
1633 /*
1634 * The data contained herein has a TLV layout,
1635 * see above for the TLV header and types.
1636 * Note that each TLV is padded to a length
1637 * that is a multiple of 4 for alignment.
1638 */
1639 uint8_t data[0];
1640 };
1641
1642 /*
1643 * Registers in this file are internal, not PCI bus memory mapped.
1644 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers.
1645 */
1646 #define IWX_PRPH_BASE (0x00000)
1647 #define IWX_PRPH_END (0xFFFFF)
1648
1649 /****************************/
1650 /* Flow Handler Definitions */
1651 /****************************/
1652
1653 /**
1654 * struct iwx_rb_status - receive buffer status
1655 * host memory mapped FH registers
1656 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1657 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1658 * @finished_rb_num [0:11] - Indicates the index of the current RB
1659 * in which the last frame was written to
1660 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1661 * which was transferred
1662 */
1663 struct iwx_rb_status {
1664 uint16_t closed_rb_num;
1665 uint16_t closed_fr_num;
1666 uint16_t finished_rb_num;
1667 uint16_t finished_fr_nam;
1668 uint32_t unused;
1669 } __packed;
1670
1671
1672 #define IWX_TFD_QUEUE_SIZE_MAX (256)
1673 #define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536)
1674 /* cb size is the exponent - 3 */
1675 #define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3)
1676 #define IWX_TFD_QUEUE_SIZE_BC_DUP (64)
1677 #define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \
1678 IWX_TFD_QUEUE_SIZE_BC_DUP)
1679 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_AX210 1024
1680 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4)
1681 #define IWX_TFH_NUM_TBS 25
1682
1683 /**
1684 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor
1685 *
1686 * This structure contains dma address and length of transmission address
1687 *
1688 * @tb_len length of the tx buffer
1689 * @addr 64 bits dma address
1690 */
1691 struct iwx_tfh_tb {
1692 uint16_t tb_len;
1693 uint64_t addr;
1694 } __packed;
1695
1696 /**
1697 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1698 * Both driver and device share these circular buffers, each of which must be
1699 * contiguous 256 TFDs.
1700 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
1701 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
1702 *
1703 * Each TFD contains pointer/size information for up to 25 data buffers
1704 * in host DRAM. These buffers collectively contain the (one) frame described
1705 * by the TFD. Each buffer must be a single contiguous block of memory within
1706 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1707 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1708 * Tx frame, up to 8 KBytes in size.
1709 *
1710 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1711 */
1712
1713 /**
1714 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD)
1715 * @ num_tbs 0-4 number of active tbs
1716 * 5 -15 reserved
1717 * @ tbs[25] transmit frame buffer descriptors
1718 * @ __pad padding
1719 */
1720 struct iwx_tfh_tfd {
1721 uint16_t num_tbs;
1722 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS];
1723 uint32_t __pad;
1724 } __packed;
1725
1726 /* Fixed (non-configurable) rx data from phy */
1727
1728 /**
1729 * struct iwx_agn_schedq_bc_tbl scheduler byte count table
1730 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR
1731 * @tfd_offset 0-11 - tx command byte count
1732 * 12-13 - number of 64 byte chunks
1733 * 14-15 - reserved
1734 */
1735 struct iwx_agn_scd_bc_tbl {
1736 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE];
1737 } __packed;
1738
1739 /**
1740 * struct iwx_gen3_bc_tbl_entry scheduler byte count table entry gen3
1741 * For AX210 and up, the table no longer needs to be contiguous in memory.
1742 * @tfd_offset: 0-13 - tx command byte count
1743 * 14-15 - number of 64 byte chunks
1744 */
1745 struct iwx_gen3_bc_tbl_entry {
1746 uint16_t tfd_offset;
1747 } __packed;
1748
1749 /**
1750 * DQA - Dynamic Queue Allocation -introduction
1751 *
1752 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi
1753 * to allow dynamic allocation of queues on-demand, rather than allocate them
1754 * statically ahead of time. Ideally, we would like to allocate one queue
1755 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2
1756 * even if it also needs to send traffic to a sleeping STA1, without being
1757 * blocked by the sleeping station.
1758 *
1759 * Although the queues in DQA mode are dynamically allocated, there are still
1760 * some queues that are statically allocated:
1761 * TXQ #0 - command queue
1762 * TXQ #1 - aux frames
1763 */
1764
1765 /* static DQA Tx queue numbers */
1766 #define IWX_DQA_CMD_QUEUE 0
1767 #define IWX_DQA_AUX_QUEUE 1
1768
1769 #define IWX_DQA_INJECT_MONITOR_QUEUE 1 /* used in monitor mode only */
1770 #define IWX_DQA_MGMT_QUEUE 1 /* default queue other modes */
1771
1772 /* Reserve 8 DQA Tx queues for QoS data frames. */
1773 #define IWX_MAX_TID_COUNT 8
1774 #define IWX_FIRST_AGG_TX_QUEUE (IWX_DQA_MGMT_QUEUE + 1)
1775 #define IWX_LAST_AGG_TX_QUEUE (IWX_FIRST_AGG_TX_QUEUE + IWX_MAX_TID_COUNT - 1)
1776 #define IWX_NUM_TX_QUEUES (IWX_LAST_AGG_TX_QUEUE + 1)
1777
1778 /**
1779 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1780 * can keep track of at one time when creating block-ack chains of frames.
1781 * Note that "64" matches the number of ack bits in a block-ack packet.
1782 */
1783 #define IWX_FRAME_LIMIT 64
1784
1785 #define IWX_TX_FIFO_BK 0
1786 #define IWX_TX_FIFO_BE 1
1787 #define IWX_TX_FIFO_VI 2
1788 #define IWX_TX_FIFO_VO 3
1789 #define IWX_TX_FIFO_MCAST 5
1790 #define IWX_TX_FIFO_CMD 7
1791
1792 enum iwx_gen2_tx_fifo {
1793 IWX_GEN2_TX_FIFO_CMD = 0,
1794 IWX_GEN2_EDCA_TX_FIFO_BK,
1795 IWX_GEN2_EDCA_TX_FIFO_BE,
1796 IWX_GEN2_EDCA_TX_FIFO_VI,
1797 IWX_GEN2_EDCA_TX_FIFO_VO,
1798 IWX_GEN2_TRIG_TX_FIFO_BK,
1799 IWX_GEN2_TRIG_TX_FIFO_BE,
1800 IWX_GEN2_TRIG_TX_FIFO_VI,
1801 IWX_GEN2_TRIG_TX_FIFO_VO,
1802 };
1803
1804 /**
1805 * TXQ config options
1806 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue
1807 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format
1808 */
1809 #define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0)
1810 #define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1)
1811
1812 #define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX
1813
1814 /**
1815 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command
1816 * @sta_id: station id
1817 * @tid: tid of the queue
1818 * @flags: see &enum iwl_tx_queue_cfg_actions
1819 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.
1820 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)
1821 * @byte_cnt_addr: address of byte count table
1822 * @tfdq_addr: address of TFD circular buffer
1823 */
1824 struct iwx_tx_queue_cfg_cmd {
1825 uint8_t sta_id;
1826 uint8_t tid;
1827 uint16_t flags;
1828 uint32_t cb_size;
1829 uint64_t byte_cnt_addr;
1830 uint64_t tfdq_addr;
1831 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */
1832
1833 /**
1834 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config
1835 * @queue_number: queue number assigned to this RA -TID
1836 * @flags: set on failure
1837 * @write_pointer: initial value for write pointer
1838 * @reserved: reserved
1839 */
1840 struct iwx_tx_queue_cfg_rsp {
1841 uint16_t queue_number;
1842 uint16_t flags;
1843 uint16_t write_pointer;
1844 uint16_t reserved;
1845 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */
1846
1847
1848 /*
1849 * Commands
1850 */
1851 #define IWX_ALIVE 0x1
1852 #define IWX_REPLY_ERROR 0x2
1853 #define IWX_INIT_COMPLETE_NOTIF 0x4
1854
1855 /* PHY context commands */
1856 #define IWX_PHY_CONTEXT_CMD 0x8
1857 #define IWX_DBG_CFG 0x9
1858
1859 /* UMAC scan commands */
1860 #define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5
1861 #define IWX_SCAN_CFG_CMD 0xc
1862 #define IWX_SCAN_REQ_UMAC 0xd
1863 #define IWX_SCAN_ABORT_UMAC 0xe
1864 #define IWX_SCAN_COMPLETE_UMAC 0xf
1865
1866 /* station table */
1867 #define IWX_ADD_STA_KEY 0x17
1868 #define IWX_ADD_STA 0x18
1869 #define IWX_REMOVE_STA 0x19
1870
1871 /* TX */
1872 #define IWX_TX_CMD 0x1c
1873 #define IWX_TXPATH_FLUSH 0x1e
1874 #define IWX_MGMT_MCAST_KEY 0x1f
1875
1876 /* scheduler config */
1877 #define IWX_SCD_QUEUE_CFG 0x1d
1878
1879 /* global key */
1880 #define IWX_WEP_KEY 0x20
1881
1882 /* MAC and Binding commands */
1883 #define IWX_MAC_CONTEXT_CMD 0x28
1884 #define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */
1885 #define IWX_TIME_EVENT_NOTIFICATION 0x2a
1886 #define IWX_BINDING_CONTEXT_CMD 0x2b
1887 #define IWX_TIME_QUOTA_CMD 0x2c
1888 #define IWX_NON_QOS_TX_COUNTER_CMD 0x2d
1889
1890 /* Calibration */
1891 #define IWX_TEMPERATURE_NOTIFICATION 0x62
1892 #define IWX_CALIBRATION_CFG_CMD 0x65
1893 #define IWX_CALIBRATION_RES_NOTIFICATION 0x66
1894 #define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67
1895 #define IWX_RADIO_VERSION_NOTIFICATION 0x68
1896
1897 /* Phy */
1898 #define IWX_PHY_CONFIGURATION_CMD 0x6a
1899
1900 /* Power - legacy power table command */
1901 #define IWX_POWER_TABLE_CMD 0x77
1902 #define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78
1903 #define IWX_LTR_CONFIG 0xee
1904
1905 /* NVM */
1906 #define IWX_NVM_ACCESS_CMD 0x88
1907
1908 #define IWX_SET_CALIB_DEFAULT_CMD 0x8e
1909
1910 #define IWX_BEACON_NOTIFICATION 0x90
1911 #define IWX_BEACON_TEMPLATE_CMD 0x91
1912 #define IWX_TX_ANT_CONFIGURATION_CMD 0x98
1913 #define IWX_BT_CONFIG 0x9b
1914 #define IWX_STATISTICS_CMD 0x9c
1915 #define IWX_STATISTICS_NOTIFICATION 0x9d
1916 #define IWX_REDUCE_TX_POWER_CMD 0x9f
1917
1918 /* RF-KILL commands and notifications */
1919 #define IWX_CARD_STATE_CMD 0xa0
1920 #define IWX_CARD_STATE_NOTIFICATION 0xa1
1921
1922 #define IWX_MISSED_BEACONS_NOTIFICATION 0xa2
1923
1924 #define IWX_MFUART_LOAD_NOTIFICATION 0xb1
1925
1926 /* Power - new power table command */
1927 #define IWX_MAC_PM_POWER_TABLE 0xa9
1928
1929 #define IWX_REPLY_RX_PHY_CMD 0xc0
1930 #define IWX_REPLY_RX_MPDU_CMD 0xc1
1931 #define IWX_BAR_FRAME_RELEASE 0xc2
1932 #define IWX_FRAME_RELEASE 0xc3
1933 #define IWX_BA_NOTIF 0xc5
1934
1935 /* Location Aware Regulatory */
1936 #define IWX_MCC_UPDATE_CMD 0xc8
1937 #define IWX_MCC_CHUB_UPDATE_CMD 0xc9
1938
1939 /* BT Coex */
1940 #define IWX_BT_COEX_PRIO_TABLE 0xcc
1941 #define IWX_BT_COEX_PROT_ENV 0xcd
1942 #define IWX_BT_PROFILE_NOTIFICATION 0xce
1943 #define IWX_BT_COEX_CI 0x5d
1944
1945 #define IWX_REPLY_SF_CFG_CMD 0xd1
1946 #define IWX_REPLY_BEACON_FILTERING_CMD 0xd2
1947
1948 /* DTS measurements */
1949 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc
1950 #define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd
1951
1952 #define IWX_REPLY_DEBUG_CMD 0xf0
1953 #define IWX_DEBUG_LOG_MSG 0xf7
1954
1955 #define IWX_MCAST_FILTER_CMD 0xd0
1956
1957 /* D3 commands/notifications */
1958 #define IWX_D3_CONFIG_CMD 0xd3
1959 #define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4
1960 #define IWX_OFFLOADS_QUERY_CMD 0xd5
1961 #define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6
1962
1963 /* for WoWLAN in particular */
1964 #define IWX_WOWLAN_PATTERNS 0xe0
1965 #define IWX_WOWLAN_CONFIGURATION 0xe1
1966 #define IWX_WOWLAN_TSC_RSC_PARAM 0xe2
1967 #define IWX_WOWLAN_TKIP_PARAM 0xe3
1968 #define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4
1969 #define IWX_WOWLAN_GET_STATUSES 0xe5
1970 #define IWX_WOWLAN_TX_POWER_PER_DB 0xe6
1971
1972 /* and for NetDetect */
1973 #define IWX_NET_DETECT_CONFIG_CMD 0x54
1974 #define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56
1975 #define IWX_NET_DETECT_PROFILES_CMD 0x57
1976 #define IWX_NET_DETECT_HOTSPOTS_CMD 0x58
1977 #define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59
1978
1979 /* system group command IDs */
1980 #define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff
1981
1982 #define IWX_REPLY_MAX 0xff
1983
1984 /* PHY_OPS subcommand IDs */
1985 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0
1986 #define IWX_CTDP_CONFIG_CMD 0x03
1987 #define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04
1988 #define IWX_CT_KILL_NOTIFICATION 0xFE
1989 #define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF
1990
1991 /* command groups */
1992 #define IWX_LEGACY_GROUP 0x0
1993 #define IWX_LONG_GROUP 0x1
1994 #define IWX_SYSTEM_GROUP 0x2
1995 #define IWX_MAC_CONF_GROUP 0x3
1996 #define IWX_PHY_OPS_GROUP 0x4
1997 #define IWX_DATA_PATH_GROUP 0x5
1998 #define IWX_PROT_OFFLOAD_GROUP 0xb
1999 #define IWX_REGULATORY_AND_NVM_GROUP 0xc
2000
2001 /* SYSTEM_GROUP group subcommand IDs */
2002
2003 #define IWX_SHARED_MEM_CFG_CMD 0x00
2004 #define IWX_SOC_CONFIGURATION_CMD 0x01
2005 #define IWX_INIT_EXTENDED_CFG_CMD 0x03
2006 #define IWX_FW_ERROR_RECOVERY_CMD 0x07
2007
2008 /* MAC_CONF group subcommand IDs */
2009 #define IWX_SESSION_PROTECTION_CMD 0x05
2010 #define IWX_MAC_CONFIG_CMD 0x08
2011 #define IWX_LINK_CONFIG_CMD 0x09
2012 #define IWX_STA_CONFIG_CMD 0x0a
2013 #define IWX_STA_REMOVE_CMD 0x0c
2014 #define IWX_SESSION_PROTECTION_NOTIF 0xfb
2015
2016 /* DATA_PATH group subcommand IDs */
2017 #define IWX_DQA_ENABLE_CMD 0x00
2018 #define IWX_RLC_CONFIG_CMD 0x08
2019 #define IWX_TLC_MNG_CONFIG_CMD 0x0f
2020 #define IWX_RX_BAID_ALLOCATION_CONFIG_CMD 0x16
2021 #define IWX_SCD_QUEUE_CONFIG_CMD 0x17
2022 #define IWX_SEC_KEY_CMD 0x18
2023 #define IWX_RX_NO_DATA_NOTIF 0xf5
2024 #define IWX_THERMAL_DUAL_CHAIN_REQUEST 0xf6
2025 #define IWX_TLC_MNG_UPDATE_NOTIF 0xf7
2026
2027 /* REGULATORY_AND_NVM group subcommand IDs */
2028 #define IWX_NVM_ACCESS_COMPLETE 0x00
2029 #define IWX_NVM_GET_INFO 0x02
2030 #define IWX_PNVM_INIT_COMPLETE 0xfe
2031
2032 /*
2033 * struct iwx_dqa_enable_cmd
2034 * @cmd_queue: the TXQ number of the command queue
2035 */
2036 struct iwx_dqa_enable_cmd {
2037 uint32_t cmd_queue;
2038 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */
2039
2040 /**
2041 * struct iwx_cmd_response - generic response struct for most commands
2042 * @status: status of the command asked, changes for each one
2043 */
2044 struct iwx_cmd_response {
2045 uint32_t status;
2046 };
2047
2048 /*
2049 * struct iwx_tx_ant_cfg_cmd
2050 * @valid: valid antenna configuration
2051 */
2052 struct iwx_tx_ant_cfg_cmd {
2053 uint32_t valid;
2054 } __packed;
2055
2056 /*
2057 * Calibration control struct.
2058 * Sent as part of the phy configuration command.
2059 * @flow_trigger: bitmap for which calibrations to perform according to
2060 * flow triggers.
2061 * @event_trigger: bitmap for which calibrations to perform according to
2062 * event triggers.
2063 */
2064 struct iwx_calib_ctrl {
2065 uint32_t flow_trigger;
2066 uint32_t event_trigger;
2067 } __packed;
2068
2069 /* This defines the bitmap of various calibrations to enable in both
2070 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD.
2071 */
2072 #define IWX_CALIB_CFG_XTAL_IDX (1 << 0)
2073 #define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1)
2074 #define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)
2075 #define IWX_CALIB_CFG_PAPD_IDX (1 << 3)
2076 #define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4)
2077 #define IWX_CALIB_CFG_DC_IDX (1 << 5)
2078 #define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6)
2079 #define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)
2080 #define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8)
2081 #define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)
2082 #define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10)
2083 #define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)
2084 #define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12)
2085 #define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)
2086 #define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)
2087 #define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)
2088 #define IWX_CALIB_CFG_DAC_IDX (1 << 16)
2089 #define IWX_CALIB_CFG_ABS_IDX (1 << 17)
2090 #define IWX_CALIB_CFG_AGC_IDX (1 << 18)
2091
2092 /*
2093 * Phy configuration command.
2094 */
2095 struct iwx_phy_cfg_cmd {
2096 uint32_t phy_cfg;
2097 struct iwx_calib_ctrl calib_control;
2098 } __packed;
2099
2100 #define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
2101 #define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
2102 #define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
2103 #define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2104 #define IWX_PHY_CFG_TX_CHAIN_A (1 << 8)
2105 #define IWX_PHY_CFG_TX_CHAIN_B (1 << 9)
2106 #define IWX_PHY_CFG_TX_CHAIN_C (1 << 10)
2107 #define IWX_PHY_CFG_RX_CHAIN_A (1 << 12)
2108 #define IWX_PHY_CFG_RX_CHAIN_B (1 << 13)
2109 #define IWX_PHY_CFG_RX_CHAIN_C (1 << 14)
2110
2111 #define IWX_MAX_DTS_TRIPS 8
2112
2113 /**
2114 * struct iwx_ct_kill_notif - CT-kill entry notification
2115 *
2116 * @temperature: the current temperature in celsius
2117 * @reserved: reserved
2118 */
2119 struct iwx_ct_kill_notif {
2120 uint16_t temperature;
2121 uint16_t reserved;
2122 } __packed; /* GRP_PHY_CT_KILL_NTF */
2123
2124 /**
2125 * struct iwx_temp_report_ths_cmd - set temperature thresholds
2126 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD)
2127 *
2128 * @num_temps: number of temperature thresholds passed
2129 * @thresholds: array with the thresholds to be configured
2130 */
2131 struct iwx_temp_report_ths_cmd {
2132 uint32_t num_temps;
2133 uint16_t thresholds[IWX_MAX_DTS_TRIPS];
2134 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */
2135
2136 /*
2137 * channel flags in NVM
2138 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo
2139 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel
2140 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed
2141 * @IWX_NVM_CHANNEL_RADAR: radar detection required
2142 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
2143 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
2144 * on same channel on 2.4 or same UNII band on 5.2
2145 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate
2146 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
2147 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
2148 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
2149 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
2150 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
2151 */
2152 #define IWX_NVM_CHANNEL_VALID (1 << 0)
2153 #define IWX_NVM_CHANNEL_IBSS (1 << 1)
2154 #define IWX_NVM_CHANNEL_ACTIVE (1 << 3)
2155 #define IWX_NVM_CHANNEL_RADAR (1 << 4)
2156 #define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5)
2157 #define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6)
2158 #define IWX_NVM_CHANNEL_DFS (1 << 7)
2159 #define IWX_NVM_CHANNEL_WIDE (1 << 8)
2160 #define IWX_NVM_CHANNEL_40MHZ (1 << 9)
2161 #define IWX_NVM_CHANNEL_80MHZ (1 << 10)
2162 #define IWX_NVM_CHANNEL_160MHZ (1 << 11)
2163 #define IWX_NVM_CHANNEL_DC_HIGH (1 << 12)
2164
2165 /**
2166 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed
2167 * @reserved: reserved
2168 */
2169 struct iwx_nvm_access_complete_cmd {
2170 uint32_t reserved;
2171 } __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */
2172
2173 /*
2174 * struct iwx_nvm_get_info - request to get NVM data
2175 */
2176 struct iwx_nvm_get_info {
2177 uint32_t reserved;
2178 } __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */
2179
2180 /**
2181 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp
2182 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty
2183 */
2184 #define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0)
2185
2186 /**
2187 * struct iwx_nvm_get_info_general - general NVM data
2188 * @flags: bit 0: 1 - empty, 0 - non-empty
2189 * @nvm_version: nvm version
2190 * @board_type: board type
2191 * @n_hw_addrs: number of reserved MAC addresses
2192 */
2193 struct iwx_nvm_get_info_general {
2194 uint32_t flags;
2195 uint16_t nvm_version;
2196 uint8_t board_type;
2197 uint8_t n_hw_addrs;
2198 } __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */
2199
2200 /**
2201 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku
2202 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled
2203 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled
2204 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled
2205 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled
2206 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled
2207 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled
2208 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled
2209 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled
2210 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled
2211 */
2212 #define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0)
2213 #define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1)
2214 #define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2)
2215 #define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3)
2216 #define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4)
2217 #define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5)
2218 #define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8)
2219 #define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14)
2220 #define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15)
2221
2222 /**
2223 * struct iwx_nvm_get_info_sku - mac information
2224 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags
2225 */
2226 struct iwx_nvm_get_info_sku {
2227 uint32_t mac_sku_flags;
2228 } __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */
2229
2230 /**
2231 * struct iwx_nvm_get_info_phy - phy information
2232 * @tx_chains: BIT 0 chain A, BIT 1 chain B
2233 * @rx_chains: BIT 0 chain A, BIT 1 chain B
2234 */
2235 struct iwx_nvm_get_info_phy {
2236 uint32_t tx_chains;
2237 uint32_t rx_chains;
2238 } __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */
2239
2240 #define IWX_NUM_CHANNELS_V1 51
2241 #define IWX_NUM_CHANNELS 110
2242
2243 /**
2244 * struct iwx_nvm_get_info_regulatory - regulatory information
2245 * @lar_enabled: is LAR enabled
2246 * @channel_profile: regulatory data of this channel
2247 * @reserved: reserved
2248 */
2249 struct iwx_nvm_get_info_regulatory_v1 {
2250 uint32_t lar_enabled;
2251 uint16_t channel_profile[IWX_NUM_CHANNELS_V1];
2252 uint16_t reserved;
2253 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */
2254
2255 /**
2256 * struct iwx_nvm_get_info_regulatory - regulatory information
2257 * @lar_enabled: is LAR enabled
2258 * @n_channels: number of valid channels in the array
2259 * @channel_profile: regulatory data of this channel
2260 */
2261 struct iwx_nvm_get_info_regulatory {
2262 uint32_t lar_enabled;
2263 uint32_t n_channels;
2264 uint32_t channel_profile[IWX_NUM_CHANNELS];
2265 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */
2266
2267 /**
2268 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data
2269 * @general: general NVM data
2270 * @mac_sku: data relating to MAC sku
2271 * @phy_sku: data relating to PHY sku
2272 * @regulatory: regulatory data
2273 */
2274 struct iwx_nvm_get_info_rsp_v3 {
2275 struct iwx_nvm_get_info_general general;
2276 struct iwx_nvm_get_info_sku mac_sku;
2277 struct iwx_nvm_get_info_phy phy_sku;
2278 struct iwx_nvm_get_info_regulatory_v1 regulatory;
2279 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */
2280
2281 /**
2282 * struct iwx_nvm_get_info_rsp - response to get NVM data
2283 * @general: general NVM data
2284 * @mac_sku: data relating to MAC sku
2285 * @phy_sku: data relating to PHY sku
2286 * @regulatory: regulatory data
2287 */
2288 struct iwx_nvm_get_info_rsp {
2289 struct iwx_nvm_get_info_general general;
2290 struct iwx_nvm_get_info_sku mac_sku;
2291 struct iwx_nvm_get_info_phy phy_sku;
2292 struct iwx_nvm_get_info_regulatory regulatory;
2293 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */
2294
2295
2296 #define IWX_ALIVE_STATUS_ERR 0xDEAD
2297 #define IWX_ALIVE_STATUS_OK 0xCAFE
2298
2299 struct iwx_lmac_debug_addrs {
2300 uint32_t error_event_table_ptr; /* SRAM address for error log */
2301 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2302 uint32_t cpu_register_ptr;
2303 uint32_t dbgm_config_ptr;
2304 uint32_t alive_counter_ptr;
2305 uint32_t scd_base_ptr; /* SRAM address for SCD */
2306 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2307 uint32_t st_fwrd_size;
2308 } __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */
2309
2310 struct iwx_lmac_alive {
2311 uint32_t ucode_major;
2312 uint32_t ucode_minor;
2313 uint8_t ver_subtype;
2314 uint8_t ver_type;
2315 uint8_t mac;
2316 uint8_t opt;
2317 uint32_t timestamp;
2318 struct iwx_lmac_debug_addrs dbg_ptrs;
2319 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */
2320
2321 struct iwx_umac_debug_addrs {
2322 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2323 uint32_t dbg_print_buff_addr;
2324 } __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */
2325
2326 struct iwx_umac_alive {
2327 uint32_t umac_major; /* UMAC version: major */
2328 uint32_t umac_minor; /* UMAC version: minor */
2329 struct iwx_umac_debug_addrs dbg_ptrs;
2330 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */
2331
2332 struct iwx_alive_resp_v4 {
2333 uint16_t status;
2334 uint16_t flags;
2335 struct iwx_lmac_alive lmac_data[2];
2336 struct iwx_umac_alive umac_data;
2337 } __packed; /* ALIVE_RES_API_S_VER_4 */
2338
2339 struct iwx_sku_id {
2340 uint32_t data[3];
2341 } __packed; /* SKU_ID_API_S_VER_1 */
2342
2343 struct iwx_alive_resp_v5 {
2344 uint16_t status;
2345 uint16_t flags;
2346 struct iwx_lmac_alive lmac_data[2];
2347 struct iwx_umac_alive umac_data;
2348 struct iwx_sku_id sku_id;
2349 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_5 */
2350
2351 struct iwx_imr_alive_info {
2352 uint64_t base_addr;
2353 uint32_t size;
2354 uint32_t enabled;
2355 } __packed; /* IMR_ALIVE_INFO_API_S_VER_1 */
2356
2357 struct iwx_alive_resp_v6 {
2358 uint16_t status;
2359 uint16_t flags;
2360 struct iwx_lmac_alive lmac_data[2];
2361 struct iwx_umac_alive umac_data;
2362 struct iwx_sku_id sku_id;
2363 struct iwx_imr_alive_info imr;
2364 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_6 */
2365
2366
2367 #define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)
2368 #define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1)
2369
2370 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc
2371 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0
2372 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1
2373 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2
2374 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3
2375
2376 /**
2377 * struct iwx_soc_configuration_cmd - Set device stabilization latency
2378 *
2379 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE
2380 * flag, because the FW treats the whole value as an integer. In
2381 * VER_2, we can set the bits independently.
2382 * @latency: time for SOC to ensure stable power & XTAL
2383 */
2384 struct iwx_soc_configuration_cmd {
2385 uint32_t flags;
2386 uint32_t latency;
2387 } __packed; /*
2388 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above)
2389 * SOC_CONFIGURATION_CMD_S_VER_2
2390 */
2391
2392 /**
2393 * commands driver may send before finishing init flow
2394 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command
2395 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands
2396 */
2397 #define IWX_INIT_DEBUG_CFG (1 << 0)
2398 #define IWX_INIT_NVM (1 << 1)
2399
2400 /**
2401 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for
2402 * before finishing init flows
2403 * @init_flags: IWX_INIT_* flag bits
2404 */
2405 struct iwx_init_extended_cfg_cmd {
2406 uint32_t init_flags;
2407 } __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */
2408
2409 /* Error response/notification */
2410 #define IWX_FW_ERR_UNKNOWN_CMD 0x0
2411 #define IWX_FW_ERR_INVALID_CMD_PARAM 0x1
2412 #define IWX_FW_ERR_SERVICE 0x2
2413 #define IWX_FW_ERR_ARC_MEMORY 0x3
2414 #define IWX_FW_ERR_ARC_CODE 0x4
2415 #define IWX_FW_ERR_WATCH_DOG 0x5
2416 #define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10
2417 #define IWX_FW_ERR_WEP_KEY_SIZE 0x11
2418 #define IWX_FW_ERR_OBSOLETE_FUNC 0x12
2419 #define IWX_FW_ERR_UNEXPECTED 0xFE
2420 #define IWX_FW_ERR_FATAL 0xFF
2421
2422 /**
2423 * struct iwx_error_resp - FW error indication
2424 * ( IWX_REPLY_ERROR = 0x2 )
2425 * @error_type: one of IWX_FW_ERR_*
2426 * @cmd_id: the command ID for which the error occurred
2427 * @bad_cmd_seq_num: sequence number of the erroneous command
2428 * @error_service: which service created the error, applicable only if
2429 * error_type = 2, otherwise 0
2430 * @timestamp: TSF in usecs.
2431 */
2432 struct iwx_error_resp {
2433 uint32_t error_type;
2434 uint8_t cmd_id;
2435 uint8_t reserved1;
2436 uint16_t bad_cmd_seq_num;
2437 uint32_t error_service;
2438 uint64_t timestamp;
2439 } __packed;
2440
2441 enum iwx_fw_dbg_reg_operator {
2442 CSR_ASSIGN,
2443 CSR_SETBIT,
2444 CSR_CLEARBIT,
2445
2446 PRPH_ASSIGN,
2447 PRPH_SETBIT,
2448 PRPH_CLEARBIT,
2449
2450 INDIRECT_ASSIGN,
2451 INDIRECT_SETBIT,
2452 INDIRECT_CLEARBIT,
2453
2454 PRPH_BLOCKBIT,
2455 };
2456
2457 /**
2458 * struct iwx_fw_dbg_reg_op - an operation on a register
2459 *
2460 * @op: &enum iwx_fw_dbg_reg_operator
2461 * @addr: offset of the register
2462 * @val: value
2463 */
2464 struct iwx_fw_dbg_reg_op {
2465 uint8_t op;
2466 uint8_t reserved[3];
2467 uint32_t addr;
2468 uint32_t val;
2469 } __packed;
2470
2471 /**
2472 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes
2473 *
2474 * @SMEM_MODE: monitor stores the data in SMEM
2475 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM
2476 * @MARBH_MODE: monitor stores the data in MARBH buffer
2477 * @MIPI_MODE: monitor outputs the data through the MIPI interface
2478 */
2479 enum iwx_fw_dbg_monitor_mode {
2480 SMEM_MODE = 0,
2481 EXTERNAL_MODE = 1,
2482 MARBH_MODE = 2,
2483 MIPI_MODE = 3,
2484 };
2485
2486 /**
2487 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments
2488 *
2489 * @data_type: the memory segment type to record
2490 * @ofs: the memory segment offset
2491 * @len: the memory segment length, in bytes
2492 *
2493 * This parses IWX_UCODE_TLV_FW_MEM_SEG
2494 */
2495 struct iwx_fw_dbg_mem_seg_tlv {
2496 uint32_t data_type;
2497 uint32_t ofs;
2498 uint32_t len;
2499 } __packed;
2500
2501 /**
2502 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data
2503 *
2504 * @version: version of the TLV - currently 0
2505 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode
2506 * @size_power: buffer size will be 2^(size_power + 11)
2507 * @base_reg: addr of the base addr register (PRPH)
2508 * @end_reg: addr of the end addr register (PRPH)
2509 * @write_ptr_reg: the addr of the reg of the write pointer
2510 * @wrap_count: the addr of the reg of the wrap_count
2511 * @base_shift: shift right of the base addr reg
2512 * @end_shift: shift right of the end addr reg
2513 * @reg_ops: array of registers operations
2514 *
2515 * This parses IWX_UCODE_TLV_FW_DBG_DEST
2516 */
2517 struct iwx_fw_dbg_dest_tlv_v1 {
2518 uint8_t version;
2519 uint8_t monitor_mode;
2520 uint8_t size_power;
2521 uint8_t reserved;
2522 uint32_t base_reg;
2523 uint32_t end_reg;
2524 uint32_t write_ptr_reg;
2525 uint32_t wrap_count;
2526 uint8_t base_shift;
2527 uint8_t end_shift;
2528 struct iwx_fw_dbg_reg_op reg_ops[0];
2529 } __packed;
2530
2531 /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */
2532 #define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000
2533 /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */
2534 #define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff
2535 /* The smem buffer chunks are in units of 256 bits */
2536 #define IWX_M2S_UNIT_SIZE 0x100
2537
2538 struct iwx_fw_dbg_dest_tlv {
2539 uint8_t version;
2540 uint8_t monitor_mode;
2541 uint8_t size_power;
2542 uint8_t reserved;
2543 uint32_t cfg_reg;
2544 uint32_t write_ptr_reg;
2545 uint32_t wrap_count;
2546 uint8_t base_shift;
2547 uint8_t size_shift;
2548 struct iwx_fw_dbg_reg_op reg_ops[0];
2549 } __packed;
2550
2551 struct iwx_fw_dbg_conf_hcmd {
2552 uint8_t id;
2553 uint8_t reserved;
2554 uint16_t len;
2555 uint8_t data[0];
2556 } __packed;
2557
2558 /**
2559 * enum iwx_fw_dbg_trigger_mode - triggers functionalities
2560 *
2561 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism
2562 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data
2563 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to
2564 * collect only monitor data
2565 */
2566 enum iwx_fw_dbg_trigger_mode {
2567 IWX_FW_DBG_TRIGGER_START = (1 << 0),
2568 IWX_FW_DBG_TRIGGER_STOP = (1 << 1),
2569 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2),
2570 };
2571
2572 /**
2573 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers
2574 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart
2575 */
2576 enum iwx_fw_dbg_trigger_flags {
2577 IWX_FW_DBG_FORCE_RESTART = (1 << 0),
2578 };
2579
2580 /**
2581 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger
2582 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type
2583 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode
2584 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode
2585 * @IWX_FW_DBG_CONF_VIF_AP: AP mode
2586 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode
2587 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode
2588 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device
2589 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device
2590 */
2591 enum iwx_fw_dbg_trigger_vif_type {
2592 IWX_FW_DBG_CONF_VIF_ANY = 0,
2593 IWX_FW_DBG_CONF_VIF_IBSS = 1,
2594 IWX_FW_DBG_CONF_VIF_STATION = 2,
2595 IWX_FW_DBG_CONF_VIF_AP = 3,
2596 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8,
2597 IWX_FW_DBG_CONF_VIF_P2P_GO = 9,
2598 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10,
2599 IWX_FW_DBG_CONF_VIF_NAN = 12,
2600 };
2601
2602 /**
2603 * enum iwl_fw_dbg_trigger - triggers available
2604 *
2605 * @FW_DBG_TRIGGER_USER: trigger log collection by user
2606 * This should not be defined as a trigger to the driver, but a value the
2607 * driver should set to indicate that the trigger was initiated by the
2608 * user.
2609 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts
2610 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are
2611 * missed.
2612 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch.
2613 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a
2614 * command response or a notification.
2615 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event.
2616 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold.
2617 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon
2618 * goes below a threshold.
2619 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang
2620 * detection.
2621 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related
2622 * events.
2623 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events.
2624 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a
2625 * threshold.
2626 * @FW_DBG_TDLS: trigger log collection upon TDLS related events.
2627 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when
2628 * the firmware sends a tx reply.
2629 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space
2630 * request.
2631 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts
2632 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure
2633 * in the driver.
2634 */
2635 enum iwx_fw_dbg_trigger {
2636 IWX_FW_DBG_TRIGGER_INVALID = 0,
2637 IWX_FW_DBG_TRIGGER_USER,
2638 IWX_FW_DBG_TRIGGER_FW_ASSERT,
2639 IWX_FW_DBG_TRIGGER_MISSED_BEACONS,
2640 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH,
2641 IWX_FW_DBG_TRIGGER_FW_NOTIF,
2642 IWX_FW_DBG_TRIGGER_MLME,
2643 IWX_FW_DBG_TRIGGER_STATS,
2644 IWX_FW_DBG_TRIGGER_RSSI,
2645 IWX_FW_DBG_TRIGGER_TXQ_TIMERS,
2646 IWX_FW_DBG_TRIGGER_TIME_EVENT,
2647 IWX_FW_DBG_TRIGGER_BA,
2648 IWX_FW_DBG_TRIGGER_TX_LATENCY,
2649 IWX_FW_DBG_TRIGGER_TDLS,
2650 IWX_FW_DBG_TRIGGER_TX_STATUS,
2651 IWX_FW_DBG_TRIGGER_USER_EXTENDED,
2652 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT,
2653 IWX_FW_DBG_TRIGGER_DRIVER,
2654
2655 /* must be last */
2656 IWX_FW_DBG_TRIGGER_MAX,
2657 };
2658
2659
2660 /**
2661 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger
2662 * @id: &enum iwx_fw_dbg_trigger
2663 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type
2664 * @stop_conf_ids: bitmap of configurations this trigger relates to.
2665 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding
2666 * to the currently running configuration is set, the data should be
2667 * collected.
2668 * @stop_delay: how many milliseconds to wait before collecting the data
2669 * after the STOP trigger fires.
2670 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both
2671 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what
2672 * configuration should be applied when the triggers kicks in.
2673 * @occurrences: number of occurrences. 0 means the trigger will never fire.
2674 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this
2675 * trigger in which another occurrence should be ignored.
2676 * @flags: &enum iwx_fw_dbg_trigger_flags
2677 */
2678 struct iwx_fw_dbg_trigger_tlv {
2679 uint32_t id;
2680 uint32_t vif_type;
2681 uint32_t stop_conf_ids;
2682 uint32_t stop_delay;
2683 uint8_t mode;
2684 uint8_t start_conf_id;
2685 uint16_t occurrences;
2686 uint16_t trig_dis_ms;
2687 uint8_t flags;
2688 uint8_t reserved[5];
2689
2690 uint8_t data[0];
2691 } __packed;
2692
2693 #define IWX_FW_DBG_START_FROM_ALIVE 0
2694 #define IWX_FW_DBG_CONF_MAX 32
2695 #define IWX_FW_DBG_INVALID 0xff
2696
2697 /**
2698 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons
2699 * @stop_consec_missed_bcon: stop recording if threshold is crossed.
2700 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed.
2701 * @start_consec_missed_bcon: start recording if threshold is crossed.
2702 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed.
2703 * @reserved1: reserved
2704 * @reserved2: reserved
2705 */
2706 struct iwx_fw_dbg_trigger_missed_bcon {
2707 uint32_t stop_consec_missed_bcon;
2708 uint32_t stop_consec_missed_bcon_since_rx;
2709 uint32_t reserved2[2];
2710 uint32_t start_consec_missed_bcon;
2711 uint32_t start_consec_missed_bcon_since_rx;
2712 uint32_t reserved1[2];
2713 } __packed;
2714
2715 /**
2716 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW.
2717 * cmds: the list of commands to trigger the collection on
2718 */
2719 struct iwx_fw_dbg_trigger_cmd {
2720 struct cmd {
2721 uint8_t cmd_id;
2722 uint8_t group_id;
2723 } __packed cmds[16];
2724 } __packed;
2725
2726 /**
2727 * iwx_fw_dbg_trigger_stats - configures trigger for statistics
2728 * @stop_offset: the offset of the value to be monitored
2729 * @stop_threshold: the threshold above which to collect
2730 * @start_offset: the offset of the value to be monitored
2731 * @start_threshold: the threshold above which to start recording
2732 */
2733 struct iwx_fw_dbg_trigger_stats {
2734 uint32_t stop_offset;
2735 uint32_t stop_threshold;
2736 uint32_t start_offset;
2737 uint32_t start_threshold;
2738 } __packed;
2739
2740 /**
2741 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI
2742 * @rssi: RSSI value to trigger at
2743 */
2744 struct iwx_fw_dbg_trigger_low_rssi {
2745 uint32_t rssi;
2746 } __packed;
2747
2748 /**
2749 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events
2750 * @stop_auth_denied: number of denied authentication to collect
2751 * @stop_auth_timeout: number of authentication timeout to collect
2752 * @stop_rx_deauth: number of Rx deauth before to collect
2753 * @stop_tx_deauth: number of Tx deauth before to collect
2754 * @stop_assoc_denied: number of denied association to collect
2755 * @stop_assoc_timeout: number of association timeout to collect
2756 * @stop_connection_loss: number of connection loss to collect
2757 * @start_auth_denied: number of denied authentication to start recording
2758 * @start_auth_timeout: number of authentication timeout to start recording
2759 * @start_rx_deauth: number of Rx deauth to start recording
2760 * @start_tx_deauth: number of Tx deauth to start recording
2761 * @start_assoc_denied: number of denied association to start recording
2762 * @start_assoc_timeout: number of association timeout to start recording
2763 * @start_connection_loss: number of connection loss to start recording
2764 */
2765 struct iwx_fw_dbg_trigger_mlme {
2766 uint8_t stop_auth_denied;
2767 uint8_t stop_auth_timeout;
2768 uint8_t stop_rx_deauth;
2769 uint8_t stop_tx_deauth;
2770
2771 uint8_t stop_assoc_denied;
2772 uint8_t stop_assoc_timeout;
2773 uint8_t stop_connection_loss;
2774 uint8_t reserved;
2775
2776 uint8_t start_auth_denied;
2777 uint8_t start_auth_timeout;
2778 uint8_t start_rx_deauth;
2779 uint8_t start_tx_deauth;
2780
2781 uint8_t start_assoc_denied;
2782 uint8_t start_assoc_timeout;
2783 uint8_t start_connection_loss;
2784 uint8_t reserved2;
2785 } __packed;
2786
2787 /**
2788 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer
2789 * @command_queue: timeout for the command queue in ms
2790 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms
2791 * @softap: timeout for the queues of a softAP in ms
2792 * @p2p_go: timeout for the queues of a P2P GO in ms
2793 * @p2p_client: timeout for the queues of a P2P client in ms
2794 * @p2p_device: timeout for the queues of a P2P device in ms
2795 * @ibss: timeout for the queues of an IBSS in ms
2796 * @tdls: timeout for the queues of a TDLS station in ms
2797 */
2798 struct iwx_fw_dbg_trigger_txq_timer {
2799 uint32_t command_queue;
2800 uint32_t bss;
2801 uint32_t softap;
2802 uint32_t p2p_go;
2803 uint32_t p2p_client;
2804 uint32_t p2p_device;
2805 uint32_t ibss;
2806 uint32_t tdls;
2807 uint32_t reserved[4];
2808 } __packed;
2809
2810 /**
2811 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger
2812 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a
2813 * trigger each time a time event notification that relates to time event
2814 * id with one of the actions in the bitmap is received and
2815 * BIT(notif->status) is set in status_bitmap.
2816 *
2817 */
2818 struct iwx_fw_dbg_trigger_time_event {
2819 struct {
2820 uint32_t id;
2821 uint32_t action_bitmap;
2822 uint32_t status_bitmap;
2823 } __packed time_events[16];
2824 } __packed;
2825
2826 /**
2827 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger
2828 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur
2829 * when an Rx BlockAck session is started.
2830 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur
2831 * when an Rx BlockAck session is stopped.
2832 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur
2833 * when a Tx BlockAck session is started.
2834 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur
2835 * when a Tx BlockAck session is stopped.
2836 * rx_bar: tid bitmap to configure on what tid the trigger should occur
2837 * when a BAR is received (for a Tx BlockAck session).
2838 * tx_bar: tid bitmap to configure on what tid the trigger should occur
2839 * when a BAR is send (for an Rx BlocAck session).
2840 * frame_timeout: tid bitmap to configure on what tid the trigger should occur
2841 * when a frame times out in the reordering buffer.
2842 */
2843 struct iwx_fw_dbg_trigger_ba {
2844 uint16_t rx_ba_start;
2845 uint16_t rx_ba_stop;
2846 uint16_t tx_ba_start;
2847 uint16_t tx_ba_stop;
2848 uint16_t rx_bar;
2849 uint16_t tx_bar;
2850 uint16_t frame_timeout;
2851 } __packed;
2852
2853 /**
2854 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger
2855 * @thrshold: the wanted threshold.
2856 * @tid_bitmap: the tid to apply the threshold on
2857 * @mode: recording mode (Internal buffer or continues recording)
2858 * @window: the size of the window before collecting.
2859 * @reserved: reserved.
2860 */
2861 struct iwx_fw_dbg_trigger_tx_latency {
2862 uint32_t thrshold;
2863 uint16_t tid_bitmap;
2864 uint16_t mode;
2865 uint32_t window;
2866 uint32_t reserved[4];
2867 } __packed;
2868
2869 /**
2870 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events.
2871 * @action_bitmap: the TDLS action to trigger the collection upon
2872 * @peer_mode: trigger on specific peer or all
2873 * @peer: the TDLS peer to trigger the collection on
2874 */
2875 struct iwx_fw_dbg_trigger_tdls {
2876 uint8_t action_bitmap;
2877 uint8_t peer_mode;
2878 uint8_t peer[ETHER_ADDR_LEN];
2879 uint8_t reserved[4];
2880 } __packed;
2881
2882 /**
2883 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response
2884 * status.
2885 * @statuses: the list of statuses to trigger the collection on
2886 */
2887 struct iwx_fw_dbg_trigger_tx_status {
2888 struct tx_status {
2889 uint8_t status;
2890 uint8_t reserved[3];
2891 } __packed statuses[16];
2892 uint32_t reserved[2];
2893 } __packed;
2894
2895 /**
2896 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration.
2897 * @id: conf id
2898 * @usniffer: should the uSniffer image be used
2899 * @num_of_hcmds: how many HCMDs to send are present here
2900 * @hcmd: a variable length host command to be sent to apply the configuration.
2901 * If there is more than one HCMD to send, they will appear one after the
2902 * other and be sent in the order that they appear in.
2903 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to
2904 * %IWX_FW_DBG_CONF_MAX configuration per run.
2905 */
2906 struct iwx_fw_dbg_conf_tlv {
2907 uint8_t id;
2908 uint8_t usniffer;
2909 uint8_t reserved;
2910 uint8_t num_of_hcmds;
2911 struct iwx_fw_dbg_conf_hcmd hcmd;
2912 } __packed;
2913
2914 #define IWX_FW_CMD_VER_UNKNOWN 99
2915
2916 /**
2917 * struct iwx_fw_cmd_version - firmware command version entry
2918 * @cmd: command ID
2919 * @group: group ID
2920 * @cmd_ver: command version
2921 * @notif_ver: notification version
2922 */
2923 struct iwx_fw_cmd_version {
2924 uint8_t cmd;
2925 uint8_t group;
2926 uint8_t cmd_ver;
2927 uint8_t notif_ver;
2928 } __packed;
2929
2930 /* Common PHY, MAC and Bindings definitions */
2931
2932 #define IWX_MAX_MACS_IN_BINDING (3)
2933 #define IWX_MAX_BINDINGS (4)
2934 #define IWX_AUX_BINDING_INDEX (3)
2935 #define IWX_MAX_PHYS (4)
2936
2937 /* Used to extract ID and color from the context dword */
2938 #define IWX_FW_CTXT_ID_POS (0)
2939 #define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS)
2940 #define IWX_FW_CTXT_COLOR_POS (8)
2941 #define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS)
2942 #define IWX_FW_CTXT_INVALID (0xffffffff)
2943
2944 #define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\
2945 (_color << IWX_FW_CTXT_COLOR_POS))
2946
2947 /* Possible actions on PHYs, MACs and Bindings */
2948 #define IWX_FW_CTXT_ACTION_STUB 0
2949 #define IWX_FW_CTXT_ACTION_ADD 1
2950 #define IWX_FW_CTXT_ACTION_MODIFY 2
2951 #define IWX_FW_CTXT_ACTION_REMOVE 3
2952 #define IWX_FW_CTXT_ACTION_NUM 4
2953 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2954
2955 /* Time Events */
2956
2957 /* Time Event types, according to MAC type */
2958
2959 /* BSS Station Events */
2960 #define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0
2961 #define IWX_TE_BSS_STA_ASSOC 1
2962 #define IWX_TE_BSS_EAP_DHCP_PROT 2
2963 #define IWX_TE_BSS_QUIET_PERIOD 3
2964
2965 /* P2P Device Events */
2966 #define IWX_TE_P2P_DEVICE_DISCOVERABLE 4
2967 #define IWX_TE_P2P_DEVICE_LISTEN 5
2968 #define IWX_TE_P2P_DEVICE_ACTION_SCAN 6
2969 #define IWX_TE_P2P_DEVICE_FULL_SCAN 7
2970
2971 /* P2P Client Events */
2972 #define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8
2973 #define IWX_TE_P2P_CLIENT_ASSOC 9
2974 #define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10
2975
2976 /* P2P GO Events */
2977 #define IWX_TE_P2P_GO_ASSOC_PROT 11
2978 #define IWX_TE_P2P_GO_REPETITIVE_NOA 12
2979 #define IWX_TE_P2P_GO_CT_WINDOW 13
2980
2981 /* WiDi Sync Events */
2982 #define IWX_TE_WIDI_TX_SYNC 14
2983
2984 /* Time event - defines for command API */
2985
2986 /**
2987 * DOC: Time Events - what is it?
2988 *
2989 * Time Events are a fw feature that allows the driver to control the presence
2990 * of the device on the channel. Since the fw supports multiple channels
2991 * concurrently, the fw may choose to jump to another channel at any time.
2992 * In order to make sure that the fw is on a specific channel at a certain time
2993 * and for a certain duration, the driver needs to issue a time event.
2994 *
2995 * The simplest example is for BSS association. The driver issues a time event,
2996 * waits for it to start, and only then tells mac80211 that we can start the
2997 * association. This way, we make sure that the association will be done
2998 * smoothly and won't be interrupted by channel switch decided within the fw.
2999 */
3000
3001 /**
3002 * DOC: The flow against the fw
3003 *
3004 * When the driver needs to make sure we are in a certain channel, at a certain
3005 * time and for a certain duration, it sends a Time Event. The flow against the
3006 * fw goes like this:
3007 * 1) Driver sends a TIME_EVENT_CMD to the fw
3008 * 2) Driver gets the response for that command. This response contains the
3009 * Unique ID (UID) of the event.
3010 * 3) The fw sends notification when the event starts.
3011 *
3012 * Of course the API provides various options that allow to cover parameters
3013 * of the flow.
3014 * What is the duration of the event?
3015 * What is the start time of the event?
3016 * Is there an end-time for the event?
3017 * How much can the event be delayed?
3018 * Can the event be split?
3019 * If yes what is the maximal number of chunks?
3020 * etc...
3021 */
3022
3023 /*
3024 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
3025 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
3026 * the first fragment is scheduled.
3027 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
3028 * the first 2 fragments are scheduled.
3029 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
3030 * number of fragments are valid.
3031 *
3032 * Other than the constant defined above, specifying a fragmentation value 'x'
3033 * means that the event can be fragmented but only the first 'x' will be
3034 * scheduled.
3035 */
3036 #define IWX_TE_V2_FRAG_NONE 0
3037 #define IWX_TE_V2_FRAG_SINGLE 1
3038 #define IWX_TE_V2_FRAG_DUAL 2
3039 #define IWX_TE_V2_FRAG_MAX 0xfe
3040 #define IWX_TE_V2_FRAG_ENDLESS 0xff
3041
3042 /* Repeat the time event endlessly (until removed) */
3043 #define IWX_TE_V2_REPEAT_ENDLESS 0xff
3044 /* If a Time Event has bounded repetitions, this is the maximal value */
3045 #define IWX_TE_V2_REPEAT_MAX 0xfe
3046
3047 #define IWX_TE_V2_PLACEMENT_POS 12
3048 #define IWX_TE_V2_ABSENCE_POS 15
3049
3050 /* Time event policy values
3051 * A notification (both event and fragment) includes a status indicating weather
3052 * the FW was able to schedule the event or not. For fragment start/end
3053 * notification the status is always success. There is no start/end fragment
3054 * notification for monolithic events.
3055 *
3056 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
3057 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
3058 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
3059 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
3060 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
3061 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
3062 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
3063 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
3064 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
3065 * @IWX_TE_V2_DEP_OTHER: depends on another time event
3066 * @IWX_TE_V2_DEP_TSF: depends on a specific time
3067 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of the same MAC
3068 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event.
3069 */
3070 #define IWX_TE_V2_DEFAULT_POLICY 0x0
3071
3072 /* notifications (event start/stop, fragment start/stop) */
3073 #define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)
3074 #define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)
3075 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)
3076 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)
3077
3078 #define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)
3079 #define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)
3080 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)
3081 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)
3082 #define IWX_T2_V2_START_IMMEDIATELY (1 << 11)
3083
3084 #define IWX_TE_V2_NOTIF_MSK 0xff
3085
3086 /* placement characteristics */
3087 #define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS)
3088 #define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1))
3089 #define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2))
3090
3091 /* are we present or absent during the Time Event. */
3092 #define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS)
3093
3094 /**
3095 * struct iwx_time_event_cmd_api - configuring Time Events
3096 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
3097 * with version 1. determined by IWX_UCODE_TLV_FLAGS)
3098 * ( IWX_TIME_EVENT_CMD = 0x29 )
3099 * @id_and_color: ID and color of the relevant MAC
3100 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3101 * @id: this field has two meanings, depending on the action:
3102 * If the action is ADD, then it means the type of event to add.
3103 * For all other actions it is the unique event ID assigned when the
3104 * event was added by the FW.
3105 * @apply_time: When to start the Time Event (in GP2)
3106 * @max_delay: maximum delay to event's start (apply time), in TU
3107 * @depends_on: the unique ID of the event we depend on (if any)
3108 * @interval: interval between repetitions, in TU
3109 * @duration: duration of event in TU
3110 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS
3111 * @max_frags: maximal number of fragments the Time Event can be divided to
3112 * @policy: defines whether uCode shall notify the host or other uCode modules
3113 * on event and/or fragment start and/or end
3114 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF
3115 * IWX_TE_EVENT_SOCIOPATHIC
3116 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_*
3117 */
3118 struct iwx_time_event_cmd {
3119 /* COMMON_INDEX_HDR_API_S_VER_1 */
3120 uint32_t id_and_color;
3121 uint32_t action;
3122 uint32_t id;
3123 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */
3124 uint32_t apply_time;
3125 uint32_t max_delay;
3126 uint32_t depends_on;
3127 uint32_t interval;
3128 uint32_t duration;
3129 uint8_t repeat;
3130 uint8_t max_frags;
3131 uint16_t policy;
3132 } __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */
3133
3134 /**
3135 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd
3136 * @status: bit 0 indicates success, all others specify errors
3137 * @id: the Time Event type
3138 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
3139 * @id_and_color: ID and color of the relevant MAC
3140 */
3141 struct iwx_time_event_resp {
3142 uint32_t status;
3143 uint32_t id;
3144 uint32_t unique_id;
3145 uint32_t id_and_color;
3146 } __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */
3147
3148 /**
3149 * struct iwx_time_event_notif - notifications of time event start/stop
3150 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a )
3151 * @timestamp: action timestamp in GP2
3152 * @session_id: session's unique id
3153 * @unique_id: unique id of the Time Event itself
3154 * @id_and_color: ID and color of the relevant MAC
3155 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END
3156 * @status: true if scheduled, false otherwise (not executed)
3157 */
3158 struct iwx_time_event_notif {
3159 uint32_t timestamp;
3160 uint32_t session_id;
3161 uint32_t unique_id;
3162 uint32_t id_and_color;
3163 uint32_t action;
3164 uint32_t status;
3165 } __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
3166
3167 /**
3168 * enum iwx_session_prot_conf_id - session protection's configurations
3169 * @SESSION_PROTECT_CONF_ASSOC: Start a session protection for association.
3170 * The firmware will allocate two events.
3171 * Valid for BSS_STA and P2P_STA.
3172 * * A rather short event that can't be fragmented and with a very
3173 * high priority. If every goes well (99% of the cases) the
3174 * association should complete within this first event. During
3175 * that event, no other activity will happen in the firmware,
3176 * which is why it can't be too long.
3177 * The length of this event is hard-coded in the firmware: 300TUs.
3178 * * Another event which can be much longer (its duration is
3179 * configurable by the driver) which has a slightly lower
3180 * priority and that can be fragmented allowing other activities
3181 * to run while this event is running.
3182 * The firmware will automatically remove both events once the driver sets
3183 * the BSS MAC as associated. Neither of the events will be removed
3184 * for the P2P_STA MAC.
3185 * Only the duration is configurable for this protection.
3186 * @SESSION_PROTECT_CONF_GO_CLIENT_ASSOC: not used
3187 * @SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV: Schedule the P2P Device to be in
3188 * listen mode. Will be fragmented. Valid only on the P2P Device MAC.
3189 * Valid only on the P2P Device MAC. The firmware will take into account
3190 * the duration, the interval and the repetition count.
3191 * @SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION: Schedule the P2P Device to be be
3192 * able to run the GO Negotiation. Will not be fragmented and not
3193 * repetitive. Valid only on the P2P Device MAC. Only the duration will
3194 * be taken into account.
3195 * @SESSION_PROTECT_CONF_MAX_ID: not used
3196 */
3197 enum iwx_session_prot_conf_id {
3198 IWX_SESSION_PROTECT_CONF_ASSOC,
3199 IWX_SESSION_PROTECT_CONF_GO_CLIENT_ASSOC,
3200 IWX_SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV,
3201 IWX_SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION,
3202 IWX_SESSION_PROTECT_CONF_MAX_ID,
3203 }; /* SESSION_PROTECTION_CONF_ID_E_VER_1 */
3204
3205 /**
3206 * struct iwx_session_prot_cmd - configure a session protection
3207 * @id_and_color: the id and color of the mac for which this session protection
3208 * is sent
3209 * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE
3210 * @conf_id: see &enum iwx_mvm_session_prot_conf_id
3211 * @duration_tu: the duration of the whole protection in TUs.
3212 * @repetition_count: not used
3213 * @interval: not used
3214 *
3215 * Note: the session protection will always be scheduled to start as
3216 * early as possible, but the maximum delay is configuration dependent.
3217 * The firmware supports only one concurrent session protection per vif.
3218 * Adding a new session protection will remove any currently running session.
3219 */
3220 struct iwx_session_prot_cmd {
3221 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */
3222 uint32_t id_and_color;
3223 uint32_t action;
3224 uint32_t conf_id;
3225 uint32_t duration_tu;
3226 uint32_t repetition_count;
3227 uint32_t interval;
3228 } __packed; /* SESSION_PROTECTION_CMD_API_S_VER_1 */
3229
3230 /**
3231 * struct iwx_session_prot_notif - session protection started / ended
3232 * @mac_id: the mac id for which the session protection started / ended
3233 * @status: 1 means success, 0 means failure
3234 * @start: 1 means the session protection started, 0 means it ended
3235 * @conf_id: see &enum iwx_mvm_session_prot_conf_id
3236 *
3237 * Note that any session protection will always get two notifications: start
3238 * and end even the firmware could not schedule it.
3239 */
3240 struct iwx_session_prot_notif {
3241 uint32_t mac_id;
3242 uint32_t status;
3243 uint32_t start;
3244 uint32_t conf_id;
3245 } __packed; /* SESSION_PROTECTION_NOTIFICATION_API_S_VER_2 */
3246
3247
3248 /* Bindings and Time Quota */
3249
3250 /**
3251 * struct iwx_binding_cmd - configuring bindings
3252 * ( IWX_BINDING_CONTEXT_CMD = 0x2b )
3253 * @id_and_color: ID and color of the relevant Binding
3254 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3255 * @macs: array of MAC id and colors which belong to the binding
3256 * @phy: PHY id and color which belongs to the binding
3257 * @lmac_id: the lmac id the binding belongs to
3258 */
3259 struct iwx_binding_cmd {
3260 /* COMMON_INDEX_HDR_API_S_VER_1 */
3261 uint32_t id_and_color;
3262 uint32_t action;
3263 /* IWX_BINDING_DATA_API_S_VER_1 */
3264 uint32_t macs[IWX_MAX_MACS_IN_BINDING];
3265 uint32_t phy;
3266 uint32_t lmac_id;
3267 } __packed; /* IWX_BINDING_CMD_API_S_VER_2 */
3268
3269 #define IWX_LMAC_24G_INDEX 0
3270 #define IWX_LMAC_5G_INDEX 1
3271
3272 /* The maximal number of fragments in the FW's schedule session */
3273 #define IWX_MAX_QUOTA 128
3274
3275 /**
3276 * struct iwx_time_quota_data - configuration of time quota per binding
3277 * @id_and_color: ID and color of the relevant Binding
3278 * @quota: absolute time quota in TU. The scheduler will try to divide the
3279 * remaining quota (after Time Events) according to this quota.
3280 * @max_duration: max uninterrupted context duration in TU
3281 */
3282 struct iwx_time_quota_data {
3283 uint32_t id_and_color;
3284 uint32_t quota;
3285 uint32_t max_duration;
3286 } __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */
3287
3288 /**
3289 * struct iwx_time_quota_cmd - configuration of time quota between bindings
3290 * ( IWX_TIME_QUOTA_CMD = 0x2c )
3291 * @quotas: allocations per binding
3292 */
3293 struct iwx_time_quota_cmd {
3294 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS];
3295 } __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
3296
3297
3298 /* PHY context */
3299
3300 /* Supported bands */
3301 #define IWX_PHY_BAND_5 (0)
3302 #define IWX_PHY_BAND_24 (1)
3303
3304 /* Supported channel width, vary if there is VHT support */
3305 #define IWX_PHY_VHT_CHANNEL_MODE20 (0x0)
3306 #define IWX_PHY_VHT_CHANNEL_MODE40 (0x1)
3307 #define IWX_PHY_VHT_CHANNEL_MODE80 (0x2)
3308 #define IWX_PHY_VHT_CHANNEL_MODE160 (0x3)
3309
3310 /*
3311 * Control channel position:
3312 * For legacy set bit means upper channel, otherwise lower.
3313 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
3314 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
3315 * center_freq
3316 * |
3317 * 40Mhz |_______|_______|
3318 * 80Mhz |_______|_______|_______|_______|
3319 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
3320 * code 011 010 001 000 | 100 101 110 111
3321 */
3322 #define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0)
3323 #define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1)
3324 #define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2)
3325 #define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3)
3326 #define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
3327 #define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
3328 #define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
3329 #define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
3330
3331 /*
3332 * @band: IWX_PHY_BAND_*
3333 * @channel: channel number
3334 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3335 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3336 */
3337 struct iwx_fw_channel_info_v1 {
3338 uint8_t band;
3339 uint8_t channel;
3340 uint8_t width;
3341 uint8_t ctrl_pos;
3342 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
3343
3344 /*
3345 * struct iwx_fw_channel_info - channel information
3346 *
3347 * @channel: channel number
3348 * @band: PHY_BAND_*
3349 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3350 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3351 * @reserved: for future use and alignment
3352 */
3353 struct iwx_fw_channel_info {
3354 uint32_t channel;
3355 uint8_t band;
3356 uint8_t width;
3357 uint8_t ctrl_pos;
3358 uint8_t reserved;
3359 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
3360
3361 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
3362 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
3363 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS)
3364 #define IWX_PHY_RX_CHAIN_VALID_POS (1)
3365 #define IWX_PHY_RX_CHAIN_VALID_MSK \
3366 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS)
3367 #define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4)
3368 #define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \
3369 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS)
3370 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
3371 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
3372 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
3373 #define IWX_PHY_RX_CHAIN_CNT_POS (10)
3374 #define IWX_PHY_RX_CHAIN_CNT_MSK \
3375 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS)
3376 #define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12)
3377 #define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \
3378 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS)
3379 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
3380 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \
3381 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS)
3382
3383 /* TODO: fix the value, make it depend on firmware at runtime? */
3384 #define IWX_NUM_PHY_CTX 3
3385
3386 /**
3387 * struct iwl_phy_context_cmd - config of the PHY context
3388 * ( IWX_PHY_CONTEXT_CMD = 0x8 )
3389 * @id_and_color: ID and color of the relevant Binding
3390 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3391 * @lmac_id: the lmac id the phy context belongs to
3392 * @ci: channel info
3393 * @rxchain_info: ???
3394 * @dsp_cfg_flags: set to 0
3395 * @reserved: reserved to align to 64 bit
3396 */
3397 struct iwx_phy_context_cmd_uhb {
3398 /* COMMON_INDEX_HDR_API_S_VER_1 */
3399 uint32_t id_and_color;
3400 uint32_t action;
3401 /* PHY_CONTEXT_DATA_API_S_VER_3 */
3402 struct iwx_fw_channel_info ci;
3403 uint32_t lmac_id;
3404 uint32_t rxchain_info;
3405 uint32_t dsp_cfg_flags;
3406 uint32_t reserved;
3407 } __packed; /* PHY_CONTEXT_CMD_API_VER_3 */
3408 struct iwx_phy_context_cmd {
3409 /* COMMON_INDEX_HDR_API_S_VER_1 */
3410 uint32_t id_and_color;
3411 uint32_t action;
3412 /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */
3413 struct iwx_fw_channel_info_v1 ci;
3414 uint32_t lmac_id;
3415 uint32_t rxchain_info; /* reserved in _VER_4 */
3416 uint32_t dsp_cfg_flags;
3417 uint32_t reserved;
3418 } __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */
3419
3420 /* TODO: complete missing documentation */
3421 /**
3422 * struct iwx_phy_context_cmd - config of the PHY context
3423 * ( IWX_PHY_CONTEXT_CMD = 0x8 )
3424 * @id_and_color: ID and color of the relevant Binding
3425 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3426 * @apply_time: 0 means immediate apply and context switch.
3427 * other value means apply new params after X usecs
3428 * @tx_param_color: ???
3429 * @channel_info:
3430 * @txchain_info: ???
3431 * @rxchain_info: ???
3432 * @acquisition_data: ???
3433 * @dsp_cfg_flags: set to 0
3434 */
3435 /*
3436 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased
3437 * the size of fw_channel_info from v1 to v2.
3438 * To keep things simple we define two versions of this struct, and both
3439 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark
3440 * magic with pointers to struct members instead.)
3441 */
3442 /* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */
3443 struct iwx_phy_context_cmd_uhb_v1 {
3444 /* COMMON_INDEX_HDR_API_S_VER_1 */
3445 uint32_t id_and_color;
3446 uint32_t action;
3447 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */
3448 uint32_t apply_time;
3449 uint32_t tx_param_color;
3450 struct iwx_fw_channel_info ci;
3451 uint32_t txchain_info;
3452 uint32_t rxchain_info;
3453 uint32_t acquisition_data;
3454 uint32_t dsp_cfg_flags;
3455 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */
3456 /* This version must be used otherwise: */
3457 struct iwx_phy_context_cmd_v1 {
3458 /* COMMON_INDEX_HDR_API_S_VER_1 */
3459 uint32_t id_and_color;
3460 uint32_t action;
3461 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */
3462 uint32_t apply_time;
3463 uint32_t tx_param_color;
3464 struct iwx_fw_channel_info_v1 ci;
3465 uint32_t txchain_info;
3466 uint32_t rxchain_info;
3467 uint32_t acquisition_data;
3468 uint32_t dsp_cfg_flags;
3469 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */
3470
3471
3472 #define IWX_RX_INFO_PHY_CNT 8
3473 #define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1
3474 #define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
3475 #define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
3476 #define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
3477 #define IWX_RX_INFO_ENERGY_ANT_A_POS 0
3478 #define IWX_RX_INFO_ENERGY_ANT_B_POS 8
3479 #define IWX_RX_INFO_ENERGY_ANT_C_POS 16
3480
3481 #define IWX_RX_INFO_AGC_IDX 1
3482 #define IWX_RX_INFO_RSSI_AB_IDX 2
3483 #define IWX_OFDM_AGC_A_MSK 0x0000007f
3484 #define IWX_OFDM_AGC_A_POS 0
3485 #define IWX_OFDM_AGC_B_MSK 0x00003f80
3486 #define IWX_OFDM_AGC_B_POS 7
3487 #define IWX_OFDM_AGC_CODE_MSK 0x3fe00000
3488 #define IWX_OFDM_AGC_CODE_POS 20
3489 #define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff
3490 #define IWX_OFDM_RSSI_A_POS 0
3491 #define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00
3492 #define IWX_OFDM_RSSI_ALLBAND_A_POS 8
3493 #define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000
3494 #define IWX_OFDM_RSSI_B_POS 16
3495 #define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
3496 #define IWX_OFDM_RSSI_ALLBAND_B_POS 24
3497
3498 /**
3499 * struct iwx_rx_phy_info - phy info
3500 * (IWX_REPLY_RX_PHY_CMD = 0xc0)
3501 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
3502 * @cfg_phy_cnt: configurable DSP phy data byte count
3503 * @stat_id: configurable DSP phy data set ID
3504 * @reserved1:
3505 * @system_timestamp: GP2 at on air rise
3506 * @timestamp: TSF at on air rise
3507 * @beacon_time_stamp: beacon at on-air rise
3508 * @phy_flags: general phy flags: band, modulation, ...
3509 * @channel: channel number
3510 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
3511 * @rate_n_flags: IWX_RATE_MCS_*
3512 * @byte_count: frame's byte-count
3513 * @frame_time: frame's time on the air, based on byte count and frame rate
3514 * calculation
3515 * @mac_active_msk: what MACs were active when the frame was received
3516 *
3517 * Before each Rx, the device sends this data. It contains PHY information
3518 * about the reception of the packet.
3519 */
3520 struct iwx_rx_phy_info {
3521 uint8_t non_cfg_phy_cnt;
3522 uint8_t cfg_phy_cnt;
3523 uint8_t stat_id;
3524 uint8_t reserved1;
3525 uint32_t system_timestamp;
3526 uint64_t timestamp;
3527 uint32_t beacon_time_stamp;
3528 uint16_t phy_flags;
3529 #define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
3530 uint16_t channel;
3531 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT];
3532 uint32_t rate_n_flags;
3533 uint32_t byte_count;
3534 uint16_t mac_active_msk;
3535 uint16_t frame_time;
3536 } __packed;
3537
3538 struct iwx_rx_mpdu_res_start {
3539 uint16_t byte_count;
3540 uint16_t reserved;
3541 } __packed;
3542
3543 /**
3544 * Values to parse %iwx_rx_phy_info phy_flags
3545 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
3546 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK:
3547 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
3548 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND:
3549 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
3550 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
3551 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
3552 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
3553 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
3554 */
3555 #define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)
3556 #define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)
3557 #define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)
3558 #define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)
3559 #define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)
3560 #define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4
3561 #define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7)
3562 #define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)
3563 #define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)
3564 #define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)
3565
3566 /**
3567 * Values written by fw for each Rx packet
3568 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
3569 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
3570 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
3571 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID:
3572 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
3573 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
3574 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
3575 * in the driver.
3576 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
3577 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
3578 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
3579 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
3580 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
3581 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
3582 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
3583 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
3584 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
3585 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
3586 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
3587 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
3588 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
3589 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
3590 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
3591 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
3592 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
3593 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK:
3594 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL:
3595 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK:
3596 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK:
3597 */
3598 #define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)
3599 #define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)
3600 #define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)
3601 #define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)
3602 #define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)
3603 #define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)
3604 #define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)
3605 #define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
3606 #define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)
3607 #define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)
3608 #define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)
3609 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)
3610 #define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)
3611 #define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)
3612 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)
3613 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)
3614 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)
3615 #define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)
3616 #define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)
3617 #define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)
3618 #define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)
3619 #define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)
3620 #define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)
3621 #define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)
3622 #define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)
3623 #define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)
3624 #define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)
3625
3626 #define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03
3627 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0
3628 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3
3629
3630 #define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f
3631 #define IWX_RX_MPDU_MFLG2_PAD 0x20
3632 #define IWX_RX_MPDU_MFLG2_AMSDU 0x40
3633
3634 #define IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f
3635 #define IWX_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80
3636
3637 #define IWX_RX_MPDU_PHY_AMPDU (1 << 5)
3638 #define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6)
3639 #define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7)
3640 #define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7)
3641 #define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8)
3642
3643 struct iwx_rx_mpdu_desc_v3 {
3644 union {
3645 uint32_t filter_match;
3646 uint32_t phy_data3;
3647 };
3648 union {
3649 uint32_t rss_hash;
3650 uint32_t phy_data2;
3651 };
3652 uint32_t partial_hash; /* ip/tcp header hash w/o some fields */
3653 uint16_t raw_xsum;
3654 uint16_t reserved_xsum;
3655 uint32_t rate_n_flags;
3656 uint8_t energy_a;
3657 uint8_t energy_b;
3658 uint8_t channel;
3659 uint8_t mac_context;
3660 uint32_t gp2_on_air_rise;
3661 union {
3662 /*
3663 * TSF value on air rise (INA), only valid if
3664 * IWX_RX_MPDU_PHY_TSF_OVERLOAD isn't set
3665 */
3666 struct {
3667 uint32_t tsf_on_air_rise0;
3668 uint32_t tsf_on_air_rise1;
3669 };
3670
3671 struct {
3672 uint32_t phy_data0;
3673
3674 /* Only valid if IWX_RX_MPDU_PHY_TSF_OVERLOAD is set. */
3675 uint32_t phy_data1;
3676 };
3677 };
3678 uint32_t reserved[2];
3679 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
3680 RX_MPDU_RES_START_API_S_VER_5 */
3681
3682 struct iwx_rx_mpdu_desc_v1 {
3683 union {
3684 uint32_t rss_hash;
3685 uint32_t phy_data2;
3686 };
3687 union {
3688 uint32_t filter_match;
3689 uint32_t phy_data3;
3690 };
3691 uint32_t rate_n_flags;
3692 uint8_t energy_a;
3693 uint8_t energy_b;
3694 uint8_t channel;
3695 uint8_t mac_context;
3696 uint32_t gp2_on_air_rise;
3697 union {
3698 struct {
3699 uint32_t tsf_on_air_rise0;
3700 uint32_t tsf_on_air_rise1;
3701 };
3702 struct {
3703 uint32_t phy_data0;
3704 uint32_t phy_data1;
3705 };
3706 };
3707 } __packed;
3708
3709 #define IWX_RX_REORDER_DATA_INVALID_BAID 0x7f
3710
3711 #define IWX_RX_MPDU_REORDER_NSSN_MASK 0x00000fff
3712 #define IWX_RX_MPDU_REORDER_SN_MASK 0x00fff000
3713 #define IWX_RX_MPDU_REORDER_SN_SHIFT 12
3714 #define IWX_RX_MPDU_REORDER_BAID_MASK 0x7f000000
3715 #define IWX_RX_MPDU_REORDER_BAID_SHIFT 24
3716 #define IWX_RX_MPDU_REORDER_BA_OLD_SN 0x80000000
3717
3718 struct iwx_rx_mpdu_desc {
3719 uint16_t mpdu_len;
3720 uint8_t mac_flags1;
3721 uint8_t mac_flags2;
3722 uint8_t amsdu_info;
3723 uint16_t phy_info;
3724 uint8_t mac_phy_idx;
3725 uint16_t raw_csum;
3726 union {
3727 uint16_t l3l4_flags;
3728 uint16_t phy_data4;
3729 };
3730 uint16_t status;
3731 uint8_t hash_filter;
3732 uint8_t sta_id_flags;
3733 uint32_t reorder_data;
3734 union {
3735 struct iwx_rx_mpdu_desc_v1 v1;
3736 struct iwx_rx_mpdu_desc_v3 v3;
3737 };
3738 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
3739 RX_MPDU_RES_START_API_S_VER_4,
3740 RX_MPDU_RES_START_API_S_VER_5 */
3741
3742 #define IWX_RX_DESC_SIZE_V1 ((sizeof(struct iwx_rx_mpdu_desc) - \
3743 sizeof(struct iwx_rx_mpdu_desc_v3)) + sizeof(struct iwx_rx_mpdu_desc_v1))
3744
3745 struct iwx_frame_release {
3746 uint8_t baid;
3747 uint8_t reserved;
3748 uint16_t nssn;
3749 };
3750
3751 /**
3752 * enum iwx_bar_frame_release_sta_tid - STA/TID information for BAR release
3753 * @IWX_BAR_FRAME_RELEASE_TID_MASK: TID mask
3754 * @IWX_BAR_FRAME_RELEASE_STA_MASK: STA mask
3755 */
3756 #define IWX_BAR_FRAME_RELEASE_TID_MASK 0x0000000f
3757 #define IWX_BAR_FRAME_RELEASE_STA_MASK 0x000001f0
3758 #define IWX_BAR_FRAME_RELEASE_STA_SHIFT 4
3759
3760 /**
3761 * enum iwx_bar_frame_release_ba_info - BA information for BAR release
3762 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
3763 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
3764 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
3765 */
3766 #define IWX_BAR_FRAME_RELEASE_NSSN_MASK 0x00000fff
3767 #define IWX_BAR_FRAME_RELEASE_SN_MASK 0x00fff000
3768 #define IWX_BAR_FRAME_RELEASE_SN_SHIFT 12
3769 #define IWX_BAR_FRAME_RELEASE_BAID_MASK 0x3f000000
3770 #define IWX_BAR_FRAME_RELEASE_BAID_SHIFT 24
3771
3772 /**
3773 * struct iwx_bar_frame_release - frame release from BAR info
3774 * @sta_tid: STA & TID information, see &enum iwx_bar_frame_release_sta_tid.
3775 * @ba_info: BA information, see &enum iwx_bar_frame_release_ba_info.
3776 */
3777 struct iwx_bar_frame_release {
3778 uint32_t sta_tid;
3779 uint32_t ba_info;
3780 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
3781
3782 /**
3783 * struct iwx_radio_version_notif - information on the radio version
3784 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 )
3785 * @radio_flavor:
3786 * @radio_step:
3787 * @radio_dash:
3788 */
3789 struct iwx_radio_version_notif {
3790 uint32_t radio_flavor;
3791 uint32_t radio_step;
3792 uint32_t radio_dash;
3793 } __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */
3794
3795 #define IWX_CARD_ENABLED 0x00
3796 #define IWX_HW_CARD_DISABLED 0x01
3797 #define IWX_SW_CARD_DISABLED 0x02
3798 #define IWX_CT_KILL_CARD_DISABLED 0x04
3799 #define IWX_HALT_CARD_DISABLED 0x08
3800 #define IWX_CARD_DISABLED_MSK 0x0f
3801 #define IWX_CARD_IS_RX_ON 0x10
3802
3803 /**
3804 * struct iwx_radio_version_notif - information on the radio version
3805 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 )
3806 * @flags: %iwx_card_state_flags
3807 */
3808 struct iwx_card_state_notif {
3809 uint32_t flags;
3810 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
3811
3812 /**
3813 * struct iwx_missed_beacons_notif - information on missed beacons
3814 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 )
3815 * @mac_id: interface ID
3816 * @consec_missed_beacons_since_last_rx: number of consecutive missed
3817 * beacons since last RX.
3818 * @consec_missed_beacons: number of consecutive missed beacons
3819 * @num_expected_beacons:
3820 * @num_recvd_beacons:
3821 */
3822 struct iwx_missed_beacons_notif {
3823 uint32_t mac_id;
3824 uint32_t consec_missed_beacons_since_last_rx;
3825 uint32_t consec_missed_beacons;
3826 uint32_t num_expected_beacons;
3827 uint32_t num_recvd_beacons;
3828 } __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */
3829
3830 /**
3831 * struct iwx_mfuart_load_notif - mfuart image version & status
3832 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 )
3833 * @installed_ver: installed image version
3834 * @external_ver: external image version
3835 * @status: MFUART loading status
3836 * @duration: MFUART loading time
3837 */
3838 struct iwx_mfuart_load_notif {
3839 uint32_t installed_ver;
3840 uint32_t external_ver;
3841 uint32_t status;
3842 uint32_t duration;
3843 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
3844
3845 /**
3846 * struct iwx_set_calib_default_cmd - set default value for calibration.
3847 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e )
3848 * @calib_index: the calibration to set value for
3849 * @length: of data
3850 * @data: the value to set for the calibration result
3851 */
3852 struct iwx_set_calib_default_cmd {
3853 uint16_t calib_index;
3854 uint16_t length;
3855 uint8_t data[0];
3856 } __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */
3857
3858 #define IWX_MAX_PORT_ID_NUM 2
3859 #define IWX_MAX_MCAST_FILTERING_ADDRESSES 256
3860
3861 /**
3862 * struct iwx_mcast_filter_cmd - configure multicast filter.
3863 * @filter_own: Set 1 to filter out multicast packets sent by station itself
3864 * @port_id: Multicast MAC addresses array specifier. This is a strange way
3865 * to identify network interface adopted in host-device IF.
3866 * It is used by FW as index in array of addresses. This array has
3867 * IWX_MAX_PORT_ID_NUM members.
3868 * @count: Number of MAC addresses in the array
3869 * @pass_all: Set 1 to pass all multicast packets.
3870 * @bssid: current association BSSID.
3871 * @addr_list: Place holder for array of MAC addresses.
3872 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
3873 */
3874 struct iwx_mcast_filter_cmd {
3875 uint8_t filter_own;
3876 uint8_t port_id;
3877 uint8_t count;
3878 uint8_t pass_all;
3879 uint8_t bssid[6];
3880 uint8_t reserved[2];
3881 uint8_t addr_list[0];
3882 } __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */
3883
3884 struct iwx_statistics_dbg {
3885 uint32_t burst_check;
3886 uint32_t burst_count;
3887 uint32_t wait_for_silence_timeout_cnt;
3888 uint32_t reserved[3];
3889 } __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */
3890
3891 struct iwx_statistics_div {
3892 uint32_t tx_on_a;
3893 uint32_t tx_on_b;
3894 uint32_t exec_time;
3895 uint32_t probe_time;
3896 uint32_t rssi_ant;
3897 uint32_t reserved2;
3898 } __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */
3899
3900 struct iwx_statistics_bt_activity {
3901 uint32_t hi_priority_tx_req_cnt;
3902 uint32_t hi_priority_tx_denied_cnt;
3903 uint32_t lo_priority_tx_req_cnt;
3904 uint32_t lo_priority_tx_denied_cnt;
3905 uint32_t hi_priority_rx_req_cnt;
3906 uint32_t hi_priority_rx_denied_cnt;
3907 uint32_t lo_priority_rx_req_cnt;
3908 uint32_t lo_priority_rx_denied_cnt;
3909 } __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3910
3911 struct iwx_statistics_general_common {
3912 uint32_t radio_temperature;
3913 struct iwx_statistics_dbg dbg;
3914 uint32_t sleep_time;
3915 uint32_t slots_out;
3916 uint32_t slots_idle;
3917 uint32_t ttl_timestamp;
3918 struct iwx_statistics_div slow_div;
3919 uint32_t rx_enable_counter;
3920 /*
3921 * num_of_sos_states:
3922 * count the number of times we have to re-tune
3923 * in order to get out of bad PHY status
3924 */
3925 uint32_t num_of_sos_states;
3926 uint32_t beacon_filtered;
3927 uint32_t missed_beacons;
3928 uint8_t beacon_filter_average_energy;
3929 uint8_t beacon_filter_reason;
3930 uint8_t beacon_filter_current_energy;
3931 uint8_t beacon_filter_reserved;
3932 uint32_t beacon_filter_delta_time;
3933 struct iwx_statistics_bt_activity bt_activity;
3934 uint64_t rx_time;
3935 uint64_t on_time_rf;
3936 uint64_t on_time_scan;
3937 uint64_t tx_time;
3938 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */
3939
3940 struct iwx_statistics_rx_non_phy {
3941 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3942 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3943 uint32_t non_bssid_frames; /* number of frames with BSSID that
3944 * doesn't belong to the STA BSSID */
3945 uint32_t filtered_frames; /* count frames that were dumped in the
3946 * filtering process */
3947 uint32_t non_channel_beacons; /* beacons with our bss id but not on
3948 * our serving channel */
3949 uint32_t channel_beacons; /* beacons with our bss id and in our
3950 * serving channel */
3951 uint32_t num_missed_bcon; /* number of missed beacons */
3952 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
3953 * ADC was in saturation */
3954 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
3955 * for INA */
3956 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
3957 uint32_t interference_data_flag; /* flag for interference data
3958 * availability. 1 when data is
3959 * available. */
3960 uint32_t channel_load; /* counts RX Enable time in uSec */
3961 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
3962 * and CCK) counter */
3963 uint32_t beacon_rssi_a;
3964 uint32_t beacon_rssi_b;
3965 uint32_t beacon_rssi_c;
3966 uint32_t beacon_energy_a;
3967 uint32_t beacon_energy_b;
3968 uint32_t beacon_energy_c;
3969 uint32_t num_bt_kills;
3970 uint32_t mac_id;
3971 uint32_t directed_data_mpdu;
3972 } __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3973
3974 struct iwx_statistics_rx_phy {
3975 uint32_t ina_cnt;
3976 uint32_t fina_cnt;
3977 uint32_t plcp_err;
3978 uint32_t crc32_err;
3979 uint32_t overrun_err;
3980 uint32_t early_overrun_err;
3981 uint32_t crc32_good;
3982 uint32_t false_alarm_cnt;
3983 uint32_t fina_sync_err_cnt;
3984 uint32_t sfd_timeout;
3985 uint32_t fina_timeout;
3986 uint32_t unresponded_rts;
3987 uint32_t rxe_frame_limit_overrun;
3988 uint32_t sent_ack_cnt;
3989 uint32_t sent_cts_cnt;
3990 uint32_t sent_ba_rsp_cnt;
3991 uint32_t dsp_self_kill;
3992 uint32_t mh_format_err;
3993 uint32_t re_acq_main_rssi_sum;
3994 uint32_t reserved;
3995 } __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */
3996
3997 struct iwx_statistics_rx_ht_phy {
3998 uint32_t plcp_err;
3999 uint32_t overrun_err;
4000 uint32_t early_overrun_err;
4001 uint32_t crc32_good;
4002 uint32_t crc32_err;
4003 uint32_t mh_format_err;
4004 uint32_t agg_crc32_good;
4005 uint32_t agg_mpdu_cnt;
4006 uint32_t agg_cnt;
4007 uint32_t unsupport_mcs;
4008 } __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */
4009
4010 /*
4011 * The first MAC indices (starting from 0)
4012 * are available to the driver, AUX follows
4013 */
4014 #define IWX_MAC_INDEX_AUX 4
4015 #define IWX_MAC_INDEX_MIN_DRIVER 0
4016 #define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX
4017
4018 #define IWX_STATION_COUNT 16
4019
4020 #define IWX_MAX_CHAINS 3
4021
4022 struct iwx_statistics_tx_non_phy_agg {
4023 uint32_t ba_timeout;
4024 uint32_t ba_reschedule_frames;
4025 uint32_t scd_query_agg_frame_cnt;
4026 uint32_t scd_query_no_agg;
4027 uint32_t scd_query_agg;
4028 uint32_t scd_query_mismatch;
4029 uint32_t frame_not_ready;
4030 uint32_t underrun;
4031 uint32_t bt_prio_kill;
4032 uint32_t rx_ba_rsp_cnt;
4033 int8_t txpower[IWX_MAX_CHAINS];
4034 int8_t reserved;
4035 uint32_t reserved2;
4036 } __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
4037
4038 struct iwx_statistics_tx_channel_width {
4039 uint32_t ext_cca_narrow_ch20[1];
4040 uint32_t ext_cca_narrow_ch40[2];
4041 uint32_t ext_cca_narrow_ch80[3];
4042 uint32_t ext_cca_narrow_ch160[4];
4043 uint32_t last_tx_ch_width_indx;
4044 uint32_t rx_detected_per_ch_width[4];
4045 uint32_t success_per_ch_width[4];
4046 uint32_t fail_per_ch_width[4];
4047 }; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
4048
4049 struct iwx_statistics_tx {
4050 uint32_t preamble_cnt;
4051 uint32_t rx_detected_cnt;
4052 uint32_t bt_prio_defer_cnt;
4053 uint32_t bt_prio_kill_cnt;
4054 uint32_t few_bytes_cnt;
4055 uint32_t cts_timeout;
4056 uint32_t ack_timeout;
4057 uint32_t expected_ack_cnt;
4058 uint32_t actual_ack_cnt;
4059 uint32_t dump_msdu_cnt;
4060 uint32_t burst_abort_next_frame_mismatch_cnt;
4061 uint32_t burst_abort_missing_next_frame_cnt;
4062 uint32_t cts_timeout_collision;
4063 uint32_t ack_or_ba_timeout_collision;
4064 struct iwx_statistics_tx_non_phy_agg agg;
4065 struct iwx_statistics_tx_channel_width channel_width;
4066 } __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */
4067
4068 struct iwx_statistics_general {
4069 struct iwx_statistics_general_common common;
4070 uint32_t beacon_counter[IWX_MAC_INDEX_AUX];
4071 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX];
4072 uint8_t reserved[8 - IWX_MAC_INDEX_AUX];
4073 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */
4074
4075 struct iwx_statistics_rx {
4076 struct iwx_statistics_rx_phy ofdm;
4077 struct iwx_statistics_rx_phy cck;
4078 struct iwx_statistics_rx_non_phy general;
4079 struct iwx_statistics_rx_ht_phy ofdm_ht;
4080 } __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */
4081
4082 /*
4083 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
4084 *
4085 * By default, uCode issues this notification after receiving a beacon
4086 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
4087 * IWX_REPLY_STATISTICS_CMD 0x9c, above.
4088 *
4089 * Statistics counters continue to increment beacon after beacon, but are
4090 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD
4091 * 0x9c with CLEAR_STATS bit set (see above).
4092 *
4093 * uCode also issues this notification during scans. uCode clears statistics
4094 * appropriately so that each notification contains statistics for only the
4095 * one channel that has just been scanned.
4096 */
4097
4098 /**
4099 * struct iwx_statistics_load - RX statistics for multi-queue devices
4100 * @air_time: accumulated air time, per mac
4101 * @byte_count: accumulated byte count, per mac
4102 * @pkt_count: accumulated packet count, per mac
4103 * @avg_energy: average RSSI, per station
4104 */
4105 struct iwx_statistics_load {
4106 uint32_t air_time[IWX_MAC_INDEX_AUX];
4107 uint32_t byte_count[IWX_MAC_INDEX_AUX];
4108 uint32_t pkt_count[IWX_MAC_INDEX_AUX];
4109 uint8_t avg_energy[IWX_STATION_COUNT];
4110 } __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */
4111
4112 struct iwx_notif_statistics {
4113 uint32_t flag;
4114 struct iwx_statistics_rx rx;
4115 struct iwx_statistics_tx tx;
4116 struct iwx_statistics_general general;
4117 struct iwx_statistics_load load_stats;
4118 } __packed; /* STATISTICS_NTFY_API_S_VER_13 */
4119
4120
4121 /**
4122 * flags used in statistics notification
4123 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report
4124 */
4125 #define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01
4126
4127 /**
4128 * flags used in statistics command
4129 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report
4130 * that's sent after this command
4131 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics
4132 * notifications
4133 */
4134 #define IWX_STATISTICS_FLG_CLEAR 0x01
4135 #define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02
4136
4137 /**
4138 * struct iwx_statistics_cmd - statistics config command
4139 * @flags: IWX_STATISTICS_* flags
4140 */
4141 struct iwx_statistics_cmd {
4142 uint32_t flags;
4143 } __packed; /* STATISTICS_CMD_API_S_VER_1 */
4144
4145
4146 /***********************************
4147 * Smart Fifo API
4148 ***********************************/
4149 /* Smart Fifo state */
4150 #define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */
4151 #define IWX_SF_FULL_ON 1
4152 #define IWX_SF_UNINIT 2
4153 #define IWX_SF_INIT_OFF 3
4154 #define IWX_SF_HW_NUM_STATES 4
4155
4156 /* Smart Fifo possible scenario */
4157 #define IWX_SF_SCENARIO_SINGLE_UNICAST 0
4158 #define IWX_SF_SCENARIO_AGG_UNICAST 1
4159 #define IWX_SF_SCENARIO_MULTICAST 2
4160 #define IWX_SF_SCENARIO_BA_RESP 3
4161 #define IWX_SF_SCENARIO_TX_RESP 4
4162 #define IWX_SF_NUM_SCENARIO 5
4163
4164 #define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */
4165 #define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
4166
4167 /* smart FIFO default values */
4168 #define IWX_SF_W_MARK_SISO 4096
4169 #define IWX_SF_W_MARK_MIMO2 8192
4170 #define IWX_SF_W_MARK_MIMO3 6144
4171 #define IWX_SF_W_MARK_LEGACY 4096
4172 #define IWX_SF_W_MARK_SCAN 4096
4173
4174 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
4175 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
4176 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4177 #define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
4178 #define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4179 #define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
4180 #define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4181 #define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
4182 #define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
4183 #define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
4184 #define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
4185
4186 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
4187 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
4188 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
4189 #define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
4190 #define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
4191 #define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
4192 #define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
4193 #define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */
4194 #define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */
4195 #define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
4196 #define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
4197
4198 #define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
4199
4200 #define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
4201
4202 /**
4203 * Smart Fifo configuration command.
4204 * @state: smart fifo state, types listed in enum %iwx_sf_state.
4205 * @watermark: Minimum allowed available free space in RXF for transient state.
4206 * @long_delay_timeouts: aging and idle timer values for each scenario
4207 * in long delay state.
4208 * @full_on_timeouts: timer values for each scenario in full on state.
4209 */
4210 struct iwx_sf_cfg_cmd {
4211 uint32_t state;
4212 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER];
4213 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];
4214 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];
4215 } __packed; /* IWX_SF_CFG_API_S_VER_2 */
4216
4217 #define IWX_AC_BK 0
4218 #define IWX_AC_BE 1
4219 #define IWX_AC_VI 2
4220 #define IWX_AC_VO 3
4221 #define IWX_AC_NUM 4
4222
4223 /**
4224 * MAC context flags
4225 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
4226 * this will require CCK RTS/CTS2self.
4227 * RTS/CTS will protect full burst time.
4228 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection
4229 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
4230 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
4231 */
4232 #define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3)
4233 #define IWX_MAC_PROT_FLG_HT_PROT (1 << 23)
4234 #define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24)
4235 #define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)
4236
4237 #define IWX_MAC_FLG_SHORT_SLOT (1 << 4)
4238 #define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5)
4239
4240 /**
4241 * Supported MAC types
4242 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type
4243 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
4244 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
4245 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
4246 * @IWX_FW_MAC_TYPE_IBSS: IBSS
4247 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station
4248 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device
4249 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client
4250 * @IWX_FW_MAC_TYPE_GO: P2P GO
4251 * @IWX_FW_MAC_TYPE_TEST: ?
4252 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type
4253 */
4254 #define IWX_FW_MAC_TYPE_FIRST 1
4255 #define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST
4256 #define IWX_FW_MAC_TYPE_LISTENER 2
4257 #define IWX_FW_MAC_TYPE_PIBSS 3
4258 #define IWX_FW_MAC_TYPE_IBSS 4
4259 #define IWX_FW_MAC_TYPE_BSS_STA 5
4260 #define IWX_FW_MAC_TYPE_P2P_DEVICE 6
4261 #define IWX_FW_MAC_TYPE_P2P_STA 7
4262 #define IWX_FW_MAC_TYPE_GO 8
4263 #define IWX_FW_MAC_TYPE_TEST 9
4264 #define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST
4265 /* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */
4266
4267 /**
4268 * TSF hw timer ID
4269 * @IWX_TSF_ID_A: use TSF A
4270 * @IWX_TSF_ID_B: use TSF B
4271 * @IWX_TSF_ID_C: use TSF C
4272 * @IWX_TSF_ID_D: use TSF D
4273 * @IWX_NUM_TSF_IDS: number of TSF timers available
4274 */
4275 #define IWX_TSF_ID_A 0
4276 #define IWX_TSF_ID_B 1
4277 #define IWX_TSF_ID_C 2
4278 #define IWX_TSF_ID_D 3
4279 #define IWX_NUM_TSF_IDS 4
4280 /* IWX_TSF_ID_API_E_VER_1 */
4281
4282 /**
4283 * struct iwx_mac_data_ap - configuration data for AP MAC context
4284 * @beacon_time: beacon transmit time in system time
4285 * @beacon_tsf: beacon transmit time in TSF
4286 * @bi: beacon interval in TU
4287 * @bi_reciprocal: 2^32 / bi
4288 * @dtim_interval: dtim transmit time in TU
4289 * @dtim_reciprocal: 2^32 / dtim_interval
4290 * @mcast_qid: queue ID for multicast traffic
4291 * NOTE: obsolete from VER2 and on
4292 * @beacon_template: beacon template ID
4293 */
4294 struct iwx_mac_data_ap {
4295 uint32_t beacon_time;
4296 uint64_t beacon_tsf;
4297 uint32_t bi;
4298 uint32_t bi_reciprocal;
4299 uint32_t dtim_interval;
4300 uint32_t dtim_reciprocal;
4301 uint32_t mcast_qid;
4302 uint32_t beacon_template;
4303 } __packed; /* AP_MAC_DATA_API_S_VER_2 */
4304
4305 /**
4306 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context
4307 * @beacon_time: beacon transmit time in system time
4308 * @beacon_tsf: beacon transmit time in TSF
4309 * @bi: beacon interval in TU
4310 * @bi_reciprocal: 2^32 / bi
4311 * @beacon_template: beacon template ID
4312 */
4313 struct iwx_mac_data_ibss {
4314 uint32_t beacon_time;
4315 uint64_t beacon_tsf;
4316 uint32_t bi;
4317 uint32_t bi_reciprocal;
4318 uint32_t beacon_template;
4319 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
4320
4321 /**
4322 * enum iwx_mac_data_policy - policy of the data path for this MAC
4323 * @TWT_SUPPORTED: twt is supported
4324 * @MORE_DATA_ACK_SUPPORTED: AP supports More Data Ack according to
4325 * paragraph 9.4.1.17 in P802.11ax_D4 specification. Used for TWT
4326 * early termination detection.
4327 * @FLEXIBLE_TWT_SUPPORTED: AP supports flexible TWT schedule
4328 * @PROTECTED_TWT_SUPPORTED: AP supports protected TWT frames (with 11w)
4329 * @BROADCAST_TWT_SUPPORTED: AP and STA support broadcast TWT
4330 * @COEX_HIGH_PRIORITY_ENABLE: high priority mode for BT coex, to be used
4331 * during 802.1X negotiation (and allowed during 4-way-HS)
4332 */
4333 #define IWX_TWT_SUPPORTED BIT (1 << 0)
4334 #define IWX_MORE_DATA_ACK_SUPPORTED (1 << 1)
4335 #define IWX_FLEXIBLE_TWT_SUPPORTED (1 << 2)
4336 #define IWX_PROTECTED_TWT_SUPPORTED (1 << 3)
4337 #define IWX_BROADCAST_TWT_SUPPORTED (1 << 4)
4338 #define IWX_COEX_HIGH_PRIORITY_ENABLE (1 << 5)
4339
4340 /**
4341 * struct iwx_mac_data_sta - configuration data for station MAC context
4342 * @is_assoc: 1 for associated state, 0 otherwise
4343 * @dtim_time: DTIM arrival time in system time
4344 * @dtim_tsf: DTIM arrival time in TSF
4345 * @bi: beacon interval in TU, applicable only when associated
4346 * @data_policy: see &enum iwl_mac_data_policy
4347 * @dtim_interval: DTIM interval in TU, applicable only when associated
4348 * @listen_interval: in beacon intervals, applicable only when associated
4349 * @assoc_id: unique ID assigned by the AP during association
4350 */
4351 struct iwx_mac_data_sta {
4352 uint32_t is_assoc;
4353 uint32_t dtim_time;
4354 uint64_t dtim_tsf;
4355 uint32_t bi;
4356 uint32_t reserved1;
4357 uint32_t dtim_interval;
4358 uint32_t data_policy;
4359 uint32_t listen_interval;
4360 uint32_t assoc_id;
4361 uint32_t assoc_beacon_arrive_time;
4362 } __packed; /* IWX_STA_MAC_DATA_API_S_VER_2 */
4363
4364 /**
4365 * struct iwx_mac_data_go - configuration data for P2P GO MAC context
4366 * @ap: iwx_mac_data_ap struct with most config data
4367 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
4368 * 0 indicates that there is no CT window.
4369 * @opp_ps_enabled: indicate that opportunistic PS allowed
4370 */
4371 struct iwx_mac_data_go {
4372 struct iwx_mac_data_ap ap;
4373 uint32_t ctwin;
4374 uint32_t opp_ps_enabled;
4375 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
4376
4377 /**
4378 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context
4379 * @sta: iwx_mac_data_sta struct with most config data
4380 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
4381 * 0 indicates that there is no CT window.
4382 */
4383 struct iwx_mac_data_p2p_sta {
4384 struct iwx_mac_data_sta sta;
4385 uint32_t ctwin;
4386 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
4387
4388 /**
4389 * struct iwx_mac_data_pibss - Pseudo IBSS config data
4390 * @stats_interval: interval in TU between statistics notifications to host.
4391 */
4392 struct iwx_mac_data_pibss {
4393 uint32_t stats_interval;
4394 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
4395
4396 /*
4397 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC
4398 * context.
4399 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
4400 * other channels as well. This should be to true only in case that the
4401 * device is discoverable and there is an active GO. Note that setting this
4402 * field when not needed, will increase the number of interrupts and have
4403 * effect on the platform power, as this setting opens the Rx filters on
4404 * all macs.
4405 */
4406 struct iwx_mac_data_p2p_dev {
4407 uint32_t is_disc_extended;
4408 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
4409
4410 /**
4411 * MAC context filter flags
4412 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames
4413 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all management and
4414 * control frames to the host
4415 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames
4416 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
4417 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
4418 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
4419 * (in station mode when associated)
4420 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
4421 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
4422 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
4423 */
4424 #define IWX_MAC_FILTER_IN_PROMISC (1 << 0)
4425 #define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)
4426 #define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2)
4427 #define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3)
4428 #define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)
4429 #define IWX_MAC_FILTER_IN_BEACON (1 << 6)
4430 #define IWX_MAC_FILTER_OUT_BCAST (1 << 8)
4431 #define IWX_MAC_FILTER_IN_CRC32 (1 << 11)
4432 #define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)
4433
4434 /**
4435 * QoS flags
4436 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ?
4437 * @IWX_MAC_QOS_FLG_TGN: HT is enabled
4438 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ?
4439 *
4440 */
4441 #define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)
4442 #define IWX_MAC_QOS_FLG_TGN (1 << 1)
4443 #define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4)
4444
4445 /**
4446 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD
4447 * @cw_min: Contention window, start value in numbers of slots.
4448 * Should be a power-of-2, minus 1. Device's default is 0x0f.
4449 * @cw_max: Contention window, max value in numbers of slots.
4450 * Should be a power-of-2, minus 1. Device's default is 0x3f.
4451 * @aifsn: Number of slots in Arbitration Interframe Space (before
4452 * performing random backoff timing prior to Tx). Device default 1.
4453 * @fifos_mask: FIFOs used by this MAC for this AC
4454 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
4455 *
4456 * One instance of this config struct for each of 4 EDCA access categories
4457 * in struct iwx_qosparam_cmd.
4458 *
4459 * Device will automatically increase contention window by (2*CW) + 1 for each
4460 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
4461 * value, to cap the CW value.
4462 */
4463 struct iwx_ac_qos {
4464 uint16_t cw_min;
4465 uint16_t cw_max;
4466 uint8_t aifsn;
4467 uint8_t fifos_mask;
4468 uint16_t edca_txop;
4469 } __packed; /* IWX_AC_QOS_API_S_VER_2 */
4470
4471 /**
4472 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts
4473 * ( IWX_MAC_CONTEXT_CMD = 0x28 )
4474 * @id_and_color: ID and color of the MAC
4475 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
4476 * @mac_type: one of IWX_FW_MAC_TYPE_*
4477 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_*
4478 * @node_addr: MAC address
4479 * @bssid_addr: BSSID
4480 * @cck_rates: basic rates available for CCK
4481 * @ofdm_rates: basic rates available for OFDM
4482 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_*
4483 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
4484 * @short_slot: 0x10 for enabling short slots, 0 otherwise
4485 * @filter_flags: combination of IWX_MAC_FILTER_*
4486 * @qos_flags: from IWX_MAC_QOS_FLG_*
4487 * @ac: one iwx_mac_qos configuration for each AC
4488 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type
4489 */
4490 struct iwx_mac_ctx_cmd {
4491 /* COMMON_INDEX_HDR_API_S_VER_1 */
4492 uint32_t id_and_color;
4493 uint32_t action;
4494 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
4495 uint32_t mac_type;
4496 uint32_t tsf_id;
4497 uint8_t node_addr[6];
4498 uint16_t reserved_for_node_addr;
4499 uint8_t bssid_addr[6];
4500 uint16_t reserved_for_bssid_addr;
4501 uint32_t cck_rates;
4502 uint32_t ofdm_rates;
4503 uint32_t protection_flags;
4504 uint32_t cck_short_preamble;
4505 uint32_t short_slot;
4506 uint32_t filter_flags;
4507 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */
4508 uint32_t qos_flags;
4509 struct iwx_ac_qos ac[IWX_AC_NUM+1];
4510 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */
4511 union {
4512 struct iwx_mac_data_ap ap;
4513 struct iwx_mac_data_go go;
4514 struct iwx_mac_data_sta sta;
4515 struct iwx_mac_data_p2p_sta p2p_sta;
4516 struct iwx_mac_data_p2p_dev p2p_dev;
4517 struct iwx_mac_data_pibss pibss;
4518 struct iwx_mac_data_ibss ibss;
4519 };
4520 } __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */
4521
4522 /**
4523 * struct iwx_mac_client_data - configuration data for client MAC context
4524 *
4525 * @is_assoc: 1 for associated state, 0 otherwise
4526 * @esr_transition_timeout: the timeout required by the AP for the eSR transition.
4527 * Available only from version 2 of the command.
4528 * This values comes from the EMLSR transition delay in the EML Capabilities
4529 * subfield.
4530 * @medium_sync_delay: the value as it appeasr in P802.11be_D2.2 Figure 9-1002j.
4531 * @assoc_id: unique ID assigned by the AP during association
4532 * @reserved1: alignment
4533 * @data_policy: see &enum iwx_mac_data_policy
4534 * @reserved2: alignment
4535 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
4536 * 0 indicates that there is no CT window.
4537 */
4538 struct iwx_mac_client_data {
4539 uint8_t is_assoc;
4540 uint8_t esr_transition_timeout;
4541 uint16_t medium_sync_delay;
4542
4543 uint16_t assoc_id;
4544 uint16_t reserved1;
4545 uint16_t data_policy;
4546 uint16_t reserved2;
4547 uint32_t ctwin;
4548 } __packed; /* MAC_CONTEXT_CONFIG_CLIENT_DATA_API_S_VER_2 */
4549
4550 /**
4551 * struct iwx_mac_p2p_dev_data - configuration data for P2P device MAC context
4552 *
4553 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
4554 * other channels as well. This should be to true only in case that the
4555 * device is discoverable and there is an active GO. Note that setting this
4556 * field when not needed, will increase the number of interrupts and have
4557 * effect on the platform power, as this setting opens the Rx filters on
4558 * all macs.
4559 */
4560 struct iwx_mac_p2p_dev_data {
4561 uint32_t is_disc_extended;
4562 } __packed; /* MAC_CONTEXT_CONFIG_P2P_DEV_DATA_API_S_VER_1 */
4563
4564 /**
4565 * enum iwx_mac_config_filter_flags - MAC context configuration filter flags
4566 *
4567 * @IWX_MAC_CFG_FILTER_PROMISC: accept all data frames
4568 * @IWX_MAC_CFG_FILTER_ACCEPT_CONTROL_AND_MGMT: pass all management and
4569 * control frames to the host
4570 * @IWX_MAC_CFG_FILTER_ACCEPT_GRP: accept multicast frames
4571 * @IWX_MAC_CFG_FILTER_ACCEPT_BEACON: accept beacon frames
4572 * @IWX_MAC_CFG_FILTER_ACCEPT_BCAST_PROBE_RESP: accept broadcast probe response
4573 * @IWX_MAC_CFG_FILTER_ACCEPT_PROBE_REQ: accept probe requests
4574 */
4575 enum iwx_mac_config_filter_flags {
4576 IWX_MAC_CFG_FILTER_PROMISC = (1 << 0),
4577 IWX_MAC_CFG_FILTER_ACCEPT_CONTROL_AND_MGMT = (1 << 1),
4578 IWX_MAC_CFG_FILTER_ACCEPT_GRP = (1 << 2),
4579 IWX_MAC_CFG_FILTER_ACCEPT_BEACON = (1 << 3),
4580 IWX_MAC_CFG_FILTER_ACCEPT_BCAST_PROBE_RESP = (1 << 4),
4581 IWX_MAC_CFG_FILTER_ACCEPT_PROBE_REQ = (1 << 5),
4582 }; /* MAC_FILTER_FLAGS_MASK_E_VER_1 */
4583
4584 /**
4585 * struct iwx_mac_config_cmd - command structure to configure MAC contexts in
4586 * MLD API
4587 * ( MAC_CONTEXT_CONFIG_CMD = 0x8 )
4588 *
4589 * @id_and_color: ID and color of the MAC
4590 * @action: action to perform, see &enum iwx_ctxt_action
4591 * @mac_type: one of &enum iwx_mac_types
4592 * @local_mld_addr: mld address
4593 * @reserved_for_local_mld_addr: reserved
4594 * @filter_flags: combination of &enum iwx_mac_config_filter_flags
4595 * @he_support: does this MAC support HE
4596 * @he_ap_support: HE AP enabled, "pseudo HE", no trigger frame handling
4597 * @eht_support: does this MAC support EHT. Requires he_support
4598 * @nic_not_ack_enabled: mark that the NIC doesn't support receiving
4599 * ACK-enabled AGG, (i.e. both BACK and non-BACK frames in single AGG).
4600 * If the NIC is not ACK_ENABLED it may use the EOF-bit in first non-0
4601 * len delim to determine if AGG or single.
4602 */
4603 struct iwx_mac_config_cmd {
4604 /* COMMON_INDEX_HDR_API_S_VER_1 */
4605 uint32_t id_and_color;
4606 uint32_t action;
4607 /* MAC_CONTEXT_TYPE_API_E */
4608 uint32_t mac_type;
4609 uint8_t local_mld_addr[6];
4610 uint16_t reserved_for_local_mld_addr;
4611 uint32_t filter_flags;
4612 uint16_t he_support;
4613 uint16_t he_ap_support;
4614 uint32_t eht_support;
4615 uint32_t nic_not_ack_enabled;
4616 /* MAC_CONTEXT_CONFIG_SPECIFIC_DATA_API_U_VER_2 */
4617 union {
4618 struct iwx_mac_client_data client;
4619 struct iwx_mac_p2p_dev_data p2p_dev;
4620 };
4621 } __packed; /* MAC_CONTEXT_CONFIG_CMD_API_S_VER_2 */
4622
4623 /**
4624 * struct iwx_he_backoff_conf - used for backoff configuration
4625 * Per each trigger-based AC, (set by MU EDCA Parameter set info-element)
4626 * used for backoff configuration of TXF5..TXF8 trigger based.
4627 * The MU-TIMER is reloaded w/ MU_TIME each time a frame from the AC is sent via
4628 * trigger-based TX.
4629 * @cwmin: CW min
4630 * @cwmax: CW max
4631 * @aifsn: AIFSN
4632 * AIFSN=0, means that no backoff from the specified TRIG-BASED AC is
4633 * allowed till the MU-TIMER is 0
4634 * @mu_time: MU time in 8TU units
4635 */
4636 struct iwx_he_backoff_conf {
4637 uint16_t cwmin;
4638 uint16_t cwmax;
4639 uint16_t aifsn;
4640 uint16_t mu_time;
4641 } __packed; /* AC_QOS_DOT11AX_API_S */
4642
4643 /**
4644 * enum iwx_link_ctx_modify_flags - indicate to the fw what fields are being
4645 * modified in &iwx_link_ctx_cfg_cmd
4646 *
4647 * @IWX_LINK_CONTEXT_MODIFY_ACTIVE: covers iwx_link_ctx_cfg_cmd::active
4648 * @IWX_LINK_CONTEXT_MODIFY_RATES_INFO: covers iwx_link_ctx_cfg_cmd::cck_rates,
4649 * iwx_link_ctx_cfg_cmd::ofdm_rates,
4650 * iwx_link_ctx_cfg_cmd::cck_short_preamble,
4651 * iwx_link_ctx_cfg_cmd::short_slot
4652 * @IWX_LINK_CONTEXT_MODIFY_PROTECT_FLAGS: covers
4653 * iwx_link_ctx_cfg_cmd::protection_flags
4654 * @IWX_LINK_CONTEXT_MODIFY_QOS_PARAMS: covers iwx_link_ctx_cfg_cmd::qos_flags,
4655 * iwx_link_ctx_cfg_cmd::ac,
4656 * @IWX_LINK_CONTEXT_MODIFY_BEACON_TIMING: covers iwx_link_ctx_cfg_cmd::bi,
4657 * iwx_link_ctx_cfg_cmd::dtim_interval,
4658 * iwx_link_ctx_cfg_cmd::dtim_time,
4659 * iwx_link_ctx_cfg_cmd::dtim_tsf,
4660 * iwx_link_ctx_cfg_cmd::assoc_beacon_arrive_time.
4661 * This flag can be set only once after assoc.
4662 * @IWX_LINK_CONTEXT_MODIFY_HE_PARAMS: covers
4663 * iwx_link_ctx_cfg_cmd::htc_trig_based_pkt_ext
4664 * iwx_link_ctx_cfg_cmd::rand_alloc_ecwmin,
4665 * iwx_link_ctx_cfg_cmd::rand_alloc_ecwmax,
4666 * iwx_link_ctx_cfg_cmd::trig_based_txf,
4667 * iwx_link_ctx_cfg_cmd::bss_color,
4668 * iwx_link_ctx_cfg_cmd::ndp_fdbk_buff_th_exp,
4669 * iwx_link_ctx_cfg_cmd::ref_bssid_addr
4670 * iwx_link_ctx_cfg_cmd::bssid_index,
4671 * iwx_link_ctx_cfg_cmd::frame_time_rts_th.
4672 * This flag can be set any time.
4673 * @IWX_LINK_CONTEXT_MODIFY_BSS_COLOR_DISABLE: covers
4674 * iwx_link_ctx_cfg_cmd::bss_color_disable
4675 * @IWX_LINK_CONTEXT_MODIFY_EHT_PARAMS: covers iwx_link_ctx_cfg_cmd::puncture_mask.
4676 * This flag can be set only if the MAC that this link relates to has
4677 * eht_support set to true.
4678 * @IWX_LINK_CONTEXT_MODIFY_ALL: set all above flags
4679 */
4680 enum iwx_link_ctx_modify_flags {
4681 IWX_LINK_CONTEXT_MODIFY_ACTIVE = (1 << 0),
4682 IWX_LINK_CONTEXT_MODIFY_RATES_INFO = (1 << 1),
4683 IWX_LINK_CONTEXT_MODIFY_PROTECT_FLAGS = (1 << 2),
4684 IWX_LINK_CONTEXT_MODIFY_QOS_PARAMS = (1 << 3),
4685 IWX_LINK_CONTEXT_MODIFY_BEACON_TIMING = (1 << 4),
4686 IWX_LINK_CONTEXT_MODIFY_HE_PARAMS = (1 << 5),
4687 IWX_LINK_CONTEXT_MODIFY_BSS_COLOR_DISABLE = (1 << 6),
4688 IWX_LINK_CONTEXT_MODIFY_EHT_PARAMS = (1 << 7),
4689 IWX_LINK_CONTEXT_MODIFY_ALL = 0xff,
4690 }; /* LINK_CONTEXT_MODIFY_MASK_E_VER_1 */
4691
4692 /**
4693 * enum iwx_link_ctx_protection_flags - link protection flags
4694 * @IWX_LINK_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
4695 * this will require CCK RTS/CTS2self.
4696 * RTS/CTS will protect full burst time.
4697 * @IWX_LINK_PROT_FLG_HT_PROT: enable HT protection
4698 * @IWX_LINK_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
4699 * @IWX_LINK_PROT_FLG_SELF_CTS_EN: allow CTS2self
4700 */
4701 enum iwx_link_ctx_protection_flags {
4702 IWX_LINK_PROT_FLG_TGG_PROTECT = (1 << 0),
4703 IWX_LINK_PROT_FLG_HT_PROT = (1 << 1),
4704 IWX_LINK_PROT_FLG_FAT_PROT = (1 << 2),
4705 IWX_LINK_PROT_FLG_SELF_CTS_EN = (1 << 3),
4706 }; /* LINK_PROTECT_FLAGS_E_VER_1 */
4707
4708 /**
4709 * struct iwx_link_config_cmd - command structure to configure the LINK context
4710 * in MLD API
4711 * ( LINK_CONFIG_CMD =0x9 )
4712 *
4713 * @action: action to perform, see &enum iwx_ctxt_action
4714 * @link_id: the id of the link that this cmd configures
4715 * @mac_id: interface ID. Relevant only if action is FW_CTXT_ACTION_ADD
4716 * @phy_id: PHY index. Can be changed only if the link was inactive
4717 * (and stays inactive). If the link is active (or becomes active),
4718 * this field is ignored.
4719 * @local_link_addr: the links MAC address. Can be changed only if the link was
4720 * inactive (and stays inactive). If the link is active
4721 * (or becomes active), this field is ignored.
4722 * @reserved_for_local_link_addr: reserved
4723 * @modify_mask: from &enum iwx_link_ctx_modify_flags, selects what to change.
4724 * Relevant only if action is FW_CTXT_ACTION_MODIFY
4725 * @active: indicates whether the link is active or not
4726 * @listen_lmac: indicates whether the link should be allocated on the Listen
4727 * Lmac or on the Main Lmac. Cannot be changed on an active Link.
4728 * Relevant only for eSR.
4729 * @cck_rates: basic rates available for CCK
4730 * @ofdm_rates: basic rates available for OFDM
4731 * @cck_short_preamble: 1 for enabling short preamble, 0 otherwise
4732 * @short_slot: 1 for enabling short slots, 0 otherwise
4733 * @protection_flags: combination of &enum iwx_link_ctx_protection_flags
4734 * @qos_flags: from &enum iwx_mac_qos_flags
4735 * @ac: one iwx_mac_qos configuration for each AC
4736 * @htc_trig_based_pkt_ext: default PE in 4us units
4737 * @rand_alloc_ecwmin: random CWmin = 2**ECWmin-1
4738 * @rand_alloc_ecwmax: random CWmax = 2**ECWmax-1
4739 * @ndp_fdbk_buff_th_exp: set exponent for the NDP feedback buffered threshold
4740 * @trig_based_txf: MU EDCA Parameter set for the trigger based traffic queues
4741 * @bi: beacon interval in TU, applicable only when associated
4742 * @dtim_interval: DTIM interval in TU.
4743 * Relevant only for GO, otherwise this is offloaded.
4744 * @puncture_mask: puncture mask for EHT
4745 * @frame_time_rts_th: HE duration RTS threshold, in units of 32us
4746 * @flags: a combination from &enum iwx_link_ctx_flags
4747 * @flags_mask: what of %flags have changed. Also &enum iwx_link_ctx_flags
4748 * Below fields are for multi-bssid:
4749 * @ref_bssid_addr: reference BSSID used by the AP
4750 * @reserved_for_ref_bssid_addr: reserved
4751 * @bssid_index: index of the associated VAP
4752 * @bss_color: 11ax AP ID that is used in the HE SIG-A to mark inter BSS frame
4753 * @spec_link_id: link_id as the AP knows it
4754 * @reserved: alignment
4755 * @ibss_bssid_addr: bssid for ibss
4756 * @reserved_for_ibss_bssid_addr: reserved
4757 * @reserved1: reserved for future use
4758 */
4759 struct iwx_link_config_cmd {
4760 uint32_t action;
4761 uint32_t link_id;
4762 uint32_t mac_id;
4763 uint32_t phy_id;
4764 uint8_t local_link_addr[6];
4765 uint16_t reserved_for_local_link_addr;
4766 uint32_t modify_mask;
4767 uint32_t active;
4768 uint32_t listen_lmac;
4769 uint32_t cck_rates;
4770 uint32_t ofdm_rates;
4771 uint32_t cck_short_preamble;
4772 uint32_t short_slot;
4773 uint32_t protection_flags;
4774 /* MAC_QOS_PARAM_API_S_VER_1 */
4775 uint32_t qos_flags;
4776 struct iwx_ac_qos ac[IWX_AC_NUM + 1];
4777 uint8_t htc_trig_based_pkt_ext;
4778 uint8_t rand_alloc_ecwmin;
4779 uint8_t rand_alloc_ecwmax;
4780 uint8_t ndp_fdbk_buff_th_exp;
4781 struct iwx_he_backoff_conf trig_based_txf[IWX_AC_NUM];
4782 uint32_t bi;
4783 uint32_t dtim_interval;
4784 uint16_t puncture_mask;
4785 uint16_t frame_time_rts_th;
4786 uint32_t flags;
4787 uint32_t flags_mask;
4788 /* The below fields are for multi-bssid */
4789 uint8_t ref_bssid_addr[6];
4790 uint16_t reserved_for_ref_bssid_addr;
4791 uint8_t bssid_index;
4792 uint8_t bss_color;
4793 uint8_t spec_link_id;
4794 uint8_t reserved;
4795 uint8_t ibss_bssid_addr[6];
4796 uint16_t reserved_for_ibss_bssid_addr;
4797 uint32_t reserved1[8];
4798 } __packed; /* LINK_CONTEXT_CONFIG_CMD_API_S_VER_1 */
4799
4800 #define MAX_HE_SUPP_NSS 2
4801 #define MAX_CHANNEL_BW_INDX_API_D_VER_2 4
4802 #define MAX_CHANNEL_BW_INDX_API_D_VER_3 5
4803
4804 /**
4805 * struct iwx_he_pkt_ext_v1 - QAM thresholds
4806 * The required PPE is set via HE Capabilities IE, per Nss x BW x MCS
4807 * The IE is organized in the following way:
4808 * Support for Nss x BW (or RU) matrix:
4809 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
4810 * Each entry contains 2 QAM thresholds for 8us and 16us:
4811 * 0=BPSK, 1=QPSK, 2=16QAM, 3=64QAM, 4=256QAM, 5=1024QAM, 6=RES, 7=NONE
4812 * i.e. QAM_th1 < QAM_th2 such if TX uses QAM_tx:
4813 * QAM_tx < QAM_th1 --> PPE=0us
4814 * QAM_th1 <= QAM_tx < QAM_th2 --> PPE=8us
4815 * QAM_th2 <= QAM_tx --> PPE=16us
4816 * @pkt_ext_qam_th: QAM thresholds
4817 * For each Nss/Bw define 2 QAM thrsholds (0..5)
4818 * For rates below the low_th, no need for PPE
4819 * For rates between low_th and high_th, need 8us PPE
4820 * For rates equal or higher then the high_th, need 16us PPE
4821 * Nss (0-siso, 1-mimo2) x BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz) x
4822 * (0-low_th, 1-high_th)
4823 */
4824 struct iwx_he_pkt_ext_v1 {
4825 uint8_t pkt_ext_qam_th[MAX_HE_SUPP_NSS][MAX_CHANNEL_BW_INDX_API_D_VER_2][2];
4826 } __packed; /* PKT_EXT_DOT11AX_API_S_VER_1 */
4827
4828 /**
4829 * struct iwx_he_pkt_ext_v2 - QAM thresholds
4830 * The required PPE is set via HE Capabilities IE, per Nss x BW x MCS
4831 * The IE is organized in the following way:
4832 * Support for Nss x BW (or RU) matrix:
4833 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
4834 * Each entry contains 2 QAM thresholds for 8us and 16us:
4835 * 0=BPSK, 1=QPSK, 2=16QAM, 3=64QAM, 4=256QAM, 5=1024QAM, 6=RES, 7=NONE
4836 * i.e. QAM_th1 < QAM_th2 such if TX uses QAM_tx:
4837 * QAM_tx < QAM_th1 --> PPE=0us
4838 * QAM_th1 <= QAM_tx < QAM_th2 --> PPE=8us
4839 * QAM_th2 <= QAM_tx --> PPE=16us
4840 * @pkt_ext_qam_th: QAM thresholds
4841 * For each Nss/Bw define 2 QAM thrsholds (0..5)
4842 * For rates below the low_th, no need for PPE
4843 * For rates between low_th and high_th, need 8us PPE
4844 * For rates equal or higher then the high_th, need 16us PPE
4845 * Nss (0-siso, 1-mimo2) x
4846 * BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz, 4-320MHz) x
4847 * (0-low_th, 1-high_th)
4848 */
4849 struct iwx_he_pkt_ext_v2 {
4850 uint8_t pkt_ext_qam_th[MAX_HE_SUPP_NSS][MAX_CHANNEL_BW_INDX_API_D_VER_3][2];
4851 } __packed; /* PKT_EXT_DOT11AX_API_S_VER_2 */
4852
4853 /**
4854 * struct iwx_mvm_sta_cfg_cmd - cmd structure to add a peer sta to the uCode's
4855 * station table
4856 * ( STA_CONFIG_CMD = 0xA )
4857 *
4858 * @sta_id: index of station in uCode's station table
4859 * @link_id: the id of the link that is used to communicate with this sta
4860 * @peer_mld_address: the peers mld address
4861 * @reserved_for_peer_mld_address: reserved
4862 * @peer_link_address: the address of the link that is used to communicate
4863 * with this sta
4864 * @reserved_for_peer_link_address: reserved
4865 * @station_type: type of this station. See &enum iwx_fw_sta_type
4866 * @assoc_id: for GO only
4867 * @beamform_flags: beam forming controls
4868 * @mfp: indicates whether the STA uses management frame protection or not.
4869 * @mimo: indicates whether the sta uses mimo or not
4870 * @mimo_protection: indicates whether the sta uses mimo protection or not
4871 * @ack_enabled: indicates that the AP supports receiving ACK-
4872 * enabled AGG, i.e. both BACK and non-BACK frames in a single AGG
4873 * @trig_rnd_alloc: indicates that trigger based random allocation
4874 * is enabled according to UORA element existence
4875 * @tx_ampdu_spacing: minimum A-MPDU spacing:
4876 * 4 - 2us density, 5 - 4us density, 6 - 8us density, 7 - 16us density
4877 * @tx_ampdu_max_size: maximum A-MPDU length: 0 - 8K, 1 - 16K, 2 - 32K,
4878 * 3 - 64K, 4 - 128K, 5 - 256K, 6 - 512K, 7 - 1024K.
4879 * @sp_length: the size of the SP in actual number of frames
4880 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver
4881 * enabled ACs.
4882 * @pkt_ext: optional, exists according to PPE-present bit in the HE/EHT-PHY
4883 * capa
4884 * @htc_flags: which features are supported in HTC
4885 */
4886 struct iwx_mvm_sta_cfg_cmd {
4887 uint32_t sta_id;
4888 uint32_t link_id;
4889 uint8_t peer_mld_address[6];
4890 uint16_t reserved_for_peer_mld_address;
4891 uint8_t peer_link_address[6];
4892 uint16_t reserved_for_peer_link_address;
4893 uint32_t station_type;
4894 uint32_t assoc_id;
4895 uint32_t beamform_flags;
4896 uint32_t mfp;
4897 uint32_t mimo;
4898 uint32_t mimo_protection;
4899 uint32_t ack_enabled;
4900 uint32_t trig_rnd_alloc;
4901 uint32_t tx_ampdu_spacing;
4902 uint32_t tx_ampdu_max_size;
4903 uint32_t sp_length;
4904 uint32_t uapsd_acs;
4905 struct iwx_he_pkt_ext_v2 pkt_ext;
4906 uint32_t htc_flags;
4907 } __packed; /* STA_CMD_API_S_VER_1 */
4908
4909 /**
4910 * struct iwx_mvm_remove_sta_cmd - a cmd structure to remove a sta added by
4911 * STA_CONFIG_CMD or AUX_STA_CONFIG_CMD
4912 * ( STA_REMOVE_CMD = 0xC )
4913 *
4914 * @sta_id: index of station to remove
4915 */
4916 struct iwx_mvm_remove_sta_cmd {
4917 uint32_t sta_id;
4918 } __packed; /* REMOVE_STA_API_S_VER_1 */
4919
iwx_reciprocal(uint32_t v)4920 static inline uint32_t iwx_reciprocal(uint32_t v)
4921 {
4922 if (!v)
4923 return 0;
4924 return 0xFFFFFFFF / v;
4925 }
4926
4927 /* Power Management Commands, Responses, Notifications */
4928
4929 /**
4930 * masks for LTR config command flags
4931 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status
4932 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow
4933 * memory access
4934 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR
4935 * reg change
4936 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from
4937 * D0 to D3
4938 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register
4939 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register
4940 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD
4941 */
4942 #define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001
4943 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002
4944 #define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004
4945 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008
4946 #define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010
4947 #define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020
4948 #define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040
4949
4950 #define IWX_LTR_VALID_STATES_NUM 4
4951
4952 /**
4953 * struct iwx_ltr_config_cmd - configures the LTR
4954 * @flags: See %enum iwx_ltr_config_flags
4955 * @static_long:
4956 * @static_short:
4957 * @ltr_cfg_values:
4958 * @ltr_short_idle_timeout:
4959 */
4960 struct iwx_ltr_config_cmd {
4961 uint32_t flags;
4962 uint32_t static_long;
4963 uint32_t static_short;
4964 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM];
4965 uint32_t ltr_short_idle_timeout;
4966 } __packed; /* LTR_CAPABLE_API_S_VER_2 */
4967
4968 /* Radio LP RX Energy Threshold measured in dBm */
4969 #define IWX_POWER_LPRX_RSSI_THRESHOLD 75
4970 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94
4971 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30
4972
4973 /**
4974 * Masks for iwx_mac_power_cmd command flags
4975 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
4976 * receiver and transmitter. '0' - does not allow.
4977 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
4978 * '1' Driver enables PM (use rest of parameters)
4979 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
4980 * '1' PM could sleep over DTIM till listen Interval.
4981 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
4982 * access categories are both delivery and trigger enabled.
4983 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
4984 * PBW Snoozing enabled
4985 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
4986 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
4987 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
4988 * detection enablement
4989 */
4990 #define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4991 #define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)
4992 #define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)
4993 #define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)
4994 #define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8)
4995 #define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)
4996 #define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)
4997 #define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)
4998
4999 #define IWX_POWER_VEC_SIZE 5
5000
5001 /**
5002 * Masks for device power command flags
5003 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK:
5004 * '1' Allow to save power by turning off receiver and transmitter.
5005 * '0' Do not allow. This flag should be always set to '1' unless
5006 * one needs to disable actual power down for debug purposes.
5007 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK:
5008 * '1' CAM (Continuous Active Mode) is set, power management is disabled.
5009 * '0' Power management is enabled, one of the power schemes is applied.
5010 */
5011 #define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
5012 #define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)
5013
5014 /**
5015 * struct iwx_device_power_cmd - device wide power command.
5016 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
5017 *
5018 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_*
5019 */
5020 struct iwx_device_power_cmd {
5021 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
5022 uint16_t flags;
5023 uint16_t reserved;
5024 } __packed;
5025
5026 /**
5027 * struct iwx_mac_power_cmd - New power command containing uAPSD support
5028 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
5029 * @id_and_color: MAC context identifier
5030 * @flags: Power table command flags from POWER_FLAGS_*
5031 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
5032 * Minimum allowed:- 3 * DTIM. Keep alive period must be
5033 * set regardless of power scheme or current power state.
5034 * FW use this value also when PM is disabled.
5035 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
5036 * PSM transition - legacy PM
5037 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
5038 * PSM transition - legacy PM
5039 * @sleep_interval: not in use
5040 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
5041 * is set. For example, if it is required to skip over
5042 * one DTIM, this value need to be set to 2 (DTIM periods).
5043 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
5044 * PSM transition - uAPSD
5045 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
5046 * PSM transition - uAPSD
5047 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
5048 * Default: 80dbm
5049 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
5050 * @snooze_interval: Maximum time between attempts to retrieve buffered data
5051 * from the AP [msec]
5052 * @snooze_window: A window of time in which PBW snoozing insures that all
5053 * packets received. It is also the minimum time from last
5054 * received unicast RX packet, before client stops snoozing
5055 * for data. [msec]
5056 * @snooze_step: TBD
5057 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
5058 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
5059 * each corresponding AC.
5060 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
5061 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
5062 * values.
5063 * @heavy_tx_thld_packets: TX threshold measured in number of packets
5064 * @heavy_rx_thld_packets: RX threshold measured in number of packets
5065 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
5066 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
5067 * @limited_ps_threshold:
5068 */
5069 struct iwx_mac_power_cmd {
5070 /* CONTEXT_DESC_API_T_VER_1 */
5071 uint32_t id_and_color;
5072
5073 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
5074 uint16_t flags;
5075 uint16_t keep_alive_seconds;
5076 uint32_t rx_data_timeout;
5077 uint32_t tx_data_timeout;
5078 uint32_t rx_data_timeout_uapsd;
5079 uint32_t tx_data_timeout_uapsd;
5080 uint8_t lprx_rssi_threshold;
5081 uint8_t skip_dtim_periods;
5082 uint16_t snooze_interval;
5083 uint16_t snooze_window;
5084 uint8_t snooze_step;
5085 uint8_t qndp_tid;
5086 uint8_t uapsd_ac_flags;
5087 uint8_t uapsd_max_sp;
5088 uint8_t heavy_tx_thld_packets;
5089 uint8_t heavy_rx_thld_packets;
5090 uint8_t heavy_tx_thld_percentage;
5091 uint8_t heavy_rx_thld_percentage;
5092 uint8_t limited_ps_threshold;
5093 uint8_t reserved;
5094 } __packed;
5095
5096 #define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)
5097 #define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)
5098
5099 /*
5100 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when
5101 * associated AP is identified as improperly implementing uAPSD protocol.
5102 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
5103 * @sta_id: index of station in uCode's station table - associated AP ID in
5104 * this context.
5105 */
5106 struct iwx_uapsd_misbehaving_ap_notif {
5107 uint32_t sta_id;
5108 uint8_t mac_id;
5109 uint8_t reserved[3];
5110 } __packed;
5111
5112 /**
5113 * struct iwx_beacon_filter_cmd
5114 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
5115 * @id_and_color: MAC context identifier
5116 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
5117 * to driver if delta in Energy values calculated for this and last
5118 * passed beacon is greater than this threshold. Zero value means that
5119 * the Energy change is ignored for beacon filtering, and beacon will
5120 * not be forced to be sent to driver regardless of this delta. Typical
5121 * energy delta 5dB.
5122 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
5123 * Send beacon to driver if delta in Energy values calculated for this
5124 * and last passed beacon is greater than this threshold. Zero value
5125 * means that the Energy change is ignored for beacon filtering while in
5126 * Roaming state, typical energy delta 1dB.
5127 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
5128 * calculated for current beacon is less than the threshold, use
5129 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
5130 * Threshold. Typical energy threshold is -72dBm.
5131 * @bf_temp_threshold: This threshold determines the type of temperature
5132 * filtering (Slow or Fast) that is selected (Units are in Celsius):
5133 * If the current temperature is above this threshold - Fast filter
5134 * will be used, If the current temperature is below this threshold -
5135 * Slow filter will be used.
5136 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
5137 * calculated for this and the last passed beacon is greater than this
5138 * threshold. Zero value means that the temperature change is ignored for
5139 * beacon filtering; beacons will not be forced to be sent to driver
5140 * regardless of whether its temperature has been changed.
5141 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
5142 * calculated for this and the last passed beacon is greater than this
5143 * threshold. Zero value means that the temperature change is ignored for
5144 * beacon filtering; beacons will not be forced to be sent to driver
5145 * regardless of whether its temperature has been changed.
5146 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
5147 * @bf_escape_timer: Send beacons to driver if no beacons were passed
5148 * for a specific period of time. Units: Beacons.
5149 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
5150 * for a longer period of time then this escape-timeout. Units: Beacons.
5151 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
5152 * @bf_threshold_absolute_low: See below.
5153 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated
5154 * for this beacon crossed this absolute threshold. For the 'Increase'
5155 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease'
5156 * direction the bf_energy_absolute_high[i] is used. Zero value means
5157 * that this specific threshold is ignored for beacon filtering, and
5158 * beacon will not be forced to be sent to driver due to this setting.
5159 */
5160 struct iwx_beacon_filter_cmd {
5161 uint32_t bf_energy_delta;
5162 uint32_t bf_roaming_energy_delta;
5163 uint32_t bf_roaming_state;
5164 uint32_t bf_temp_threshold;
5165 uint32_t bf_temp_fast_filter;
5166 uint32_t bf_temp_slow_filter;
5167 uint32_t bf_enable_beacon_filter;
5168 uint32_t bf_debug_flag;
5169 uint32_t bf_escape_timer;
5170 uint32_t ba_escape_timer;
5171 uint32_t ba_enable_beacon_abort;
5172 uint32_t bf_threshold_absolute_low[2];
5173 uint32_t bf_threshold_absolute_high[2];
5174 } __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */
5175
5176 /* Beacon filtering and beacon abort */
5177 #define IWX_BF_ENERGY_DELTA_DEFAULT 5
5178 #define IWX_BF_ENERGY_DELTA_MAX 255
5179 #define IWX_BF_ENERGY_DELTA_MIN 0
5180
5181 #define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
5182 #define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255
5183 #define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0
5184
5185 #define IWX_BF_ROAMING_STATE_DEFAULT 72
5186 #define IWX_BF_ROAMING_STATE_MAX 255
5187 #define IWX_BF_ROAMING_STATE_MIN 0
5188
5189 #define IWX_BF_TEMP_THRESHOLD_DEFAULT 112
5190 #define IWX_BF_TEMP_THRESHOLD_MAX 255
5191 #define IWX_BF_TEMP_THRESHOLD_MIN 0
5192
5193 #define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1
5194 #define IWX_BF_TEMP_FAST_FILTER_MAX 255
5195 #define IWX_BF_TEMP_FAST_FILTER_MIN 0
5196
5197 #define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5
5198 #define IWX_BF_TEMP_SLOW_FILTER_MAX 255
5199 #define IWX_BF_TEMP_SLOW_FILTER_MIN 0
5200
5201 #define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1
5202
5203 #define IWX_BF_DEBUG_FLAG_DEFAULT 0
5204
5205 #define IWX_BF_ESCAPE_TIMER_DEFAULT 50
5206 #define IWX_BF_ESCAPE_TIMER_MAX 1024
5207 #define IWX_BF_ESCAPE_TIMER_MIN 0
5208
5209 #define IWX_BA_ESCAPE_TIMER_DEFAULT 6
5210 #define IWX_BA_ESCAPE_TIMER_D3 9
5211 #define IWX_BA_ESCAPE_TIMER_MAX 1024
5212 #define IWX_BA_ESCAPE_TIMER_MIN 0
5213
5214 #define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1
5215
5216 #define IWX_BF_CMD_CONFIG_DEFAULTS \
5217 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \
5218 .bf_roaming_energy_delta = \
5219 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
5220 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \
5221 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \
5222 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \
5223 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \
5224 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \
5225 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \
5226 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT)
5227
5228 /* uCode API values for HT/VHT bit rates */
5229 #define IWX_RATE_HT_SISO_MCS_0_PLCP 0
5230 #define IWX_RATE_HT_SISO_MCS_1_PLCP 1
5231 #define IWX_RATE_HT_SISO_MCS_2_PLCP 2
5232 #define IWX_RATE_HT_SISO_MCS_3_PLCP 3
5233 #define IWX_RATE_HT_SISO_MCS_4_PLCP 4
5234 #define IWX_RATE_HT_SISO_MCS_5_PLCP 5
5235 #define IWX_RATE_HT_SISO_MCS_6_PLCP 6
5236 #define IWX_RATE_HT_SISO_MCS_7_PLCP 7
5237 #define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8
5238 #define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9
5239 #define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA
5240 #define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB
5241 #define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC
5242 #define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD
5243 #define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE
5244 #define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF
5245 #define IWX_RATE_VHT_SISO_MCS_0_PLCP 0
5246 #define IWX_RATE_VHT_SISO_MCS_1_PLCP 1
5247 #define IWX_RATE_VHT_SISO_MCS_2_PLCP 2
5248 #define IWX_RATE_VHT_SISO_MCS_3_PLCP 3
5249 #define IWX_RATE_VHT_SISO_MCS_4_PLCP 4
5250 #define IWX_RATE_VHT_SISO_MCS_5_PLCP 5
5251 #define IWX_RATE_VHT_SISO_MCS_6_PLCP 6
5252 #define IWX_RATE_VHT_SISO_MCS_7_PLCP 7
5253 #define IWX_RATE_VHT_SISO_MCS_8_PLCP 8
5254 #define IWX_RATE_VHT_SISO_MCS_9_PLCP 9
5255 #define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10
5256 #define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11
5257 #define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12
5258 #define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13
5259 #define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14
5260 #define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15
5261 #define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16
5262 #define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17
5263 #define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18
5264 #define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19
5265 #define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20
5266 #define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
5267 #define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
5268 #define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
5269 #define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
5270 #define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
5271
5272 /*
5273 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX].
5274 */
5275 enum {
5276 IWX_RATE_1M_INDEX = 0,
5277 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX,
5278 IWX_RATE_2M_INDEX,
5279 IWX_RATE_5M_INDEX,
5280 IWX_RATE_11M_INDEX,
5281 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX,
5282 IWX_RATE_6M_INDEX,
5283 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX,
5284 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX,
5285 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX,
5286 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX,
5287 IWX_RATE_9M_INDEX,
5288 IWX_RATE_12M_INDEX,
5289 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX,
5290 IWX_RATE_MCS_8_INDEX,
5291 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX,
5292 IWX_RATE_18M_INDEX,
5293 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX,
5294 IWX_RATE_24M_INDEX,
5295 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX,
5296 IWX_RATE_MCS_9_INDEX,
5297 IWX_RATE_36M_INDEX,
5298 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX,
5299 IWX_RATE_MCS_10_INDEX,
5300 IWX_RATE_48M_INDEX,
5301 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX,
5302 IWX_RATE_MCS_11_INDEX,
5303 IWX_RATE_54M_INDEX,
5304 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX,
5305 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX,
5306 IWX_RATE_MCS_7_INDEX,
5307 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX,
5308 IWX_RATE_MCS_12_INDEX,
5309 IWX_RATE_MCS_13_INDEX,
5310 IWX_RATE_MCS_14_INDEX,
5311 IWX_RATE_MCS_15_INDEX,
5312 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX,
5313 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX,
5314 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1,
5315 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1,
5316 };
5317
5318 #define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX))
5319
5320 /* fw API values for legacy bit rates, both OFDM and CCK */
5321 #define IWX_RATE_6M_PLCP 13
5322 #define IWX_RATE_9M_PLCP 15
5323 #define IWX_RATE_12M_PLCP 5
5324 #define IWX_RATE_18M_PLCP 7
5325 #define IWX_RATE_24M_PLCP 9
5326 #define IWX_RATE_36M_PLCP 11
5327 #define IWX_RATE_48M_PLCP 1
5328 #define IWX_RATE_54M_PLCP 3
5329 #define IWX_RATE_1M_PLCP 10
5330 #define IWX_RATE_2M_PLCP 20
5331 #define IWX_RATE_5M_PLCP 55
5332 #define IWX_RATE_11M_PLCP 110
5333 #define IWX_RATE_INVM_PLCP 0xff
5334
5335 /*
5336 * rate_n_flags bit fields version 1
5337 *
5338 * The 32-bit value has different layouts in the low 8 bites depending on the
5339 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
5340 * for CCK and OFDM).
5341 *
5342 * High-throughput (HT) rate format
5343 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
5344 * Very High-throughput (VHT) rate format
5345 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
5346 * Legacy OFDM rate format for bits 7:0
5347 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
5348 * Legacy CCK rate format for bits 7:0:
5349 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
5350 */
5351
5352 /* Bit 8: (1) HT format, (0) legacy or VHT format */
5353 #define IWX_RATE_MCS_HT_POS 8
5354 #define IWX_RATE_MCS_HT_MSK_V1 (1 << IWX_RATE_MCS_HT_POS)
5355
5356 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
5357 #define IWX_RATE_MCS_CCK_POS_V1 9
5358 #define IWX_RATE_MCS_CCK_MSK_V1 (1 << IWX_RATE_MCS_CCK_POS_V1)
5359
5360 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
5361 #define IWX_RATE_MCS_VHT_POS_V1 26
5362 #define IWX_RATE_MCS_VHT_MSK_V1 (1 << IWX_RATE_MCS_VHT_POS_V1)
5363
5364
5365 /*
5366 * High-throughput (HT) rate format for bits 7:0
5367 *
5368 * 2-0: MCS rate base
5369 * 0) 6 Mbps
5370 * 1) 12 Mbps
5371 * 2) 18 Mbps
5372 * 3) 24 Mbps
5373 * 4) 36 Mbps
5374 * 5) 48 Mbps
5375 * 6) 54 Mbps
5376 * 7) 60 Mbps
5377 * 4-3: 0) Single stream (SISO)
5378 * 1) Dual stream (MIMO)
5379 * 2) Triple stream (MIMO)
5380 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
5381 * (bits 7-6 are zero)
5382 *
5383 * Together the low 5 bits work out to the MCS index because we don't
5384 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
5385 * streams and 16-23 have three streams. We could also support MCS 32
5386 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
5387 */
5388 #define IWX_RATE_HT_MCS_RATE_CODE_MSK_V1 0x7
5389 #define IWX_RATE_HT_MCS_NSS_POS_V1 3
5390 #define IWX_RATE_HT_MCS_NSS_MSK_V1 (3 << IWX_RATE_HT_MCS_NSS_POS_V1)
5391 #define IWX_RATE_HT_MCS_MIMO2_MSK_V1 (1 << IWX_RATE_HT_MCS_NSS_POS_V1)
5392
5393 /* Bit 10: (1) Use Green Field preamble */
5394 #define IWX_RATE_HT_MCS_GF_POS 10
5395 #define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS)
5396
5397 #define IWX_RATE_HT_MCS_INDEX_MSK_V1 0x3f
5398
5399 /*
5400 * Very High-throughput (VHT) rate format for bits 7:0
5401 *
5402 * 3-0: VHT MCS (0-9)
5403 * 5-4: number of streams - 1:
5404 * 0) Single stream (SISO)
5405 * 1) Dual stream (MIMO)
5406 * 2) Triple stream (MIMO)
5407 */
5408
5409 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
5410 #define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf
5411 #define IWX_RATE_VHT_MCS_NSS_POS 4
5412 #define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS)
5413 #define IWX_RATE_VHT_MCS_MIMO2_MSK (1 << IWX_RATE_VHT_MCS_NSS_POS)
5414
5415 /*
5416 * Legacy OFDM rate format for bits 7:0
5417 *
5418 * 3-0: 0xD) 6 Mbps
5419 * 0xF) 9 Mbps
5420 * 0x5) 12 Mbps
5421 * 0x7) 18 Mbps
5422 * 0x9) 24 Mbps
5423 * 0xB) 36 Mbps
5424 * 0x1) 48 Mbps
5425 * 0x3) 54 Mbps
5426 * (bits 7-4 are 0)
5427 *
5428 * Legacy CCK rate format for bits 7:0:
5429 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
5430 *
5431 * 6-0: 10) 1 Mbps
5432 * 20) 2 Mbps
5433 * 55) 5.5 Mbps
5434 * 110) 11 Mbps
5435 * (bit 7 is 0)
5436 */
5437 #define IWX_RATE_LEGACY_RATE_MSK_V1 0xff
5438
5439 /* Bit 10 - OFDM HE */
5440 #define IWX_RATE_MCS_HE_POS_V1 10
5441 #define IWX_RATE_MCS_HE_MSK_V1 (1 << RATE_MCS_HE_POS_V1)
5442
5443 /*
5444 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
5445 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
5446 */
5447 #define IWX_RATE_MCS_CHAN_WIDTH_POS 11
5448 #define IWX_RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5449 #define IWX_RATE_MCS_CHAN_WIDTH_20_V1 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5450 #define IWX_RATE_MCS_CHAN_WIDTH_40_V1 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5451 #define IWX_RATE_MCS_CHAN_WIDTH_80_V1 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5452 #define IWX_RATE_MCS_CHAN_WIDTH_160_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5453
5454 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
5455 #define IWX_RATE_MCS_SGI_POS_V1 13
5456 #define IWX_RATE_MCS_SGI_MSK_V1 (1 << IWX_RATE_MCS_SGI_POS_V1)
5457
5458 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C (unused) */
5459 #define IWX_RATE_MCS_ANT_POS 14
5460 #define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS)
5461 #define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS)
5462 #define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \
5463 IWX_RATE_MCS_ANT_B_MSK)
5464 #define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK
5465 #define IWX_RATE_MCS_ANT_NUM 2
5466
5467 /* Bit 17: (0) SS, (1) SS*2 */
5468 #define IWX_RATE_MCS_STBC_POS 17
5469 #define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS)
5470
5471 /* Bit 18: OFDM-HE dual carrier mode */
5472 #define IWX_RATE_HE_DUAL_CARRIER_MODE 18
5473 #define IWX_RATE_HE_DUAL_CARRIER_MODE_MSK (1 << IWX_RATE_HE_DUAL_CARRIER_MODE)
5474
5475 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
5476 #define IWX_RATE_MCS_BF_POS 19
5477 #define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS)
5478
5479 /*
5480 * Bit 20-21: HE LTF type and guard interval
5481 * HE (ext) SU:
5482 * 0 1xLTF+0.8us
5483 * 1 2xLTF+0.8us
5484 * 2 2xLTF+1.6us
5485 * 3 & SGI (bit 13) clear 4xLTF+3.2us
5486 * 3 & SGI (bit 13) set 4xLTF+0.8us
5487 * HE MU:
5488 * 0 4xLTF+0.8us
5489 * 1 2xLTF+0.8us
5490 * 2 2xLTF+1.6us
5491 * 3 4xLTF+3.2us
5492 * HE TRIG:
5493 * 0 1xLTF+1.6us
5494 * 1 2xLTF+1.6us
5495 * 2 4xLTF+3.2us
5496 * 3 (does not occur)
5497 */
5498 #define IWX_RATE_MCS_HE_GI_LTF_POS 20
5499 #define IWX_RATE_MCS_HE_GI_LTF_MSK_V1 (3 << IWX_RATE_MCS_HE_GI_LTF_POS)
5500
5501 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
5502 #define IWX_RATE_MCS_HE_TYPE_POS_V1 22
5503 #define IWX_RATE_MCS_HE_TYPE_SU_V1 (0 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5504 #define IWX_RATE_MCS_HE_TYPE_EXT_SU_V1 (1 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5505 #define IWX_RATE_MCS_HE_TYPE_MU_V1 (2 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5506 #define IWX_RATE_MCS_HE_TYPE_TRIG_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5507 #define IWX_RATE_MCS_HE_TYPE_MSK_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5508
5509 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
5510 #define IWX_RATE_MCS_DUP_POS_V1 24
5511 #define IWX_RATE_MCS_DUP_MSK_V1 (3 << IWX_RATE_MCS_DUP_POS_V1)
5512
5513 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
5514 #define IWX_RATE_MCS_LDPC_POS_V1 27
5515 #define IWX_RATE_MCS_LDPC_MSK_V1 (1 << IWX_RATE_MCS_LDPC_POS_V1)
5516
5517 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
5518 #define IWX_RATE_MCS_HE_106T_POS_V1 28
5519 #define IWX_RATE_MCS_HE_106T_MSK_V1 (1 << IWX_RATE_MCS_HE_106T_POS_V1)
5520
5521 /* Bit 30-31: (1) RTS, (2) CTS */
5522 #define IWX_RATE_MCS_RTS_REQUIRED_POS (30)
5523 #define IWX_RATE_MCS_RTS_REQUIRED_MSK (1 << IWX_RATE_MCS_RTS_REQUIRED_POS)
5524 #define IWX_RATE_MCS_CTS_REQUIRED_POS (31)
5525 #define IWX_RATE_MCS_CTS_REQUIRED_MSK (1 << IWX_RATE_MCS_CTS_REQUIRED_POS)
5526
5527
5528 /* rate_n_flags bit field version 2
5529 *
5530 * The 32-bit value has different layouts in the low 8 bits depending on the
5531 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
5532 * for CCK and OFDM).
5533 *
5534 */
5535
5536 /* Bits 10-8: rate format
5537 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT)
5538 * (3) Very High-throughput (VHT) (4) High-efficiency (HE)
5539 * (5) Extremely High-throughput (EHT)
5540 */
5541 #define IWX_RATE_MCS_MOD_TYPE_POS 8
5542 #define IWX_RATE_MCS_MOD_TYPE_MSK (0x7 << IWX_RATE_MCS_MOD_TYPE_POS)
5543 #define IWX_RATE_MCS_CCK_MSK (0 << IWX_RATE_MCS_MOD_TYPE_POS)
5544 #define IWX_RATE_MCS_LEGACY_OFDM_MSK (1 << IWX_RATE_MCS_MOD_TYPE_POS)
5545 #define IWX_RATE_MCS_HT_MSK (2 << IWX_RATE_MCS_MOD_TYPE_POS)
5546 #define IWX_RATE_MCS_VHT_MSK (3 << IWX_RATE_MCS_MOD_TYPE_POS)
5547 #define IWX_RATE_MCS_HE_MSK (4 << IWX_RATE_MCS_MOD_TYPE_POS)
5548 #define IWX_RATE_MCS_EHT_MSK (5 << IWX_RATE_MCS_MOD_TYPE_POS)
5549
5550 /*
5551 * Legacy CCK rate format for bits 0:3:
5552 *
5553 * (0) 0xa - 1 Mbps
5554 * (1) 0x14 - 2 Mbps
5555 * (2) 0x37 - 5.5 Mbps
5556 * (3) 0x6e - 11 nbps
5557 *
5558 * Legacy OFDM rate format for bits 0:3:
5559 *
5560 * (0) 6 Mbps
5561 * (1) 9 Mbps
5562 * (2) 12 Mbps
5563 * (3) 18 Mbps
5564 * (4) 24 Mbps
5565 * (5) 36 Mbps
5566 * (6) 48 Mbps
5567 * (7) 54 Mbps
5568 *
5569 */
5570 #define IWX_RATE_LEGACY_RATE_MSK 0x7
5571
5572 /*
5573 * HT, VHT, HE, EHT rate format for bits 3:0
5574 * 3-0: MCS
5575 *
5576 */
5577 #define IWX_RATE_HT_MCS_CODE_MSK 0x7
5578 #define IWX_RATE_MCS_NSS_POS 4
5579 #define IWX_RATE_MCS_NSS_MSK (1 << IWX_RATE_MCS_NSS_POS)
5580 #define IWX_RATE_MCS_CODE_MSK 0xf
5581 #define IWX_RATE_HT_MCS_INDEX(r) ((((r) & IWX_RATE_MCS_NSS_MSK) >> 1) | \
5582 ((r) & IWX_RATE_HT_MCS_CODE_MSK))
5583
5584 /* Bits 7-5: reserved */
5585
5586 /*
5587 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz
5588 */
5589 #define IWX_RATE_MCS_CHAN_WIDTH_MSK (0x7 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5590 #define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5591 #define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5592 #define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5593 #define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5594 #define IWX_RATE_MCS_CHAN_WIDTH_320 (4 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5595
5596 /* Bit 15-14: Antenna selection:
5597 * Bit 14: Ant A active
5598 * Bit 15: Ant B active
5599 *
5600 * All relevant definitions are same as in v1
5601 */
5602
5603 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */
5604 #define IWX_RATE_MCS_LDPC_POS 16
5605 #define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS)
5606
5607 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */
5608
5609 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */
5610
5611 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */
5612
5613 /*
5614 * Bit 22-20: HE LTF type and guard interval
5615 * CCK:
5616 * 0 long preamble
5617 * 1 short preamble
5618 * HT/VHT:
5619 * 0 0.8us
5620 * 1 0.4us
5621 * HE (ext) SU:
5622 * 0 1xLTF+0.8us
5623 * 1 2xLTF+0.8us
5624 * 2 2xLTF+1.6us
5625 * 3 4xLTF+3.2us
5626 * 4 4xLTF+0.8us
5627 * HE MU:
5628 * 0 4xLTF+0.8us
5629 * 1 2xLTF+0.8us
5630 * 2 2xLTF+1.6us
5631 * 3 4xLTF+3.2us
5632 * HE TRIG:
5633 * 0 1xLTF+1.6us
5634 * 1 2xLTF+1.6us
5635 * 2 4xLTF+3.2us
5636 * */
5637 #define IWX_RATE_MCS_HE_GI_LTF_MSK (0x7 << IWX_RATE_MCS_HE_GI_LTF_POS)
5638 #define IWX_RATE_MCS_SGI_POS IWX_RATE_MCS_HE_GI_LTF_POS
5639 #define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS)
5640 #define IWX_RATE_MCS_HE_SU_4_LTF 3
5641 #define IWX_RATE_MCS_HE_SU_4_LTF_08_GI 4
5642
5643 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
5644 #define IWX_RATE_MCS_HE_TYPE_POS 23
5645 #define IWX_RATE_MCS_HE_TYPE_SU (0 << IWX_RATE_MCS_HE_TYPE_POS)
5646 #define IWX_RATE_MCS_HE_TYPE_EXT_SU (1 << IWX_RATE_MCS_HE_TYPE_POS)
5647 #define IWX_RATE_MCS_HE_TYPE_MU (2 << IWX_RATE_MCS_HE_TYPE_POS)
5648 #define IWX_RATE_MCS_HE_TYPE_TRIG (3 << IWX_RATE_MCS_HE_TYPE_POS)
5649 #define IWX_RATE_MCS_HE_TYPE_MSK (3 << IWX_RATE_MCS_HE_TYPE_POS)
5650
5651 /* Bit 25: duplicate channel enabled
5652 *
5653 * if this bit is set, duplicate is according to BW (bits 11-13):
5654 *
5655 * CCK: 2x 20MHz
5656 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16)
5657 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160)
5658 * */
5659 #define IWX_RATE_MCS_DUP_POS 25
5660 #define IWX_RATE_MCS_DUP_MSK (1 << IWX_RATE_MCS_DUP_POS)
5661
5662 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
5663 #define IWX_RATE_MCS_HE_106T_POS 26
5664 #define IWX_RATE_MCS_HE_106T_MSK (1 << IWX_RATE_MCS_HE_106T_POS)
5665
5666 /* Bit 27: EHT extra LTF:
5667 * instead of 1 LTF for SISO use 2 LTFs,
5668 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/
5669 #define IWX_RATE_MCS_EHT_EXTRA_LTF_POS 27
5670 #define IWX_RATE_MCS_EHT_EXTRA_LTF_MSK (1 << IWX_RATE_MCS_EHT_EXTRA_LTF_POS)
5671
5672 /* Bit 31-28: reserved */
5673
5674
5675 /* Link Quality definitions */
5676
5677 /* # entries in rate scale table to support Tx retries */
5678 #define IWX_LQ_MAX_RETRY_NUM 16
5679
5680 /* Link quality command flags bit fields */
5681
5682 /* Bit 0: (0) Don't use RTS (1) Use RTS */
5683 #define IWX_LQ_FLAG_USE_RTS_POS 0
5684 #define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS)
5685
5686 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
5687 #define IWX_LQ_FLAG_COLOR_POS 1
5688 #define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS)
5689
5690 /* Bit 4-5: Tx RTS BW Signalling
5691 * (0) No RTS BW signalling
5692 * (1) Static BW signalling
5693 * (2) Dynamic BW signalling
5694 */
5695 #define IWX_LQ_FLAG_RTS_BW_SIG_POS 4
5696 #define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5697 #define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5698 #define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5699
5700 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
5701 * Dynamic BW selection allows Tx with narrower BW then requested in rates
5702 */
5703 #define IWX_LQ_FLAG_DYNAMIC_BW_POS 6
5704 #define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS)
5705
5706 #define IWX_RLC_CHAIN_INFO_DRIVER_FORCE (1 << 0)
5707 #define IWL_RLC_CHAIN_INFO_VALID 0x000e
5708 #define IWL_RLC_CHAIN_INFO_FORCE 0x0070
5709 #define IWL_RLC_CHAIN_INFO_FORCE_MIMO 0x0380
5710 #define IWL_RLC_CHAIN_INFO_COUNT 0x0c00
5711 #define IWL_RLC_CHAIN_INFO_MIMO_COUNT 0x3000
5712
5713 /**
5714 * struct iwx_rlc_properties - RLC properties
5715 * @rx_chain_info: RX chain info, IWX_RLC_CHAIN_INFO_*
5716 * @reserved: reserved
5717 */
5718 struct iwx_rlc_properties {
5719 uint32_t rx_chain_info;
5720 uint32_t reserved;
5721 } __packed; /* RLC_PROPERTIES_S_VER_1 */
5722
5723 #define IWX_SAD_MODE_ENABLED (1 << 0)
5724 #define IWX_SAD_MODE_DEFAULT_ANT_MSK 0x6
5725 #define IWX_SAD_MODE_DEFAULT_ANT_FW 0x0
5726 #define IWX_SAD_MODE_DEFAULT_ANT_A 0x2
5727 #define IWX_SAD_MODE_DEFAULT_ANT_B 0x4
5728
5729 /**
5730 * struct iwx_sad_properties - SAD properties
5731 * @chain_a_sad_mode: chain A SAD mode, IWX_SAD_MODE_*
5732 * @chain_b_sad_mode: chain B SAD mode, IWX_SAD_MODE_*
5733 * @mac_id: MAC index
5734 * @reserved: reserved
5735 */
5736 struct iwx_sad_properties {
5737 uint32_t chain_a_sad_mode;
5738 uint32_t chain_b_sad_mode;
5739 uint32_t mac_id;
5740 uint32_t reserved;
5741 } __packed;
5742
5743 /**
5744 * struct iwx_rlc_config_cmd - RLC configuration
5745 * @phy_id: PHY index
5746 * @rlc: RLC properties, &struct iwx_rlc_properties
5747 * @sad: SAD (single antenna diversity) options, &struct iwx_sad_properties
5748 * @flags: flags, IWX_RLC_FLAGS_*
5749 * @reserved: reserved
5750 */
5751 struct iwx_rlc_config_cmd {
5752 uint32_t phy_id;
5753 struct iwx_rlc_properties rlc;
5754 struct iwx_sad_properties sad;
5755 uint8_t flags;
5756 uint8_t reserved[3];
5757 } __packed; /* RLC_CONFIG_CMD_API_S_VER_2 */
5758
5759 #define IWX_MAX_BAID_OLD 16 /* MAX_IMMEDIATE_BA_API_D_VER_2 */
5760 #define IWX_MAX_BAID 32 /* MAX_IMMEDIATE_BA_API_D_VER_3 */
5761
5762 /**
5763 * BAID allocation/config action
5764 * @IWX_RX_BAID_ACTION_ADD: add a new BAID session
5765 * @IWX_RX_BAID_ACTION_MODIFY: modify the BAID session
5766 * @IWX_RX_BAID_ACTION_REMOVE: remove the BAID session
5767 */
5768 #define IWX_RX_BAID_ACTION_ADD 0
5769 #define IWX_RX_BAID_ACTION_MODIFY 1
5770 #define IWX_RX_BAID_ACTION_REMOVE 2
5771 /* RX_BAID_ALLOCATION_ACTION_E_VER_1 */
5772
5773 /**
5774 * struct iwx_rx_baid_cfg_cmd_alloc - BAID allocation data
5775 * @sta_id_mask: station ID mask
5776 * @tid: the TID for this session
5777 * @reserved: reserved
5778 * @ssn: the starting sequence number
5779 * @win_size: RX BA session window size
5780 */
5781 struct iwx_rx_baid_cfg_cmd_alloc {
5782 uint32_t sta_id_mask;
5783 uint8_t tid;
5784 uint8_t reserved[3];
5785 uint16_t ssn;
5786 uint16_t win_size;
5787 } __packed; /* RX_BAID_ALLOCATION_ADD_CMD_API_S_VER_1 */
5788
5789 /**
5790 * struct iwx_rx_baid_cfg_cmd_modify - BAID modification data
5791 * @old_sta_id_mask: old station ID mask
5792 * @new_sta_id_mask: new station ID mask
5793 * @tid: TID of the BAID
5794 */
5795 struct iwx_rx_baid_cfg_cmd_modify {
5796 uint32_t old_sta_id_mask;
5797 uint32_t new_sta_id_mask;
5798 uint32_t tid;
5799 } __packed; /* RX_BAID_ALLOCATION_MODIFY_CMD_API_S_VER_2 */
5800
5801 /**
5802 * struct iwx_rx_baid_cfg_cmd_remove_v1 - BAID removal data
5803 * @baid: the BAID to remove
5804 */
5805 struct iwx_rx_baid_cfg_cmd_remove_v1 {
5806 uint32_t baid;
5807 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_1 */
5808
5809 /**
5810 * struct iwx_rx_baid_cfg_cmd_remove - BAID removal data
5811 * @sta_id_mask: the station mask of the BAID to remove
5812 * @tid: the TID of the BAID to remove
5813 */
5814 struct iwx_rx_baid_cfg_cmd_remove {
5815 uint32_t sta_id_mask;
5816 uint32_t tid;
5817 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_2 */
5818
5819 /**
5820 * struct iwx_rx_baid_cfg_cmd - BAID allocation/config command
5821 * @action: the action, from &enum iwx_rx_baid_action
5822 */
5823 struct iwx_rx_baid_cfg_cmd {
5824 uint32_t action;
5825 union {
5826 struct iwx_rx_baid_cfg_cmd_alloc alloc;
5827 struct iwx_rx_baid_cfg_cmd_modify modify;
5828 struct iwx_rx_baid_cfg_cmd_remove_v1 remove_v1;
5829 struct iwx_rx_baid_cfg_cmd_remove remove;
5830 }; /* RX_BAID_ALLOCATION_OPERATION_API_U_VER_2 */
5831 } __packed; /* RX_BAID_ALLOCATION_CONFIG_CMD_API_S_VER_2 */
5832
5833 /**
5834 * struct iwx_rx_baid_cfg_resp - BAID allocation response
5835 * @baid: the allocated BAID
5836 */
5837 struct iwx_rx_baid_cfg_resp {
5838 uint32_t baid;
5839 }; /* RX_BAID_ALLOCATION_RESPONSE_API_S_VER_1 */
5840
5841 /**
5842 * scheduler queue operation
5843 * @IWX_SCD_QUEUE_ADD: allocate a new queue
5844 * @IWX_SCD_QUEUE_REMOVE: remove a queue
5845 * @IWX_SCD_QUEUE_MODIFY: modify a queue
5846 */
5847 #define IWX_SCD_QUEUE_ADD 0
5848 #define IWX_SCD_QUEUE_REMOVE 1
5849 #define IWX_SCD_QUEUE_MODIFY 2
5850
5851 /**
5852 * struct iwx_scd_queue_cfg_cmd - scheduler queue allocation command
5853 * @operation: the operation, see &enum iwl_scd_queue_cfg_operation
5854 * @u.add.sta_mask: station mask
5855 * @u.add.tid: TID
5856 * @u.add.reserved: reserved
5857 * @u.add.flags: flags from &enum iwl_tx_queue_cfg_actions, except
5858 * %TX_QUEUE_CFG_ENABLE_QUEUE is not valid
5859 * @u.add.cb_size: size code
5860 * @u.add.bc_dram_addr: byte-count table IOVA
5861 * @u.add.tfdq_dram_addr: TFD queue IOVA
5862 * @u.remove.sta_mask: station mask of queue to remove
5863 * @u.remove.tid: TID of queue to remove
5864 * @u.modify.old_sta_mask: old station mask for modify
5865 * @u.modify.tid: TID of queue to modify
5866 * @u.modify.new_sta_mask: new station mask for modify
5867 */
5868 struct iwx_scd_queue_cfg_cmd {
5869 uint32_t operation;
5870 union {
5871 struct {
5872 uint32_t sta_mask;
5873 uint8_t tid;
5874 uint8_t reserved[3];
5875 uint32_t flags;
5876 uint32_t cb_size;
5877 uint64_t bc_dram_addr;
5878 uint64_t tfdq_dram_addr;
5879 } __packed add; /* TX_QUEUE_CFG_CMD_ADD_API_S_VER_1 */
5880 struct {
5881 uint32_t sta_mask;
5882 uint32_t tid;
5883 } __packed remove; /* TX_QUEUE_CFG_CMD_REMOVE_API_S_VER_1 */
5884 struct {
5885 uint32_t old_sta_mask;
5886 uint32_t tid;
5887 uint32_t new_sta_mask;
5888 } __packed modify; /* TX_QUEUE_CFG_CMD_MODIFY_API_S_VER_1 */
5889 } __packed u; /* TX_QUEUE_CFG_CMD_OPERATION_API_U_VER_1 */
5890 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_3 */
5891
5892 /**
5893 * enum iwx_sec_key_flags - security key command key flags
5894 * @IWX_SEC_KEY_FLAG_CIPHER_MASK: cipher mask
5895 * @IWX_SEC_KEY_FLAG_CIPHER_WEP: WEP cipher
5896 * @IWX_SEC_KEY_FLAG_CIPHER_CCMP: CCMP/CMAC cipher
5897 * @IWX_SEC_KEY_FLAG_CIPHER_TKIP: TKIP cipher
5898 * @IWX_SEC_KEY_FLAG_CIPHER_GCMP: GCMP/GMAC cipher
5899 * @IWX_SEC_KEY_FLAG_NO_TX: don't install for TX
5900 * @IWX_SEC_KEY_FLAG_KEY_SIZE: large key size (WEP-104, GCMP-256, GMAC-256)
5901 * @IWX_SEC_KEY_FLAG_MFP: MFP is in used for this key
5902 * @IWX_SEC_KEY_FLAG_MCAST_KEY: this is a multicast key
5903 * @IWX_SEC_KEY_FLAG_SPP_AMSDU: SPP A-MSDU should be used
5904 */
5905 enum iwx_sec_key_flags {
5906 IWX_SEC_KEY_FLAG_CIPHER_MASK = 0x07,
5907 IWX_SEC_KEY_FLAG_CIPHER_WEP = 0x01,
5908 IWX_SEC_KEY_FLAG_CIPHER_CCMP = 0x02,
5909 IWX_SEC_KEY_FLAG_CIPHER_TKIP = 0x03,
5910 IWX_SEC_KEY_FLAG_CIPHER_GCMP = 0x05,
5911 IWX_SEC_KEY_FLAG_NO_TX = 0x08,
5912 IWX_SEC_KEY_FLAG_KEY_SIZE = 0x10,
5913 IWX_SEC_KEY_FLAG_MFP = 0x20,
5914 IWX_SEC_KEY_FLAG_MCAST_KEY = 0x40,
5915 IWX_SEC_KEY_FLAG_SPP_AMSDU = 0x80,
5916 };
5917
5918 #define IWX_SEC_WEP_KEY_OFFSET 3
5919
5920 /**
5921 * struct iwx_sec_key_cmd - security key command
5922 * @action: action from &enum iwx_ctxt_action
5923 * @u.add.sta_mask: station mask for the new key
5924 * @u.add.key_id: key ID (0-7) for the new key
5925 * @u.add.key_flags: key flags per &enum iwx_sec_key_flags
5926 * @u.add.key: key material. WEP keys should start from &IWX_SEC_WEP_KEY_OFFSET.
5927 * @u.add.tkip_mic_rx_key: TKIP MIC RX key
5928 * @u.add.tkip_mic_tx_key: TKIP MIC TX key
5929 * @u.add.rx_seq: RX sequence counter value
5930 * @u.add.tx_seq: TX sequence counter value
5931 * @u.modify.old_sta_mask: old station mask
5932 * @u.modify.new_sta_mask: new station mask
5933 * @u.modify.key_id: key ID
5934 * @u.modify.key_flags: new key flags
5935 * @u.remove.sta_mask: station mask
5936 * @u.remove.key_id: key ID
5937 * @u.remove.key_flags: key flags
5938 */
5939 struct iwx_sec_key_cmd {
5940 uint32_t action;
5941 union {
5942 struct {
5943 uint32_t sta_mask;
5944 uint32_t key_id;
5945 uint32_t key_flags;
5946 uint8_t key[32];
5947 uint8_t tkip_mic_rx_key[8];
5948 uint8_t tkip_mic_tx_key[8];
5949 uint64_t rx_seq;
5950 uint64_t tx_seq;
5951 } __packed add; /* SEC_KEY_ADD_CMD_API_S_VER_1 */
5952 struct {
5953 uint32_t old_sta_mask;
5954 uint32_t new_sta_mask;
5955 uint32_t key_id;
5956 uint32_t key_flags;
5957 } __packed modify; /* SEC_KEY_MODIFY_CMD_API_S_VER_1 */
5958 struct {
5959 uint32_t sta_mask;
5960 uint32_t key_id;
5961 uint32_t key_flags;
5962 } __packed remove; /* SEC_KEY_REMOVE_CMD_API_S_VER_1 */
5963 } __packed u; /* SEC_KEY_OPERATION_API_U_VER_1 */
5964 } __packed; /* SEC_KEY_CMD_API_S_VER_1 */
5965
5966 /**
5967 * Options for TLC config flags
5968 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
5969 * bandwidths <= 80MHz
5970 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
5971 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
5972 * bandwidth
5973 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
5974 * for BPSK (MCS 0) with 1 spatial
5975 * stream
5976 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
5977 * for BPSK (MCS 0) with 2 spatial
5978 * streams
5979 */
5980 #define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0)
5981 #define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1)
5982 #define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2)
5983 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3)
5984 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4)
5985
5986 /**
5987 * enum iwx_tlc_mng_cfg_cw - channel width options
5988 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
5989 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
5990 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
5991 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
5992 * @IWX_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
5993 */
5994 enum iwx_tlc_mng_cfg_cw {
5995 IWX_TLC_MNG_CH_WIDTH_20MHZ,
5996 IWX_TLC_MNG_CH_WIDTH_40MHZ,
5997 IWX_TLC_MNG_CH_WIDTH_80MHZ,
5998 IWX_TLC_MNG_CH_WIDTH_160MHZ,
5999 IWX_TLC_MNG_CH_WIDTH_320MHZ,
6000 };
6001
6002 /**
6003 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A
6004 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B
6005 */
6006 #define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0)
6007 #define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1)
6008
6009 /**
6010 * enum iwx_tlc_mng_cfg_mode - supported modes
6011 * @IWX_TLC_MNG_MODE_CCK: enable CCK
6012 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
6013 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT
6014 * @IWX_TLC_MNG_MODE_HT: enable HT
6015 * @IWX_TLC_MNG_MODE_VHT: enable VHT
6016 * @IWX_TLC_MNG_MODE_HE: enable HE
6017 * @IWX_TLC_MNG_MODE_EHT: enable EHT
6018 */
6019 enum iwx_tlc_mng_cfg_mode {
6020 IWX_TLC_MNG_MODE_CCK = 0,
6021 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK,
6022 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK,
6023 IWX_TLC_MNG_MODE_HT,
6024 IWX_TLC_MNG_MODE_VHT,
6025 IWX_TLC_MNG_MODE_HE,
6026 IWX_TLC_MNG_MODE_EHT,
6027 };
6028
6029 /**
6030 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0
6031 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1
6032 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2
6033 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3
6034 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4
6035 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5
6036 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6
6037 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7
6038 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8
6039 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9
6040 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10
6041 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11
6042 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
6043 */
6044 enum iwx_tlc_mng_ht_rates {
6045 IWX_TLC_MNG_HT_RATE_MCS0 = 0,
6046 IWX_TLC_MNG_HT_RATE_MCS1,
6047 IWX_TLC_MNG_HT_RATE_MCS2,
6048 IWX_TLC_MNG_HT_RATE_MCS3,
6049 IWX_TLC_MNG_HT_RATE_MCS4,
6050 IWX_TLC_MNG_HT_RATE_MCS5,
6051 IWX_TLC_MNG_HT_RATE_MCS6,
6052 IWX_TLC_MNG_HT_RATE_MCS7,
6053 IWX_TLC_MNG_HT_RATE_MCS8,
6054 IWX_TLC_MNG_HT_RATE_MCS9,
6055 IWX_TLC_MNG_HT_RATE_MCS10,
6056 IWX_TLC_MNG_HT_RATE_MCS11,
6057 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11,
6058 };
6059
6060 #define IWX_TLC_NSS_1 0
6061 #define IWX_TLC_NSS_2 1
6062 #define IWX_TLC_NSS_MAX 2
6063
6064
6065 /**
6066 * IWX_TLC_MCS_PER_BW - mcs index per BW
6067 * @IWX_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
6068 * @IWX_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
6069 * @IWX_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
6070 * @IWX_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3
6071 * @IWX_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4
6072 */
6073 #define IWX_TLC_MCS_PER_BW_80 0
6074 #define IWX_TLC_MCS_PER_BW_160 1
6075 #define IWX_TLC_MCS_PER_BW_320 2
6076 #define IWX_TLC_MCS_PER_BW_NUM_V3 (IWX_TLC_MCS_PER_BW_160 + 1)
6077 #define IWX_TLC_MCS_PER_BW_NUM_V4 (IWX_TLC_MCS_PER_BW_320 + 1)
6078
6079 /**
6080 * struct iwx_tlc_config_cmd_v3 - TLC configuration version 3
6081 * @sta_id: station id
6082 * @reserved1: reserved
6083 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw
6084 * @mode: &enum iwx_tlc_mng_cfg_mode
6085 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK
6086 * @amsdu: 1 = TX amsdu is supported, 0 = not supported
6087 * @flags: bitmask of IWX_TLC_MNG_CFG_*
6088 * @non_ht_rates: bitmap of supported legacy rates
6089 * @ht_rates: MCS index 0 - 11, per <nss, channel-width>
6090 * pair (0 - 80mhz width and below, 1 - 160mhz).
6091 * @max_mpdu_len: max MPDU length, in bytes
6092 * @sgi_ch_width_supp: bitmap of SGI support per channel width
6093 * use (1 << IWX_TLC_MNG_CFG_CW_*)
6094 * @reserved2: reserved
6095 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
6096 * set zero for no limit.
6097 */
6098 struct iwx_tlc_config_cmd_v3 {
6099 uint8_t sta_id;
6100 uint8_t reserved1[3];
6101 uint8_t max_ch_width;
6102 uint8_t mode;
6103 uint8_t chains;
6104 uint8_t amsdu;
6105 uint16_t flags;
6106 uint16_t non_ht_rates;
6107 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V3];
6108 uint16_t max_mpdu_len;
6109 uint8_t sgi_ch_width_supp;
6110 uint8_t reserved2;
6111 uint32_t max_tx_op;
6112 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */
6113
6114 /**
6115 * struct iwx_tlc_config_cmd_v4 - TLC configuration
6116 * @sta_id: station id
6117 * @reserved1: reserved
6118 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw
6119 * @mode: &enum iwx_tlc_mng_cfg_mode
6120 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK
6121 * @sgi_ch_width_supp: bitmap of SGI support per channel width
6122 * use (1 << IWX_TLC_MNG_CFG_CW_*)
6123 * @flags: bitmask of IWX_TLC_MNG_CFG_*
6124 * @non_ht_rates: bitmap of supported legacy rates
6125 * @ht_rates: MCS index 0 - 11, per <nss, channel-width>
6126 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
6127 * @max_mpdu_len: max MPDU length, in bytes
6128 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
6129 * set zero for no limit.
6130 */
6131 struct iwx_tlc_config_cmd_v4 {
6132 uint8_t sta_id;
6133 uint8_t reserved1[3];
6134 uint8_t max_ch_width;
6135 uint8_t mode;
6136 uint8_t chains;
6137 uint8_t sgi_ch_width_supp;
6138 uint16_t flags;
6139 uint16_t non_ht_rates;
6140 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V4];
6141 uint16_t max_mpdu_len;
6142 uint16_t max_tx_op;
6143 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */
6144
6145 /**
6146 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update
6147 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
6148 */
6149 #define IWX_TLC_NOTIF_FLAG_RATE (1 << 0)
6150 #define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1)
6151
6152 /**
6153 * struct iwx_tlc_update_notif - TLC notification from FW
6154 * @sta_id: station id
6155 * @reserved: reserved
6156 * @flags: bitmap of notifications reported
6157 * @rate: current initial rate; using rate_n_flags version 1 if notification
6158 * version is < 3 at run-time, else rate_n_flags version 2
6159 * @amsdu_size: Max AMSDU size, in bytes
6160 * @amsdu_enabled: bitmap for per-TID AMSDU enablement
6161 */
6162 struct iwx_tlc_update_notif {
6163 uint8_t sta_id;
6164 uint8_t reserved[3];
6165 uint32_t flags;
6166 uint32_t rate;
6167 uint32_t amsdu_size;
6168 uint32_t amsdu_enabled;
6169 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
6170
6171 /* Antenna flags. */
6172 #define IWX_ANT_A (1 << 0)
6173 #define IWX_ANT_B (1 << 1)
6174 #define IWX_ANT_C (1 << 2)
6175 /* Shortcuts. */
6176 #define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B)
6177 #define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C)
6178 #define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C)
6179
6180 /*
6181 * TX command security control
6182 */
6183 #define IWX_TX_CMD_SEC_WEP 0x01
6184 #define IWX_TX_CMD_SEC_CCM 0x02
6185 #define IWX_TX_CMD_SEC_TKIP 0x03
6186 #define IWX_TX_CMD_SEC_EXT 0x04
6187 #define IWX_TX_CMD_SEC_MSK 0x07
6188 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6
6189 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
6190 #define IWX_TX_CMD_SEC_KEY128 0x08
6191
6192 /* TODO: how does these values are OK with only 16 bit variable??? */
6193 /*
6194 * TX command next frame info
6195 *
6196 * bits 0:2 - security control (IWX_TX_CMD_SEC_*)
6197 * bit 3 - immediate ACK required
6198 * bit 4 - rate is taken from STA table
6199 * bit 5 - frame belongs to BA stream
6200 * bit 6 - immediate BA response expected
6201 * bit 7 - unused
6202 * bits 8:15 - Station ID
6203 * bits 16:31 - rate
6204 */
6205 #define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
6206 #define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
6207 #define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
6208 #define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
6209 #define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
6210 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
6211 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
6212 #define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
6213 #define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16)
6214
6215 /*
6216 * TX command Frame life time in us - to be written in pm_frame_timeout
6217 */
6218 #define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
6219 #define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
6220 #define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
6221 #define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
6222
6223 /*
6224 * TID for non QoS frames - to be written in tid_tspec
6225 */
6226 #define IWX_TID_NON_QOS 0
6227
6228 /*
6229 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
6230 */
6231 #define IWX_DEFAULT_TX_RETRY 15
6232 #define IWX_MGMT_DFAULT_RETRY_LIMIT 3
6233 #define IWX_RTS_DFAULT_RETRY_LIMIT 3
6234 #define IWX_BAR_DFAULT_RETRY_LIMIT 60
6235 #define IWX_LOW_RETRY_LIMIT 7
6236
6237 /*
6238 * The FH will write back to the first TB only, so we need to copy some data
6239 * into the buffer regardless of whether it should be mapped or not.
6240 * This indicates how big the first TB must be to include the scratch buffer
6241 * and the assigned PN.
6242 * Since PN location is 8 bytes at offset 12, it's 20 now.
6243 * If we make it bigger then allocations will be bigger and copy slower, so
6244 * that's probably not useful.
6245 */
6246 #define IWX_FIRST_TB_SIZE 20
6247 #define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1))
6248
6249 /**
6250 * %iwx_tx_cmd offload_assist values
6251 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words)
6252 * from mac header end. For normal case it is 4 words for SNAP.
6253 * note: tx_cmd, mac header and pad are not counted in the offset.
6254 * This is used to help the offload in case there is tunneling such as
6255 * IPv6 in IPv4, in such case the ip header offset should point to the
6256 * inner ip header and IPv4 checksum of the external header should be
6257 * calculated by driver.
6258 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
6259 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum
6260 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV
6261 * field. Doesn't include the pad.
6262 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
6263 * alignment
6264 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
6265 */
6266 #define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0)
6267 #define IWX_TX_CMD_OFFLD_L4_EN (1 << 6)
6268 #define IWX_TX_CMD_OFFLD_L3_EN (1 << 7)
6269 #define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8)
6270 #define IWX_TX_CMD_OFFLD_PAD (1 << 13)
6271 #define IWX_TX_CMD_OFFLD_AMSDU (1 << 14)
6272 #define IWX_TX_CMD_OFFLD_MH_MASK 0x1f
6273 #define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f
6274
6275 struct iwx_dram_sec_info {
6276 uint32_t pn_low;
6277 uint16_t pn_high;
6278 uint16_t aux_info;
6279 } __packed; /* DRAM_SEC_INFO_API_S_VER_1 */
6280
6281 /**
6282 * bitmasks for tx_flags in TX command for 22000
6283 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command
6284 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs
6285 * to a secured STA
6286 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate
6287 * selection, retry limits and BT kill
6288 */
6289 /* Valid for TX_FLAGS_BITS_API_S_VER_3: */
6290 #define IWX_TX_FLAGS_CMD_RATE (1 << 0)
6291 #define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1)
6292 #define IWX_TX_FLAGS_HIGH_PRI (1 << 2)
6293 /* Valid for TX_FLAGS_BITS_API_S_VER_4 and above: */
6294 #define IWX_TX_FLAGS_RTS (1 << 3)
6295 #define IWX_TX_FLAGS_CTS (1 << 4)
6296 /* TX_FLAGS_BITS_API_S_VER_4 */
6297
6298 /**
6299 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices
6300 * ( TX_CMD = 0x1c )
6301 * @len: in bytes of the payload, see below for details
6302 * @offload_assist: TX offload configuration
6303 * @flags: combination of TX_FLAGS_*
6304 * @dram_info: FW internal DRAM storage
6305 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
6306 * cleared. Combination of RATE_MCS_*
6307 * @hdr: 802.11 header
6308 */
6309 struct iwx_tx_cmd_gen2 {
6310 uint16_t len;
6311 uint16_t offload_assist;
6312 uint32_t flags;
6313 struct iwx_dram_sec_info dram_info;
6314 uint32_t rate_n_flags;
6315 struct ieee80211_frame hdr[0];
6316 } __packed; /* TX_CMD_API_S_VER_7,
6317 TX_CMD_API_S_VER_9 */
6318
6319 /**
6320 * struct iwx_tx_cmd_gen3 - TX command struct to FW for AX210+ devices
6321 * ( TX_CMD = 0x1c )
6322 * @len: in bytes of the payload, see below for details
6323 * @flags: combination of TX_FLAGS_*
6324 * @offload_assist: TX offload configuration
6325 * @dram_info: FW internal DRAM storage
6326 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
6327 * cleared. Combination of RATE_MCS_*
6328 * @reserved: reserved
6329 * @hdr: 802.11 header
6330 */
6331 struct iwx_tx_cmd_gen3 {
6332 uint16_t len;
6333 uint16_t flags;
6334 uint32_t offload_assist;
6335 struct iwx_dram_sec_info dram_info;
6336 uint32_t rate_n_flags;
6337 uint8_t reserved[8];
6338 struct ieee80211_frame hdr[];
6339 } __packed; /* TX_CMD_API_S_VER_8,
6340 TX_CMD_API_S_VER_10 */
6341
6342 /*
6343 * TX response related data
6344 */
6345
6346 /*
6347 * status that is returned by the fw after attempts to Tx
6348 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
6349 * STA table
6350 * Valid only if frame_count =1
6351 */
6352 #define IWX_TX_STATUS_MSK 0x000000ff
6353 #define IWX_TX_STATUS_SUCCESS 0x01
6354 #define IWX_TX_STATUS_DIRECT_DONE 0x02
6355 /* postpone TX */
6356 #define IWX_TX_STATUS_POSTPONE_DELAY 0x40
6357 #define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41
6358 #define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42
6359 #define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
6360 #define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44
6361 /* abort TX */
6362 #define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
6363 #define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82
6364 #define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83
6365 #define IWX_TX_STATUS_FAIL_UNDERRUN 0x84
6366 #define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85
6367 #define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
6368 #define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
6369 #define IWX_TX_STATUS_FAIL_DEST_PS 0x88
6370 #define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89
6371 #define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a
6372 #define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b
6373 #define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
6374 #define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d
6375 #define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
6376 #define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f
6377 #define IWX_TX_STATUS_FAIL_FW_DROP 0x90
6378 #define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91
6379 #define IWX_TX_STATUS_INTERNAL_ABORT 0x92
6380 #define IWX_TX_MODE_MSK 0x00000f00
6381 #define IWX_TX_MODE_NO_BURST 0x00000000
6382 #define IWX_TX_MODE_IN_BURST_SEQ 0x00000100
6383 #define IWX_TX_MODE_FIRST_IN_BURST 0x00000200
6384 #define IWX_TX_QUEUE_NUM_MSK 0x0001f000
6385 #define IWX_TX_NARROW_BW_MSK 0x00060000
6386 #define IWX_TX_NARROW_BW_1DIV2 0x00020000
6387 #define IWX_TX_NARROW_BW_1DIV4 0x00040000
6388 #define IWX_TX_NARROW_BW_1DIV8 0x00060000
6389
6390 /*
6391 * TX aggregation status
6392 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
6393 * occur if tx failed for this frame when it was a member of a previous
6394 * aggregation block). If rate scaling is used, retry count indicates the
6395 * rate table entry used for all frames in the new agg.
6396 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
6397 * this frame
6398 */
6399 #define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff
6400 #define IWX_AGG_TX_STATE_TRANSMITTED 0x0000
6401 #define IWX_AGG_TX_STATE_UNDERRUN 0x0001
6402 #define IWX_AGG_TX_STATE_BT_PRIO 0x0002
6403 #define IWX_AGG_TX_STATE_FEW_BYTES 0x0004
6404 #define IWX_AGG_TX_STATE_ABORT 0x0008
6405 #define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010
6406 #define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020
6407 #define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040
6408 #define IWX_AGG_TX_STATE_SCD_QUERY 0x0080
6409 #define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100
6410 #define IWX_AGG_TX_STATE_RESPONSE 0x01ff
6411 #define IWX_AGG_TX_STATE_DUMP_TX 0x0200
6412 #define IWX_AGG_TX_STATE_DELAY_TX 0x0400
6413 #define IWX_AGG_TX_STATE_TRY_CNT_POS 12
6414 #define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS)
6415
6416 #define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \
6417 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
6418 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL)
6419
6420 /*
6421 * The mask below describes a status where we are absolutely sure that the MPDU
6422 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
6423 * written the bytes to the TXE, but we know nothing about what the DSP did.
6424 */
6425 #define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \
6426 IWX_AGG_TX_STATE_ABORT | \
6427 IWX_AGG_TX_STATE_SCD_QUERY)
6428
6429 /*
6430 * IWX_REPLY_TX = 0x1c (response)
6431 *
6432 * This response may be in one of two slightly different formats, indicated
6433 * by the frame_count field:
6434 *
6435 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
6436 * frame. Multiple attempts, at various bit rates, may have been made for
6437 * this frame.
6438 *
6439 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
6440 * frames that used block-acknowledge. All frames were transmitted at
6441 * same rate. Rate scaling may have been used if first frame in this new
6442 * agg block failed in previous agg block(s).
6443 *
6444 * Note that, for aggregation, ACK (block-ack) status is not delivered
6445 * here; block-ack has not been received by the time the device records
6446 * this status.
6447 * This status relates to reasons the tx might have been blocked or aborted
6448 * within the device, rather than whether it was received successfully by
6449 * the destination station.
6450 */
6451
6452 /**
6453 * struct iwx_agg_tx_status - per packet TX aggregation status
6454 * @status: enum iwx_tx_agg_status
6455 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
6456 */
6457 struct iwx_agg_tx_status {
6458 uint16_t status;
6459 uint16_t sequence;
6460 } __packed;
6461
6462 /*
6463 * definitions for initial rate index field
6464 * bits [3:0] initial rate index
6465 * bits [6:4] rate table color, used for the initial rate
6466 * bit-7 invalid rate indication
6467 */
6468 #define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f
6469 #define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70
6470 #define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80
6471
6472 #define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
6473 #define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
6474
6475 /**
6476 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet
6477 * ( IWX_REPLY_TX = 0x1c )
6478 * @frame_count: 1 no aggregation, >1 aggregation
6479 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
6480 * @failure_rts: num of failures due to unsuccessful RTS
6481 * @failure_frame: num failures due to no ACK (unused for agg)
6482 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
6483 * Tx of all the batch. IWX_RATE_MCS_*
6484 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
6485 * for agg: RTS + CTS + aggregation tx time + block-ack time.
6486 * in usec.
6487 * @pa_status: tx power info
6488 * @pa_integ_res_a: tx power info
6489 * @pa_integ_res_b: tx power info
6490 * @pa_integ_res_c: tx power info
6491 * @measurement_req_id: tx power info
6492 * @tfd_info: TFD information set by the FH
6493 * @seq_ctl: sequence control from the Tx cmd
6494 * @byte_cnt: byte count from the Tx cmd
6495 * @tlc_info: TLC rate info
6496 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
6497 * @frame_ctrl: frame control
6498 * @status: for non-agg: frame status IWX_TX_STATUS_*
6499 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields
6500 * follow this one, up to frame_count.
6501 *
6502 * After the array of statuses comes the SSN of the SCD. Look at
6503 * %iwx_get_scd_ssn for more details.
6504 */
6505 struct iwx_tx_resp_v3 {
6506 uint8_t frame_count;
6507 uint8_t bt_kill_count;
6508 uint8_t failure_rts;
6509 uint8_t failure_frame;
6510 uint32_t initial_rate;
6511 uint16_t wireless_media_time;
6512
6513 uint8_t pa_status;
6514 uint8_t pa_integ_res_a[3];
6515 uint8_t pa_integ_res_b[3];
6516 uint8_t pa_integ_res_c[3];
6517 uint16_t measurement_req_id;
6518 uint16_t reserved;
6519
6520 uint32_t tfd_info;
6521 uint16_t seq_ctl;
6522 uint16_t byte_cnt;
6523 uint8_t tlc_info;
6524 uint8_t ra_tid;
6525 uint16_t frame_ctrl;
6526
6527 struct iwx_agg_tx_status status;
6528 } __packed; /* IWX_TX_RSP_API_S_VER_3 */
6529
6530 /**
6531 * struct iwx_tx_resp - notifies that fw is TXing a packet
6532 * ( REPLY_TX = 0x1c )
6533 * @frame_count: 1 no aggregation, >1 aggregation
6534 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
6535 * @failure_rts: num of failures due to unsuccessful RTS
6536 * @failure_frame: num failures due to no ACK (unused for agg)
6537 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
6538 * Tx of all the batch. RATE_MCS_*
6539 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
6540 * for agg: RTS + CTS + aggregation tx time + block-ack time.
6541 * in usec.
6542 * @pa_status: tx power info
6543 * @pa_integ_res_a: tx power info
6544 * @pa_integ_res_b: tx power info
6545 * @pa_integ_res_c: tx power info
6546 * @measurement_req_id: tx power info
6547 * @reduced_tpc: transmit power reduction used
6548 * @reserved: reserved
6549 * @tfd_info: TFD information set by the FH
6550 * @seq_ctl: sequence control from the Tx cmd
6551 * @byte_cnt: byte count from the Tx cmd
6552 * @tlc_info: TLC rate info
6553 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
6554 * @frame_ctrl: frame control
6555 * @tx_queue: TX queue for this response
6556 * @reserved2: reserved for padding/alignment
6557 * @status: for non-agg: frame status TX_STATUS_*
6558 * For version 6 TX response isn't received for aggregation at all.
6559 *
6560 * After the array of statuses comes the SSN of the SCD. Look at
6561 * %iwl_mvm_get_scd_ssn for more details.
6562 */
6563 struct iwx_tx_resp {
6564 uint8_t frame_count;
6565 uint8_t bt_kill_count;
6566 uint8_t failure_rts;
6567 uint8_t failure_frame;
6568 uint32_t initial_rate;
6569 uint16_t wireless_media_time;
6570
6571 uint8_t pa_status;
6572 uint8_t pa_integ_res_a[3];
6573 uint8_t pa_integ_res_b[3];
6574 uint8_t pa_integ_res_c[3];
6575 uint16_t measurement_req_id;
6576 uint8_t reduced_tpc;
6577 uint8_t reserved;
6578
6579 uint32_t tfd_info;
6580 uint16_t seq_ctl;
6581 uint16_t byte_cnt;
6582 uint8_t tlc_info;
6583 uint8_t ra_tid;
6584 uint16_t frame_ctrl;
6585 uint16_t tx_queue;
6586 uint16_t reserved2;
6587 struct iwx_agg_tx_status status;
6588 } __packed; /* TX_RSP_API_S_VER_6 */
6589
6590 /**
6591 * struct iwx_compressed_ba_tfd - progress of a TFD queue
6592 * @q_num: TFD queue number
6593 * @tfd_index: Index of first un-acked frame in the TFD queue
6594 * @scd_queue: For debug only - the physical queue the TFD queue is bound to
6595 * @tid: TID of the queue (0-7)
6596 * @reserved: reserved for alignment
6597 */
6598 struct iwx_compressed_ba_tfd {
6599 uint16_t q_num;
6600 uint16_t tfd_index;
6601 uint8_t scd_queue;
6602 uint8_t tid;
6603 uint8_t reserved[2];
6604 } __packed; /* COMPRESSED_BA_TFD_API_S_VER_1 */
6605
6606 /**
6607 * struct iwx_compressed_ba_ratid - progress of a RA TID queue
6608 * @q_num: RA TID queue number
6609 * @tid: TID of the queue
6610 * @ssn: BA window current SSN
6611 */
6612 struct iwx_compressed_ba_ratid {
6613 uint8_t q_num;
6614 uint8_t tid;
6615 uint16_t ssn;
6616 } __packed; /* COMPRESSED_BA_RATID_API_S_VER_1 */
6617
6618 /*
6619 * enum iwx_ba_resp_flags - TX aggregation status
6620 * @IWX_MVM_BA_RESP_TX_AGG: generated due to BA
6621 * @IWX_MVM_BA_RESP_TX_BAR: generated due to BA after BAR
6622 * @IWX_MVM_BA_RESP_TX_AGG_FAIL: aggregation didn't receive BA
6623 * @IWX_MVM_BA_RESP_TX_UNDERRUN: aggregation got underrun
6624 * @IWX_MVM_BA_RESP_TX_BT_KILL: aggregation got BT-kill
6625 * @IWX_MVM_BA_RESP_TX_DSP_TIMEOUT: aggregation didn't finish within the
6626 * expected time
6627 */
6628 enum iwx_ba_resp_flags {
6629 IWX_MVM_BA_RESP_TX_AGG,
6630 IWX_MVM_BA_RESP_TX_BAR,
6631 IWX_MVM_BA_RESP_TX_AGG_FAIL,
6632 IWX_MVM_BA_RESP_TX_UNDERRUN,
6633 IWX_MVM_BA_RESP_TX_BT_KILL,
6634 IWX_MVM_BA_RESP_TX_DSP_TIMEOUT
6635 };
6636
6637 /**
6638 * struct iwx_compressed_ba_notif - notifies about reception of BA
6639 * ( BA_NOTIF = 0xc5 )
6640 * @flags: status flag, see the &iwx_ba_resp_flags
6641 * @sta_id: Index of recipient (BA-sending) station in fw's station table
6642 * @reduced_txp: power reduced according to TPC. This is the actual value and
6643 * not a copy from the LQ command. Thus, if not the first rate was used
6644 * for Tx-ing then this value will be set to 0 by FW.
6645 * @tlc_rate_info: TLC rate info, initial rate index, TLC table color
6646 * @retry_cnt: retry count
6647 * @query_byte_cnt: SCD query byte count
6648 * @query_frame_cnt: SCD query frame count
6649 * @txed: number of frames sent in the aggregation (all-TIDs)
6650 * @done: number of frames that were Acked by the BA (all-TIDs)
6651 * @reserved: reserved (for alignment)
6652 * @wireless_time: Wireless-media time
6653 * @tx_rate: the rate the aggregation was sent at
6654 * @tfd_cnt: number of TFD-Q elements
6655 * @ra_tid_cnt: number of RATID-Q elements
6656 * @tfd: array of TFD queue status updates. See &iwx_compressed_ba_tfd
6657 * for details. Length in @tfd_cnt.
6658 * @ra_tid: array of RA-TID queue status updates. For debug purposes only. See
6659 * &iwx_compressed_ba_ratid for more details. Length in @ra_tid_cnt.
6660 */
6661 struct iwx_compressed_ba_notif {
6662 uint32_t flags;
6663 uint8_t sta_id;
6664 uint8_t reduced_txp;
6665 uint8_t tlc_rate_info;
6666 uint8_t retry_cnt;
6667 uint32_t query_byte_cnt;
6668 uint16_t query_frame_cnt;
6669 uint16_t txed;
6670 uint16_t done;
6671 uint16_t reserved;
6672 uint32_t wireless_time;
6673 uint32_t tx_rate;
6674 uint16_t tfd_cnt;
6675 uint16_t ra_tid_cnt;
6676 struct iwx_compressed_ba_ratid ra_tid[0];
6677 struct iwx_compressed_ba_tfd tfd[];
6678 } __packed; /* COMPRESSED_BA_RES_API_S_VER_4 */
6679
6680
6681 struct iwx_beacon_notif {
6682 struct iwx_tx_resp_v3 beacon_notify_hdr;
6683 uint64_t tsf;
6684 uint32_t ibss_mgr_status;
6685 } __packed;
6686
6687 /**
6688 * dump (flush) control flags
6689 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
6690 * and the TFD queues are empty.
6691 */
6692 #define IWX_DUMP_TX_FIFO_FLUSH (1 << 1)
6693
6694 /**
6695 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command
6696 * @queues_ctl: bitmap of queues to flush
6697 * @flush_ctl: control flags
6698 * @reserved: reserved
6699 */
6700 struct iwx_tx_path_flush_cmd_v1 {
6701 uint32_t queues_ctl;
6702 uint16_t flush_ctl;
6703 uint16_t reserved;
6704 } __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */
6705
6706 /**
6707 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command
6708 * @sta_id: station ID to flush
6709 * @tid_mask: TID mask to flush
6710 * @reserved: reserved
6711 */
6712 struct iwx_tx_path_flush_cmd {
6713 uint32_t sta_id;
6714 uint16_t tid_mask;
6715 uint16_t reserved;
6716 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */
6717
6718 #define IWX_TX_FLUSH_QUEUE_RSP 16
6719
6720 /**
6721 * struct iwx_flush_queue_info - virtual flush queue info
6722 * @queue_num: virtual queue id
6723 * @read_before_flush: read pointer before flush
6724 * @read_after_flush: read pointer after flush
6725 */
6726 struct iwx_flush_queue_info {
6727 uint16_t tid;
6728 uint16_t queue_num;
6729 uint16_t read_before_flush;
6730 uint16_t read_after_flush;
6731 } __packed; /* TFDQ_FLUSH_INFO_API_S_VER_1 */
6732
6733 /**
6734 * struct iwx_tx_path_flush_cmd_rsp -- queue/FIFO flush command response
6735 * @num_flushed_queues: number of queues in queues array
6736 * @queues: all flushed queues
6737 */
6738 struct iwx_tx_path_flush_cmd_rsp {
6739 uint16_t sta_id;
6740 uint16_t num_flushed_queues;
6741 struct iwx_flush_queue_info queues[IWX_TX_FLUSH_QUEUE_RSP];
6742 } __packed; /* TX_PATH_FLUSH_CMD_RSP_API_S_VER_1 */
6743
6744
6745 /**
6746 * iwx_get_scd_ssn - returns the SSN of the SCD
6747 * @tx_resp: the Tx response from the fw (agg or non-agg)
6748 *
6749 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
6750 * it can't know that everything will go well until the end of the AMPDU, it
6751 * can't know in advance the number of MPDUs that will be sent in the current
6752 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
6753 * Hence, it can't know in advance what the SSN of the SCD will be at the end
6754 * of the batch. This is why the SSN of the SCD is written at the end of the
6755 * whole struct at a variable offset. This function knows how to cope with the
6756 * variable offset and returns the SSN of the SCD.
6757 */
iwx_get_scd_ssn(struct iwx_tx_resp * tx_resp)6758 static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp)
6759 {
6760 return le32_to_cpup((uint32_t *)&tx_resp->status +
6761 tx_resp->frame_count) & 0xfff;
6762 }
6763
6764 /**
6765 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command
6766 * @token:
6767 * @sta_id: station id
6768 * @tid:
6769 * @scd_queue: scheduler queue to config
6770 * @enable: 1 queue enable, 0 queue disable
6771 * @aggregate: 1 aggregated queue, 0 otherwise
6772 * @tx_fifo: %enum iwx_tx_fifo
6773 * @window: BA window size
6774 * @ssn: SSN for the BA agreement
6775 */
6776 struct iwx_scd_txq_cfg_cmd {
6777 uint8_t token;
6778 uint8_t sta_id;
6779 uint8_t tid;
6780 uint8_t scd_queue;
6781 uint8_t enable;
6782 uint8_t aggregate;
6783 uint8_t tx_fifo;
6784 uint8_t window;
6785 uint16_t ssn;
6786 uint16_t reserved;
6787 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
6788
6789 /**
6790 * struct iwx_scd_txq_cfg_rsp
6791 * @token: taken from the command
6792 * @sta_id: station id from the command
6793 * @tid: tid from the command
6794 * @scd_queue: scd_queue from the command
6795 */
6796 struct iwx_scd_txq_cfg_rsp {
6797 uint8_t token;
6798 uint8_t sta_id;
6799 uint8_t tid;
6800 uint8_t scd_queue;
6801 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
6802
6803
6804 /* Scan Commands, Responses, Notifications */
6805
6806 /* Max number of IEs for direct SSID scans in a command */
6807 #define IWX_PROBE_OPTION_MAX 20
6808
6809 /**
6810 * struct iwx_ssid_ie - directed scan network information element
6811 *
6812 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD,
6813 * selected by "type" bit field in struct iwx_scan_channel;
6814 * each channel may select different ssids from among the 20 entries.
6815 * SSID IEs get transmitted in reverse order of entry.
6816 */
6817 struct iwx_ssid_ie {
6818 uint8_t id;
6819 uint8_t len;
6820 uint8_t ssid[IEEE80211_NWID_LEN];
6821 } __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
6822
6823 /* scan offload */
6824 #define IWX_SCAN_MAX_BLACKLIST_LEN 64
6825 #define IWX_SCAN_SHORT_BLACKLIST_LEN 16
6826 #define IWX_SCAN_MAX_PROFILES 11
6827 #define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
6828
6829 /* Default watchdog (in MS) for scheduled scan iteration */
6830 #define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
6831
6832 #define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
6833 #define IWX_CAN_ABORT_STATUS 1
6834
6835 #define IWX_FULL_SCAN_MULTIPLIER 5
6836 #define IWX_FAST_SCHED_SCAN_ITERATIONS 3
6837 #define IWX_MAX_SCHED_SCAN_PLANS 2
6838
6839 /**
6840 * iwx_scan_schedule_lmac - schedule of scan offload
6841 * @delay: delay between iterations, in seconds.
6842 * @iterations: num of scan iterations
6843 * @full_scan_mul: number of partial scans before each full scan
6844 */
6845 struct iwx_scan_schedule_lmac {
6846 uint16_t delay;
6847 uint8_t iterations;
6848 uint8_t full_scan_mul;
6849 } __packed; /* SCAN_SCHEDULE_API_S */
6850
6851 /**
6852 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
6853 * @tx_flags: combination of TX_CMD_FLG_*
6854 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
6855 * cleared. Combination of RATE_MCS_*
6856 * @sta_id: index of destination station in FW station table
6857 * @reserved: for alignment and future use
6858 */
6859 struct iwx_scan_req_tx_cmd {
6860 uint32_t tx_flags;
6861 uint32_t rate_n_flags;
6862 uint8_t sta_id;
6863 uint8_t reserved[3];
6864 } __packed;
6865
6866 #define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)
6867 #define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)
6868
6869 /**
6870 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
6871 * @flags: bits 1-20: directed scan to i'th ssid
6872 * other bits &enum iwx_scan_channel_flags_lmac
6873 * @channel_number: channel number 1-13 etc
6874 * @iter_count: scan iteration on this channel
6875 * @iter_interval: interval in seconds between iterations on one channel
6876 */
6877 struct iwx_scan_channel_cfg_lmac {
6878 uint32_t flags;
6879 uint16_t channel_num;
6880 uint16_t iter_count;
6881 uint32_t iter_interval;
6882 } __packed;
6883
6884 /*
6885 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
6886 * @offset: offset in the data block
6887 * @len: length of the segment
6888 */
6889 struct iwx_scan_probe_segment {
6890 uint16_t offset;
6891 uint16_t len;
6892 } __packed;
6893
6894 /* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
6895 * @mac_header: first (and common) part of the probe
6896 * @band_data: band specific data
6897 * @common_data: last (and common) part of the probe
6898 * @buf: raw data block
6899 */
6900 struct iwx_scan_probe_req_v1 {
6901 struct iwx_scan_probe_segment mac_header;
6902 struct iwx_scan_probe_segment band_data[2];
6903 struct iwx_scan_probe_segment common_data;
6904 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE];
6905 } __packed;
6906
6907 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2
6908 * @mac_header: first (and common) part of the probe
6909 * @band_data: band specific data
6910 * @common_data: last (and common) part of the probe
6911 * @buf: raw data block
6912 */
6913 struct iwx_scan_probe_req {
6914 struct iwx_scan_probe_segment mac_header;
6915 struct iwx_scan_probe_segment band_data[3];
6916 struct iwx_scan_probe_segment common_data;
6917 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE];
6918 } __packed;
6919
6920
6921 #define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0)
6922 #define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)
6923 #define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)
6924 #define IWX_SCAN_CHANNEL_FLAG_EBS_FRAG (1 << 3)
6925 #define IWX_SCAN_CHANNEL_FLAG_FORCE_EBS (1 << 4)
6926 #define IWX_SCAN_CHANNEL_FLAG_ENABLE_CHAN_ORDER (1 << 5)
6927 #define IWX_SCAN_CHANNEL_FLAG_6G_PSC_NO_FILTER (1 << 6)
6928
6929 /* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
6930 * @flags: enum iwx_scan_channel_flags
6931 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
6932 * involved.
6933 * 1 - EBS is disabled.
6934 * 2 - every second scan will be full scan(and so on).
6935 */
6936 struct iwx_scan_channel_opt {
6937 uint16_t flags;
6938 uint16_t non_ebs_ratio;
6939 } __packed;
6940
6941 #define IWX_SCAN_PRIORITY_LOW 0
6942 #define IWX_SCAN_PRIORITY_MEDIUM 1
6943 #define IWX_SCAN_PRIORITY_HIGH 2
6944
6945 enum iwx_scan_priority_ext {
6946 IWX_SCAN_PRIORITY_EXT_0_LOWEST,
6947 IWX_SCAN_PRIORITY_EXT_1,
6948 IWX_SCAN_PRIORITY_EXT_2,
6949 IWX_SCAN_PRIORITY_EXT_3,
6950 IWX_SCAN_PRIORITY_EXT_4,
6951 IWX_SCAN_PRIORITY_EXT_5,
6952 IWX_SCAN_PRIORITY_EXT_6,
6953 IWX_SCAN_PRIORITY_EXT_7_HIGHEST,
6954 };
6955
6956 /**
6957 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
6958 * @last_schedule_line: last schedule line executed (fast or regular)
6959 * @last_schedule_iteration: last scan iteration executed before scan abort
6960 * @status: enum iwx_scan_offload_complete_status
6961 * @ebs_status: EBS success status &enum iwx_scan_ebs_status
6962 * @time_after_last_iter; time in seconds elapsed after last iteration
6963 */
6964 struct iwx_periodic_scan_complete {
6965 uint8_t last_schedule_line;
6966 uint8_t last_schedule_iteration;
6967 uint8_t status;
6968 uint8_t ebs_status;
6969 uint32_t time_after_last_iter;
6970 uint32_t reserved;
6971 } __packed;
6972
6973 /**
6974 * struct iwx_scan_results_notif - scan results for one channel -
6975 * SCAN_RESULT_NTF_API_S_VER_3
6976 * @channel: which channel the results are from
6977 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
6978 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request
6979 * @num_probe_not_sent: # of request that weren't sent due to not enough time
6980 * @duration: duration spent in channel, in usecs
6981 */
6982 struct iwx_scan_results_notif {
6983 uint8_t channel;
6984 uint8_t band;
6985 uint8_t probe_status;
6986 uint8_t num_probe_not_sent;
6987 uint32_t duration;
6988 } __packed;
6989
6990 #define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0)
6991 #define IWX_SCAN_CLIENT_NETDETECT (1 << 1)
6992 #define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2)
6993
6994 /**
6995 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S
6996 * @ssid: MAC address to filter out
6997 * @reported_rssi: AP rssi reported to the host
6998 * @client_bitmap: clients ignore this entry - enum scan_framework_client
6999 */
7000 struct iwx_scan_offload_blacklist {
7001 uint8_t ssid[ETHER_ADDR_LEN];
7002 uint8_t reported_rssi;
7003 uint8_t client_bitmap;
7004 } __packed;
7005
7006 #define IWX_NETWORK_TYPE_BSS 1
7007 #define IWX_NETWORK_TYPE_IBSS 2
7008 #define IWX_NETWORK_TYPE_ANY 3
7009
7010 #define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4
7011 #define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8
7012 #define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc
7013
7014 /**
7015 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S
7016 * @ssid_index: index to ssid list in fixed part
7017 * @unicast_cipher: encryption algorithm to match - bitmap
7018 * @aut_alg: authentication algorithm to match - bitmap
7019 * @network_type: enum iwx_scan_offload_network_type
7020 * @band_selection: enum iwx_scan_offload_band_selection
7021 * @client_bitmap: clients waiting for match - enum scan_framework_client
7022 */
7023 struct iwx_scan_offload_profile {
7024 uint8_t ssid_index;
7025 uint8_t unicast_cipher;
7026 uint8_t auth_alg;
7027 uint8_t network_type;
7028 uint8_t band_selection;
7029 uint8_t client_bitmap;
7030 uint8_t reserved[2];
7031 } __packed;
7032
7033 /**
7034 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
7035 * @blacklist: AP list to filter off from scan results
7036 * @profiles: profiles to search for match
7037 * @blacklist_len: length of blacklist
7038 * @num_profiles: num of profiles in the list
7039 * @match_notify: clients waiting for match found notification
7040 * @pass_match: clients waiting for the results
7041 * @active_clients: active clients bitmap - enum scan_framework_client
7042 * @any_beacon_notify: clients waiting for match notification without match
7043 */
7044 struct iwx_scan_offload_profile_cfg {
7045 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES];
7046 uint8_t blacklist_len;
7047 uint8_t num_profiles;
7048 uint8_t match_notify;
7049 uint8_t pass_match;
7050 uint8_t active_clients;
7051 uint8_t any_beacon_notify;
7052 uint8_t reserved[2];
7053 } __packed;
7054
7055 #define IWX_SCAN_OFFLOAD_COMPLETED 1
7056 #define IWX_SCAN_OFFLOAD_ABORTED 2
7057
7058 /* UMAC Scan API */
7059
7060 #define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)
7061 #define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)
7062 #define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)
7063 #define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)
7064 #define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)
7065 #define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)
7066 #define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)
7067 #define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)
7068 #define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)
7069 #define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)
7070 #define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)
7071 #define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)
7072 #define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)
7073 #define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)
7074 #define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)
7075 #define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)
7076 #define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)
7077 #define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)
7078
7079 /* Bits 26-31 are for num of channels in channel_array */
7080 #define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
7081
7082 /* OFDM basic rates */
7083 #define IWX_SCAN_CONFIG_RATE_6M (1 << 0)
7084 #define IWX_SCAN_CONFIG_RATE_9M (1 << 1)
7085 #define IWX_SCAN_CONFIG_RATE_12M (1 << 2)
7086 #define IWX_SCAN_CONFIG_RATE_18M (1 << 3)
7087 #define IWX_SCAN_CONFIG_RATE_24M (1 << 4)
7088 #define IWX_SCAN_CONFIG_RATE_36M (1 << 5)
7089 #define IWX_SCAN_CONFIG_RATE_48M (1 << 6)
7090 #define IWX_SCAN_CONFIG_RATE_54M (1 << 7)
7091 /* CCK basic rates */
7092 #define IWX_SCAN_CONFIG_RATE_1M (1 << 8)
7093 #define IWX_SCAN_CONFIG_RATE_2M (1 << 9)
7094 #define IWX_SCAN_CONFIG_RATE_5M (1 << 10)
7095 #define IWX_SCAN_CONFIG_RATE_11M (1 << 11)
7096
7097 /* Bits 16-27 are for supported rates */
7098 #define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
7099
7100 #define IWX_CHANNEL_FLAG_EBS (1 << 0)
7101 #define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)
7102 #define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2)
7103 #define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)
7104
7105 /**
7106 * struct iwx_scan_dwell
7107 * @active: default dwell time for active scan
7108 * @passive: default dwell time for passive scan
7109 * @fragmented: default dwell time for fragmented scan
7110 * @extended: default dwell time for channels 1, 6 and 11
7111 */
7112 struct iwx_scan_dwell {
7113 uint8_t active;
7114 uint8_t passive;
7115 uint8_t fragmented;
7116 uint8_t extended;
7117 } __packed;
7118
7119
7120 #define IWX_SCAN_TWO_LMACS 2
7121 #define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */
7122 #define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */
7123
7124 /**
7125 * struct iwl_scan_config
7126 * @enable_cam_mode: whether to enable CAM mode.
7127 * @enable_promiscuous_mode: whether to enable promiscuous mode
7128 * @bcast_sta_id: the index of the station in the fw. Deprecated starting with
7129 * API version 5.
7130 * @reserved: reserved
7131 * @tx_chains: valid_tx antenna - ANT_* definitions
7132 * @rx_chains: valid_rx antenna - ANT_* definitions
7133 */
7134 struct iwx_scan_config {
7135 uint8_t enable_cam_mode;
7136 uint8_t enable_promiscuous_mode;
7137 uint8_t bcast_sta_id;
7138 uint8_t reserved;
7139 uint32_t tx_chains;
7140 uint32_t rx_chains;
7141 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_5 */
7142
7143 /**
7144 * struct iwx_scan_config_v2
7145 * @flags: enum scan_config_flags
7146 * @tx_chains: valid_tx antenna - ANT_* definitions
7147 * @rx_chains: valid_rx antenna - ANT_* definitions
7148 * @legacy_rates: default legacy rates - enum scan_config_rates
7149 * @out_of_channel_time: default max out of serving channel time
7150 * @suspend_time: default max suspend time
7151 * @dwell_active: default dwell time for active scan
7152 * @dwell_passive: default dwell time for passive scan
7153 * @dwell_fragmented: default dwell time for fragmented scan
7154 * @dwell_extended: default dwell time for channels 1, 6 and 11
7155 * @mac_addr: default mac address to be used in probes
7156 * @bcast_sta_id: the index of the station in the fw
7157 * @channel_flags: default channel flags - enum iwx_channel_flags
7158 * scan_config_channel_flag
7159 * @channel_array: default supported channels
7160 */
7161 struct iwx_scan_config_v2 {
7162 uint32_t flags;
7163 uint32_t tx_chains;
7164 uint32_t rx_chains;
7165 uint32_t legacy_rates;
7166 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS];
7167 uint32_t suspend_time[IWX_SCAN_TWO_LMACS];
7168 struct iwx_scan_dwell dwell;
7169 uint8_t mac_addr[ETHER_ADDR_LEN];
7170 uint8_t bcast_sta_id;
7171 uint8_t channel_flags;
7172 uint8_t channel_array[];
7173 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */
7174
7175 /**
7176 * iwx_umac_scan_flags
7177 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
7178 * can be preempted by other scan requests with higher priority.
7179 * The low priority scan will be resumed when the higher priority scan is
7180 * completed.
7181 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
7182 * when scan starts.
7183 */
7184 #define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)
7185 #define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)
7186
7187 #define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0
7188 #define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8
7189
7190 #define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)
7191 #define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)
7192 #define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)
7193 #define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)
7194 #define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)
7195 #define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)
7196 #define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)
7197 #define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)
7198 #define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)
7199 #define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)
7200 #define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)
7201 /* Extended dwell is obsolete when adaptive dwell is used, making this
7202 * bit reusable. Hence, probe request defer is used only when adaptive
7203 * dwell is supported. */
7204 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10)
7205 #define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11)
7206 #define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13)
7207 #define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14)
7208 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15)
7209
7210 /**
7211 * UMAC scan general flags #2
7212 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete
7213 * notification per channel or not.
7214 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel
7215 * reorder optimization or not.
7216 */
7217 #define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)
7218 #define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1)
7219
7220 /**
7221 * UMAC scan general flags version 2
7222 *
7223 * The FW flags were reordered and hence the driver introduce version 2
7224 *
7225 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled
7226 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons
7227 * during scan iterations
7228 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification
7229 * on every iteration instead of only once after the last iteration
7230 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1
7231 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2
7232 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching
7233 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX
7234 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell
7235 * for active channel
7236 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests
7237 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start
7238 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs
7239 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned
7240 * as passive
7241 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and
7242 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover
7243 * the reported collocated APs
7244 */
7245 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0)
7246 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1)
7247 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2)
7248 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3)
7249 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4)
7250 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5)
7251 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6)
7252 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7)
7253 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8)
7254 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9)
7255 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10)
7256 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11)
7257 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12)
7258
7259 /**
7260 * struct iwx_scan_channel_cfg_umac
7261 * @flags: bitmap - 0-19: directed scan to i'th ssid.
7262 * @channel_num: channel number 1-13 etc.
7263 * @iter_count: repetition count for the channel.
7264 * @iter_interval: interval between two scan iterations on one channel.
7265 */
7266 struct iwx_scan_channel_cfg_umac {
7267 uint32_t flags;
7268 union {
7269 struct {
7270 uint8_t channel_num;
7271 uint8_t iter_count;
7272 uint16_t iter_interval;
7273 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */
7274 struct {
7275 uint8_t channel_num;
7276 uint8_t band;
7277 uint8_t iter_count;
7278 uint8_t iter_interval;
7279 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */
7280 };
7281 } __packed;
7282
7283 /**
7284 * struct iwx_scan_umac_schedule
7285 * @interval: interval in seconds between scan iterations
7286 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
7287 * @reserved: for alignment and future use
7288 */
7289 struct iwx_scan_umac_schedule {
7290 uint16_t interval;
7291 uint8_t iter_count;
7292 uint8_t reserved;
7293 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
7294
7295 /**
7296 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command
7297 * parameters following channels configuration array.
7298 * @schedule: two scheduling plans.
7299 * @delay: delay in TUs before starting the first scan iteration
7300 * @reserved: for future use and alignment
7301 * @preq: probe request with IEs blocks
7302 * @direct_scan: list of SSIDs for directed active scan
7303 */
7304 struct iwx_scan_req_umac_tail_v1 {
7305 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
7306 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
7307 uint16_t delay;
7308 uint16_t reserved;
7309 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
7310 struct iwx_scan_probe_req_v1 preq;
7311 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
7312 } __packed;
7313
7314 /**
7315 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command
7316 * parameters following channels configuration array.
7317 * @schedule: two scheduling plans.
7318 * @delay: delay in TUs before starting the first scan iteration
7319 * @reserved: for future use and alignment
7320 * @preq: probe request with IEs blocks
7321 * @direct_scan: list of SSIDs for directed active scan
7322 */
7323 struct iwx_scan_req_umac_tail_v2 {
7324 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
7325 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
7326 uint16_t delay;
7327 uint16_t reserved;
7328 /* SCAN_PROBE_PARAMS_API_S_VER_2 */
7329 struct iwx_scan_probe_req preq;
7330 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
7331 } __packed;
7332
7333 /**
7334 * struct iwx_scan_umac_chan_param
7335 * @flags: channel flags &enum iwl_scan_channel_flags
7336 * @count: num of channels in scan request
7337 * @reserved: for future use and alignment
7338 */
7339 struct iwx_scan_umac_chan_param {
7340 uint8_t flags;
7341 uint8_t count;
7342 uint16_t reserved;
7343 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
7344
7345 #define IWX_SCAN_LB_LMAC_IDX 0
7346 #define IWX_SCAN_HB_LMAC_IDX 1
7347
7348 /**
7349 * struct iwx_scan_req_umac
7350 * @flags: &enum iwl_umac_scan_flags
7351 * @uid: scan id, &enum iwl_umac_scan_uid_offsets
7352 * @ooc_priority: out of channel priority - &enum iwl_scan_priority
7353 * @general_flags: &enum iwl_umac_scan_general_flags
7354 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
7355 * @extended_dwell: dwell time for channels 1, 6 and 11
7356 * @active_dwell: dwell time for active scan per LMAC
7357 * @passive_dwell: dwell time for passive scan per LMAC
7358 * @fragmented_dwell: dwell time for fragmented passive scan
7359 * @adwell_default_n_aps: for adaptive dwell the default number of APs
7360 * per channel
7361 * @adwell_default_n_aps_social: for adaptive dwell the default
7362 * number of APs per social (1,6,11) channel
7363 * @general_flags2: &enum iwl_umac_scan_general_flags2
7364 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added
7365 * to total scan time
7366 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
7367 * are 2 LMACs (high band and low band)
7368 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
7369 * @scan_priority: scan internal prioritization &enum iwl_scan_priority
7370 * @num_of_fragments: Number of fragments needed for full coverage per band.
7371 * Relevant only for fragmented scan.
7372 * @channel: &struct iwx_scan_umac_chan_param
7373 * @reserved: for future use and alignment
7374 * @reserved3: for future use and alignment
7375 * @data: &struct iwx_scan_channel_cfg_umac and
7376 * &struct iwx_scan_req_umac_tail
7377 */
7378 struct iwx_scan_req_umac {
7379 uint32_t flags;
7380 uint32_t uid;
7381 uint32_t ooc_priority;
7382 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
7383 uint16_t general_flags;
7384 uint8_t reserved;
7385 uint8_t scan_start_mac_id;
7386 union {
7387 struct {
7388 uint8_t extended_dwell;
7389 uint8_t active_dwell;
7390 uint8_t passive_dwell;
7391 uint8_t fragmented_dwell;
7392 uint32_t max_out_time;
7393 uint32_t suspend_time;
7394 uint32_t scan_priority;
7395 struct iwx_scan_umac_chan_param channel;
7396 uint8_t data[];
7397 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
7398 struct {
7399 uint8_t extended_dwell;
7400 uint8_t active_dwell;
7401 uint8_t passive_dwell;
7402 uint8_t fragmented_dwell;
7403 uint32_t max_out_time[2];
7404 uint32_t suspend_time[2];
7405 uint32_t scan_priority;
7406 struct iwx_scan_umac_chan_param channel;
7407 uint8_t data[];
7408 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */
7409 struct {
7410 uint8_t active_dwell;
7411 uint8_t passive_dwell;
7412 uint8_t fragmented_dwell;
7413 uint8_t adwell_default_n_aps;
7414 uint8_t adwell_default_n_aps_social;
7415 uint8_t reserved3;
7416 uint16_t adwell_max_budget;
7417 uint32_t max_out_time[2];
7418 uint32_t suspend_time[2];
7419 uint32_t scan_priority;
7420 struct iwx_scan_umac_chan_param channel;
7421 uint8_t data[];
7422 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */
7423 struct {
7424 uint8_t active_dwell[2];
7425 uint8_t reserved2;
7426 uint8_t adwell_default_n_aps;
7427 uint8_t adwell_default_n_aps_social;
7428 uint8_t general_flags2;
7429 uint16_t adwell_max_budget;
7430 uint32_t max_out_time[2];
7431 uint32_t suspend_time[2];
7432 uint32_t scan_priority;
7433 uint8_t passive_dwell[2];
7434 uint8_t num_of_fragments[2];
7435 struct iwx_scan_umac_chan_param channel;
7436 uint8_t data[];
7437 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */
7438 struct {
7439 uint8_t active_dwell[2];
7440 uint8_t adwell_default_hb_n_aps;
7441 uint8_t adwell_default_lb_n_aps;
7442 uint8_t adwell_default_n_aps_social;
7443 uint8_t general_flags2;
7444 uint16_t adwell_max_budget;
7445 uint32_t max_out_time[2];
7446 uint32_t suspend_time[2];
7447 uint32_t scan_priority;
7448 uint8_t passive_dwell[2];
7449 uint8_t num_of_fragments[2];
7450 struct iwx_scan_umac_chan_param channel;
7451 uint8_t data[];
7452 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */
7453 };
7454 } __packed;
7455
7456 #define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac)
7457 #define IWX_SCAN_REQ_UMAC_SIZE_V7 48
7458 #define IWX_SCAN_REQ_UMAC_SIZE_V6 44
7459 #define IWX_SCAN_REQ_UMAC_SIZE_V1 36
7460
7461 /**
7462 * struct iwx_scan_general_params_v10
7463 * @flags: &enum iwx_umac_scan_flags
7464 * @reserved: reserved for future
7465 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
7466 * @active_dwell: dwell time for active scan per LMAC
7467 * @adwell_default_2g: adaptive dwell default number of APs
7468 * for 2.4GHz channel
7469 * @adwell_default_5g: adaptive dwell default number of APs
7470 * for 5GHz channels
7471 * @adwell_default_social_chn: adaptive dwell default number of
7472 * APs per social channel
7473 * @reserved1: reserved for future
7474 * @adwell_max_budget: the maximal number of TUs that adaptive dwell
7475 * can add to the total scan time
7476 * @max_out_of_time: max out of serving channel time, per LMAC
7477 * @suspend_time: max suspend time, per LMAC
7478 * @scan_priority: priority of the request
7479 * @passive_dwell: continues dwell time for passive channel
7480 * (without adaptive dwell)
7481 * @num_of_fragments: number of fragments needed for full fragmented
7482 * scan coverage.
7483 */
7484 struct iwx_scan_general_params_v10 {
7485 uint16_t flags;
7486 uint8_t reserved;
7487 uint8_t scan_start_mac_id;
7488 uint8_t active_dwell[IWX_SCAN_TWO_LMACS];
7489 uint8_t adwell_default_2g;
7490 uint8_t adwell_default_5g;
7491 uint8_t adwell_default_social_chn;
7492 uint8_t reserved1;
7493 uint16_t adwell_max_budget;
7494 uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS];
7495 uint32_t suspend_time[IWX_SCAN_TWO_LMACS];
7496 uint32_t scan_priority;
7497 uint8_t passive_dwell[IWX_SCAN_TWO_LMACS];
7498 uint8_t num_of_fragments[IWX_SCAN_TWO_LMACS];
7499 } __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_10 */
7500
7501 /**
7502 * struct iwx_scan_channel_params_v6
7503 * @flags: channel flags &enum iwl_scan_channel_flags
7504 * @count: num of channels in scan request
7505 * @n_aps_override: override the number of APs the FW uses to calculate dwell
7506 * time when adaptive dwell is used.
7507 * Channel k will use n_aps_override[i] when BIT(20 + i) is set in
7508 * channel_config[k].flags
7509 * @channel_config: array of explicit channel configurations
7510 * for 2.4Ghz and 5.2Ghz bands
7511 */
7512 struct iwx_scan_channel_params_v6 {
7513 uint8_t flags;
7514 uint8_t count;
7515 uint8_t n_aps_override[2];
7516 struct iwx_scan_channel_cfg_umac channel_config[67];
7517 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_6 */
7518
7519 /**
7520 * struct iwx_scan_periodic_parms_v1
7521 * @schedule: can scheduling parameter
7522 * @delay: initial delay of the periodic scan in seconds
7523 * @reserved: reserved for future
7524 */
7525 struct iwx_scan_periodic_parms_v1 {
7526 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
7527 uint16_t delay;
7528 uint16_t reserved;
7529 } __packed; /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
7530
7531 #define IWX_SCAN_SHORT_SSID_MAX_SIZE 8
7532 #define IWX_SCAN_BSSID_MAX_SIZE 16
7533
7534 /**
7535 * struct iwx_scan_probe_params_v4
7536 * @preq: scan probe request params
7537 * @short_ssid_num: number of valid short SSIDs in short ssid array
7538 * @bssid_num: number of valid bssid in bssids array
7539 * @reserved: reserved
7540 * @direct_scan: list of ssids
7541 * @short_ssid: array of short ssids
7542 * @bssid_array: array of bssids
7543 */
7544 struct iwx_scan_probe_params_v4 {
7545 struct iwx_scan_probe_req preq;
7546 uint8_t short_ssid_num;
7547 uint8_t bssid_num;
7548 uint16_t reserved;
7549 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
7550 uint32_t short_ssid[IWX_SCAN_SHORT_SSID_MAX_SIZE];
7551 uint8_t bssid_array[IWX_SCAN_BSSID_MAX_SIZE][ETHER_ADDR_LEN];
7552 } __packed; /* SCAN_PROBE_PARAMS_API_S_VER_4 */
7553
7554 /**
7555 * struct iwx_scan_req_params_v14
7556 * @general_params: &struct iwx_scan_general_params_v10
7557 * @channel_params: &struct iwx_scan_channel_params_v6
7558 * @periodic_params: &struct iwx_scan_periodic_parms_v1
7559 * @probe_params: &struct iwx_scan_probe_params_v4
7560 */
7561 struct iwx_scan_req_params_v14 {
7562 struct iwx_scan_general_params_v10 general_params;
7563 struct iwx_scan_channel_params_v6 channel_params;
7564 struct iwx_scan_periodic_parms_v1 periodic_params;
7565 struct iwx_scan_probe_params_v4 probe_params;
7566 } __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_14 */
7567
7568 /**
7569 * struct iwx_scan_req_umac_v14
7570 * @uid: scan id, &enum iwl_umac_scan_uid_offsets
7571 * @ooc_priority: out of channel priority - &enum iwx_scan_priority
7572 * @scan_params: scan parameters
7573 */
7574 struct iwx_scan_req_umac_v14 {
7575 uint32_t uid;
7576 uint32_t ooc_priority;
7577 struct iwx_scan_req_params_v14 scan_params;
7578 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_14 */
7579
7580 /**
7581 * struct iwx_umac_scan_abort
7582 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7583 * @flags: reserved
7584 */
7585 struct iwx_umac_scan_abort {
7586 uint32_t uid;
7587 uint32_t flags;
7588 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
7589
7590 /**
7591 * struct iwx_umac_scan_complete
7592 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7593 * @last_schedule: last scheduling line
7594 * @last_iter: last scan iteration number
7595 * @scan status: &enum iwx_scan_offload_complete_status
7596 * @ebs_status: &enum iwx_scan_ebs_status
7597 * @time_from_last_iter: time elapsed from last iteration
7598 * @reserved: for future use
7599 */
7600 struct iwx_umac_scan_complete {
7601 uint32_t uid;
7602 uint8_t last_schedule;
7603 uint8_t last_iter;
7604 uint8_t status;
7605 uint8_t ebs_status;
7606 uint32_t time_from_last_iter;
7607 uint32_t reserved;
7608 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
7609
7610 #define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
7611 /**
7612 * struct iwx_scan_offload_profile_match - match information
7613 * @bssid: matched bssid
7614 * @channel: channel where the match occurred
7615 * @energy:
7616 * @matching_feature:
7617 * @matching_channels: bitmap of channels that matched, referencing
7618 * the channels passed in tue scan offload request
7619 */
7620 struct iwx_scan_offload_profile_match {
7621 uint8_t bssid[ETHER_ADDR_LEN];
7622 uint16_t reserved;
7623 uint8_t channel;
7624 uint8_t energy;
7625 uint8_t matching_feature;
7626 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
7627 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
7628
7629 /**
7630 * struct iwx_scan_offload_profiles_query - match results query response
7631 * @matched_profiles: bitmap of matched profiles, referencing the
7632 * matches passed in the scan offload request
7633 * @last_scan_age: age of the last offloaded scan
7634 * @n_scans_done: number of offloaded scans done
7635 * @gp2_d0u: GP2 when D0U occurred
7636 * @gp2_invoked: GP2 when scan offload was invoked
7637 * @resume_while_scanning: not used
7638 * @self_recovery: obsolete
7639 * @reserved: reserved
7640 * @matches: array of match information, one for each match
7641 */
7642 struct iwx_scan_offload_profiles_query {
7643 uint32_t matched_profiles;
7644 uint32_t last_scan_age;
7645 uint32_t n_scans_done;
7646 uint32_t gp2_d0u;
7647 uint32_t gp2_invoked;
7648 uint8_t resume_while_scanning;
7649 uint8_t self_recovery;
7650 uint16_t reserved;
7651 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES];
7652 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
7653
7654 /**
7655 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration
7656 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7657 * @scanned_channels: number of channels scanned and number of valid elements in
7658 * results array
7659 * @status: one of SCAN_COMP_STATUS_*
7660 * @bt_status: BT on/off status
7661 * @last_channel: last channel that was scanned
7662 * @tsf_low: TSF timer (lower half) in usecs
7663 * @tsf_high: TSF timer (higher half) in usecs
7664 * @results: array of scan results, only "scanned_channels" of them are valid
7665 */
7666 struct iwx_umac_scan_iter_complete_notif {
7667 uint32_t uid;
7668 uint8_t scanned_channels;
7669 uint8_t status;
7670 uint8_t bt_status;
7671 uint8_t last_channel;
7672 uint32_t tsf_low;
7673 uint32_t tsf_high;
7674 struct iwx_scan_results_notif results[];
7675 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
7676
7677 #define IWX_GSCAN_START_CMD 0x0
7678 #define IWX_GSCAN_STOP_CMD 0x1
7679 #define IWX_GSCAN_SET_HOTLIST_CMD 0x2
7680 #define IWX_GSCAN_RESET_HOTLIST_CMD 0x3
7681 #define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4
7682 #define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5
7683 #define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD
7684 #define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE
7685 #define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF
7686
7687 /* STA API */
7688
7689 /**
7690 * flags for the ADD_STA host command
7691 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL:
7692 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA:
7693 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled
7694 * @IWX_STA_FLG_PS: set if STA is in Power Save
7695 * @IWX_STA_FLG_INVALID: set if STA is invalid
7696 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled
7697 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
7698 * @IWX_STA_FLG_DRAIN_FLOW: drain flow
7699 * @IWX_STA_FLG_PAN: STA is for PAN interface
7700 * @IWX_STA_FLG_CLASS_AUTH:
7701 * @IWX_STA_FLG_CLASS_ASSOC:
7702 * @IWX_STA_FLG_CLASS_MIMO_PROT:
7703 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
7704 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
7705 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
7706 * initialised by driver and can be updated by fw upon reception of
7707 * action frames that can change the channel width. When cleared the fw
7708 * will send all the frames in 20MHz even when FAT channel is requested.
7709 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
7710 * driver and can be updated by fw upon reception of action frames.
7711 * @IWX_STA_FLG_MFP_EN: Management Frame Protection
7712 */
7713 #define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)
7714 #define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)
7715
7716 #define IWX_STA_FLG_DISABLE_TX (1 << 4)
7717
7718 #define IWX_STA_FLG_PS (1 << 8)
7719 #define IWX_STA_FLG_DRAIN_FLOW (1 << 12)
7720 #define IWX_STA_FLG_PAN (1 << 13)
7721 #define IWX_STA_FLG_CLASS_AUTH (1 << 14)
7722 #define IWX_STA_FLG_CLASS_ASSOC (1 << 15)
7723 #define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17)
7724
7725 #define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19
7726 #define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7727 #define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7728 #define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7729 #define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7730 #define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7731 #define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7732 #define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7733 #define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7734 #define IWX_STA_FLG_MAX_AGG_SIZE_2M (8 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7735 #define IWX_STA_FLG_MAX_AGG_SIZE_4M (9 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7736 #define IWX_STA_FLG_MAX_AGG_SIZE_MSK (0xf << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7737
7738 #define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23
7739 #define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7740 #define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7741 #define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7742 #define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7743 #define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7744
7745 #define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26)
7746 #define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26)
7747 #define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26)
7748 #define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26)
7749 #define IWX_STA_FLG_FAT_EN_MSK (3 << 26)
7750
7751 #define IWX_STA_FLG_MIMO_EN_SISO (0 << 28)
7752 #define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28)
7753 #define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28)
7754 #define IWX_STA_FLG_MIMO_EN_MSK (3 << 28)
7755
7756 /**
7757 * key flags for the ADD_STA host command
7758 * @IWX_STA_KEY_FLG_NO_ENC: no encryption
7759 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm
7760 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm
7761 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm
7762 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
7763 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm
7764 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
7765 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithm value
7766 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
7767 * station info array (1 - n 1X mode)
7768 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key
7769 * @IWX_STA_KEY_NOT_VALID: key is invalid
7770 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
7771 * @IWX_STA_KEY_MULTICAST: set for multicast key
7772 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection
7773 */
7774 #define IWX_STA_KEY_FLG_NO_ENC (0 << 0)
7775 #define IWX_STA_KEY_FLG_WEP (1 << 0)
7776 #define IWX_STA_KEY_FLG_CCM (2 << 0)
7777 #define IWX_STA_KEY_FLG_TKIP (3 << 0)
7778 #define IWX_STA_KEY_FLG_EXT (4 << 0)
7779 #define IWX_STA_KEY_FLG_CMAC (6 << 0)
7780 #define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)
7781 #define IWX_STA_KEY_FLG_EN_MSK (7 << 0)
7782 #define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)
7783 #define IWX_STA_KEY_FLG_KEYID_POS 8
7784 #define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS)
7785 #define IWX_STA_KEY_NOT_VALID (1 << 11)
7786 #define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12)
7787 #define IWX_STA_KEY_MULTICAST (1 << 14)
7788 #define IWX_STA_KEY_MFP (1 << 15)
7789
7790 /**
7791 * indicate to the fw what flag are being changed
7792 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
7793 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
7794 * @IWX_STA_MODIFY_TX_RATE: unused
7795 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
7796 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
7797 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
7798 * @IWX_STA_MODIFY_PROT_TH:
7799 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station
7800 */
7801 #define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0)
7802 #define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1)
7803 #define IWX_STA_MODIFY_TX_RATE (1 << 2)
7804 #define IWX_STA_MODIFY_ADD_BA_TID (1 << 3)
7805 #define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4)
7806 #define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)
7807 #define IWX_STA_MODIFY_PROT_TH (1 << 6)
7808 #define IWX_STA_MODIFY_QUEUES (1 << 7)
7809
7810 #define IWX_STA_MODE_MODIFY 1
7811
7812 /**
7813 * type of sleep of the station
7814 * @IWX_STA_SLEEP_STATE_AWAKE:
7815 * @IWX_STA_SLEEP_STATE_PS_POLL:
7816 * @IWX_STA_SLEEP_STATE_UAPSD:
7817 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on
7818 * (last) released frame
7819 */
7820 #define IWX_STA_SLEEP_STATE_AWAKE 0
7821 #define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0)
7822 #define IWX_STA_SLEEP_STATE_UAPSD (1 << 1)
7823 #define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2)
7824
7825 /* STA ID and color bits definitions */
7826 #define IWX_STA_ID_SEED (0x0f)
7827 #define IWX_STA_ID_POS (0)
7828 #define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS)
7829
7830 #define IWX_STA_COLOR_SEED (0x7)
7831 #define IWX_STA_COLOR_POS (4)
7832 #define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS)
7833
7834 #define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
7835 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS)
7836 #define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \
7837 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS)
7838
7839 #define IWX_STA_KEY_MAX_NUM (16)
7840 #define IWX_STA_KEY_IDX_INVALID (0xff)
7841 #define IWX_STA_KEY_MAX_DATA_KEY_NUM (4)
7842 #define IWX_MAX_GLOBAL_KEYS (4)
7843 #define IWX_STA_KEY_LEN_WEP40 (5)
7844 #define IWX_STA_KEY_LEN_WEP104 (13)
7845
7846 /**
7847 * struct iwx_keyinfo - key information
7848 * @key_flags: type %iwx_sta_key_flag
7849 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
7850 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
7851 * @key_offset: key offset in the fw's key table
7852 * @key: 16-byte unicast decryption key
7853 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
7854 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
7855 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
7856 */
7857 struct iwx_keyinfo {
7858 uint16_t key_flags;
7859 uint8_t tkip_rx_tsc_byte2;
7860 uint8_t reserved1;
7861 uint16_t tkip_rx_ttak[5];
7862 uint8_t key_offset;
7863 uint8_t reserved2;
7864 uint8_t key[16];
7865 uint64_t tx_secur_seq_cnt;
7866 uint64_t hw_tkip_mic_rx_key;
7867 uint64_t hw_tkip_mic_tx_key;
7868 } __packed;
7869
7870 #define IWX_ADD_STA_STATUS_MASK 0xFF
7871 #define IWX_ADD_STA_BAID_VALID_MASK 0x8000
7872 #define IWX_ADD_STA_BAID_MASK 0x7F00
7873 #define IWX_ADD_STA_BAID_SHIFT 8
7874
7875 /**
7876 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table.
7877 * ( REPLY_ADD_STA = 0x18 )
7878 * @add_modify: see &enum iwl_sta_mode
7879 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
7880 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
7881 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
7882 * @mac_id_n_color: the Mac context this station belongs to,
7883 * see &enum iwl_ctxt_id_and_color
7884 * @addr: station's MAC address
7885 * @reserved2: reserved
7886 * @sta_id: index of station in uCode's station table
7887 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
7888 * alone. 1 - modify, 0 - don't change.
7889 * @reserved3: reserved
7890 * @station_flags: look at &enum iwl_sta_flags
7891 * @station_flags_msk: what of %station_flags have changed,
7892 * also &enum iwl_sta_flags
7893 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
7894 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
7895 * add_immediate_ba_ssn.
7896 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
7897 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
7898 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
7899 * add_immediate_ba_tid.
7900 * @sleep_tx_count: number of packets to transmit to station even though it is
7901 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
7902 * keeps track of STA sleep state.
7903 * @station_type: type of this station. See &enum iwl_sta_type.
7904 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag.
7905 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
7906 * mac-addr.
7907 * @beamform_flags: beam forming controls
7908 * @tfd_queue_msk: tfd queues used by this station.
7909 * Obsolete for new TX API (9 and above).
7910 * @rx_ba_window: aggregation window size
7911 * @sp_length: the size of the SP in actual number of frames
7912 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver
7913 * enabled ACs.
7914 *
7915 * The device contains an internal table of per-station information, with info
7916 * on security keys, aggregation parameters, and Tx rates for initial Tx
7917 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD).
7918 *
7919 * ADD_STA sets up the table entry for one station, either creating a new
7920 * entry, or modifying a pre-existing one.
7921 */
7922 struct iwx_add_sta_cmd {
7923 uint8_t add_modify;
7924 uint8_t awake_acs;
7925 uint16_t tid_disable_tx;
7926 uint32_t mac_id_n_color;
7927 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
7928 uint16_t reserved2;
7929 uint8_t sta_id;
7930 uint8_t modify_mask;
7931 uint16_t reserved3;
7932 uint32_t station_flags;
7933 uint32_t station_flags_msk;
7934 uint8_t add_immediate_ba_tid;
7935 uint8_t remove_immediate_ba_tid;
7936 uint16_t add_immediate_ba_ssn;
7937 uint16_t sleep_tx_count;
7938 uint8_t sleep_state_flags;
7939 uint8_t station_type;
7940 uint16_t assoc_id;
7941 uint16_t beamform_flags;
7942 uint32_t tfd_queue_msk;
7943 uint16_t rx_ba_window;
7944 uint8_t sp_length;
7945 uint8_t uapsd_acs;
7946 } __packed; /* ADD_STA_CMD_API_S_VER_10 */
7947
7948 /**
7949 * FW station types
7950 * ( REPLY_ADD_STA = 0x18 )
7951 * @IWX_STA_LINK: Link station - normal RX and TX traffic.
7952 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons
7953 * and probe responses.
7954 * @IWX_STA_MULTICAST: multicast traffic,
7955 * @IWX_STA_TDLS_LINK: TDLS link station
7956 * @IWX_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on).
7957 */
7958 #define IWX_STA_LINK 0
7959 #define IWX_STA_GENERAL_PURPOSE 1
7960 #define IWX_STA_MULTICAST 2
7961 #define IWX_STA_TDLS_LINK 3
7962 #define IWX_STA_AUX_ACTIVITY 4
7963
7964 /**
7965 * struct iwx_add_sta_key_common - add/modify sta key common part
7966 * ( REPLY_ADD_STA_KEY = 0x17 )
7967 * @sta_id: index of station in uCode's station table
7968 * @key_offset: key offset in key storage
7969 * @key_flags: IWX_STA_KEY_FLG_*
7970 * @key: key material data
7971 * @rx_secur_seq_cnt: RX security sequence counter for the key
7972 */
7973 struct iwx_add_sta_key_common {
7974 uint8_t sta_id;
7975 uint8_t key_offset;
7976 uint16_t key_flags;
7977 uint8_t key[32];
7978 uint8_t rx_secur_seq_cnt[16];
7979 } __packed;
7980
7981 /**
7982 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key
7983 * @common: see &struct iwx_add_sta_key_common
7984 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
7985 * @reserved: reserved
7986 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
7987 */
7988 struct iwx_add_sta_key_cmd_v1 {
7989 struct iwx_add_sta_key_common common;
7990 uint8_t tkip_rx_tsc_byte2;
7991 uint8_t reserved;
7992 uint16_t tkip_rx_ttak[5];
7993 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */
7994
7995 /**
7996 * struct iwx_add_sta_key_cmd - add/modify sta key
7997 * @common: see &struct iwx_add_sta_key_common
7998 * @rx_mic_key: TKIP RX unicast or multicast key
7999 * @tx_mic_key: TKIP TX key
8000 * @transmit_seq_cnt: TSC, transmit packet number
8001 */
8002 struct iwx_add_sta_key_cmd {
8003 struct iwx_add_sta_key_common common;
8004 uint64_t rx_mic_key;
8005 uint64_t tx_mic_key;
8006 uint64_t transmit_seq_cnt;
8007 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */
8008
8009 /**
8010 * status in the response to ADD_STA command
8011 * @IWX_ADD_STA_SUCCESS: operation was executed successfully
8012 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
8013 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
8014 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
8015 * that doesn't exist.
8016 */
8017 #define IWX_ADD_STA_SUCCESS 0x1
8018 #define IWX_ADD_STA_STATIONS_OVERLOAD 0x2
8019 #define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4
8020 #define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8
8021
8022 /**
8023 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table
8024 * ( IWX_REMOVE_STA = 0x19 )
8025 * @sta_id: the station id of the station to be removed
8026 */
8027 struct iwx_rm_sta_cmd {
8028 uint8_t sta_id;
8029 uint8_t reserved[3];
8030 } __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */
8031
8032 /**
8033 * struct iwx_mgmt_mcast_key_cmd
8034 * ( IWX_MGMT_MCAST_KEY = 0x1f )
8035 * @ctrl_flags: %iwx_sta_key_flag
8036 * @IGTK:
8037 * @K1: IGTK master key
8038 * @K2: IGTK sub key
8039 * @sta_id: station ID that support IGTK
8040 * @key_id:
8041 * @receive_seq_cnt: initial RSC/PN needed for replay check
8042 */
8043 struct iwx_mgmt_mcast_key_cmd {
8044 uint32_t ctrl_flags;
8045 uint8_t IGTK[16];
8046 uint8_t K1[16];
8047 uint8_t K2[16];
8048 uint32_t key_id;
8049 uint32_t sta_id;
8050 uint64_t receive_seq_cnt;
8051 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
8052
8053 struct iwx_wep_key {
8054 uint8_t key_index;
8055 uint8_t key_offset;
8056 uint16_t reserved1;
8057 uint8_t key_size;
8058 uint8_t reserved2[3];
8059 uint8_t key[16];
8060 } __packed;
8061
8062 struct iwx_wep_key_cmd {
8063 uint32_t mac_id_n_color;
8064 uint8_t num_keys;
8065 uint8_t decryption_type;
8066 uint8_t flags;
8067 uint8_t reserved;
8068 struct iwx_wep_key wep_key[0];
8069 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
8070
8071 /*
8072 * BT coex
8073 */
8074
8075 #define IWX_BT_COEX_DISABLE 0x0
8076 #define IWX_BT_COEX_NW 0x1
8077 #define IWX_BT_COEX_BT 0x2
8078 #define IWX_BT_COEX_WIFI 0x3
8079 /* BT_COEX_MODES_E */
8080
8081 #define IWX_BT_COEX_MPLUT_ENABLED (1 << 0)
8082 #define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)
8083 #define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2)
8084 #define IWX_BT_COEX_CORUN_ENABLED (1 << 3)
8085 #define IWX_BT_COEX_HIGH_BAND_RET (1 << 4)
8086 /* BT_COEX_MODULES_ENABLE_E_VER_1 */
8087
8088 /**
8089 * struct iwx_bt_coex_cmd - bt coex configuration command
8090 * @mode: enum %iwx_bt_coex_mode
8091 * @enabled_modules: enum %iwx_bt_coex_enabled_modules
8092 *
8093 * The structure is used for the BT_COEX command.
8094 */
8095 struct iwx_bt_coex_cmd {
8096 uint32_t mode;
8097 uint32_t enabled_modules;
8098 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
8099
8100
8101 /*
8102 * Location Aware Regulatory (LAR) API - MCC updates
8103 */
8104
8105 /**
8106 * struct iwx_mcc_update_cmd - Request the device to update geographic
8107 * regulatory profile according to the given MCC (Mobile Country Code).
8108 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
8109 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
8110 * MCC in the cmd response will be the relevant MCC in the NVM.
8111 * @mcc: given mobile country code
8112 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_*
8113 * @reserved: reserved for alignment
8114 * @key: integrity key for MCC API OEM testing
8115 * @reserved2: reserved
8116 */
8117 struct iwx_mcc_update_cmd {
8118 uint16_t mcc;
8119 uint8_t source_id;
8120 uint8_t reserved;
8121 uint32_t key;
8122 uint32_t reserved2[5];
8123 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
8124
8125 /**
8126 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD.
8127 * Contains the new channel control profile map, if changed, and the new MCC
8128 * (mobile country code).
8129 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
8130 * @status: see &enum iwx_mcc_update_status
8131 * @mcc: the new applied MCC
8132 * @cap: capabilities for all channels which matches the MCC
8133 * @source_id: the MCC source, see IWX_MCC_SOURCE_*
8134 * @time: time elapsed from the MCC test start (in 30 seconds TU)
8135 * @reserved: reserved.
8136 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
8137 * channels, depending on platform)
8138 * @channels: channel control data map, DWORD for each channel. Only the first
8139 * 16bits are used.
8140 */
8141 struct iwx_mcc_update_resp_v3 {
8142 uint32_t status;
8143 uint16_t mcc;
8144 uint8_t cap;
8145 uint8_t source_id;
8146 uint16_t time;
8147 uint16_t geo_info;
8148 uint32_t n_channels;
8149 uint32_t channels[0];
8150 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */
8151
8152 /**
8153 * geographic information.
8154 * @GEO_NO_INFO: no special info for this geo profile.
8155 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params
8156 * for the 5 GHz band.
8157 */
8158 #define IWX_GEO_NO_INFO 0
8159 #define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)
8160
8161 /**
8162 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD.
8163 * Contains the new channel control profile map, if changed, and the new MCC
8164 * (mobile country code).
8165 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
8166 * @status: see &enum iwl_mcc_update_status
8167 * @mcc: the new applied MCC
8168 * @cap: capabilities for all channels which matches the MCC
8169 * @time: time elapsed from the MCC test start (in units of 30 seconds)
8170 * @geo_info: geographic specific profile information
8171 * see IWX_GEO_*
8172 * @source_id: the MCC source, see IWX_MCC_SOURCE_*
8173 * @reserved: for four bytes alignment.
8174 * @n_channels: number of channels in @channels_data.
8175 * @channels: channel control data map, DWORD for each channel. Only the first
8176 * 16bits are used.
8177 */
8178 struct iwx_mcc_update_resp {
8179 uint32_t status;
8180 uint16_t mcc;
8181 uint16_t cap;
8182 uint16_t time;
8183 uint16_t geo_info;
8184 uint8_t source_id;
8185 uint8_t reserved[3];
8186 uint32_t n_channels;
8187 uint32_t channels[0];
8188 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */
8189
8190 /**
8191 * struct iwx_mcc_chub_notif - chub notifies of mcc change
8192 * (MCC_CHUB_UPDATE_CMD = 0xc9)
8193 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
8194 * the cellular and connectivity cores that gets updates of the mcc, and
8195 * notifies the ucode directly of any mcc change.
8196 * The ucode requests the driver to request the device to update geographic
8197 * regulatory profile according to the given MCC (Mobile Country Code).
8198 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
8199 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
8200 * MCC in the cmd response will be the relevant MCC in the NVM.
8201 * @mcc: given mobile country code
8202 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_*
8203 * @reserved1: reserved for alignment
8204 */
8205 struct iwx_mcc_chub_notif {
8206 uint16_t mcc;
8207 uint8_t source_id;
8208 uint8_t reserved1;
8209 } __packed; /* LAR_MCC_NOTIFY_S */
8210
8211 enum iwx_mcc_update_status {
8212 IWX_MCC_RESP_NEW_CHAN_PROFILE,
8213 IWX_MCC_RESP_SAME_CHAN_PROFILE,
8214 IWX_MCC_RESP_INVALID,
8215 IWX_MCC_RESP_NVM_DISABLED,
8216 IWX_MCC_RESP_ILLEGAL,
8217 IWX_MCC_RESP_LOW_PRIORITY,
8218 IWX_MCC_RESP_TEST_MODE_ACTIVE,
8219 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE,
8220 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
8221 };
8222
8223 #define IWX_MCC_SOURCE_OLD_FW 0
8224 #define IWX_MCC_SOURCE_ME 1
8225 #define IWX_MCC_SOURCE_BIOS 2
8226 #define IWX_MCC_SOURCE_3G_LTE_HOST 3
8227 #define IWX_MCC_SOURCE_3G_LTE_DEVICE 4
8228 #define IWX_MCC_SOURCE_WIFI 5
8229 #define IWX_MCC_SOURCE_RESERVED 6
8230 #define IWX_MCC_SOURCE_DEFAULT 7
8231 #define IWX_MCC_SOURCE_UNINITIALIZED 8
8232 #define IWX_MCC_SOURCE_MCC_API 9
8233 #define IWX_MCC_SOURCE_GET_CURRENT 0x10
8234 #define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11
8235
8236 /*
8237 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
8238 * As the firmware is slowly running out of command IDs and grouping of
8239 * commands is desirable anyway, the firmware is extending the command
8240 * header from 4 bytes to 8 bytes to introduce a group (in place of the
8241 * former flags field, since that's always 0 on commands and thus can
8242 * be easily used to distinguish between the two).
8243 *
8244 * These functions retrieve specific information from the id field in
8245 * the iwx_host_cmd struct which contains the command id, the group id,
8246 * and the version of the command.
8247 */
8248 static inline uint8_t
iwx_cmd_opcode(uint32_t cmdid)8249 iwx_cmd_opcode(uint32_t cmdid)
8250 {
8251 return cmdid & 0xff;
8252 }
8253
8254 static inline uint8_t
iwx_cmd_groupid(uint32_t cmdid)8255 iwx_cmd_groupid(uint32_t cmdid)
8256 {
8257 return ((cmdid & 0Xff00) >> 8);
8258 }
8259
8260 static inline uint8_t
iwx_cmd_version(uint32_t cmdid)8261 iwx_cmd_version(uint32_t cmdid)
8262 {
8263 return ((cmdid & 0xff0000) >> 16);
8264 }
8265
8266 static inline uint32_t
iwx_cmd_id(uint8_t opcode,uint8_t groupid,uint8_t version)8267 iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
8268 {
8269 return opcode + (groupid << 8) + (version << 16);
8270 }
8271
8272 /* make uint16_t wide id out of uint8_t group and opcode */
8273 #define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
8274
8275 struct iwx_cmd_header {
8276 uint8_t code;
8277 uint8_t flags;
8278 uint8_t idx;
8279 uint8_t qid;
8280 } __packed;
8281
8282 struct iwx_cmd_header_wide {
8283 uint8_t opcode;
8284 uint8_t group_id;
8285 uint8_t idx;
8286 uint8_t qid;
8287 uint16_t length;
8288 uint8_t reserved;
8289 uint8_t version;
8290 } __packed;
8291
8292 #define IWX_POWER_SCHEME_CAM 1
8293 #define IWX_POWER_SCHEME_BPS 2
8294 #define IWX_POWER_SCHEME_LP 3
8295
8296 #define IWX_DEF_CMD_PAYLOAD_SIZE 320
8297 #define IWX_MAX_CMD_PAYLOAD_SIZE (4096 - sizeof(struct iwx_cmd_header_wide))
8298 #define IWX_CMD_FAILED_MSK 0x40
8299
8300 /**
8301 * struct iwx_device_cmd
8302 *
8303 * For allocation of the command and tx queues, this establishes the overall
8304 * size of the largest command we send to uCode, except for commands that
8305 * aren't fully copied and use other TFD space.
8306 */
8307 struct iwx_device_cmd {
8308 union {
8309 struct {
8310 struct iwx_cmd_header hdr;
8311 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE];
8312 };
8313 struct {
8314 struct iwx_cmd_header_wide hdr_wide;
8315 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE -
8316 sizeof(struct iwx_cmd_header_wide) +
8317 sizeof(struct iwx_cmd_header)];
8318 };
8319 };
8320 } __packed;
8321
8322 struct iwx_rx_packet {
8323 /*
8324 * The first 4 bytes of the RX frame header contain both the RX frame
8325 * size and some flags.
8326 * Bit fields:
8327 * 31: flag flush RB request
8328 * 30: flag ignore TC (terminal counter) request
8329 * 29: flag fast IRQ request
8330 * 28-26: Reserved
8331 * 25: Offload enabled
8332 * 24: RPF enabled
8333 * 23: RSS enabled
8334 * 22: Checksum enabled
8335 * 21-16: RX queue
8336 * 15-14: Reserved
8337 * 13-00: RX frame size
8338 */
8339 uint32_t len_n_flags;
8340 struct iwx_cmd_header hdr;
8341 uint8_t data[];
8342 } __packed;
8343
8344 #define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
8345 #define IWX_FH_RSCSR_FRAME_INVALID 0x55550000
8346 #define IWX_FH_RSCSR_FRAME_ALIGN 0x40
8347 #define IWX_FH_RSCSR_RPA_EN (1 << 25)
8348 #define IWX_FH_RSCSR_RADA_EN (1 << 26)
8349 #define IWX_FH_RSCSR_RXQ_POS 16
8350 #define IWX_FH_RSCSR_RXQ_MASK 0x3F0000
8351
8352 static uint32_t
iwx_rx_packet_len(const struct iwx_rx_packet * pkt)8353 iwx_rx_packet_len(const struct iwx_rx_packet *pkt)
8354 {
8355
8356 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK;
8357 }
8358
8359 static uint32_t
iwx_rx_packet_payload_len(const struct iwx_rx_packet * pkt)8360 iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt)
8361 {
8362
8363 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr);
8364 }
8365
8366
8367 #define IWX_MIN_DBM -100
8368 #define IWX_MAX_DBM -33 /* realistic guess */
8369
8370 #define IWX_READ(sc, reg) \
8371 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
8372
8373 #define IWX_WRITE(sc, reg, val) \
8374 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
8375
8376 #define IWX_WRITE_1(sc, reg, val) \
8377 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
8378
8379 #define IWX_SETBITS(sc, reg, mask) \
8380 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask))
8381
8382 #define IWX_CLRBITS(sc, reg, mask) \
8383 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask))
8384
8385 #define IWX_BARRIER_WRITE(sc) \
8386 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
8387 BUS_SPACE_BARRIER_WRITE)
8388
8389 #define IWX_BARRIER_READ_WRITE(sc) \
8390 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
8391 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
8392