xref: /openbsd/sys/dev/pci/ixgbe_type.h (revision 42152828)
1 /*	$OpenBSD: ixgbe_type.h,v 1.40 2024/10/27 04:44:41 yasuoka Exp $	*/
2 
3 /******************************************************************************
4   SPDX-License-Identifier: BSD-3-Clause
5 
6   Copyright (c) 2001-2017, Intel Corporation
7   All rights reserved.
8 
9   Redistribution and use in source and binary forms, with or without
10   modification, are permitted provided that the following conditions are met:
11 
12    1. Redistributions of source code must retain the above copyright notice,
13       this list of conditions and the following disclaimer.
14 
15    2. Redistributions in binary form must reproduce the above copyright
16       notice, this list of conditions and the following disclaimer in the
17       documentation and/or other materials provided with the distribution.
18 
19    3. Neither the name of the Intel Corporation nor the names of its
20       contributors may be used to endorse or promote products derived from
21       this software without specific prior written permission.
22 
23   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33   POSSIBILITY OF SUCH DAMAGE.
34 
35 ******************************************************************************/
36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 331224 2018-03-19 20:55:05Z erj $*/
37 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 326022 2017-11-20 19:36:21Z pfg $*/
38 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_mbx.h 326022 2017-11-20 19:36:21Z pfg $*/
39 
40 #ifndef _IXGBE_TYPE_H_
41 #define _IXGBE_TYPE_H_
42 
43 /*
44  * The following is a brief description of the error categories used by the
45  * ERROR_REPORT* macros.
46  *
47  * - IXGBE_ERROR_INVALID_STATE
48  * This category is for errors which represent a serious failure state that is
49  * unexpected, and could be potentially harmful to device operation. It should
50  * not be used for errors relating to issues that can be worked around or
51  * ignored.
52  *
53  * - IXGBE_ERROR_POLLING
54  * This category is for errors related to polling/timeout issues and should be
55  * used in any case where the timeout occurred, or a failure to obtain a lock, or
56  * failure to receive data within the time limit.
57  *
58  * - IXGBE_ERROR_CAUTION
59  * This category should be used for reporting issues that may be the cause of
60  * other errors, such as temperature warnings. It should indicate an event which
61  * could be serious, but hasn't necessarily caused problems yet.
62  *
63  * - IXGBE_ERROR_SOFTWARE
64  * This category is intended for errors due to software state preventing
65  * something. The category is not intended for errors due to bad arguments, or
66  * due to unsupported features. It should be used when a state occurs which
67  * prevents action but is not a serious issue.
68  *
69  * - IXGBE_ERROR_ARGUMENT
70  * This category is for when a bad or invalid argument is passed. It should be
71  * used whenever a function is called and error checking has detected the
72  * argument is wrong or incorrect.
73  *
74  * - IXGBE_ERROR_UNSUPPORTED
75  * This category is for errors which are due to unsupported circumstances or
76  * configuration issues. It should not be used when the issue is due to an
77  * invalid argument, but for when something has occurred that is unsupported
78  * (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
79  */
80 
81 /* Vendor ID */
82 #define IXGBE_INTEL_VENDOR_ID			0x8086
83 
84 /* Device IDs */
85 #define IXGBE_DEV_ID_82598			0x10B6
86 #define IXGBE_DEV_ID_82598_BX			0x1508
87 #define IXGBE_DEV_ID_82598AF_DUAL_PORT		0x10C6
88 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT	0x10C7
89 #define IXGBE_DEV_ID_82598AT			0x10C8
90 #define IXGBE_DEV_ID_82598AT2			0x150B
91 #define IXGBE_DEV_ID_82598AT_DUAL_PORT		0x10D7
92 #define IXGBE_DEV_ID_82598EB_SFP_LOM		0x10DB
93 #define IXGBE_DEV_ID_82598EB_CX4		0x10DD
94 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT	0x10EC
95 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT		0x10F1
96 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM	0x10E1
97 #define IXGBE_DEV_ID_82598EB_XF_LR		0x10F4
98 #define IXGBE_DEV_ID_82599_KX4			0x10F7
99 #define IXGBE_DEV_ID_82599_KX4_MEZZ		0x1514
100 #define IXGBE_DEV_ID_82599_KR			0x1517
101 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE	0x10F8
102 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ	0x000C
103 #define IXGBE_DEV_ID_82599_CX4			0x10F9
104 #define IXGBE_DEV_ID_82599_SFP			0x10FB
105 #define IXGBE_SUBDEV_ID_82599_SFP		0x11A9
106 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0		0x1071
107 #define IXGBE_SUBDEV_ID_82599_RNDC		0x1F72
108 #define IXGBE_SUBDEV_ID_82599_560FLR		0x17D0
109 #define IXGBE_SUBDEV_ID_82599_ECNA_DP		0x0470
110 #define IXGBE_SUBDEV_ID_82599_SP_560FLR		0x211B
111 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6		0x2159
112 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP		0x000D
113 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP		0x0008
114 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1	0x8976
115 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2	0x06EE
116 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE	0x152A
117 #define IXGBE_DEV_ID_82599_SFP_FCOE		0x1529
118 #define IXGBE_DEV_ID_82599_SFP_EM		0x1507
119 #define IXGBE_DEV_ID_82599_SFP_SF2		0x154D
120 #define IXGBE_DEV_ID_82599_SFP_SF_QP		0x154A
121 #define IXGBE_DEV_ID_82599_QSFP_SF_QP		0x1558
122 #define IXGBE_DEV_ID_82599EN_SFP		0x1557
123 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1	0x0001
124 #define IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
125 #define IXGBE_DEV_ID_82599_T3_LOM		0x151C
126 #define IXGBE_DEV_ID_82599_VF			0x10ED
127 #define IXGBE_DEV_ID_82599_VF_HV		0x152E
128 #define IXGBE_DEV_ID_82599_BYPASS		0x155D
129 #define IXGBE_DEV_ID_X540T			0x1528
130 #define IXGBE_DEV_ID_X540_VF			0x1515
131 #define IXGBE_DEV_ID_X540_VF_HV			0x1530
132 #define IXGBE_DEV_ID_X540_BYPASS		0x155C
133 #define IXGBE_DEV_ID_X540T1			0x1560
134 #define IXGBE_DEV_ID_X550T			0x1563
135 #define IXGBE_DEV_ID_X550T1			0x15D1
136 #define IXGBE_DEV_ID_X550EM_A_KR		0x15C2
137 #define IXGBE_DEV_ID_X550EM_A_KR_L		0x15C3
138 #define IXGBE_DEV_ID_X550EM_A_SFP_N		0x15C4
139 #define IXGBE_DEV_ID_X550EM_A_SGMII		0x15C6
140 #define IXGBE_DEV_ID_X550EM_A_SGMII_L		0x15C7
141 #define IXGBE_DEV_ID_X550EM_A_10G_T		0x15C8
142 #define IXGBE_DEV_ID_X550EM_A_QSFP		0x15CA
143 #define IXGBE_DEV_ID_X550EM_A_QSFP_N		0x15CC
144 #define IXGBE_DEV_ID_X550EM_A_SFP		0x15CE
145 #define IXGBE_DEV_ID_X550EM_A_1G_T		0x15E4
146 #define IXGBE_DEV_ID_X550EM_A_1G_T_L		0x15E5
147 #define IXGBE_DEV_ID_X550EM_X_KX4		0x15AA
148 #define IXGBE_DEV_ID_X550EM_X_KR		0x15AB
149 #define IXGBE_DEV_ID_X550EM_X_SFP		0x15AC
150 #define IXGBE_DEV_ID_X550EM_X_10G_T		0x15AD
151 #define IXGBE_DEV_ID_X550EM_X_1G_T		0x15AE
152 #define IXGBE_DEV_ID_X550EM_X_XFI		0x15B0
153 #define IXGBE_DEV_ID_X550_VF_HV			0x1564
154 #define IXGBE_DEV_ID_X550_VF			0x1565
155 #define IXGBE_DEV_ID_X550EM_A_VF		0x15C5
156 #define IXGBE_DEV_ID_X550EM_A_VF_HV		0x15B4
157 #define IXGBE_DEV_ID_X550EM_X_VF		0x15A8
158 #define IXGBE_DEV_ID_X550EM_X_VF_HV		0x15A9
159 
160 #define IXGBE_CAT(r,m) IXGBE_##r##m
161 
162 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
163 
164 /* General Registers */
165 #define IXGBE_CTRL		0x00000
166 #define IXGBE_STATUS		0x00008
167 #define IXGBE_CTRL_EXT		0x00018
168 #define IXGBE_ESDP		0x00020
169 #define IXGBE_EODSDP		0x00028
170 #define IXGBE_I2CCTL_82599	0x00028
171 #define IXGBE_I2CCTL		IXGBE_I2CCTL_82599
172 #define IXGBE_I2CCTL_X540	IXGBE_I2CCTL_82599
173 #define IXGBE_I2CCTL_X550	0x15F5C
174 #define IXGBE_I2CCTL_X550EM_x	IXGBE_I2CCTL_X550
175 #define IXGBE_I2CCTL_X550EM_a	IXGBE_I2CCTL_X550
176 #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
177 #define IXGBE_PHY_GPIO		0x00028
178 #define IXGBE_MAC_GPIO		0x00030
179 #define IXGBE_PHYINT_STATUS0	0x00100
180 #define IXGBE_PHYINT_STATUS1	0x00104
181 #define IXGBE_PHYINT_STATUS2	0x00108
182 #define IXGBE_LEDCTL		0x00200
183 #define IXGBE_FRTIMER		0x00048
184 #define IXGBE_TCPTIMER		0x0004C
185 #define IXGBE_CORESPARE		0x00600
186 #define IXGBE_EXVET		0x05078
187 
188 /* NVM Registers */
189 #define IXGBE_EEC		0x10010
190 #define IXGBE_EEC_X540		IXGBE_EEC
191 #define IXGBE_EEC_X550		IXGBE_EEC
192 #define IXGBE_EEC_X550EM_x	IXGBE_EEC
193 #define IXGBE_EEC_X550EM_a	0x15FF8
194 #define IXGBE_EEC_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), EEC)
195 
196 #define IXGBE_EERD		0x10014
197 #define IXGBE_EEWR		0x10018
198 
199 #define IXGBE_FLA		0x1001C
200 #define IXGBE_FLA_X540		IXGBE_FLA
201 #define IXGBE_FLA_X550		IXGBE_FLA
202 #define IXGBE_FLA_X550EM_x	IXGBE_FLA
203 #define IXGBE_FLA_X550EM_a	0x15F68
204 #define IXGBE_FLA_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), FLA)
205 
206 #define IXGBE_EEMNGCTL	0x10110
207 #define IXGBE_EEMNGDATA	0x10114
208 #define IXGBE_FLMNGCTL	0x10118
209 #define IXGBE_FLMNGDATA	0x1011C
210 #define IXGBE_FLMNGCNT	0x10120
211 #define IXGBE_FLOP	0x1013C
212 
213 #define IXGBE_GRC		0x10200
214 #define IXGBE_GRC_X540		IXGBE_GRC
215 #define IXGBE_GRC_X550		IXGBE_GRC
216 #define IXGBE_GRC_X550EM_x	IXGBE_GRC
217 #define IXGBE_GRC_X550EM_a	0x15F64
218 #define IXGBE_GRC_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), GRC)
219 
220 #define IXGBE_SRAMREL		0x10210
221 #define IXGBE_SRAMREL_X540	IXGBE_SRAMREL
222 #define IXGBE_SRAMREL_X550	IXGBE_SRAMREL
223 #define IXGBE_SRAMREL_X550EM_x	IXGBE_SRAMREL
224 #define IXGBE_SRAMREL_X550EM_a	0x15F6C
225 #define IXGBE_SRAMREL_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SRAMREL)
226 
227 #define IXGBE_PHYDBG	0x10218
228 
229 /* General Receive Control */
230 #define IXGBE_GRC_MNG	0x00000001 /* Manageability Enable */
231 #define IXGBE_GRC_APME	0x00000002 /* APM enabled in EEPROM */
232 
233 #define IXGBE_VPDDIAG0	0x10204
234 #define IXGBE_VPDDIAG1	0x10208
235 
236 /* I2CCTL Bit Masks */
237 #define IXGBE_I2C_CLK_IN		0x00000001
238 #define IXGBE_I2C_CLK_IN_X540		IXGBE_I2C_CLK_IN
239 #define IXGBE_I2C_CLK_IN_X550		0x00004000
240 #define IXGBE_I2C_CLK_IN_X550EM_x	IXGBE_I2C_CLK_IN_X550
241 #define IXGBE_I2C_CLK_IN_X550EM_a	IXGBE_I2C_CLK_IN_X550
242 #define IXGBE_I2C_CLK_IN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), I2C_CLK_IN)
243 
244 #define IXGBE_I2C_CLK_OUT		0x00000002
245 #define IXGBE_I2C_CLK_OUT_X540		IXGBE_I2C_CLK_OUT
246 #define IXGBE_I2C_CLK_OUT_X550		0x00000200
247 #define IXGBE_I2C_CLK_OUT_X550EM_x	IXGBE_I2C_CLK_OUT_X550
248 #define IXGBE_I2C_CLK_OUT_X550EM_a	IXGBE_I2C_CLK_OUT_X550
249 #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
250 
251 #define IXGBE_I2C_DATA_IN		0x00000004
252 #define IXGBE_I2C_DATA_IN_X540		IXGBE_I2C_DATA_IN
253 #define IXGBE_I2C_DATA_IN_X550		0x00001000
254 #define IXGBE_I2C_DATA_IN_X550EM_x	IXGBE_I2C_DATA_IN_X550
255 #define IXGBE_I2C_DATA_IN_X550EM_a	IXGBE_I2C_DATA_IN_X550
256 #define IXGBE_I2C_DATA_IN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), I2C_DATA_IN)
257 
258 #define IXGBE_I2C_DATA_OUT		0x00000008
259 #define IXGBE_I2C_DATA_OUT_X540		IXGBE_I2C_DATA_OUT
260 #define IXGBE_I2C_DATA_OUT_X550		0x00000400
261 #define IXGBE_I2C_DATA_OUT_X550EM_x	IXGBE_I2C_DATA_OUT_X550
262 #define IXGBE_I2C_DATA_OUT_X550EM_a	IXGBE_I2C_DATA_OUT_X550
263 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
264 
265 #define IXGBE_I2C_DATA_OE_N_EN		0
266 #define IXGBE_I2C_DATA_OE_N_EN_X540	IXGBE_I2C_DATA_OE_N_EN
267 #define IXGBE_I2C_DATA_OE_N_EN_X550	0x00000800
268 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x	IXGBE_I2C_DATA_OE_N_EN_X550
269 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a	IXGBE_I2C_DATA_OE_N_EN_X550
270 #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
271 
272 #define IXGBE_I2C_BB_EN			0
273 #define IXGBE_I2C_BB_EN_X540		IXGBE_I2C_BB_EN
274 #define IXGBE_I2C_BB_EN_X550		0x00000100
275 #define IXGBE_I2C_BB_EN_X550EM_x	IXGBE_I2C_BB_EN_X550
276 #define IXGBE_I2C_BB_EN_X550EM_a	IXGBE_I2C_BB_EN_X550
277 #define IXGBE_I2C_BB_EN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), I2C_BB_EN)
278 
279 #define IXGBE_I2C_CLK_OE_N_EN		0
280 #define IXGBE_I2C_CLK_OE_N_EN_X540	IXGBE_I2C_CLK_OE_N_EN
281 #define IXGBE_I2C_CLK_OE_N_EN_X550	0x00002000
282 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x	IXGBE_I2C_CLK_OE_N_EN_X550
283 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a	IXGBE_I2C_CLK_OE_N_EN_X550
284 #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
285 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT	500
286 
287 
288 
289 #define NVM_OROM_OFFSET		0x17
290 #define NVM_OROM_BLK_LOW	0x83
291 #define NVM_OROM_BLK_HI		0x84
292 #define NVM_OROM_PATCH_MASK	0xFF
293 #define NVM_OROM_SHIFT		8
294 
295 #define NVM_VER_MASK		0x00FF /* version mask */
296 #define NVM_VER_SHIFT		8     /* version bit shift */
297 #define NVM_OEM_PROD_VER_PTR	0x1B  /* OEM Product version block pointer */
298 #define NVM_OEM_PROD_VER_CAP_OFF 0x1  /* OEM Product version format offset */
299 #define NVM_OEM_PROD_VER_OFF_L	0x2   /* OEM Product version offset low */
300 #define NVM_OEM_PROD_VER_OFF_H	0x3   /* OEM Product version offset high */
301 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
302 #define NVM_OEM_PROD_VER_MOD_LEN 0x3  /* OEM Product version module length */
303 #define NVM_ETK_OFF_LOW		0x2D  /* version low order word */
304 #define NVM_ETK_OFF_HI		0x2E  /* version high order word */
305 #define NVM_ETK_SHIFT		16    /* high version word shift */
306 #define NVM_VER_INVALID		0xFFFF
307 #define NVM_ETK_VALID		0x8000
308 #define NVM_INVALID_PTR		0xFFFF
309 #define NVM_VER_SIZE		32    /* version string size */
310 
311 struct ixgbe_nvm_version {
312 	uint32_t etk_id;
313 	uint8_t  nvm_major;
314 	uint16_t nvm_minor;
315 	uint8_t  nvm_id;
316 
317 	bool oem_valid;
318 	uint8_t   oem_major;
319 	uint8_t   oem_minor;
320 	uint16_t  oem_release;
321 
322 	bool or_valid;
323 	uint8_t  or_major;
324 	uint16_t or_build;
325 	uint8_t  or_patch;
326 
327 };
328 
329 /* Interrupt Registers */
330 #define IXGBE_EICR		0x00800
331 #define IXGBE_EICS		0x00808
332 #define IXGBE_EIMS		0x00880
333 #define IXGBE_EIMC		0x00888
334 #define IXGBE_EIAC		0x00810
335 #define IXGBE_EIAM		0x00890
336 #define IXGBE_EICS_EX(_i)	(0x00A90 + (_i) * 4)
337 #define IXGBE_EIMS_EX(_i)	(0x00AA0 + (_i) * 4)
338 #define IXGBE_EIMC_EX(_i)	(0x00AB0 + (_i) * 4)
339 #define IXGBE_EIAM_EX(_i)	(0x00AD0 + (_i) * 4)
340 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
341 /*
342  * 82598 EITR is 16 bits but set the limits based on the max
343  * supported by all ixgbe hardware
344  */
345 #define IXGBE_MAX_INT_RATE	488281
346 #define IXGBE_MIN_INT_RATE	956
347 #define IXGBE_MAX_EITR		0x00000FF8
348 #define IXGBE_MIN_EITR		8
349 #define IXGBE_EITR(_i)		(((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
350 				 (0x012300 + (((_i) - 24) * 4)))
351 #define IXGBE_EITR_ITR_INT_MASK	0x00000FF8
352 #define IXGBE_EITR_LLI_MOD	0x00008000
353 #define IXGBE_EITR_CNT_WDIS	0x80000000
354 #define IXGBE_IVAR(_i)		(0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
355 #define IXGBE_IVAR_MISC		0x00A00 /* misc MSI-X interrupt causes */
356 #define IXGBE_EITRSEL		0x00894
357 #define IXGBE_MSIXT		0x00000 /* MSI-X Table. 0x0000 - 0x01C */
358 #define IXGBE_MSIXPBA		0x02000 /* MSI-X Pending bit array */
359 #define IXGBE_PBACL(_i)	(((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
360 #define IXGBE_GPIE		0x00898
361 
362 /* Flow Control Registers */
363 #define IXGBE_FCADBUL		0x03210
364 #define IXGBE_FCADBUH		0x03214
365 #define IXGBE_FCAMACL		0x04328
366 #define IXGBE_FCAMACH		0x0432C
367 #define IXGBE_FCRTH_82599(_i)	(0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
368 #define IXGBE_FCRTL_82599(_i)	(0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
369 #define IXGBE_PFCTOP		0x03008
370 #define IXGBE_FCTTV(_i)		(0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
371 #define IXGBE_FCRTL(_i)		(0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
372 #define IXGBE_FCRTH(_i)		(0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
373 #define IXGBE_FCRTV		0x032A0
374 #define IXGBE_FCCFG		0x03D00
375 #define IXGBE_TFCS		0x0CE00
376 
377 /* Receive DMA Registers */
378 #define IXGBE_RDBAL(_i)	(((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
379 			 (0x0D000 + (((_i) - 64) * 0x40)))
380 #define IXGBE_RDBAH(_i)	(((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
381 			 (0x0D004 + (((_i) - 64) * 0x40)))
382 #define IXGBE_RDLEN(_i)	(((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
383 			 (0x0D008 + (((_i) - 64) * 0x40)))
384 #define IXGBE_RDH(_i)	(((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
385 			 (0x0D010 + (((_i) - 64) * 0x40)))
386 #define IXGBE_RDT(_i)	(((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
387 			 (0x0D018 + (((_i) - 64) * 0x40)))
388 #define IXGBE_RXDCTL(_i)	(((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
389 				 (0x0D028 + (((_i) - 64) * 0x40)))
390 #define IXGBE_RSCCTL(_i)	(((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
391 				 (0x0D02C + (((_i) - 64) * 0x40)))
392 #define IXGBE_RSCDBU	0x03028
393 #define IXGBE_RDDCC	0x02F20
394 #define IXGBE_RXMEMWRAP	0x03190
395 #define IXGBE_STARCTRL	0x03024
396 /*
397  * Split and Replication Receive Control Registers
398  * 00-15 : 0x02100 + n*4
399  * 16-64 : 0x01014 + n*0x40
400  * 64-127: 0x0D014 + (n-64)*0x40
401  */
402 #define IXGBE_SRRCTL(_i)	(((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
403 				 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
404 				 (0x0D014 + (((_i) - 64) * 0x40))))
405 /*
406  * Rx DCA Control Register:
407  * 00-15 : 0x02200 + n*4
408  * 16-64 : 0x0100C + n*0x40
409  * 64-127: 0x0D00C + (n-64)*0x40
410  */
411 #define IXGBE_DCA_RXCTRL(_i)	(((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
412 				 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
413 				 (0x0D00C + (((_i) - 64) * 0x40))))
414 #define IXGBE_RDRXCTL		0x02F00
415 /* 8 of these 0x03C00 - 0x03C1C */
416 #define IXGBE_RXPBSIZE(_i)	(0x03C00 + ((_i) * 4))
417 #define IXGBE_RXCTRL		0x03000
418 #define IXGBE_DROPEN		0x03D04
419 #define IXGBE_RXPBSIZE_SHIFT	10
420 #define IXGBE_RXPBSIZE_MASK	0x000FFC00
421 
422 /* Receive Registers */
423 #define IXGBE_RXCSUM		0x05000
424 #define IXGBE_RFCTL		0x05008
425 #define IXGBE_DRECCCTL		0x02F08
426 #define IXGBE_DRECCCTL_DISABLE	0
427 #define IXGBE_DRECCCTL2		0x02F8C
428 
429 /* Multicast Table Array - 128 entries */
430 #define IXGBE_MTA(_i)		(0x05200 + ((_i) * 4))
431 #define IXGBE_RAL(_i)		(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
432 				 (0x0A200 + ((_i) * 8)))
433 #define IXGBE_RAH(_i)		(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
434 				 (0x0A204 + ((_i) * 8)))
435 #define IXGBE_MPSAR_LO(_i)	(0x0A600 + ((_i) * 8))
436 #define IXGBE_MPSAR_HI(_i)	(0x0A604 + ((_i) * 8))
437 /* Packet split receive type */
438 #define IXGBE_PSRTYPE(_i)	(((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
439 				 (0x0EA00 + ((_i) * 4)))
440 /* array of 4096 1-bit vlan filters */
441 #define IXGBE_VFTA(_i)		(0x0A000 + ((_i) * 4))
442 /*array of 4096 4-bit vlan vmdq indices */
443 #define IXGBE_VFTAVIND(_j, _i)	(0x0A200 + ((_j) * 0x200) + ((_i) * 4))
444 #define IXGBE_FCTRL		0x05080
445 #define IXGBE_VLNCTRL		0x05088
446 #define IXGBE_MCSTCTRL		0x05090
447 #define IXGBE_MRQC		0x05818
448 #define IXGBE_SAQF(_i)	(0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
449 #define IXGBE_DAQF(_i)	(0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
450 #define IXGBE_SDPQF(_i)	(0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
451 #define IXGBE_FTQF(_i)	(0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
452 #define IXGBE_ETQF(_i)	(0x05128 + ((_i) * 4)) /* EType Queue Filter */
453 #define IXGBE_ETQS(_i)	(0x0EC00 + ((_i) * 4)) /* EType Queue Select */
454 #define IXGBE_SYNQF	0x0EC30 /* SYN Packet Queue Filter */
455 #define IXGBE_RQTC	0x0EC70
456 #define IXGBE_MTQC	0x08120
457 #define IXGBE_VLVF(_i)	(0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
458 #define IXGBE_VLVFB(_i)	(0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
459 #define IXGBE_VMVIR(_i)	(0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
460 #define IXGBE_PFFLPL		0x050B0
461 #define IXGBE_PFFLPH		0x050B4
462 #define IXGBE_VT_CTL		0x051B0
463 #define IXGBE_PFMAILBOX(_i)	(0x04B00 + (4 * (_i))) /* 64 total */
464 /* 64 Mailboxes, 16 DW each */
465 #define IXGBE_PFMBMEM(_i)	(0x13000 + (64 * (_i)))
466 #define IXGBE_PFMBICR_INDEX(_i)	((_i) >> 4)
467 #define IXGBE_PFMBICR_SHIFT(_i)	((_i) % 16)
468 #define IXGBE_PFMBICR(_i)	(0x00710 + (4 * (_i))) /* 4 total */
469 #define IXGBE_PFMBIMR(_i)	(0x00720 + (4 * (_i))) /* 4 total */
470 #define IXGBE_PFVFLRE(_i)	((((_i) & 1) ? 0x001C0 : 0x00600))
471 #define IXGBE_PFVFLREC(_i)	(0x00700 + ((_i) * 4))
472 #define IXGBE_PFVFLRE_INDEX(_i)	((_i) >> 5)
473 #define IXGBE_PFVFLRE_SHIFT(_i)	((_i) % 32)
474 #define IXGBE_VFRE(_i)		(0x051E0 + ((_i) * 4))
475 #define IXGBE_VFTE(_i)		(0x08110 + ((_i) * 4))
476 #define IXGBE_VMECM(_i)		(0x08790 + ((_i) * 4))
477 #define IXGBE_QDE		0x2F04
478 #define IXGBE_VMTXSW(_i)	(0x05180 + ((_i) * 4)) /* 2 total */
479 #define IXGBE_VMOLR(_i)		(0x0F000 + ((_i) * 4)) /* 64 total */
480 #define IXGBE_UTA(_i)		(0x0F400 + ((_i) * 4))
481 #define IXGBE_MRCTL(_i)		(0x0F600 + ((_i) * 4))
482 #define IXGBE_VMRVLAN(_i)	(0x0F610 + ((_i) * 4))
483 #define IXGBE_VMRVM(_i)		(0x0F630 + ((_i) * 4))
484 #define IXGBE_LVMMC_RX		0x2FA8
485 #define IXGBE_LVMMC_TX		0x8108
486 #define IXGBE_LMVM_RX		0x2FA4
487 #define IXGBE_LMVM_TX		0x8124
488 #define IXGBE_WQBR_RX(_i)	(0x2FB0 + ((_i) * 4)) /* 4 total */
489 #define IXGBE_WQBR_TX(_i)	(0x8130 + ((_i) * 4)) /* 4 total */
490 #define IXGBE_L34T_IMIR(_i)	(0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
491 #define IXGBE_RXFECCERR0	0x051B8
492 #define IXGBE_LLITHRESH		0x0EC90
493 #define IXGBE_IMIR(_i)		(0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
494 #define IXGBE_IMIREXT(_i)	(0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
495 #define IXGBE_IMIRVP		0x05AC0
496 #define IXGBE_VMD_CTL		0x0581C
497 #define IXGBE_RETA(_i)		(0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
498 #define IXGBE_ERETA(_i)		(0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
499 #define IXGBE_RSSRK(_i)		(0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
500 
501 /* Registers for setting up RSS on X550 with SRIOV
502  * _p - pool number (0..63)
503  * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
504  */
505 #define IXGBE_PFVFMRQC(_p)	(0x03400 + ((_p) * 4))
506 #define IXGBE_PFVFRSSRK(_i, _p)	(0x018000 + ((_i) * 4) + ((_p) * 0x40))
507 #define IXGBE_PFVFRETA(_i, _p)	(0x019000 + ((_i) * 4) + ((_p) * 0x40))
508 
509 /* Flow Director registers */
510 #define IXGBE_FDIRCTRL	0x0EE00
511 #define IXGBE_FDIRHKEY	0x0EE68
512 #define IXGBE_FDIRSKEY	0x0EE6C
513 #define IXGBE_FDIRDIP4M	0x0EE3C
514 #define IXGBE_FDIRSIP4M	0x0EE40
515 #define IXGBE_FDIRTCPM	0x0EE44
516 #define IXGBE_FDIRUDPM	0x0EE48
517 #define IXGBE_FDIRSCTPM	0x0EE78
518 #define IXGBE_FDIRIP6M	0x0EE74
519 #define IXGBE_FDIRM	0x0EE70
520 
521 /* Flow Director Stats registers */
522 #define IXGBE_FDIRFREE	0x0EE38
523 #define IXGBE_FDIRLEN	0x0EE4C
524 #define IXGBE_FDIRUSTAT	0x0EE50
525 #define IXGBE_FDIRFSTAT	0x0EE54
526 #define IXGBE_FDIRMATCH	0x0EE58
527 #define IXGBE_FDIRMISS	0x0EE5C
528 
529 /* Flow Director Programming registers */
530 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
531 #define IXGBE_FDIRIPSA	0x0EE18
532 #define IXGBE_FDIRIPDA	0x0EE1C
533 #define IXGBE_FDIRPORT	0x0EE20
534 #define IXGBE_FDIRVLAN	0x0EE24
535 #define IXGBE_FDIRHASH	0x0EE28
536 #define IXGBE_FDIRCMD	0x0EE2C
537 
538 /* Transmit DMA registers */
539 #define IXGBE_TDBAL(_i)		(0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
540 #define IXGBE_TDBAH(_i)		(0x06004 + ((_i) * 0x40))
541 #define IXGBE_TDLEN(_i)		(0x06008 + ((_i) * 0x40))
542 #define IXGBE_TDH(_i)		(0x06010 + ((_i) * 0x40))
543 #define IXGBE_TDT(_i)		(0x06018 + ((_i) * 0x40))
544 #define IXGBE_TXDCTL(_i)	(0x06028 + ((_i) * 0x40))
545 #define IXGBE_TDWBAL(_i)	(0x06038 + ((_i) * 0x40))
546 #define IXGBE_TDWBAH(_i)	(0x0603C + ((_i) * 0x40))
547 #define IXGBE_DTXCTL		0x07E00
548 
549 #define IXGBE_DMATXCTL		0x04A80
550 #define IXGBE_PFVFSPOOF(_i)	(0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
551 #define IXGBE_PFDTXGSWC		0x08220
552 #define IXGBE_DTXMXSZRQ		0x08100
553 #define IXGBE_DTXTCPFLGL	0x04A88
554 #define IXGBE_DTXTCPFLGH	0x04A8C
555 #define IXGBE_LBDRPEN		0x0CA00
556 #define IXGBE_TXPBTHRESH(_i)	(0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
557 
558 #define IXGBE_DMATXCTL_TE	0x1 /* Transmit Enable */
559 #define IXGBE_DMATXCTL_NS	0x2 /* No Snoop LSO hdr buffer */
560 #define IXGBE_DMATXCTL_GDV	0x8 /* Global Double VLAN */
561 #define IXGBE_DMATXCTL_MDP_EN	0x20 /* Bit 5 */
562 #define IXGBE_DMATXCTL_MBINTEN	0x40 /* Bit 6 */
563 #define IXGBE_DMATXCTL_VT_SHIFT	16  /* VLAN EtherType */
564 
565 #define IXGBE_PFDTXGSWC_VT_LBEN	0x1 /* Local L2 VT switch enable */
566 
567 /* Anti-spoofing defines */
568 #define IXGBE_SPOOF_MACAS_MASK		0xFF
569 #define IXGBE_SPOOF_VLANAS_MASK		0xFF00
570 #define IXGBE_SPOOF_VLANAS_SHIFT	8
571 #define IXGBE_SPOOF_ETHERTYPEAS		0xFF000000
572 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT	16
573 #define IXGBE_PFVFSPOOF_REG_COUNT	8
574 /* 16 of these (0-15) */
575 #define IXGBE_DCA_TXCTRL(_i)		(0x07200 + ((_i) * 4))
576 /* Tx DCA Control register : 128 of these (0-127) */
577 #define IXGBE_DCA_TXCTRL_82599(_i)	(0x0600C + ((_i) * 0x40))
578 #define IXGBE_TIPG			0x0CB00
579 #define IXGBE_TXPBSIZE(_i)		(0x0CC00 + ((_i) * 4)) /* 8 of these */
580 #define IXGBE_MNGTXMAP			0x0CD10
581 #define IXGBE_TIPG_FIBER_DEFAULT	3
582 #define IXGBE_TXPBSIZE_SHIFT		10
583 
584 /* Wake up registers */
585 #define IXGBE_WUC	0x05800
586 #define IXGBE_WUFC	0x05808
587 #define IXGBE_WUS	0x05810
588 #define IXGBE_IPAV	0x05838
589 #define IXGBE_IP4AT	0x05840 /* IPv4 table 0x5840-0x5858 */
590 #define IXGBE_IP6AT	0x05880 /* IPv6 table 0x5880-0x588F */
591 
592 #define IXGBE_WUPL	0x05900
593 #define IXGBE_WUPM	0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
594 #define IXGBE_PROXYS	0x05F60 /* Proxying Status Register */
595 #define IXGBE_PROXYFC	0x05F64 /* Proxying Filter Control Register */
596 #define IXGBE_VXLANCTRL	0x0000507C /* Rx filter VXLAN UDPPORT Register */
597 
598 /* masks for accessing VXLAN and GENEVE UDP ports */
599 #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK	0x0000ffff /* VXLAN port */
600 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK	0xffff0000 /* GENEVE port */
601 #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK	0xffffffff /* GENEVE/VXLAN */
602 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT	16
603 
604 #define IXGBE_FHFT(_n)	(0x09000 + ((_n) * 0x100)) /* Flex host filter table */
605 /* Ext Flexible Host Filter Table */
606 #define IXGBE_FHFT_EXT(_n)	(0x09800 + ((_n) * 0x100))
607 #define IXGBE_FHFT_EXT_X550(_n)	(0x09600 + ((_n) * 0x100))
608 
609 /* Four Flexible Filters are supported */
610 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX		4
611 /* Six Flexible Filters are supported */
612 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6	6
613 /* Eight Flexible Filters are supported */
614 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8	8
615 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX	2
616 
617 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
618 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX		128
619 #define IXGBE_FHFT_LENGTH_OFFSET		0xFC  /* Length byte in FHFT */
620 #define IXGBE_FHFT_LENGTH_MASK			0x0FF /* Length in lower byte */
621 
622 /* Definitions for power management and wakeup registers */
623 /* Wake Up Control */
624 #define IXGBE_WUC_PME_EN	0x00000002 /* PME Enable */
625 #define IXGBE_WUC_PME_STATUS	0x00000004 /* PME Status */
626 #define IXGBE_WUC_WKEN		0x00000010 /* Enable PE_WAKE_N pin assertion  */
627 
628 /* Wake Up Filter Control */
629 #define IXGBE_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
630 #define IXGBE_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
631 #define IXGBE_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
632 #define IXGBE_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
633 #define IXGBE_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
634 #define IXGBE_WUFC_ARP	0x00000020 /* ARP Request Packet Wakeup Enable */
635 #define IXGBE_WUFC_IPV4	0x00000040 /* Directed IPv4 Packet Wakeup Enable */
636 #define IXGBE_WUFC_IPV6	0x00000080 /* Directed IPv6 Packet Wakeup Enable */
637 #define IXGBE_WUFC_MNG	0x00000100 /* Directed Mgmt Packet Wakeup Enable */
638 
639 #define IXGBE_WUFC_IGNORE_TCO	0x00008000 /* Ignore WakeOn TCO packets */
640 #define IXGBE_WUFC_FLX0	0x00010000 /* Flexible Filter 0 Enable */
641 #define IXGBE_WUFC_FLX1	0x00020000 /* Flexible Filter 1 Enable */
642 #define IXGBE_WUFC_FLX2	0x00040000 /* Flexible Filter 2 Enable */
643 #define IXGBE_WUFC_FLX3	0x00080000 /* Flexible Filter 3 Enable */
644 #define IXGBE_WUFC_FLX4	0x00100000 /* Flexible Filter 4 Enable */
645 #define IXGBE_WUFC_FLX5	0x00200000 /* Flexible Filter 5 Enable */
646 #define IXGBE_WUFC_FLX_FILTERS		0x000F0000 /* Mask for 4 flex filters */
647 #define IXGBE_WUFC_FLX_FILTERS_6	0x003F0000 /* Mask for 6 flex filters */
648 #define IXGBE_WUFC_FLX_FILTERS_8	0x00FF0000 /* Mask for 8 flex filters */
649 #define IXGBE_WUFC_FW_RST_WK	0x80000000 /* Ena wake on FW reset assertion */
650 /* Mask for Ext. flex filters */
651 #define IXGBE_WUFC_EXT_FLX_FILTERS	0x00300000
652 #define IXGBE_WUFC_ALL_FILTERS		0x000F00FF /* Mask all 4 flex filters */
653 #define IXGBE_WUFC_ALL_FILTERS_6	0x003F00FF /* Mask all 6 flex filters */
654 #define IXGBE_WUFC_ALL_FILTERS_8	0x00FF00FF /* Mask all 8 flex filters */
655 #define IXGBE_WUFC_FLX_OFFSET	16 /* Offset to the Flexible Filters bits */
656 
657 /* Wake Up Status */
658 #define IXGBE_WUS_LNKC		IXGBE_WUFC_LNKC
659 #define IXGBE_WUS_MAG		IXGBE_WUFC_MAG
660 #define IXGBE_WUS_EX		IXGBE_WUFC_EX
661 #define IXGBE_WUS_MC		IXGBE_WUFC_MC
662 #define IXGBE_WUS_BC		IXGBE_WUFC_BC
663 #define IXGBE_WUS_ARP		IXGBE_WUFC_ARP
664 #define IXGBE_WUS_IPV4		IXGBE_WUFC_IPV4
665 #define IXGBE_WUS_IPV6		IXGBE_WUFC_IPV6
666 #define IXGBE_WUS_MNG		IXGBE_WUFC_MNG
667 #define IXGBE_WUS_FLX0		IXGBE_WUFC_FLX0
668 #define IXGBE_WUS_FLX1		IXGBE_WUFC_FLX1
669 #define IXGBE_WUS_FLX2		IXGBE_WUFC_FLX2
670 #define IXGBE_WUS_FLX3		IXGBE_WUFC_FLX3
671 #define IXGBE_WUS_FLX4		IXGBE_WUFC_FLX4
672 #define IXGBE_WUS_FLX5		IXGBE_WUFC_FLX5
673 #define IXGBE_WUS_FLX_FILTERS	IXGBE_WUFC_FLX_FILTERS
674 #define IXGBE_WUS_FW_RST_WK	IXGBE_WUFC_FW_RST_WK
675 /* Proxy Status */
676 #define IXGBE_PROXYS_EX		0x00000004 /* Exact packet received */
677 #define IXGBE_PROXYS_ARP_DIR	0x00000020 /* ARP w/filter match received */
678 #define IXGBE_PROXYS_NS		0x00000200 /* IPV6 NS received */
679 #define IXGBE_PROXYS_NS_DIR	0x00000400 /* IPV6 NS w/DA match received */
680 #define IXGBE_PROXYS_ARP	0x00000800 /* ARP request packet received */
681 #define IXGBE_PROXYS_MLD	0x00001000 /* IPv6 MLD packet received */
682 
683 /* Proxying Filter Control */
684 #define IXGBE_PROXYFC_ENABLE	0x00000001 /* Port Proxying Enable */
685 #define IXGBE_PROXYFC_EX	0x00000004 /* Directed Exact Proxy Enable */
686 #define IXGBE_PROXYFC_ARP_DIR	0x00000020 /* Directed ARP Proxy Enable */
687 #define IXGBE_PROXYFC_NS	0x00000200 /* IPv6 Neighbor Solicitation */
688 #define IXGBE_PROXYFC_ARP	0x00000800 /* ARP Request Proxy Enable */
689 #define IXGBE_PROXYFC_MLD	0x00000800 /* IPv6 MLD Proxy Enable */
690 #define IXGBE_PROXYFC_NO_TCO	0x00008000 /* Ignore TCO packets */
691 
692 #define IXGBE_WUPL_LENGTH_MASK	0xFFFF
693 
694 /* DCB registers */
695 #define IXGBE_DCB_MAX_TRAFFIC_CLASS	8
696 #define IXGBE_RMCS		0x03D00
697 #define IXGBE_DPMCS		0x07F40
698 #define IXGBE_PDPMCS		0x0CD00
699 #define IXGBE_RUPPBMR		0x050A0
700 #define IXGBE_RT2CR(_i)		(0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
701 #define IXGBE_RT2SR(_i)		(0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
702 #define IXGBE_TDTQ2TCCR(_i)	(0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
703 #define IXGBE_TDTQ2TCSR(_i)	(0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
704 #define IXGBE_TDPT2TCCR(_i)	(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
705 #define IXGBE_TDPT2TCSR(_i)	(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
706 
707 /* Power Management */
708 /* DMA Coalescing configuration */
709 struct ixgbe_dmac_config {
710 	uint16_t	watchdog_timer; /* usec units */
711 	uint32_t	link_speed;
712 	uint8_t	fcoe_tc;
713 	uint8_t	num_tcs;
714 };
715 
716 /*
717  * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
718  * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
719  * 87500 bytes [85KB]
720  */
721 #define IXGBE_DMACRXT_10G		0x55
722 #define IXGBE_DMACRXT_1G		0x09
723 #define IXGBE_DMACRXT_100M		0x01
724 
725 /* DMA Coalescing registers */
726 #define IXGBE_DMCMNGTH			0x15F20 /* Management Threshold */
727 #define IXGBE_DMACR			0x02400 /* Control register */
728 #define IXGBE_DMCTH(_i)			(0x03300 + ((_i) * 4)) /* 8 of these */
729 #define IXGBE_DMCTLX			0x02404 /* Time to Lx request */
730 /* DMA Coalescing register fields */
731 #define IXGBE_DMCMNGTH_DMCMNGTH_MASK	0x000FFFF0 /* Mng Threshold mask */
732 #define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT	4 /* Management Threshold shift */
733 #define IXGBE_DMACR_DMACWT_MASK		0x0000FFFF /* Watchdog Timer mask */
734 #define IXGBE_DMACR_HIGH_PRI_TC_MASK	0x00FF0000
735 #define IXGBE_DMACR_HIGH_PRI_TC_SHIFT	16
736 #define IXGBE_DMACR_EN_MNG_IND		0x10000000 /* Enable Mng Indications */
737 #define IXGBE_DMACR_LX_COAL_IND		0x40000000 /* Lx Coalescing indicate */
738 #define IXGBE_DMACR_DMAC_EN		0x80000000 /* DMA Coalescing Enable */
739 #define IXGBE_DMCTH_DMACRXT_MASK	0x000001FF /* Receive Threshold mask */
740 #define IXGBE_DMCTLX_TTLX_MASK		0x00000FFF /* Time to Lx request mask */
741 
742 /* EEE registers */
743 #define IXGBE_EEER			0x043A0 /* EEE register */
744 #define IXGBE_EEE_STAT			0x04398 /* EEE Status */
745 #define IXGBE_EEE_SU			0x04380 /* EEE Set up */
746 #define IXGBE_EEE_SU_TEEE_DLY_SHIFT	26
747 #define IXGBE_TLPIC			0x041F4 /* EEE Tx LPI count */
748 #define IXGBE_RLPIC			0x041F8 /* EEE Rx LPI count */
749 
750 /* EEE register fields */
751 #define IXGBE_EEER_TX_LPI_EN		0x00010000 /* Enable EEE LPI TX path */
752 #define IXGBE_EEER_RX_LPI_EN		0x00020000 /* Enable EEE LPI RX path */
753 #define IXGBE_EEE_STAT_NEG		0x20000000 /* EEE support neg on link */
754 #define IXGBE_EEE_RX_LPI_STATUS		0x40000000 /* RX Link in LPI status */
755 #define IXGBE_EEE_TX_LPI_STATUS		0x80000000 /* TX Link in LPI status */
756 
757 /* Security Control Registers */
758 #define IXGBE_SECTXCTRL		0x08800
759 #define IXGBE_SECTXSTAT		0x08804
760 #define IXGBE_SECTXBUFFAF	0x08808
761 #define IXGBE_SECTXMINIFG	0x08810
762 #define IXGBE_SECRXCTRL		0x08D00
763 #define IXGBE_SECRXSTAT		0x08D04
764 
765 /* Security Bit Fields and Masks */
766 #define IXGBE_SECTXCTRL_SECTX_DIS	0x00000001
767 #define IXGBE_SECTXCTRL_TX_DIS		0x00000002
768 #define IXGBE_SECTXCTRL_STORE_FORWARD	0x00000004
769 
770 #define IXGBE_SECTXSTAT_SECTX_RDY	0x00000001
771 #define IXGBE_SECTXSTAT_ECC_TXERR	0x00000002
772 
773 #define IXGBE_SECRXCTRL_SECRX_DIS	0x00000001
774 #define IXGBE_SECRXCTRL_RX_DIS		0x00000002
775 
776 #define IXGBE_SECRXSTAT_SECRX_RDY	0x00000001
777 #define IXGBE_SECRXSTAT_ECC_RXERR	0x00000002
778 
779 /* LinkSec (MacSec) Registers */
780 #define IXGBE_LSECTXCAP		0x08A00
781 #define IXGBE_LSECRXCAP		0x08F00
782 #define IXGBE_LSECTXCTRL	0x08A04
783 #define IXGBE_LSECTXSCL		0x08A08 /* SCI Low */
784 #define IXGBE_LSECTXSCH		0x08A0C /* SCI High */
785 #define IXGBE_LSECTXSA		0x08A10
786 #define IXGBE_LSECTXPN0		0x08A14
787 #define IXGBE_LSECTXPN1		0x08A18
788 #define IXGBE_LSECTXKEY0(_n)	(0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
789 #define IXGBE_LSECTXKEY1(_n)	(0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
790 #define IXGBE_LSECRXCTRL	0x08F04
791 #define IXGBE_LSECRXSCL		0x08F08
792 #define IXGBE_LSECRXSCH		0x08F0C
793 #define IXGBE_LSECRXSA(_i)	(0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
794 #define IXGBE_LSECRXPN(_i)	(0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
795 #define IXGBE_LSECRXKEY(_n, _m)	(0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
796 #define IXGBE_LSECTXUT		0x08A3C /* OutPktsUntagged */
797 #define IXGBE_LSECTXPKTE	0x08A40 /* OutPktsEncrypted */
798 #define IXGBE_LSECTXPKTP	0x08A44 /* OutPktsProtected */
799 #define IXGBE_LSECTXOCTE	0x08A48 /* OutOctetsEncrypted */
800 #define IXGBE_LSECTXOCTP	0x08A4C /* OutOctetsProtected */
801 #define IXGBE_LSECRXUT		0x08F40 /* InPktsUntagged/InPktsNoTag */
802 #define IXGBE_LSECRXOCTD	0x08F44 /* InOctetsDecrypted */
803 #define IXGBE_LSECRXOCTV	0x08F48 /* InOctetsValidated */
804 #define IXGBE_LSECRXBAD		0x08F4C /* InPktsBadTag */
805 #define IXGBE_LSECRXNOSCI	0x08F50 /* InPktsNoSci */
806 #define IXGBE_LSECRXUNSCI	0x08F54 /* InPktsUnknownSci */
807 #define IXGBE_LSECRXUNCH	0x08F58 /* InPktsUnchecked */
808 #define IXGBE_LSECRXDELAY	0x08F5C /* InPktsDelayed */
809 #define IXGBE_LSECRXLATE	0x08F60 /* InPktsLate */
810 #define IXGBE_LSECRXOK(_n)	(0x08F64 + (0x04 * (_n))) /* InPktsOk */
811 #define IXGBE_LSECRXINV(_n)	(0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
812 #define IXGBE_LSECRXNV(_n)	(0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
813 #define IXGBE_LSECRXUNSA	0x08F7C /* InPktsUnusedSa */
814 #define IXGBE_LSECRXNUSA	0x08F80 /* InPktsNotUsingSa */
815 
816 /* LinkSec (MacSec) Bit Fields and Masks */
817 #define IXGBE_LSECTXCAP_SUM_MASK	0x00FF0000
818 #define IXGBE_LSECTXCAP_SUM_SHIFT	16
819 #define IXGBE_LSECRXCAP_SUM_MASK	0x00FF0000
820 #define IXGBE_LSECRXCAP_SUM_SHIFT	16
821 
822 #define IXGBE_LSECTXCTRL_EN_MASK	0x00000003
823 #define IXGBE_LSECTXCTRL_DISABLE	0x0
824 #define IXGBE_LSECTXCTRL_AUTH		0x1
825 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT	0x2
826 #define IXGBE_LSECTXCTRL_AISCI		0x00000020
827 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK	0xFFFFFF00
828 #define IXGBE_LSECTXCTRL_RSV_MASK	0x000000D8
829 
830 #define IXGBE_LSECRXCTRL_EN_MASK	0x0000000C
831 #define IXGBE_LSECRXCTRL_EN_SHIFT	2
832 #define IXGBE_LSECRXCTRL_DISABLE	0x0
833 #define IXGBE_LSECRXCTRL_CHECK		0x1
834 #define IXGBE_LSECRXCTRL_STRICT		0x2
835 #define IXGBE_LSECRXCTRL_DROP		0x3
836 #define IXGBE_LSECRXCTRL_PLSH		0x00000040
837 #define IXGBE_LSECRXCTRL_RP		0x00000080
838 #define IXGBE_LSECRXCTRL_RSV_MASK	0xFFFFFF33
839 
840 /* IpSec Registers */
841 #define IXGBE_IPSTXIDX		0x08900
842 #define IXGBE_IPSTXSALT		0x08904
843 #define IXGBE_IPSTXKEY(_i)	(0x08908 + (4 * (_i))) /* 4 of these (0-3) */
844 #define IXGBE_IPSRXIDX		0x08E00
845 #define IXGBE_IPSRXIPADDR(_i)	(0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
846 #define IXGBE_IPSRXSPI		0x08E14
847 #define IXGBE_IPSRXIPIDX	0x08E18
848 #define IXGBE_IPSRXKEY(_i)	(0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
849 #define IXGBE_IPSRXSALT		0x08E2C
850 #define IXGBE_IPSRXMOD		0x08E30
851 
852 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE	0x4
853 
854 /* DCB registers */
855 #define IXGBE_RTRPCS		0x02430
856 #define IXGBE_RTTDCS		0x04900
857 #define IXGBE_RTTDCS_ARBDIS	0x00000040 /* DCB arbiter disable */
858 #define IXGBE_RTTPCS		0x0CD00
859 #define IXGBE_RTRUP2TC		0x03020
860 #define IXGBE_RTTUP2TC		0x0C800
861 #define IXGBE_RTRPT4C(_i)	(0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
862 #define IXGBE_TXLLQ(_i)		(0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
863 #define IXGBE_RTRPT4S(_i)	(0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
864 #define IXGBE_RTTDT2C(_i)	(0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
865 #define IXGBE_RTTDT2S(_i)	(0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
866 #define IXGBE_RTTPT2C(_i)	(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
867 #define IXGBE_RTTPT2S(_i)	(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
868 #define IXGBE_RTTDQSEL		0x04904
869 #define IXGBE_RTTDT1C		0x04908
870 #define IXGBE_RTTDT1S		0x0490C
871 #define IXGBE_RTTDTECC		0x04990
872 #define IXGBE_RTTDTECC_NO_BCN	0x00000100
873 
874 #define IXGBE_RTTBCNRC			0x04984
875 #define IXGBE_RTTBCNRC_RS_ENA		0x80000000
876 #define IXGBE_RTTBCNRC_RF_DEC_MASK	0x00003FFF
877 #define IXGBE_RTTBCNRC_RF_INT_SHIFT	14
878 #define IXGBE_RTTBCNRC_RF_INT_MASK \
879 	(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
880 #define IXGBE_RTTBCNRM	0x04980
881 
882 /* BCN (for DCB) Registers */
883 #define IXGBE_RTTBCNRS	0x04988
884 #define IXGBE_RTTBCNCR	0x08B00
885 #define IXGBE_RTTBCNACH	0x08B04
886 #define IXGBE_RTTBCNACL	0x08B08
887 #define IXGBE_RTTBCNTG	0x04A90
888 #define IXGBE_RTTBCNIDX	0x08B0C
889 #define IXGBE_RTTBCNCP	0x08B10
890 #define IXGBE_RTFRTIMER	0x08B14
891 #define IXGBE_RTTBCNRTT	0x05150
892 #define IXGBE_RTTBCNRD	0x0498C
893 
894 /* FCoE DMA Context Registers */
895 /* FCoE Direct DMA Context */
896 #define IXGBE_FCDDC(_i, _j)	(0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
897 #define IXGBE_FCPTRL		0x02410 /* FC User Desc. PTR Low */
898 #define IXGBE_FCPTRH		0x02414 /* FC USer Desc. PTR High */
899 #define IXGBE_FCBUFF		0x02418 /* FC Buffer Control */
900 #define IXGBE_FCDMARW		0x02420 /* FC Receive DMA RW */
901 #define IXGBE_FCBUFF_VALID	(1 << 0)   /* DMA Context Valid */
902 #define IXGBE_FCBUFF_BUFFSIZE	(3 << 3)   /* User Buffer Size */
903 #define IXGBE_FCBUFF_WRCONTX	(1 << 7)   /* 0: Initiator, 1: Target */
904 #define IXGBE_FCBUFF_BUFFCNT	0x0000ff00 /* Number of User Buffers */
905 #define IXGBE_FCBUFF_OFFSET	0xffff0000 /* User Buffer Offset */
906 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT	3
907 #define IXGBE_FCBUFF_BUFFCNT_SHIFT	8
908 #define IXGBE_FCBUFF_OFFSET_SHIFT	16
909 #define IXGBE_FCDMARW_WE		(1 << 14)   /* Write enable */
910 #define IXGBE_FCDMARW_RE		(1 << 15)   /* Read enable */
911 #define IXGBE_FCDMARW_FCOESEL		0x000001ff  /* FC X_ID: 11 bits */
912 #define IXGBE_FCDMARW_LASTSIZE		0xffff0000  /* Last User Buffer Size */
913 #define IXGBE_FCDMARW_LASTSIZE_SHIFT	16
914 /* FCoE SOF/EOF */
915 #define IXGBE_TEOFF		0x04A94 /* Tx FC EOF */
916 #define IXGBE_TSOFF		0x04A98 /* Tx FC SOF */
917 #define IXGBE_REOFF		0x05158 /* Rx FC EOF */
918 #define IXGBE_RSOFF		0x051F8 /* Rx FC SOF */
919 /* FCoE Filter Context Registers */
920 #define IXGBE_FCD_ID		0x05114 /* FCoE D_ID */
921 #define IXGBE_FCSMAC		0x0510C /* FCoE Source MAC */
922 #define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT	16
923 /* FCoE Direct Filter Context */
924 #define IXGBE_FCDFC(_i, _j)	(0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
925 #define IXGBE_FCDFCD(_i)	(0x30000 + ((_i) * 0x4))
926 #define IXGBE_FCFLT		0x05108 /* FC FLT Context */
927 #define IXGBE_FCFLTRW		0x05110 /* FC Filter RW Control */
928 #define IXGBE_FCPARAM		0x051d8 /* FC Offset Parameter */
929 #define IXGBE_FCFLT_VALID	(1 << 0)   /* Filter Context Valid */
930 #define IXGBE_FCFLT_FIRST	(1 << 1)   /* Filter First */
931 #define IXGBE_FCFLT_SEQID	0x00ff0000 /* Sequence ID */
932 #define IXGBE_FCFLT_SEQCNT	0xff000000 /* Sequence Count */
933 #define IXGBE_FCFLTRW_RVALDT	(1 << 13)  /* Fast Re-Validation */
934 #define IXGBE_FCFLTRW_WE	(1 << 14)  /* Write Enable */
935 #define IXGBE_FCFLTRW_RE	(1 << 15)  /* Read Enable */
936 /* FCoE Receive Control */
937 #define IXGBE_FCRXCTRL		0x05100 /* FC Receive Control */
938 #define IXGBE_FCRXCTRL_FCOELLI	(1 << 0)   /* Low latency interrupt */
939 #define IXGBE_FCRXCTRL_SAVBAD	(1 << 1)   /* Save Bad Frames */
940 #define IXGBE_FCRXCTRL_FRSTRDH	(1 << 2)   /* EN 1st Read Header */
941 #define IXGBE_FCRXCTRL_LASTSEQH	(1 << 3)   /* EN Last Header in Seq */
942 #define IXGBE_FCRXCTRL_ALLH	(1 << 4)   /* EN All Headers */
943 #define IXGBE_FCRXCTRL_FRSTSEQH	(1 << 5)   /* EN 1st Seq. Header */
944 #define IXGBE_FCRXCTRL_ICRC	(1 << 6)   /* Ignore Bad FC CRC */
945 #define IXGBE_FCRXCTRL_FCCRCBO	(1 << 7)   /* FC CRC Byte Ordering */
946 #define IXGBE_FCRXCTRL_FCOEVER	0x00000f00 /* FCoE Version: 4 bits */
947 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT	8
948 /* FCoE Redirection */
949 #define IXGBE_FCRECTL		0x0ED00 /* FC Redirection Control */
950 #define IXGBE_FCRETA0		0x0ED10 /* FC Redirection Table 0 */
951 #define IXGBE_FCRETA(_i)	(IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
952 #define IXGBE_FCRECTL_ENA	0x1 /* FCoE Redir Table Enable */
953 #define IXGBE_FCRETASEL_ENA	0x2 /* FCoE FCRETASEL bit */
954 #define IXGBE_FCRETA_SIZE	8 /* Max entries in FCRETA */
955 #define IXGBE_FCRETA_ENTRY_MASK	0x0000007f /* 7 bits for the queue index */
956 #define IXGBE_FCRETA_SIZE_X550	32 /* Max entries in FCRETA */
957 /* Higher 7 bits for the queue index */
958 #define IXGBE_FCRETA_ENTRY_HIGH_MASK	0x007F0000
959 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT	16
960 
961 /* Stats registers */
962 #define IXGBE_CRCERRS	0x04000
963 #define IXGBE_ILLERRC	0x04004
964 #define IXGBE_ERRBC	0x04008
965 #define IXGBE_MSPDC	0x04010
966 #define IXGBE_MPC(_i)	(0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
967 #define IXGBE_MLFC	0x04034
968 #define IXGBE_MRFC	0x04038
969 #define IXGBE_RLEC	0x04040
970 #define IXGBE_LXONTXC	0x03F60
971 #define IXGBE_LXONRXC	0x0CF60
972 #define IXGBE_LXOFFTXC	0x03F68
973 #define IXGBE_LXOFFRXC	0x0CF68
974 #define IXGBE_LXONRXCNT		0x041A4
975 #define IXGBE_LXOFFRXCNT	0x041A8
976 #define IXGBE_PXONRXCNT(_i)	(0x04140 + ((_i) * 4)) /* 8 of these */
977 #define IXGBE_PXOFFRXCNT(_i)	(0x04160 + ((_i) * 4)) /* 8 of these */
978 #define IXGBE_PXON2OFFCNT(_i)	(0x03240 + ((_i) * 4)) /* 8 of these */
979 #define IXGBE_PXONTXC(_i)	(0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
980 #define IXGBE_PXONRXC(_i)	(0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
981 #define IXGBE_PXOFFTXC(_i)	(0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
982 #define IXGBE_PXOFFRXC(_i)	(0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
983 #define IXGBE_PRC64		0x0405C
984 #define IXGBE_PRC127		0x04060
985 #define IXGBE_PRC255		0x04064
986 #define IXGBE_PRC511		0x04068
987 #define IXGBE_PRC1023		0x0406C
988 #define IXGBE_PRC1522		0x04070
989 #define IXGBE_GPRC		0x04074
990 #define IXGBE_BPRC		0x04078
991 #define IXGBE_MPRC		0x0407C
992 #define IXGBE_GPTC		0x04080
993 #define IXGBE_GORCL		0x04088
994 #define IXGBE_GORCH		0x0408C
995 #define IXGBE_GOTCL		0x04090
996 #define IXGBE_GOTCH		0x04094
997 #define IXGBE_RNBC(_i)		(0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
998 #define IXGBE_RUC		0x040A4
999 #define IXGBE_RFC		0x040A8
1000 #define IXGBE_ROC		0x040AC
1001 #define IXGBE_RJC		0x040B0
1002 #define IXGBE_MNGPRC		0x040B4
1003 #define IXGBE_MNGPDC		0x040B8
1004 #define IXGBE_MNGPTC		0x0CF90
1005 #define IXGBE_TORL		0x040C0
1006 #define IXGBE_TORH		0x040C4
1007 #define IXGBE_TPR		0x040D0
1008 #define IXGBE_TPT		0x040D4
1009 #define IXGBE_PTC64		0x040D8
1010 #define IXGBE_PTC127		0x040DC
1011 #define IXGBE_PTC255		0x040E0
1012 #define IXGBE_PTC511		0x040E4
1013 #define IXGBE_PTC1023		0x040E8
1014 #define IXGBE_PTC1522		0x040EC
1015 #define IXGBE_MPTC		0x040F0
1016 #define IXGBE_BPTC		0x040F4
1017 #define IXGBE_XEC		0x04120
1018 #define IXGBE_SSVPC		0x08780
1019 
1020 #define IXGBE_RQSMR(_i)	(0x02300 + ((_i) * 4))
1021 #define IXGBE_TQSMR(_i)	(((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
1022 			 (0x08600 + ((_i) * 4)))
1023 #define IXGBE_TQSM(_i)	(0x08600 + ((_i) * 4))
1024 
1025 #define IXGBE_QPRC(_i)	(0x01030 + ((_i) * 0x40)) /* 16 of these */
1026 #define IXGBE_QPTC(_i)	(0x06030 + ((_i) * 0x40)) /* 16 of these */
1027 #define IXGBE_QBRC(_i)	(0x01034 + ((_i) * 0x40)) /* 16 of these */
1028 #define IXGBE_QBTC(_i)	(0x06034 + ((_i) * 0x40)) /* 16 of these */
1029 #define IXGBE_QBRC_L(_i)	(0x01034 + ((_i) * 0x40)) /* 16 of these */
1030 #define IXGBE_QBRC_H(_i)	(0x01038 + ((_i) * 0x40)) /* 16 of these */
1031 #define IXGBE_QPRDC(_i)		(0x01430 + ((_i) * 0x40)) /* 16 of these */
1032 #define IXGBE_QBTC_L(_i)	(0x08700 + ((_i) * 0x8)) /* 16 of these */
1033 #define IXGBE_QBTC_H(_i)	(0x08704 + ((_i) * 0x8)) /* 16 of these */
1034 #define IXGBE_FCCRC		0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
1035 #define IXGBE_FCOERPDC		0x0241C /* FCoE Rx Packets Dropped Count */
1036 #define IXGBE_FCLAST		0x02424 /* FCoE Last Error Count */
1037 #define IXGBE_FCOEPRC		0x02428 /* Number of FCoE Packets Received */
1038 #define IXGBE_FCOEDWRC		0x0242C /* Number of FCoE DWords Received */
1039 #define IXGBE_FCOEPTC		0x08784 /* Number of FCoE Packets Transmitted */
1040 #define IXGBE_FCOEDWTC		0x08788 /* Number of FCoE DWords Transmitted */
1041 #define IXGBE_FCCRC_CNT_MASK	0x0000FFFF /* CRC_CNT: bit 0 - 15 */
1042 #define IXGBE_FCLAST_CNT_MASK	0x0000FFFF /* Last_CNT: bit 0 - 15 */
1043 #define IXGBE_O2BGPTC		0x041C4
1044 #define IXGBE_O2BSPC		0x087B0
1045 #define IXGBE_B2OSPC		0x041C0
1046 #define IXGBE_B2OGPRC		0x02F90
1047 #define IXGBE_BUPRC		0x04180
1048 #define IXGBE_BMPRC		0x04184
1049 #define IXGBE_BBPRC		0x04188
1050 #define IXGBE_BUPTC		0x0418C
1051 #define IXGBE_BMPTC		0x04190
1052 #define IXGBE_BBPTC		0x04194
1053 #define IXGBE_BCRCERRS		0x04198
1054 #define IXGBE_BXONRXC		0x0419C
1055 #define IXGBE_BXOFFRXC		0x041E0
1056 #define IXGBE_BXONTXC		0x041E4
1057 #define IXGBE_BXOFFTXC		0x041E8
1058 
1059 /* Management */
1060 #define IXGBE_MAVTV(_i)		(0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
1061 #define IXGBE_MFUTP(_i)		(0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
1062 #define IXGBE_MANC		0x05820
1063 #define IXGBE_MFVAL		0x05824
1064 #define IXGBE_MANC2H		0x05860
1065 #define IXGBE_MDEF(_i)		(0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
1066 #define IXGBE_MIPAF		0x058B0
1067 #define IXGBE_MMAL(_i)		(0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
1068 #define IXGBE_MMAH(_i)		(0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
1069 #define IXGBE_FTFT		0x09400 /* 0x9400-0x97FC */
1070 #define IXGBE_METF(_i)		(0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
1071 #define IXGBE_MDEF_EXT(_i)	(0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
1072 #define IXGBE_LSWFW		0x15F14
1073 #define IXGBE_BMCIP(_i)		(0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1074 #define IXGBE_BMCIPVAL		0x05060
1075 #define IXGBE_BMCIP_IPADDR_TYPE	0x00000001
1076 #define IXGBE_BMCIP_IPADDR_VALID	0x00000002
1077 
1078 /* Management Bit Fields and Masks */
1079 #define IXGBE_MANC_MPROXYE	0x40000000 /* Management Proxy Enable */
1080 #define IXGBE_MANC_RCV_TCO_EN	0x00020000 /* Rcv TCO packet enable */
1081 #define IXGBE_MANC_EN_BMC2OS	0x10000000 /* Ena BMC2OS and OS2BMC traffic */
1082 #define IXGBE_MANC_EN_BMC2OS_SHIFT	28
1083 
1084 /* Firmware Semaphore Register */
1085 #define IXGBE_FWSM_MODE_MASK	0xE
1086 #define IXGBE_FWSM_TS_ENABLED	0x1
1087 #define IXGBE_FWSM_FW_MODE_PT	0x4
1088 
1089 /* ARC Subsystem registers */
1090 #define IXGBE_HICR		0x15F00
1091 #define IXGBE_FWSTS		0x15F0C
1092 #define IXGBE_HSMC0R		0x15F04
1093 #define IXGBE_HSMC1R		0x15F08
1094 #define IXGBE_SWSR		0x15F10
1095 #define IXGBE_HFDR		0x15FE8
1096 #define IXGBE_FLEX_MNG		0x15800 /* 0x15800 - 0x15EFC */
1097 
1098 #define IXGBE_HICR_EN		0x01  /* Enable bit - RO */
1099 /* Driver sets this bit when done to put command in RAM */
1100 #define IXGBE_HICR_C		0x02
1101 #define IXGBE_HICR_SV		0x04  /* Status Validity */
1102 #define IXGBE_HICR_FW_RESET_ENABLE	0x40
1103 #define IXGBE_HICR_FW_RESET	0x80
1104 
1105 /* PCI-E registers */
1106 #define IXGBE_GCR		0x11000
1107 #define IXGBE_GTV		0x11004
1108 #define IXGBE_FUNCTAG		0x11008
1109 #define IXGBE_GLT		0x1100C
1110 #define IXGBE_PCIEPIPEADR	0x11004
1111 #define IXGBE_PCIEPIPEDAT	0x11008
1112 #define IXGBE_GSCL_1		0x11010
1113 #define IXGBE_GSCL_2		0x11014
1114 #define IXGBE_GSCL_1_X540	IXGBE_GSCL_1
1115 #define IXGBE_GSCL_2_X540	IXGBE_GSCL_2
1116 #define IXGBE_GSCL_3		0x11018
1117 #define IXGBE_GSCL_4		0x1101C
1118 #define IXGBE_GSCN_0		0x11020
1119 #define IXGBE_GSCN_1		0x11024
1120 #define IXGBE_GSCN_2		0x11028
1121 #define IXGBE_GSCN_3		0x1102C
1122 #define IXGBE_GSCN_0_X540	IXGBE_GSCN_0
1123 #define IXGBE_GSCN_1_X540	IXGBE_GSCN_1
1124 #define IXGBE_GSCN_2_X540	IXGBE_GSCN_2
1125 #define IXGBE_GSCN_3_X540	IXGBE_GSCN_3
1126 #define IXGBE_FACTPS		0x10150
1127 #define IXGBE_FACTPS_X540	IXGBE_FACTPS
1128 #define IXGBE_GSCL_1_X550	0x11800
1129 #define IXGBE_GSCL_2_X550	0x11804
1130 #define IXGBE_GSCL_1_X550EM_x	IXGBE_GSCL_1_X550
1131 #define IXGBE_GSCL_2_X550EM_x	IXGBE_GSCL_2_X550
1132 #define IXGBE_GSCN_0_X550	0x11820
1133 #define IXGBE_GSCN_1_X550	0x11824
1134 #define IXGBE_GSCN_2_X550	0x11828
1135 #define IXGBE_GSCN_3_X550	0x1182C
1136 #define IXGBE_GSCN_0_X550EM_x	IXGBE_GSCN_0_X550
1137 #define IXGBE_GSCN_1_X550EM_x	IXGBE_GSCN_1_X550
1138 #define IXGBE_GSCN_2_X550EM_x	IXGBE_GSCN_2_X550
1139 #define IXGBE_GSCN_3_X550EM_x	IXGBE_GSCN_3_X550
1140 #define IXGBE_FACTPS_X550	IXGBE_FACTPS
1141 #define IXGBE_FACTPS_X550EM_x	IXGBE_FACTPS
1142 #define IXGBE_GSCL_1_X550EM_a	IXGBE_GSCL_1_X550
1143 #define IXGBE_GSCL_2_X550EM_a	IXGBE_GSCL_2_X550
1144 #define IXGBE_GSCN_0_X550EM_a	IXGBE_GSCN_0_X550
1145 #define IXGBE_GSCN_1_X550EM_a	IXGBE_GSCN_1_X550
1146 #define IXGBE_GSCN_2_X550EM_a	IXGBE_GSCN_2_X550
1147 #define IXGBE_GSCN_3_X550EM_a	IXGBE_GSCN_3_X550
1148 #define IXGBE_FACTPS_X550EM_a	0x15FEC
1149 #define IXGBE_FACTPS_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), FACTPS)
1150 
1151 #define IXGBE_PCIEANACTL	0x11040
1152 #define IXGBE_SWSM		0x10140
1153 #define IXGBE_SWSM_X540		IXGBE_SWSM
1154 #define IXGBE_SWSM_X550		IXGBE_SWSM
1155 #define IXGBE_SWSM_X550EM_x	IXGBE_SWSM
1156 #define IXGBE_SWSM_X550EM_a	0x15F70
1157 #define IXGBE_SWSM_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SWSM)
1158 
1159 #define IXGBE_FWSM		0x10148
1160 #define IXGBE_FWSM_X540		IXGBE_FWSM
1161 #define IXGBE_FWSM_X550		IXGBE_FWSM
1162 #define IXGBE_FWSM_X550EM_x	IXGBE_FWSM
1163 #define IXGBE_FWSM_X550EM_a	0x15F74
1164 #define IXGBE_FWSM_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), FWSM)
1165 
1166 #define IXGBE_SWFW_SYNC		IXGBE_GSSR
1167 #define IXGBE_SWFW_SYNC_X540	IXGBE_SWFW_SYNC
1168 #define IXGBE_SWFW_SYNC_X550	IXGBE_SWFW_SYNC
1169 #define IXGBE_SWFW_SYNC_X550EM_x	IXGBE_SWFW_SYNC
1170 #define IXGBE_SWFW_SYNC_X550EM_a	0x15F78
1171 #define IXGBE_SWFW_SYNC_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SWFW_SYNC)
1172 
1173 #define IXGBE_GSSR		0x10160
1174 #define IXGBE_MREVID		0x11064
1175 #define IXGBE_DCA_ID		0x11070
1176 #define IXGBE_DCA_CTRL		0x11074
1177 
1178 /* PCI-E registers 82599-Specific */
1179 #define IXGBE_GCR_EXT		0x11050
1180 #define IXGBE_GSCL_5_82599	0x11030
1181 #define IXGBE_GSCL_6_82599	0x11034
1182 #define IXGBE_GSCL_7_82599	0x11038
1183 #define IXGBE_GSCL_8_82599	0x1103C
1184 #define IXGBE_GSCL_5_X540	IXGBE_GSCL_5_82599
1185 #define IXGBE_GSCL_6_X540	IXGBE_GSCL_6_82599
1186 #define IXGBE_GSCL_7_X540	IXGBE_GSCL_7_82599
1187 #define IXGBE_GSCL_8_X540	IXGBE_GSCL_8_82599
1188 #define IXGBE_PHYADR_82599	0x11040
1189 #define IXGBE_PHYDAT_82599	0x11044
1190 #define IXGBE_PHYCTL_82599	0x11048
1191 #define IXGBE_PBACLR_82599	0x11068
1192 #define IXGBE_CIAA		0x11088
1193 #define IXGBE_CIAD		0x1108C
1194 #define IXGBE_CIAA_82599	IXGBE_CIAA
1195 #define IXGBE_CIAD_82599	IXGBE_CIAD
1196 #define IXGBE_CIAA_X540		IXGBE_CIAA
1197 #define IXGBE_CIAD_X540		IXGBE_CIAD
1198 #define IXGBE_GSCL_5_X550	0x11810
1199 #define IXGBE_GSCL_6_X550	0x11814
1200 #define IXGBE_GSCL_7_X550	0x11818
1201 #define IXGBE_GSCL_8_X550	0x1181C
1202 #define IXGBE_GSCL_5_X550EM_x	IXGBE_GSCL_5_X550
1203 #define IXGBE_GSCL_6_X550EM_x	IXGBE_GSCL_6_X550
1204 #define IXGBE_GSCL_7_X550EM_x	IXGBE_GSCL_7_X550
1205 #define IXGBE_GSCL_8_X550EM_x	IXGBE_GSCL_8_X550
1206 #define IXGBE_CIAA_X550		0x11508
1207 #define IXGBE_CIAD_X550		0x11510
1208 #define IXGBE_CIAA_X550EM_x	IXGBE_CIAA_X550
1209 #define IXGBE_CIAD_X550EM_x	IXGBE_CIAD_X550
1210 #define IXGBE_GSCL_5_X550EM_a	IXGBE_GSCL_5_X550
1211 #define IXGBE_GSCL_6_X550EM_a	IXGBE_GSCL_6_X550
1212 #define IXGBE_GSCL_7_X550EM_a	IXGBE_GSCL_7_X550
1213 #define IXGBE_GSCL_8_X550EM_a	IXGBE_GSCL_8_X550
1214 #define IXGBE_CIAA_X550EM_a	IXGBE_CIAA_X550
1215 #define IXGBE_CIAD_X550EM_a	IXGBE_CIAD_X550
1216 #define IXGBE_CIAA_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), CIAA)
1217 #define IXGBE_CIAD_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), CIAD)
1218 #define IXGBE_PICAUSE		0x110B0
1219 #define IXGBE_PIENA		0x110B8
1220 #define IXGBE_CDQ_MBR_82599	0x110B4
1221 #define IXGBE_PCIESPARE		0x110BC
1222 #define IXGBE_MISC_REG_82599	0x110F0
1223 #define IXGBE_ECC_CTRL_0_82599	0x11100
1224 #define IXGBE_ECC_CTRL_1_82599	0x11104
1225 #define IXGBE_ECC_STATUS_82599	0x110E0
1226 #define IXGBE_BAR_CTRL_82599	0x110F4
1227 
1228 /* PCI Express Control */
1229 #define IXGBE_GCR_CMPL_TMOUT_MASK	0x0000F000
1230 #define IXGBE_GCR_CMPL_TMOUT_10ms	0x00001000
1231 #define IXGBE_GCR_CMPL_TMOUT_RESEND	0x00010000
1232 #define IXGBE_GCR_CAP_VER2		0x00040000
1233 
1234 #define IXGBE_GCR_EXT_MSIX_EN		0x80000000
1235 #define IXGBE_GCR_EXT_BUFFERS_CLEAR	0x40000000
1236 #define IXGBE_GCR_EXT_VT_MODE_16	0x00000001
1237 #define IXGBE_GCR_EXT_VT_MODE_32	0x00000002
1238 #define IXGBE_GCR_EXT_VT_MODE_64	0x00000003
1239 #define IXGBE_GCR_EXT_SRIOV		(IXGBE_GCR_EXT_MSIX_EN | \
1240 					 IXGBE_GCR_EXT_VT_MODE_64)
1241 #define IXGBE_GCR_EXT_VT_MODE_MASK	0x00000003
1242 /* Time Sync Registers */
1243 #define IXGBE_TSYNCRXCTL	0x05188 /* Rx Time Sync Control register - RW */
1244 #define IXGBE_TSYNCTXCTL	0x08C00 /* Tx Time Sync Control register - RW */
1245 #define IXGBE_RXSTMPL	0x051E8 /* Rx timestamp Low - RO */
1246 #define IXGBE_RXSTMPH	0x051A4 /* Rx timestamp High - RO */
1247 #define IXGBE_RXSATRL	0x051A0 /* Rx timestamp attribute low - RO */
1248 #define IXGBE_RXSATRH	0x051A8 /* Rx timestamp attribute high - RO */
1249 #define IXGBE_RXMTRL	0x05120 /* RX message type register low - RW */
1250 #define IXGBE_TXSTMPL	0x08C04 /* Tx timestamp value Low - RO */
1251 #define IXGBE_TXSTMPH	0x08C08 /* Tx timestamp value High - RO */
1252 #define IXGBE_SYSTIML	0x08C0C /* System time register Low - RO */
1253 #define IXGBE_SYSTIMH	0x08C10 /* System time register High - RO */
1254 #define IXGBE_SYSTIMR	0x08C58 /* System time register Residue - RO */
1255 #define IXGBE_TIMINCA	0x08C14 /* Increment attributes register - RW */
1256 #define IXGBE_TIMADJL	0x08C18 /* Time Adjustment Offset register Low - RW */
1257 #define IXGBE_TIMADJH	0x08C1C /* Time Adjustment Offset register High - RW */
1258 #define IXGBE_TSAUXC	0x08C20 /* TimeSync Auxiliary Control register - RW */
1259 #define IXGBE_TRGTTIML0	0x08C24 /* Target Time Register 0 Low - RW */
1260 #define IXGBE_TRGTTIMH0	0x08C28 /* Target Time Register 0 High - RW */
1261 #define IXGBE_TRGTTIML1	0x08C2C /* Target Time Register 1 Low - RW */
1262 #define IXGBE_TRGTTIMH1	0x08C30 /* Target Time Register 1 High - RW */
1263 #define IXGBE_CLKTIML	0x08C34 /* Clock Out Time Register Low - RW */
1264 #define IXGBE_CLKTIMH	0x08C38 /* Clock Out Time Register High - RW */
1265 #define IXGBE_FREQOUT0	0x08C34 /* Frequency Out 0 Control register - RW */
1266 #define IXGBE_FREQOUT1	0x08C38 /* Frequency Out 1 Control register - RW */
1267 #define IXGBE_AUXSTMPL0	0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1268 #define IXGBE_AUXSTMPH0	0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1269 #define IXGBE_AUXSTMPL1	0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1270 #define IXGBE_AUXSTMPH1	0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1271 #define IXGBE_TSIM	0x08C68 /* TimeSync Interrupt Mask Register - RW */
1272 #define IXGBE_TSICR	0x08C60 /* TimeSync Interrupt Cause Register - WO */
1273 #define IXGBE_TSSDP	0x0003C /* TimeSync SDP Configuration Register - RW */
1274 
1275 /* Diagnostic Registers */
1276 #define IXGBE_RDSTATCTL		0x02C20
1277 #define IXGBE_RDSTAT(_i)	(0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1278 #define IXGBE_RDHMPN		0x02F08
1279 #define IXGBE_RIC_DW(_i)	(0x02F10 + ((_i) * 4))
1280 #define IXGBE_RDPROBE		0x02F20
1281 #define IXGBE_RDMAM		0x02F30
1282 #define IXGBE_RDMAD		0x02F34
1283 #define IXGBE_TDHMPN		0x07F08
1284 #define IXGBE_TDHMPN2		0x082FC
1285 #define IXGBE_TXDESCIC		0x082CC
1286 #define IXGBE_TIC_DW(_i)	(0x07F10 + ((_i) * 4))
1287 #define IXGBE_TIC_DW2(_i)	(0x082B0 + ((_i) * 4))
1288 #define IXGBE_TDPROBE		0x07F20
1289 #define IXGBE_TXBUFCTRL		0x0C600
1290 #define IXGBE_TXBUFDATA0	0x0C610
1291 #define IXGBE_TXBUFDATA1	0x0C614
1292 #define IXGBE_TXBUFDATA2	0x0C618
1293 #define IXGBE_TXBUFDATA3	0x0C61C
1294 #define IXGBE_RXBUFCTRL		0x03600
1295 #define IXGBE_RXBUFDATA0	0x03610
1296 #define IXGBE_RXBUFDATA1	0x03614
1297 #define IXGBE_RXBUFDATA2	0x03618
1298 #define IXGBE_RXBUFDATA3	0x0361C
1299 #define IXGBE_PCIE_DIAG(_i)	(0x11090 + ((_i) * 4)) /* 8 of these */
1300 #define IXGBE_RFVAL		0x050A4
1301 #define IXGBE_MDFTC1		0x042B8
1302 #define IXGBE_MDFTC2		0x042C0
1303 #define IXGBE_MDFTFIFO1		0x042C4
1304 #define IXGBE_MDFTFIFO2		0x042C8
1305 #define IXGBE_MDFTS		0x042CC
1306 #define IXGBE_RXDATAWRPTR(_i)	(0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1307 #define IXGBE_RXDESCWRPTR(_i)	(0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1308 #define IXGBE_RXDATARDPTR(_i)	(0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1309 #define IXGBE_RXDESCRDPTR(_i)	(0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1310 #define IXGBE_TXDATAWRPTR(_i)	(0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1311 #define IXGBE_TXDESCWRPTR(_i)	(0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1312 #define IXGBE_TXDATARDPTR(_i)	(0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1313 #define IXGBE_TXDESCRDPTR(_i)	(0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1314 #define IXGBE_PCIEECCCTL	0x1106C
1315 #define IXGBE_RXWRPTR(_i)	(0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1316 #define IXGBE_RXUSED(_i)	(0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1317 #define IXGBE_RXRDPTR(_i)	(0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1318 #define IXGBE_RXRDWRPTR(_i)	(0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1319 #define IXGBE_TXWRPTR(_i)	(0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1320 #define IXGBE_TXUSED(_i)	(0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1321 #define IXGBE_TXRDPTR(_i)	(0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1322 #define IXGBE_TXRDWRPTR(_i)	(0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1323 #define IXGBE_PCIEECCCTL0	0x11100
1324 #define IXGBE_PCIEECCCTL1	0x11104
1325 #define IXGBE_RXDBUECC		0x03F70
1326 #define IXGBE_TXDBUECC		0x0CF70
1327 #define IXGBE_RXDBUEST		0x03F74
1328 #define IXGBE_TXDBUEST		0x0CF74
1329 #define IXGBE_PBTXECC		0x0C300
1330 #define IXGBE_PBRXECC		0x03300
1331 #define IXGBE_GHECCR		0x110B0
1332 
1333 /* MAC Registers */
1334 #define IXGBE_PCS1GCFIG		0x04200
1335 #define IXGBE_PCS1GLCTL		0x04208
1336 #define IXGBE_PCS1GLSTA		0x0420C
1337 #define IXGBE_PCS1GDBG0		0x04210
1338 #define IXGBE_PCS1GDBG1		0x04214
1339 #define IXGBE_PCS1GANA		0x04218
1340 #define IXGBE_PCS1GANLP		0x0421C
1341 #define IXGBE_PCS1GANNP		0x04220
1342 #define IXGBE_PCS1GANLPNP	0x04224
1343 #define IXGBE_HLREG0		0x04240
1344 #define IXGBE_HLREG1		0x04244
1345 #define IXGBE_PAP		0x04248
1346 #define IXGBE_MACA		0x0424C
1347 #define IXGBE_APAE		0x04250
1348 #define IXGBE_ARD		0x04254
1349 #define IXGBE_AIS		0x04258
1350 #define IXGBE_MSCA		0x0425C
1351 #define IXGBE_MSRWD		0x04260
1352 #define IXGBE_MLADD		0x04264
1353 #define IXGBE_MHADD		0x04268
1354 #define IXGBE_MAXFRS		0x04268
1355 #define IXGBE_TREG		0x0426C
1356 #define IXGBE_PCSS1		0x04288
1357 #define IXGBE_PCSS2		0x0428C
1358 #define IXGBE_XPCSS		0x04290
1359 #define IXGBE_MFLCN		0x04294
1360 #define IXGBE_SERDESC		0x04298
1361 #define IXGBE_MAC_SGMII_BUSY	0x04298
1362 #define IXGBE_MACS		0x0429C
1363 #define IXGBE_AUTOC		0x042A0
1364 #define IXGBE_LINKS		0x042A4
1365 #define IXGBE_LINKS2		0x04324
1366 #define IXGBE_AUTOC2		0x042A8
1367 #define IXGBE_AUTOC3		0x042AC
1368 #define IXGBE_ANLP1		0x042B0
1369 #define IXGBE_ANLP2		0x042B4
1370 #define IXGBE_MACC		0x04330
1371 #define IXGBE_ATLASCTL		0x04800
1372 #define IXGBE_MMNGC		0x042D0
1373 #define IXGBE_ANLPNP1		0x042D4
1374 #define IXGBE_ANLPNP2		0x042D8
1375 #define IXGBE_KRPCSFC		0x042E0
1376 #define IXGBE_KRPCSS		0x042E4
1377 #define IXGBE_FECS1		0x042E8
1378 #define IXGBE_FECS2		0x042EC
1379 #define IXGBE_SMADARCTL		0x14F10
1380 #define IXGBE_MPVC		0x04318
1381 #define IXGBE_SGMIIC		0x04314
1382 
1383 /* Statistics Registers */
1384 #define IXGBE_RXNFGPC		0x041B0
1385 #define IXGBE_RXNFGBCL		0x041B4
1386 #define IXGBE_RXNFGBCH		0x041B8
1387 #define IXGBE_RXDGPC		0x02F50
1388 #define IXGBE_RXDGBCL		0x02F54
1389 #define IXGBE_RXDGBCH		0x02F58
1390 #define IXGBE_RXDDGPC		0x02F5C
1391 #define IXGBE_RXDDGBCL		0x02F60
1392 #define IXGBE_RXDDGBCH		0x02F64
1393 #define IXGBE_RXLPBKGPC		0x02F68
1394 #define IXGBE_RXLPBKGBCL	0x02F6C
1395 #define IXGBE_RXLPBKGBCH	0x02F70
1396 #define IXGBE_RXDLPBKGPC	0x02F74
1397 #define IXGBE_RXDLPBKGBCL	0x02F78
1398 #define IXGBE_RXDLPBKGBCH	0x02F7C
1399 #define IXGBE_TXDGPC		0x087A0
1400 #define IXGBE_TXDGBCL		0x087A4
1401 #define IXGBE_TXDGBCH		0x087A8
1402 
1403 #define IXGBE_RXDSTATCTRL	0x02F40
1404 
1405 /* Copper Pond 2 link timeout */
1406 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1407 
1408 /* Omer CORECTL */
1409 #define IXGBE_CORECTL			0x014F00
1410 /* BARCTRL */
1411 #define IXGBE_BARCTRL			0x110F4
1412 #define IXGBE_BARCTRL_FLSIZE		0x0700
1413 #define IXGBE_BARCTRL_FLSIZE_SHIFT	8
1414 #define IXGBE_BARCTRL_CSRSIZE		0x2000
1415 
1416 /* RSCCTL Bit Masks */
1417 #define IXGBE_RSCCTL_RSCEN	0x01
1418 #define IXGBE_RSCCTL_MAXDESC_1	0x00
1419 #define IXGBE_RSCCTL_MAXDESC_4	0x04
1420 #define IXGBE_RSCCTL_MAXDESC_8	0x08
1421 #define IXGBE_RSCCTL_MAXDESC_16	0x0C
1422 #define IXGBE_RSCCTL_TS_DIS	0x02
1423 
1424 /* RSCDBU Bit Masks */
1425 #define IXGBE_RSCDBU_RSCSMALDIS_MASK	0x0000007F
1426 #define IXGBE_RSCDBU_RSCACKDIS		0x00000080
1427 
1428 /* RDRXCTL Bit Masks */
1429 #define IXGBE_RDRXCTL_RDMTS_1_2		0x00000000 /* Rx Desc Min THLD Size */
1430 #define IXGBE_RDRXCTL_CRCSTRIP		0x00000002 /* CRC Strip */
1431 #define IXGBE_RDRXCTL_PSP		0x00000004 /* Pad Small Packet */
1432 #define IXGBE_RDRXCTL_MVMEN		0x00000020
1433 #define IXGBE_RDRXCTL_RSC_PUSH_DIS	0x00000020
1434 #define IXGBE_RDRXCTL_DMAIDONE		0x00000008 /* DMA init cycle done */
1435 #define IXGBE_RDRXCTL_RSC_PUSH		0x00000080
1436 #define IXGBE_RDRXCTL_AGGDIS		0x00010000 /* Aggregation disable */
1437 #define IXGBE_RDRXCTL_RSCFRSTSIZE	0x003E0000 /* RSC First packet size */
1438 #define IXGBE_RDRXCTL_RSCLLIDIS		0x00800000 /* Disable RSC compl on LLI*/
1439 #define IXGBE_RDRXCTL_RSCACKC		0x02000000 /* must set 1 when RSC ena */
1440 #define IXGBE_RDRXCTL_FCOE_WRFIX	0x04000000 /* must set 1 when RSC ena */
1441 #define IXGBE_RDRXCTL_MBINTEN		0x10000000
1442 #define IXGBE_RDRXCTL_MDP_EN		0x20000000
1443 
1444 /* RQTC Bit Masks and Shifts */
1445 #define IXGBE_RQTC_SHIFT_TC(_i)	((_i) * 4)
1446 #define IXGBE_RQTC_TC0_MASK	(0x7 << 0)
1447 #define IXGBE_RQTC_TC1_MASK	(0x7 << 4)
1448 #define IXGBE_RQTC_TC2_MASK	(0x7 << 8)
1449 #define IXGBE_RQTC_TC3_MASK	(0x7 << 12)
1450 #define IXGBE_RQTC_TC4_MASK	(0x7 << 16)
1451 #define IXGBE_RQTC_TC5_MASK	(0x7 << 20)
1452 #define IXGBE_RQTC_TC6_MASK	(0x7 << 24)
1453 #define IXGBE_RQTC_TC7_MASK	(0x7 << 28)
1454 
1455 /* PSRTYPE.RQPL Bit masks and shift */
1456 #define IXGBE_PSRTYPE_RQPL_MASK		0x7
1457 #define IXGBE_PSRTYPE_RQPL_SHIFT	29
1458 
1459 /* CTRL Bit Masks */
1460 #define IXGBE_CTRL_GIO_DIS	0x00000004 /* Global IO Master Disable bit */
1461 #define IXGBE_CTRL_LNK_RST	0x00000008 /* Link Reset. Resets everything. */
1462 #define IXGBE_CTRL_RST		0x04000000 /* Reset (SW) */
1463 #define IXGBE_CTRL_RST_MASK	(IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1464 
1465 /* FACTPS */
1466 #define IXGBE_FACTPS_MNGCG	0x20000000 /* Manageability Clock Gated */
1467 #define IXGBE_FACTPS_LFS	0x40000000 /* LAN Function Select */
1468 
1469 /* MHADD Bit Masks */
1470 #define IXGBE_MHADD_MFS_MASK	0xFFFF0000
1471 #define IXGBE_MHADD_MFS_SHIFT	16
1472 
1473 /* Extended Device Control */
1474 #define IXGBE_CTRL_EXT_PFRSTD	0x00004000 /* Physical Function Reset Done */
1475 #define IXGBE_CTRL_EXT_NS_DIS	0x00010000 /* No Snoop disable */
1476 #define IXGBE_CTRL_EXT_RO_DIS	0x00020000 /* Relaxed Ordering disable */
1477 #define IXGBE_CTRL_EXT_DRV_LOAD	0x10000000 /* Driver loaded bit for FW */
1478 
1479 /* Direct Cache Access (DCA) definitions */
1480 #define IXGBE_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
1481 #define IXGBE_DCA_CTRL_DCA_DISABLE	0x00000001 /* DCA Disable */
1482 
1483 #define IXGBE_DCA_CTRL_DCA_MODE_CB1	0x00 /* DCA Mode CB1 */
1484 #define IXGBE_DCA_CTRL_DCA_MODE_CB2	0x02 /* DCA Mode CB2 */
1485 
1486 #define IXGBE_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
1487 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599	0xFF000000 /* Rx CPUID Mask */
1488 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599	24 /* Rx CPUID Shift */
1489 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* Rx Desc enable */
1490 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* Rx Desc header ena */
1491 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* Rx Desc payload ena */
1492 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN	(1 << 9) /* Rx rd Desc Relax Order */
1493 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN	(1 << 13) /* Rx wr data Relax Order */
1494 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN	(1 << 15) /* Rx wr header RO */
1495 
1496 #define IXGBE_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
1497 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599	0xFF000000 /* Tx CPUID Mask */
1498 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599	24 /* Tx CPUID Shift */
1499 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
1500 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN	(1 << 9) /* Tx rd Desc Relax Order */
1501 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN	(1 << 11) /* Tx Desc writeback RO bit */
1502 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN	(1 << 13) /* Tx rd data Relax Order */
1503 #define IXGBE_DCA_MAX_QUEUES_82598	16 /* DCA regs only on 16 queues */
1504 
1505 /* MSCA Bit Masks */
1506 #define IXGBE_MSCA_NP_ADDR_MASK		0x0000FFFF /* MDI Addr (new prot) */
1507 #define IXGBE_MSCA_NP_ADDR_SHIFT	0
1508 #define IXGBE_MSCA_DEV_TYPE_MASK	0x001F0000 /* Dev Type (new prot) */
1509 #define IXGBE_MSCA_DEV_TYPE_SHIFT	16 /* Register Address (old prot */
1510 #define IXGBE_MSCA_PHY_ADDR_MASK	0x03E00000 /* PHY Address mask */
1511 #define IXGBE_MSCA_PHY_ADDR_SHIFT	21 /* PHY Address shift*/
1512 #define IXGBE_MSCA_OP_CODE_MASK		0x0C000000 /* OP CODE mask */
1513 #define IXGBE_MSCA_OP_CODE_SHIFT	26 /* OP CODE shift */
1514 #define IXGBE_MSCA_ADDR_CYCLE		0x00000000 /* OP CODE 00 (addr cycle) */
1515 #define IXGBE_MSCA_WRITE		0x04000000 /* OP CODE 01 (wr) */
1516 #define IXGBE_MSCA_READ			0x0C000000 /* OP CODE 11 (rd) */
1517 #define IXGBE_MSCA_READ_AUTOINC		0x08000000 /* OP CODE 10 (rd auto inc)*/
1518 #define IXGBE_MSCA_ST_CODE_MASK		0x30000000 /* ST Code mask */
1519 #define IXGBE_MSCA_ST_CODE_SHIFT	28 /* ST Code shift */
1520 #define IXGBE_MSCA_NEW_PROTOCOL		0x00000000 /* ST CODE 00 (new prot) */
1521 #define IXGBE_MSCA_OLD_PROTOCOL		0x10000000 /* ST CODE 01 (old prot) */
1522 #define IXGBE_MSCA_MDI_COMMAND		0x40000000 /* Initiate MDI command */
1523 #define IXGBE_MSCA_MDI_IN_PROG_EN	0x80000000 /* MDI in progress ena */
1524 
1525 /* MSRWD bit masks */
1526 #define IXGBE_MSRWD_WRITE_DATA_MASK	0x0000FFFF
1527 #define IXGBE_MSRWD_WRITE_DATA_SHIFT	0
1528 #define IXGBE_MSRWD_READ_DATA_MASK	0xFFFF0000
1529 #define IXGBE_MSRWD_READ_DATA_SHIFT	16
1530 
1531 /* Atlas registers */
1532 #define IXGBE_ATLAS_PDN_LPBK		0x24
1533 #define IXGBE_ATLAS_PDN_10G		0xB
1534 #define IXGBE_ATLAS_PDN_1G		0xC
1535 #define IXGBE_ATLAS_PDN_AN		0xD
1536 
1537 /* Atlas bit masks */
1538 #define IXGBE_ATLASCTL_WRITE_CMD	0x00010000
1539 #define IXGBE_ATLAS_PDN_TX_REG_EN	0x10
1540 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL	0xF0
1541 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL	0xF0
1542 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL	0xF0
1543 
1544 /* Omer bit masks */
1545 #define IXGBE_CORECTL_WRITE_CMD		0x00010000
1546 
1547 /* Device Type definitions for new protocol MDIO commands */
1548 #define IXGBE_MDIO_ZERO_DEV_TYPE		0x0
1549 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE		0x1
1550 #define IXGBE_MDIO_PCS_DEV_TYPE			0x3
1551 #define IXGBE_MDIO_PHY_XS_DEV_TYPE		0x4
1552 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE		0x7
1553 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE	0x1E   /* Device 30 */
1554 #define IXGBE_TWINAX_DEV			1
1555 
1556 #define IXGBE_MDIO_COMMAND_TIMEOUT	100 /* PHY Timeout for 1 GB mode */
1557 
1558 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL		0x0 /* VS1 Ctrl Reg */
1559 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS		0x1 /* VS1 Status Reg */
1560 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS	0x0008 /* 1 = Link Up */
1561 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS	0x0010 /* 0-10G, 1-1G */
1562 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED		0x0018
1563 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED		0x0010
1564 
1565 #define IXGBE_MDIO_AUTO_NEG_CONTROL	0x0 /* AUTO_NEG Control Reg */
1566 #define IXGBE_MDIO_AUTO_NEG_STATUS	0x1 /* AUTO_NEG Status Reg */
1567 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT	0xC800 /* AUTO_NEG Vendor Status Reg */
1568 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
1569 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1570 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC	0x1 /* AUTO_NEG Vendor Tx LSC */
1571 #define IXGBE_MDIO_AUTO_NEG_ADVT	0x10 /* AUTO_NEG Advt Reg */
1572 #define IXGBE_MDIO_AUTO_NEG_LP		0x13 /* AUTO_NEG LP Status Reg */
1573 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT	0x3C /* AUTO_NEG EEE Advt Reg */
1574 #define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT	0x8  /* AUTO NEG EEE 10GBaseT Advt */
1575 #define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4  /* AUTO NEG EEE 1000BaseT Advt */
1576 #define IXGBE_AUTO_NEG_100BASE_EEE_ADVT	0x2  /* AUTO NEG EEE 100BaseT Advt */
1577 #define IXGBE_MDIO_PHY_XS_CONTROL	0x0 /* PHY_XS Control Reg */
1578 #define IXGBE_MDIO_PHY_XS_RESET		0x8000 /* PHY_XS Reset */
1579 #define IXGBE_MDIO_PHY_ID_HIGH		0x2 /* PHY ID High Reg*/
1580 #define IXGBE_MDIO_PHY_ID_LOW		0x3 /* PHY ID Low Reg*/
1581 #define IXGBE_MDIO_PHY_SPEED_ABILITY	0x4 /* Speed Ability Reg */
1582 #define IXGBE_MDIO_PHY_SPEED_10G	0x0001 /* 10G capable */
1583 #define IXGBE_MDIO_PHY_SPEED_1G		0x0010 /* 1G capable */
1584 #define IXGBE_MDIO_PHY_SPEED_100M	0x0020 /* 100M capable */
1585 #define IXGBE_MDIO_PHY_EXT_ABILITY	0xB /* Ext Ability Reg */
1586 #define IXGBE_MDIO_PHY_10GBASET_ABILITY		0x0004 /* 10GBaseT capable */
1587 #define IXGBE_MDIO_PHY_1000BASET_ABILITY	0x0020 /* 1000BaseT capable */
1588 #define IXGBE_MDIO_PHY_100BASETX_ABILITY	0x0080 /* 100BaseTX capable */
1589 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE	0x0800 /* Set low power mode */
1590 #define IXGBE_AUTO_NEG_LP_STATUS	0xE820 /* AUTO NEG Rx LP Status Reg */
1591 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP	0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */
1592 #define IXGBE_AUTO_NEG_LP_10GBASE_CAP	0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */
1593 #define IXGBE_AUTO_NEG_10GBASET_STAT	0x0021 /* AUTO NEG 10G BaseT Stat */
1594 
1595 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3		0xCC02 /* Vendor Alarms 3 Reg */
1596 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK	0x3 /* PHY Reset Complete Mask */
1597 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1598 #define IXGBE_MDIO_POWER_UP_STALL		0x8000 /* Power Up Stall */
1599 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK	0xFF00 /* int std mask */
1600 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG	0xFC00 /* chip std int flag */
1601 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK	0xFF01 /* int chip-wide mask */
1602 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG	0xFC01 /* int chip-wide mask */
1603 #define IXGBE_MDIO_GLOBAL_ALARM_1		0xCC00 /* Global alarm 1 */
1604 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT	0x0010 /* device fault */
1605 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL	0x4000 /* high temp failure */
1606 #define IXGBE_MDIO_GLOBAL_FAULT_MSG		0xC850 /* Global Fault Message */
1607 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP	0x8007 /* high temp failure */
1608 #define IXGBE_MDIO_GLOBAL_INT_MASK		0xD400 /* Global int mask */
1609 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN	0x1000 /* autoneg vendor alarm int enable */
1610 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT		0x4 /* int in Global alarm 1 */
1611 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN	0x1 /* vendor alarm int enable */
1612 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT		0x200 /* vendor alarm2 int mask */
1613 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN	0x4000 /* int high temp enable */
1614 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */
1615 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR	0x0000 /* PMA/PMD Control Reg */
1616 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR	0xC30A /* PHY_XS SDA/SCL Addr Reg */
1617 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA	0xC30B /* PHY_XS SDA/SCL Data Reg */
1618 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT	0xC30C /* PHY_XS SDA/SCL Status Reg */
1619 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1620 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN   0x1 /* PHY TX Vendor LASI enable */
1621 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1622 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
1623 
1624 #define IXGBE_PCRC8ECL		0x0E810 /* PCR CRC-8 Error Count Lo */
1625 #define IXGBE_PCRC8ECH		0x0E811 /* PCR CRC-8 Error Count Hi */
1626 #define IXGBE_PCRC8ECH_MASK	0x1F
1627 #define IXGBE_LDPCECL		0x0E820 /* PCR Uncorrected Error Count Lo */
1628 #define IXGBE_LDPCECH		0x0E821 /* PCR Uncorrected Error Count Hi */
1629 
1630 /* MII clause 22/28 definitions */
1631 #define IXGBE_MDIO_PHY_LOW_POWER_MODE	0x0800
1632 
1633 #define IXGBE_MDIO_XENPAK_LASI_STATUS		0x9005 /* XENPAK LASI Status register*/
1634 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM	0x1 /* Link Status Alarm change */
1635 
1636 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS		0x4 /* Indicates if link is up */
1637 
1638 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK	0x7 /* Speed/Duplex Mask */
1639 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK		0x6 /* Speed Mask */
1640 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF	0x0 /* 10Mb/s Half Duplex */
1641 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL	0x1 /* 10Mb/s Full Duplex */
1642 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF	0x2 /* 100Mb/s Half Duplex */
1643 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL	0x3 /* 100Mb/s Full Duplex */
1644 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF	0x4 /* 1Gb/s Half Duplex */
1645 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL	0x5 /* 1Gb/s Full Duplex */
1646 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF	0x6 /* 10Gb/s Half Duplex */
1647 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL	0x7 /* 10Gb/s Full Duplex */
1648 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB		0x4 /* 1Gb/s */
1649 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB		0x6 /* 10Gb/s */
1650 
1651 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG	0x20   /* 10G Control Reg */
1652 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1653 #define IXGBE_MII_AUTONEG_XNP_TX_REG		0x17   /* 1G XNP Transmit */
1654 #define IXGBE_MII_AUTONEG_ADVERTISE_REG		0x10   /* 100M Advertisement */
1655 #define IXGBE_MII_10GBASE_T_ADVERTISE		0x1000 /* full duplex, bit:12*/
1656 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX	0x4000 /* full duplex, bit:14*/
1657 #define IXGBE_MII_1GBASE_T_ADVERTISE		0x8000 /* full duplex, bit:15*/
1658 #define IXGBE_MII_2_5GBASE_T_ADVERTISE		0x0400
1659 #define IXGBE_MII_5GBASE_T_ADVERTISE		0x0800
1660 #define IXGBE_MII_100BASE_T_ADVERTISE		0x0100 /* full duplex, bit:8 */
1661 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF	0x0080 /* half duplex, bit:7 */
1662 #define IXGBE_MII_RESTART			0x200
1663 #define IXGBE_MII_AUTONEG_COMPLETE		0x20
1664 #define IXGBE_MII_AUTONEG_LINK_UP		0x04
1665 #define IXGBE_MII_AUTONEG_REG			0x0
1666 
1667 #define IXGBE_PHY_REVISION_MASK		0xFFFFFFF0
1668 #define IXGBE_MAX_PHY_ADDR		32
1669 
1670 /* PHY IDs*/
1671 #define TN1010_PHY_ID	0x00A19410
1672 #define TNX_FW_REV	0xB
1673 #define X540_PHY_ID	0x01540200
1674 #define X550_PHY_ID2	0x01540223
1675 #define X550_PHY_ID3	0x01540221
1676 #define X557_PHY_ID	0x01540240
1677 #define X557_PHY_ID2	0x01540250
1678 #define AQ_FW_REV	0x20
1679 #define QT2022_PHY_ID	0x0043A400
1680 #define ATH_PHY_ID	0x03429050
1681 
1682 /* PHY Types */
1683 #define IXGBE_M88E1500_E_PHY_ID	0x01410DD0
1684 #define IXGBE_M88E1543_E_PHY_ID	0x01410EA0
1685 
1686 /* Special PHY Init Routine */
1687 #define IXGBE_PHY_INIT_OFFSET_NL	0x002B
1688 #define IXGBE_PHY_INIT_END_NL		0xFFFF
1689 #define IXGBE_CONTROL_MASK_NL		0xF000
1690 #define IXGBE_DATA_MASK_NL		0x0FFF
1691 #define IXGBE_CONTROL_SHIFT_NL		12
1692 #define IXGBE_DELAY_NL			0
1693 #define IXGBE_DATA_NL			1
1694 #define IXGBE_CONTROL_NL		0x000F
1695 #define IXGBE_CONTROL_EOL_NL		0x0FFF
1696 #define IXGBE_CONTROL_SOL_NL		0x0000
1697 
1698 /* General purpose Interrupt Enable */
1699 #define IXGBE_SDP0_GPIEN	0x00000001 /* SDP0 */
1700 #define IXGBE_SDP1_GPIEN	0x00000002 /* SDP1 */
1701 #define IXGBE_SDP2_GPIEN	0x00000004 /* SDP2 */
1702 #define IXGBE_SDP0_GPIEN_X540	0x00000002 /* SDP0 on X540 and X550 */
1703 #define IXGBE_SDP1_GPIEN_X540	0x00000004 /* SDP1 on X540 and X550 */
1704 #define IXGBE_SDP2_GPIEN_X540	0x00000008 /* SDP2 on X540 and X550 */
1705 #define IXGBE_SDP0_GPIEN_X550	IXGBE_SDP0_GPIEN_X540
1706 #define IXGBE_SDP1_GPIEN_X550	IXGBE_SDP1_GPIEN_X540
1707 #define IXGBE_SDP2_GPIEN_X550	IXGBE_SDP2_GPIEN_X540
1708 #define IXGBE_SDP0_GPIEN_X550EM_x	IXGBE_SDP0_GPIEN_X540
1709 #define IXGBE_SDP1_GPIEN_X550EM_x	IXGBE_SDP1_GPIEN_X540
1710 #define IXGBE_SDP2_GPIEN_X550EM_x	IXGBE_SDP2_GPIEN_X540
1711 #define IXGBE_SDP0_GPIEN_X550EM_a	IXGBE_SDP0_GPIEN_X540
1712 #define IXGBE_SDP1_GPIEN_X550EM_a	IXGBE_SDP1_GPIEN_X540
1713 #define IXGBE_SDP2_GPIEN_X550EM_a	IXGBE_SDP2_GPIEN_X540
1714 #define IXGBE_SDP0_GPIEN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1715 #define IXGBE_SDP1_GPIEN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1716 #define IXGBE_SDP2_GPIEN_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1717 
1718 #define IXGBE_GPIE_MSIX_MODE	0x00000010 /* MSI-X mode */
1719 #define IXGBE_GPIE_OCD		0x00000020 /* Other Clear Disable */
1720 #define IXGBE_GPIE_EIMEN	0x00000040 /* Immediate Interrupt Enable */
1721 #define IXGBE_GPIE_EIAME	0x40000000
1722 #define IXGBE_GPIE_PBA_SUPPORT	0x80000000
1723 #define IXGBE_GPIE_LLI_DELAY_SHIFT  7
1724 #define IXGBE_GPIE_RSC_DELAY_SHIFT	11
1725 #define IXGBE_GPIE_VTMODE_MASK	0x0000C000 /* VT Mode Mask */
1726 #define IXGBE_GPIE_VTMODE_16	0x00004000 /* 16 VFs 8 queues per VF */
1727 #define IXGBE_GPIE_VTMODE_32	0x00008000 /* 32 VFs 4 queues per VF */
1728 #define IXGBE_GPIE_VTMODE_64	0x0000C000 /* 64 VFs 2 queues per VF */
1729 
1730 /* Packet Buffer Initialization */
1731 #define IXGBE_MAX_PACKET_BUFFERS	8
1732 
1733 #define IXGBE_TXPBSIZE_20KB	0x00005000 /* 20KB Packet Buffer */
1734 #define IXGBE_TXPBSIZE_40KB	0x0000A000 /* 40KB Packet Buffer */
1735 #define IXGBE_RXPBSIZE_48KB	0x0000C000 /* 48KB Packet Buffer */
1736 #define IXGBE_RXPBSIZE_64KB	0x00010000 /* 64KB Packet Buffer */
1737 #define IXGBE_RXPBSIZE_80KB	0x00014000 /* 80KB Packet Buffer */
1738 #define IXGBE_RXPBSIZE_128KB	0x00020000 /* 128KB Packet Buffer */
1739 #define IXGBE_RXPBSIZE_MAX	0x00080000 /* 512KB Packet Buffer */
1740 #define IXGBE_TXPBSIZE_MAX	0x00028000 /* 160KB Packet Buffer */
1741 
1742 #define IXGBE_TXPKT_SIZE_MAX	0xA /* Max Tx Packet size */
1743 #define IXGBE_MAX_PB		8
1744 
1745 /* Packet buffer allocation strategies */
1746 enum {
1747 	PBA_STRATEGY_EQUAL	= 0, /* Distribute PB space equally */
1748 #define PBA_STRATEGY_EQUAL	PBA_STRATEGY_EQUAL
1749 	PBA_STRATEGY_WEIGHTED	= 1, /* Weight front half of TCs */
1750 #define PBA_STRATEGY_WEIGHTED	PBA_STRATEGY_WEIGHTED
1751 };
1752 
1753 /* Transmit Flow Control status */
1754 #define IXGBE_TFCS_TXON  0x00000001
1755 #define IXGBE_TFCS_TXOFF	0x00000001
1756 #define IXGBE_TFCS_TXOFF0	0x00000100
1757 #define IXGBE_TFCS_TXOFF1	0x00000200
1758 #define IXGBE_TFCS_TXOFF2	0x00000400
1759 #define IXGBE_TFCS_TXOFF3	0x00000800
1760 #define IXGBE_TFCS_TXOFF4	0x00001000
1761 #define IXGBE_TFCS_TXOFF5	0x00002000
1762 #define IXGBE_TFCS_TXOFF6	0x00004000
1763 #define IXGBE_TFCS_TXOFF7	0x00008000
1764 
1765 /* TCP Timer */
1766 #define IXGBE_TCPTIMER_KS		0x00000100
1767 #define IXGBE_TCPTIMER_COUNT_ENABLE	0x00000200
1768 #define IXGBE_TCPTIMER_COUNT_FINISH	0x00000400
1769 #define IXGBE_TCPTIMER_LOOP		0x00000800
1770 #define IXGBE_TCPTIMER_DURATION_MASK	0x000000FF
1771 
1772 /* HLREG0 Bit Masks */
1773 #define IXGBE_HLREG0_TXCRCEN		0x00000001 /* bit  0 */
1774 #define IXGBE_HLREG0_RXCRCSTRP		0x00000002 /* bit  1 */
1775 #define IXGBE_HLREG0_JUMBOEN		0x00000004 /* bit  2 */
1776 #define IXGBE_HLREG0_TXPADEN		0x00000400 /* bit 10 */
1777 #define IXGBE_HLREG0_TXPAUSEEN		0x00001000 /* bit 12 */
1778 #define IXGBE_HLREG0_RXPAUSEEN		0x00004000 /* bit 14 */
1779 #define IXGBE_HLREG0_LPBK		0x00008000 /* bit 15 */
1780 #define IXGBE_HLREG0_MDCSPD		0x00010000 /* bit 16 */
1781 #define IXGBE_HLREG0_CONTMDC		0x00020000 /* bit 17 */
1782 #define IXGBE_HLREG0_CTRLFLTR		0x00040000 /* bit 18 */
1783 #define IXGBE_HLREG0_PREPEND		0x00F00000 /* bits 20-23 */
1784 #define IXGBE_HLREG0_PRIPAUSEEN		0x01000000 /* bit 24 */
1785 #define IXGBE_HLREG0_RXPAUSERECDA	0x06000000 /* bits 25-26 */
1786 #define IXGBE_HLREG0_RXLNGTHERREN	0x08000000 /* bit 27 */
1787 #define IXGBE_HLREG0_RXPADSTRIPEN	0x10000000 /* bit 28 */
1788 
1789 /* VMD_CTL bitmasks */
1790 #define IXGBE_VMD_CTL_VMDQ_EN		0x00000001
1791 #define IXGBE_VMD_CTL_VMDQ_FILTER	0x00000002
1792 
1793 /* VT_CTL bitmasks */
1794 #define IXGBE_VT_CTL_DIS_DEFPL		0x20000000 /* disable default pool */
1795 #define IXGBE_VT_CTL_REPLEN		0x40000000 /* replication enabled */
1796 #define IXGBE_VT_CTL_VT_ENABLE		0x00000001  /* Enable VT Mode */
1797 #define IXGBE_VT_CTL_POOL_SHIFT		7
1798 #define IXGBE_VT_CTL_POOL_MASK		(0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1799 
1800 /* VMOLR bitmasks */
1801 #define IXGBE_VMOLR_UPE		0x00400000 /* unicast promiscuous */
1802 #define IXGBE_VMOLR_VPE		0x00800000 /* VLAN promiscuous */
1803 #define IXGBE_VMOLR_AUPE	0x01000000 /* accept untagged packets */
1804 #define IXGBE_VMOLR_ROMPE	0x02000000 /* accept packets in MTA tbl */
1805 #define IXGBE_VMOLR_ROPE	0x04000000 /* accept packets in UC tbl */
1806 #define IXGBE_VMOLR_BAM		0x08000000 /* accept broadcast packets */
1807 #define IXGBE_VMOLR_MPE		0x10000000 /* multicast promiscuous */
1808 
1809 /* VFRE bitmask */
1810 #define IXGBE_VFRE_ENABLE_ALL	0xFFFFFFFF
1811 
1812 #define IXGBE_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
1813 
1814 /* RDHMPN and TDHMPN bitmasks */
1815 #define IXGBE_RDHMPN_RDICADDR		0x007FF800
1816 #define IXGBE_RDHMPN_RDICRDREQ		0x00800000
1817 #define IXGBE_RDHMPN_RDICADDR_SHIFT	11
1818 #define IXGBE_TDHMPN_TDICADDR		0x003FF800
1819 #define IXGBE_TDHMPN_TDICRDREQ		0x00800000
1820 #define IXGBE_TDHMPN_TDICADDR_SHIFT	11
1821 
1822 #define IXGBE_RDMAM_MEM_SEL_SHIFT		13
1823 #define IXGBE_RDMAM_DWORD_SHIFT			9
1824 #define IXGBE_RDMAM_DESC_COMP_FIFO		1
1825 #define IXGBE_RDMAM_DFC_CMD_FIFO		2
1826 #define IXGBE_RDMAM_RSC_HEADER_ADDR		3
1827 #define IXGBE_RDMAM_TCN_STATUS_RAM		4
1828 #define IXGBE_RDMAM_WB_COLL_FIFO		5
1829 #define IXGBE_RDMAM_QSC_CNT_RAM			6
1830 #define IXGBE_RDMAM_QSC_FCOE_RAM		7
1831 #define IXGBE_RDMAM_QSC_QUEUE_CNT		8
1832 #define IXGBE_RDMAM_QSC_QUEUE_RAM		0xA
1833 #define IXGBE_RDMAM_QSC_RSC_RAM			0xB
1834 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE		135
1835 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT		4
1836 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE		48
1837 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT		7
1838 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE	32
1839 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT	4
1840 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE	256
1841 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT	9
1842 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE		8
1843 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT		4
1844 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE		64
1845 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT		4
1846 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE		512
1847 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT		5
1848 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE		32
1849 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT		4
1850 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE		128
1851 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT		8
1852 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE		32
1853 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT		8
1854 
1855 #define IXGBE_TXDESCIC_READY	0x80000000
1856 
1857 /* Receive Checksum Control */
1858 #define IXGBE_RXCSUM_IPPCSE	0x00001000 /* IP payload checksum enable */
1859 #define IXGBE_RXCSUM_PCSD	0x00002000 /* packet checksum disabled */
1860 
1861 /* FCRTL Bit Masks */
1862 #define IXGBE_FCRTL_XONE	0x80000000 /* XON enable */
1863 #define IXGBE_FCRTH_FCEN	0x80000000 /* Packet buffer fc enable */
1864 
1865 /* PAP bit masks*/
1866 #define IXGBE_PAP_TXPAUSECNT_MASK	0x0000FFFF /* Pause counter mask */
1867 
1868 /* RMCS Bit Masks */
1869 #define IXGBE_RMCS_RRM			0x00000002 /* Rx Recycle Mode enable */
1870 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1871 #define IXGBE_RMCS_RAC			0x00000004
1872 /* Deficit Fixed Prio ena */
1873 #define IXGBE_RMCS_DFP			IXGBE_RMCS_RAC
1874 #define IXGBE_RMCS_TFCE_802_3X		0x00000008 /* Tx Priority FC ena */
1875 #define IXGBE_RMCS_TFCE_PRIORITY	0x00000010 /* Tx Priority FC ena */
1876 #define IXGBE_RMCS_ARBDIS		0x00000040 /* Arbitration disable bit */
1877 
1878 /* FCCFG Bit Masks */
1879 #define IXGBE_FCCFG_TFCE_802_3X		0x00000008 /* Tx link FC enable */
1880 #define IXGBE_FCCFG_TFCE_PRIORITY	0x00000010 /* Tx priority FC enable */
1881 
1882 /* Interrupt register bitmasks */
1883 
1884 /* Extended Interrupt Cause Read */
1885 #define IXGBE_EICR_RTX_QUEUE	0x0000FFFF /* RTx Queue Interrupt */
1886 #define IXGBE_EICR_FLOW_DIR	0x00010000 /* FDir Exception */
1887 #define IXGBE_EICR_RX_MISS	0x00020000 /* Packet Buffer Overrun */
1888 #define IXGBE_EICR_PCI		0x00040000 /* PCI Exception */
1889 #define IXGBE_EICR_MAILBOX	0x00080000 /* VF to PF Mailbox Interrupt */
1890 #define IXGBE_EICR_LSC		0x00100000 /* Link Status Change */
1891 #define IXGBE_EICR_LINKSEC	0x00200000 /* PN Threshold */
1892 #define IXGBE_EICR_MNG		0x00400000 /* Manageability Event Interrupt */
1893 #define IXGBE_EICR_TS		0x00800000 /* Thermal Sensor Event */
1894 #define IXGBE_EICR_TIMESYNC	0x01000000 /* Timesync Event */
1895 #define IXGBE_EICR_GPI_SDP0	0x01000000 /* Gen Purpose Interrupt on SDP0 */
1896 #define IXGBE_EICR_GPI_SDP1	0x02000000 /* Gen Purpose Interrupt on SDP1 */
1897 #define IXGBE_EICR_GPI_SDP2	0x04000000 /* Gen Purpose Interrupt on SDP2 */
1898 #define IXGBE_EICR_ECC		0x10000000 /* ECC Error */
1899 #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */
1900 #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1901 #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1902 #define IXGBE_EIMS_GPI_SDP0_X540 IXGBE_EICR_GPI_SDP0_X540 /* deprecated */
1903 #define IXGBE_EIMS_GPI_SDP1_X540 IXGBE_EICR_GPI_SDP1_X540 /* deprecated */
1904 #define IXGBE_EIMS_GPI_SDP2_X540 IXGBE_EICR_GPI_SDP2_X540 /* deprecated */
1905 #define IXGBE_EICR_GPI_SDP0_X550	IXGBE_EICR_GPI_SDP0_X540
1906 #define IXGBE_EICR_GPI_SDP1_X550	IXGBE_EICR_GPI_SDP1_X540
1907 #define IXGBE_EICR_GPI_SDP2_X550	IXGBE_EICR_GPI_SDP2_X540
1908 #define IXGBE_EICR_GPI_SDP0_X550EM_x	IXGBE_EICR_GPI_SDP0_X540
1909 #define IXGBE_EICR_GPI_SDP1_X550EM_x	IXGBE_EICR_GPI_SDP1_X540
1910 #define IXGBE_EICR_GPI_SDP2_X550EM_x	IXGBE_EICR_GPI_SDP2_X540
1911 #define IXGBE_EICR_GPI_SDP0_X550EM_a	IXGBE_EICR_GPI_SDP0_X540
1912 #define IXGBE_EICR_GPI_SDP1_X550EM_a	IXGBE_EICR_GPI_SDP1_X540
1913 #define IXGBE_EICR_GPI_SDP2_X550EM_a	IXGBE_EICR_GPI_SDP2_X540
1914 #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1915 #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1916 #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)	IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1917 
1918 #define IXGBE_EICR_PBUR		0x10000000 /* Packet Buffer Handler Error */
1919 #define IXGBE_EICR_DHER		0x20000000 /* Descriptor Handler Error */
1920 #define IXGBE_EICR_TCP_TIMER	0x40000000 /* TCP Timer */
1921 #define IXGBE_EICR_OTHER	0x80000000 /* Interrupt Cause Active */
1922 
1923 /* Extended Interrupt Cause Set */
1924 #define IXGBE_EICS_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1925 #define IXGBE_EICS_FLOW_DIR	IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1926 #define IXGBE_EICS_RX_MISS	IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1927 #define IXGBE_EICS_PCI		IXGBE_EICR_PCI /* PCI Exception */
1928 #define IXGBE_EICS_MAILBOX	IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1929 #define IXGBE_EICS_LSC		IXGBE_EICR_LSC /* Link Status Change */
1930 #define IXGBE_EICS_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
1931 #define IXGBE_EICS_TIMESYNC	IXGBE_EICR_TIMESYNC /* Timesync Event */
1932 #define IXGBE_EICS_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1933 #define IXGBE_EICS_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1934 #define IXGBE_EICS_GPI_SDP2	IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1935 #define IXGBE_EICS_ECC		IXGBE_EICR_ECC /* ECC Error */
1936 #define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1937 #define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1938 #define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1939 #define IXGBE_EICS_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1940 #define IXGBE_EICS_DHER		IXGBE_EICR_DHER /* Desc Handler Error */
1941 #define IXGBE_EICS_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
1942 #define IXGBE_EICS_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
1943 
1944 /* Extended Interrupt Mask Set */
1945 #define IXGBE_EIMS_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1946 #define IXGBE_EIMS_FLOW_DIR	IXGBE_EICR_FLOW_DIR /* FDir Exception */
1947 #define IXGBE_EIMS_RX_MISS	IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1948 #define IXGBE_EIMS_PCI		IXGBE_EICR_PCI /* PCI Exception */
1949 #define IXGBE_EIMS_MAILBOX	IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1950 #define IXGBE_EIMS_LSC		IXGBE_EICR_LSC /* Link Status Change */
1951 #define IXGBE_EIMS_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
1952 #define IXGBE_EIMS_TS		IXGBE_EICR_TS /* Thermal Sensor Event */
1953 #define IXGBE_EIMS_TIMESYNC	IXGBE_EICR_TIMESYNC /* Timesync Event */
1954 #define IXGBE_EIMS_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1955 #define IXGBE_EIMS_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1956 #define IXGBE_EIMS_GPI_SDP2	IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1957 #define IXGBE_EIMS_ECC		IXGBE_EICR_ECC /* ECC Error */
1958 #define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1959 #define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1960 #define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1961 #define IXGBE_EIMS_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1962 #define IXGBE_EIMS_DHER		IXGBE_EICR_DHER /* Descr Handler Error */
1963 #define IXGBE_EIMS_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
1964 #define IXGBE_EIMS_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
1965 
1966 /* Extended Interrupt Mask Clear */
1967 #define IXGBE_EIMC_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1968 #define IXGBE_EIMC_FLOW_DIR	IXGBE_EICR_FLOW_DIR /* FDir Exception */
1969 #define IXGBE_EIMC_RX_MISS	IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1970 #define IXGBE_EIMC_PCI		IXGBE_EICR_PCI /* PCI Exception */
1971 #define IXGBE_EIMC_MAILBOX	IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1972 #define IXGBE_EIMC_LSC		IXGBE_EICR_LSC /* Link Status Change */
1973 #define IXGBE_EIMC_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
1974 #define IXGBE_EIMC_TIMESYNC	IXGBE_EICR_TIMESYNC /* Timesync Event */
1975 #define IXGBE_EIMC_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1976 #define IXGBE_EIMC_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1977 #define IXGBE_EIMC_GPI_SDP2	IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1978 #define IXGBE_EIMC_ECC		IXGBE_EICR_ECC /* ECC Error */
1979 #define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1980 #define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1981 #define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw)	IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1982 #define IXGBE_EIMC_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1983 #define IXGBE_EIMC_DHER		IXGBE_EICR_DHER /* Desc Handler Err */
1984 #define IXGBE_EIMC_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
1985 #define IXGBE_EIMC_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
1986 
1987 #define IXGBE_EIMS_ENABLE_MASK ( \
1988 				IXGBE_EIMS_RTX_QUEUE	| \
1989 				IXGBE_EIMS_LSC		| \
1990 				IXGBE_EIMS_TCP_TIMER	| \
1991 				IXGBE_EIMS_OTHER)
1992 
1993 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1994 #define IXGBE_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
1995 #define IXGBE_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
1996 #define IXGBE_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
1997 #define IXGBE_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
1998 #define IXGBE_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
1999 #define IXGBE_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
2000 #define IXGBE_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
2001 #define IXGBE_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
2002 #define IXGBE_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
2003 #define IXGBE_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of control bits */
2004 #define IXGBE_IMIR_SIZE_BP_82599	0x00001000 /* Packet size bypass */
2005 #define IXGBE_IMIR_CTRL_URG_82599	0x00002000 /* Check URG bit in header */
2006 #define IXGBE_IMIR_CTRL_ACK_82599	0x00004000 /* Check ACK bit in header */
2007 #define IXGBE_IMIR_CTRL_PSH_82599	0x00008000 /* Check PSH bit in header */
2008 #define IXGBE_IMIR_CTRL_RST_82599	0x00010000 /* Check RST bit in header */
2009 #define IXGBE_IMIR_CTRL_SYN_82599	0x00020000 /* Check SYN bit in header */
2010 #define IXGBE_IMIR_CTRL_FIN_82599	0x00040000 /* Check FIN bit in header */
2011 #define IXGBE_IMIR_CTRL_BP_82599	0x00080000 /* Bypass chk of ctrl bits */
2012 #define IXGBE_IMIR_LLI_EN_82599		0x00100000 /* Enables low latency Int */
2013 #define IXGBE_IMIR_RX_QUEUE_MASK_82599	0x0000007F /* Rx Queue Mask */
2014 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599	21 /* Rx Queue Shift */
2015 #define IXGBE_IMIRVP_PRIORITY_MASK	0x00000007 /* VLAN priority mask */
2016 #define IXGBE_IMIRVP_PRIORITY_EN	0x00000008 /* VLAN priority enable */
2017 
2018 #define IXGBE_MAX_FTQF_FILTERS		128
2019 #define IXGBE_FTQF_PROTOCOL_MASK	0x00000003
2020 #define IXGBE_FTQF_PROTOCOL_TCP		0x00000000
2021 #define IXGBE_FTQF_PROTOCOL_UDP		0x00000001
2022 #define IXGBE_FTQF_PROTOCOL_SCTP	2
2023 #define IXGBE_FTQF_PRIORITY_MASK	0x00000007
2024 #define IXGBE_FTQF_PRIORITY_SHIFT	2
2025 #define IXGBE_FTQF_POOL_MASK		0x0000003F
2026 #define IXGBE_FTQF_POOL_SHIFT		8
2027 #define IXGBE_FTQF_5TUPLE_MASK_MASK	0x0000001F
2028 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT	25
2029 #define IXGBE_FTQF_SOURCE_ADDR_MASK	0x1E
2030 #define IXGBE_FTQF_DEST_ADDR_MASK	0x1D
2031 #define IXGBE_FTQF_SOURCE_PORT_MASK	0x1B
2032 #define IXGBE_FTQF_DEST_PORT_MASK	0x17
2033 #define IXGBE_FTQF_PROTOCOL_COMP_MASK	0x0F
2034 #define IXGBE_FTQF_POOL_MASK_EN		0x40000000
2035 #define IXGBE_FTQF_QUEUE_ENABLE		0x80000000
2036 
2037 /* Interrupt clear mask */
2038 #define IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
2039 
2040 /* Interrupt Vector Allocation Registers */
2041 #define IXGBE_IVAR_REG_NUM		25
2042 #define IXGBE_IVAR_REG_NUM_82599	64
2043 #define IXGBE_IVAR_TXRX_ENTRY		96
2044 #define IXGBE_IVAR_RX_ENTRY		64
2045 #define IXGBE_IVAR_RX_QUEUE(_i)		(0 + (_i))
2046 #define IXGBE_IVAR_TX_QUEUE(_i)		(64 + (_i))
2047 #define IXGBE_IVAR_TX_ENTRY		32
2048 
2049 #define IXGBE_IVAR_TCP_TIMER_INDEX	96 /* 0 based index */
2050 #define IXGBE_IVAR_OTHER_CAUSES_INDEX	97 /* 0 based index */
2051 
2052 #define IXGBE_MSIX_VECTOR(_i)		(0 + (_i))
2053 
2054 #define IXGBE_IVAR_ALLOC_VAL		0x80 /* Interrupt Allocation valid */
2055 
2056 /* ETYPE Queue Filter/Select Bit Masks */
2057 #define IXGBE_MAX_ETQF_FILTERS		8
2058 #define IXGBE_ETQF_FCOE			0x08000000 /* bit 27 */
2059 #define IXGBE_ETQF_BCN			0x10000000 /* bit 28 */
2060 #define IXGBE_ETQF_TX_ANTISPOOF		0x20000000 /* bit 29 */
2061 #define IXGBE_ETQF_1588			0x40000000 /* bit 30 */
2062 #define IXGBE_ETQF_FILTER_EN		0x80000000 /* bit 31 */
2063 #define IXGBE_ETQF_POOL_ENABLE		(1 << 26) /* bit 26 */
2064 #define IXGBE_ETQF_POOL_SHIFT		20
2065 
2066 #define IXGBE_ETQS_RX_QUEUE		0x007F0000 /* bits 22:16 */
2067 #define IXGBE_ETQS_RX_QUEUE_SHIFT	16
2068 #define IXGBE_ETQS_LLI			0x20000000 /* bit 29 */
2069 #define IXGBE_ETQS_QUEUE_EN		0x80000000 /* bit 31 */
2070 
2071 /*
2072  * ETQF filter list: one static filter per filter consumer. This is
2073  *		   to avoid filter collisions later. Add new filters
2074  *		   here!!
2075  *
2076  * Current filters:
2077  *	EAPOL 802.1x (0x888e): Filter 0
2078  *	FCoE (0x8906):	 Filter 2
2079  *	1588 (0x88f7):	 Filter 3
2080  *	FIP  (0x8914):	 Filter 4
2081  *	LLDP (0x88CC):	 Filter 5
2082  *	LACP (0x8809):	 Filter 6
2083  *	FC   (0x8808):	 Filter 7
2084  */
2085 #define IXGBE_ETQF_FILTER_EAPOL		0
2086 #define IXGBE_ETQF_FILTER_FCOE		2
2087 #define IXGBE_ETQF_FILTER_1588		3
2088 #define IXGBE_ETQF_FILTER_FIP		4
2089 #define IXGBE_ETQF_FILTER_LLDP		5
2090 #define IXGBE_ETQF_FILTER_LACP		6
2091 #define IXGBE_ETQF_FILTER_FC		7
2092 /* VLAN Control Bit Masks */
2093 #define IXGBE_VLNCTRL_VET		0x0000FFFF  /* bits 0-15 */
2094 #define IXGBE_VLNCTRL_CFI		0x10000000  /* bit 28 */
2095 #define IXGBE_VLNCTRL_CFIEN		0x20000000  /* bit 29 */
2096 #define IXGBE_VLNCTRL_VFE		0x40000000  /* bit 30 */
2097 #define IXGBE_VLNCTRL_VME		0x80000000  /* bit 31 */
2098 
2099 /* VLAN pool filtering masks */
2100 #define IXGBE_VLVF_VIEN			0x80000000  /* filter is valid */
2101 #define IXGBE_VLVF_ENTRIES		64
2102 #define IXGBE_VLVF_VLANID_MASK		0x00000FFF
2103 /* Per VF Port VLAN insertion rules */
2104 #define IXGBE_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
2105 #define IXGBE_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
2106 
2107 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE	0x8100  /* 802.1q protocol */
2108 
2109 /* STATUS Bit Masks */
2110 #define IXGBE_STATUS_LAN_ID		0x0000000C /* LAN ID */
2111 #define IXGBE_STATUS_LAN_ID_SHIFT	2 /* LAN ID Shift*/
2112 #define IXGBE_STATUS_GIO		0x00080000 /* GIO Master Ena Status */
2113 
2114 #define IXGBE_STATUS_LAN_ID_0	0x00000000 /* LAN ID 0 */
2115 #define IXGBE_STATUS_LAN_ID_1	0x00000004 /* LAN ID 1 */
2116 
2117 /* ESDP Bit Masks */
2118 #define IXGBE_ESDP_SDP0		0x00000001 /* SDP0 Data Value */
2119 #define IXGBE_ESDP_SDP1		0x00000002 /* SDP1 Data Value */
2120 #define IXGBE_ESDP_SDP2		0x00000004 /* SDP2 Data Value */
2121 #define IXGBE_ESDP_SDP3		0x00000008 /* SDP3 Data Value */
2122 #define IXGBE_ESDP_SDP4		0x00000010 /* SDP4 Data Value */
2123 #define IXGBE_ESDP_SDP5		0x00000020 /* SDP5 Data Value */
2124 #define IXGBE_ESDP_SDP6		0x00000040 /* SDP6 Data Value */
2125 #define IXGBE_ESDP_SDP7		0x00000080 /* SDP7 Data Value */
2126 #define IXGBE_ESDP_SDP0_DIR	0x00000100 /* SDP0 IO direction */
2127 #define IXGBE_ESDP_SDP1_DIR	0x00000200 /* SDP1 IO direction */
2128 #define IXGBE_ESDP_SDP2_DIR	0x00000400 /* SDP1 IO direction */
2129 #define IXGBE_ESDP_SDP3_DIR	0x00000800 /* SDP3 IO direction */
2130 #define IXGBE_ESDP_SDP4_DIR	0x00001000 /* SDP4 IO direction */
2131 #define IXGBE_ESDP_SDP5_DIR	0x00002000 /* SDP5 IO direction */
2132 #define IXGBE_ESDP_SDP6_DIR	0x00004000 /* SDP6 IO direction */
2133 #define IXGBE_ESDP_SDP7_DIR	0x00008000 /* SDP7 IO direction */
2134 #define IXGBE_ESDP_SDP0_NATIVE	0x00010000 /* SDP0 IO mode */
2135 #define IXGBE_ESDP_SDP1_NATIVE	0x00020000 /* SDP1 IO mode */
2136 
2137 
2138 /* LEDCTL Bit Masks */
2139 #define IXGBE_LED_IVRT_BASE		0x00000040
2140 #define IXGBE_LED_BLINK_BASE		0x00000080
2141 #define IXGBE_LED_MODE_MASK_BASE	0x0000000F
2142 #define IXGBE_LED_OFFSET(_base, _i)	(_base << (8 * (_i)))
2143 #define IXGBE_LED_MODE_SHIFT(_i)	(8*(_i))
2144 #define IXGBE_LED_IVRT(_i)	IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
2145 #define IXGBE_LED_BLINK(_i)	IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
2146 #define IXGBE_LED_MODE_MASK(_i)	IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
2147 #define IXGBE_X557_LED_MANUAL_SET_MASK	(1 << 8)
2148 #define IXGBE_X557_MAX_LED_INDEX	3
2149 #define IXGBE_X557_LED_PROVISIONING	0xC430
2150 
2151 /* LED modes */
2152 #define IXGBE_LED_LINK_UP	0x0
2153 #define IXGBE_LED_LINK_10G	0x1
2154 #define IXGBE_LED_MAC		0x2
2155 #define IXGBE_LED_FILTER	0x3
2156 #define IXGBE_LED_LINK_ACTIVE	0x4
2157 #define IXGBE_LED_LINK_1G	0x5
2158 #define IXGBE_LED_ON		0xE
2159 #define IXGBE_LED_OFF		0xF
2160 
2161 /* AUTOC Bit Masks */
2162 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
2163 #define IXGBE_AUTOC_KX4_SUPP	0x80000000
2164 #define IXGBE_AUTOC_KX_SUPP	0x40000000
2165 #define IXGBE_AUTOC_PAUSE	0x30000000
2166 #define IXGBE_AUTOC_ASM_PAUSE	0x20000000
2167 #define IXGBE_AUTOC_SYM_PAUSE	0x10000000
2168 #define IXGBE_AUTOC_RF		0x08000000
2169 #define IXGBE_AUTOC_PD_TMR	0x06000000
2170 #define IXGBE_AUTOC_AN_RX_LOOSE	0x01000000
2171 #define IXGBE_AUTOC_AN_RX_DRIFT	0x00800000
2172 #define IXGBE_AUTOC_AN_RX_ALIGN	0x007C0000
2173 #define IXGBE_AUTOC_FECA	0x00040000
2174 #define IXGBE_AUTOC_FECR	0x00020000
2175 #define IXGBE_AUTOC_KR_SUPP	0x00010000
2176 #define IXGBE_AUTOC_AN_RESTART	0x00001000
2177 #define IXGBE_AUTOC_FLU		0x00000001
2178 #define IXGBE_AUTOC_LMS_SHIFT	13
2179 #define IXGBE_AUTOC_LMS_10G_SERIAL	(0x3 << IXGBE_AUTOC_LMS_SHIFT)
2180 #define IXGBE_AUTOC_LMS_KX4_KX_KR	(0x4 << IXGBE_AUTOC_LMS_SHIFT)
2181 #define IXGBE_AUTOC_LMS_SGMII_1G_100M	(0x5 << IXGBE_AUTOC_LMS_SHIFT)
2182 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN	(0x6 << IXGBE_AUTOC_LMS_SHIFT)
2183 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII	(0x7 << IXGBE_AUTOC_LMS_SHIFT)
2184 #define IXGBE_AUTOC_LMS_MASK		(0x7 << IXGBE_AUTOC_LMS_SHIFT)
2185 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN	(0x0 << IXGBE_AUTOC_LMS_SHIFT)
2186 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN	(0x1 << IXGBE_AUTOC_LMS_SHIFT)
2187 #define IXGBE_AUTOC_LMS_1G_AN		(0x2 << IXGBE_AUTOC_LMS_SHIFT)
2188 #define IXGBE_AUTOC_LMS_KX4_AN		(0x4 << IXGBE_AUTOC_LMS_SHIFT)
2189 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN	(0x6 << IXGBE_AUTOC_LMS_SHIFT)
2190 #define IXGBE_AUTOC_LMS_ATTACH_TYPE	(0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2191 
2192 #define IXGBE_AUTOC_1G_PMA_PMD_MASK	0x00000200
2193 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT	9
2194 #define IXGBE_AUTOC_10G_PMA_PMD_MASK	0x00000180
2195 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT	7
2196 #define IXGBE_AUTOC_10G_XAUI	(0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2197 #define IXGBE_AUTOC_10G_KX4	(0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2198 #define IXGBE_AUTOC_10G_CX4	(0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2199 #define IXGBE_AUTOC_1G_BX	(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2200 #define IXGBE_AUTOC_1G_KX	(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2201 #define IXGBE_AUTOC_1G_SFI	(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2202 #define IXGBE_AUTOC_1G_KX_BX	(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2203 
2204 #define IXGBE_AUTOC2_UPPER_MASK	0xFFFF0000
2205 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK	0x00030000
2206 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT	16
2207 #define IXGBE_AUTOC2_10G_KR	(0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2208 #define IXGBE_AUTOC2_10G_XFI	(0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2209 #define IXGBE_AUTOC2_10G_SFI	(0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2210 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK	0x50000000
2211 #define IXGBE_AUTOC2_LINK_DISABLE_MASK		0x70000000
2212 
2213 #define IXGBE_MACC_FLU		0x00000001
2214 #define IXGBE_MACC_FSV_10G	0x00030000
2215 #define IXGBE_MACC_FS		0x00040000
2216 #define IXGBE_MAC_RX2TX_LPBK	0x00000002
2217 
2218 /* Veto Bit definition */
2219 #define IXGBE_MMNGC_MNG_VETO	0x00000001
2220 
2221 /* LINKS Bit Masks */
2222 #define IXGBE_LINKS_KX_AN_COMP	0x80000000
2223 #define IXGBE_LINKS_UP		0x40000000
2224 #define IXGBE_LINKS_SPEED	0x20000000
2225 #define IXGBE_LINKS_MODE	0x18000000
2226 #define IXGBE_LINKS_RX_MODE	0x06000000
2227 #define IXGBE_LINKS_TX_MODE	0x01800000
2228 #define IXGBE_LINKS_XGXS_EN	0x00400000
2229 #define IXGBE_LINKS_SGMII_EN	0x02000000
2230 #define IXGBE_LINKS_PCS_1G_EN	0x00200000
2231 #define IXGBE_LINKS_1G_AN_EN	0x00100000
2232 #define IXGBE_LINKS_KX_AN_IDLE	0x00080000
2233 #define IXGBE_LINKS_1G_SYNC	0x00040000
2234 #define IXGBE_LINKS_10G_ALIGN	0x00020000
2235 #define IXGBE_LINKS_10G_LANE_SYNC	0x00017000
2236 #define IXGBE_LINKS_TL_FAULT		0x00001000
2237 #define IXGBE_LINKS_SIGNAL		0x00000F00
2238 
2239 #define IXGBE_LINKS_SPEED_NON_STD	0x08000000
2240 #define IXGBE_LINKS_SPEED_82599		0x30000000
2241 #define IXGBE_LINKS_SPEED_10G_82599	0x30000000
2242 #define IXGBE_LINKS_SPEED_1G_82599	0x20000000
2243 #define IXGBE_LINKS_SPEED_100_82599	0x10000000
2244 #define IXGBE_LINKS_SPEED_10_X550EM_A	0x00000000
2245 #define IXGBE_LINK_UP_TIME		90 /* 9.0 Seconds */
2246 #define IXGBE_AUTO_NEG_TIME		45 /* 4.5 Seconds */
2247 
2248 #define IXGBE_LINKS2_AN_SUPPORTED	0x00000040
2249 
2250 /* PCS1GLSTA Bit Masks */
2251 #define IXGBE_PCS1GLSTA_LINK_OK		1
2252 #define IXGBE_PCS1GLSTA_SYNK_OK		0x10
2253 #define IXGBE_PCS1GLSTA_AN_COMPLETE	0x10000
2254 #define IXGBE_PCS1GLSTA_AN_PAGE_RX	0x20000
2255 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT	0x40000
2256 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT	0x80000
2257 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS	0x100000
2258 
2259 #define IXGBE_PCS1GANA_SYM_PAUSE	0x80
2260 #define IXGBE_PCS1GANA_ASM_PAUSE	0x100
2261 
2262 /* PCS1GLCTL Bit Masks */
2263 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
2264 #define IXGBE_PCS1GLCTL_FLV_LINK_UP	1
2265 #define IXGBE_PCS1GLCTL_FORCE_LINK	0x20
2266 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH	0x40
2267 #define IXGBE_PCS1GLCTL_AN_ENABLE	0x10000
2268 #define IXGBE_PCS1GLCTL_AN_RESTART	0x20000
2269 
2270 /* ANLP1 Bit Masks */
2271 #define IXGBE_ANLP1_PAUSE		0x0C00
2272 #define IXGBE_ANLP1_SYM_PAUSE		0x0400
2273 #define IXGBE_ANLP1_ASM_PAUSE		0x0800
2274 #define IXGBE_ANLP1_AN_STATE_MASK	0x000f0000
2275 
2276 /* SW Semaphore Register bitmasks */
2277 #define IXGBE_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
2278 #define IXGBE_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
2279 #define IXGBE_SWSM_WMNG		0x00000004 /* Wake MNG Clock */
2280 #define IXGBE_SWFW_REGSMP	0x80000000 /* Register Semaphore bit 31 */
2281 
2282 /* SW_FW_SYNC/GSSR definitions */
2283 #define IXGBE_GSSR_EEP_SM		0x0001
2284 #define IXGBE_GSSR_PHY0_SM		0x0002
2285 #define IXGBE_GSSR_PHY1_SM		0x0004
2286 #define IXGBE_GSSR_MAC_CSR_SM		0x0008
2287 #define IXGBE_GSSR_FLASH_SM		0x0010
2288 #define IXGBE_GSSR_NVM_UPDATE_SM	0x0200
2289 #define IXGBE_GSSR_SW_MNG_SM		0x0400
2290 #define IXGBE_GSSR_TOKEN_SM	0x40000000 /* SW bit for shared access */
2291 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2292 #define IXGBE_GSSR_I2C_MASK	0x1800
2293 #define IXGBE_GSSR_NVM_PHY_MASK	0xF
2294 
2295 /* FW Status register bitmask */
2296 #define IXGBE_FWSTS_FWRI	0x00000200 /* Firmware Reset Indication */
2297 
2298 /* EEC Register */
2299 #define IXGBE_EEC_SK		0x00000001 /* EEPROM Clock */
2300 #define IXGBE_EEC_CS		0x00000002 /* EEPROM Chip Select */
2301 #define IXGBE_EEC_DI		0x00000004 /* EEPROM Data In */
2302 #define IXGBE_EEC_DO		0x00000008 /* EEPROM Data Out */
2303 #define IXGBE_EEC_FWE_MASK	0x00000030 /* FLASH Write Enable */
2304 #define IXGBE_EEC_FWE_DIS	0x00000010 /* Disable FLASH writes */
2305 #define IXGBE_EEC_FWE_EN	0x00000020 /* Enable FLASH writes */
2306 #define IXGBE_EEC_FWE_SHIFT	4
2307 #define IXGBE_EEC_REQ		0x00000040 /* EEPROM Access Request */
2308 #define IXGBE_EEC_GNT		0x00000080 /* EEPROM Access Grant */
2309 #define IXGBE_EEC_PRES		0x00000100 /* EEPROM Present */
2310 #define IXGBE_EEC_ARD		0x00000200 /* EEPROM Auto Read Done */
2311 #define IXGBE_EEC_FLUP		0x00800000 /* Flash update command */
2312 #define IXGBE_EEC_SEC1VAL	0x02000000 /* Sector 1 Valid */
2313 #define IXGBE_EEC_FLUDONE	0x04000000 /* Flash update done */
2314 /* EEPROM Addressing bits based on type (0-small, 1-large) */
2315 #define IXGBE_EEC_ADDR_SIZE	0x00000400
2316 #define IXGBE_EEC_SIZE		0x00007800 /* EEPROM Size */
2317 #define IXGBE_EERD_MAX_ADDR	0x00003FFF /* EERD allows 14 bits for addr. */
2318 
2319 #define IXGBE_EEC_SIZE_SHIFT		11
2320 #define IXGBE_EEPROM_WORD_SIZE_SHIFT	6
2321 #define IXGBE_EEPROM_OPCODE_BITS	8
2322 
2323 /* FLA Register */
2324 #define IXGBE_FLA_LOCKED	0x00000040
2325 
2326 /* Part Number String Length */
2327 #define IXGBE_PBANUM_LENGTH	11
2328 
2329 /* Checksum and EEPROM pointers */
2330 #define IXGBE_PBANUM_PTR_GUARD		0xFAFA
2331 #define IXGBE_EEPROM_CHECKSUM		0x3F
2332 #define IXGBE_EEPROM_SUM		0xBABA
2333 #define IXGBE_EEPROM_CTRL_4		0x45
2334 #define IXGBE_EE_CTRL_4_INST_ID		0x10
2335 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT	4
2336 #define IXGBE_PCIE_ANALOG_PTR		0x03
2337 #define IXGBE_ATLAS0_CONFIG_PTR		0x04
2338 #define IXGBE_PHY_PTR			0x04
2339 #define IXGBE_ATLAS1_CONFIG_PTR		0x05
2340 #define IXGBE_OPTION_ROM_PTR		0x05
2341 #define IXGBE_PCIE_GENERAL_PTR		0x06
2342 #define IXGBE_PCIE_CONFIG0_PTR		0x07
2343 #define IXGBE_PCIE_CONFIG1_PTR		0x08
2344 #define IXGBE_CORE0_PTR			0x09
2345 #define IXGBE_CORE1_PTR			0x0A
2346 #define IXGBE_MAC0_PTR			0x0B
2347 #define IXGBE_MAC1_PTR			0x0C
2348 #define IXGBE_CSR0_CONFIG_PTR		0x0D
2349 #define IXGBE_CSR1_CONFIG_PTR		0x0E
2350 #define IXGBE_PCIE_ANALOG_PTR_X550	0x02
2351 #define IXGBE_SHADOW_RAM_SIZE_X550	0x4000
2352 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE	0x24
2353 #define IXGBE_PCIE_CONFIG_SIZE		0x08
2354 #define IXGBE_EEPROM_LAST_WORD		0x41
2355 #define IXGBE_FW_PTR			0x0F
2356 #define IXGBE_PBANUM0_PTR		0x15
2357 #define IXGBE_PBANUM1_PTR		0x16
2358 #define IXGBE_ALT_MAC_ADDR_PTR		0x37
2359 #define IXGBE_FREE_SPACE_PTR		0X3E
2360 
2361 #define IXGBE_SAN_MAC_ADDR_PTR		0x28
2362 #define IXGBE_DEVICE_CAPS		0x2C
2363 #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR	0x11
2364 #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR	0x04
2365 
2366 #define IXGBE_PCIE_MSIX_82599_CAPS	0x72
2367 #define IXGBE_MAX_MSIX_VECTORS_82599	0x40
2368 #define IXGBE_PCIE_MSIX_82598_CAPS	0x62
2369 #define IXGBE_MAX_MSIX_VECTORS_82598	0x13
2370 
2371 /* MSI-X capability fields masks */
2372 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK	0x7FF
2373 
2374 /* Legacy EEPROM word offsets */
2375 #define IXGBE_ISCSI_BOOT_CAPS		0x0033
2376 #define IXGBE_ISCSI_SETUP_PORT_0	0x0030
2377 #define IXGBE_ISCSI_SETUP_PORT_1	0x0034
2378 
2379 /* EEPROM Commands - SPI */
2380 #define IXGBE_EEPROM_MAX_RETRY_SPI	5000 /* Max wait 5ms for RDY signal */
2381 #define IXGBE_EEPROM_STATUS_RDY_SPI	0x01
2382 #define IXGBE_EEPROM_READ_OPCODE_SPI	0x03  /* EEPROM read opcode */
2383 #define IXGBE_EEPROM_WRITE_OPCODE_SPI	0x02  /* EEPROM write opcode */
2384 #define IXGBE_EEPROM_A8_OPCODE_SPI	0x08  /* opcode bit-3 = addr bit-8 */
2385 #define IXGBE_EEPROM_WREN_OPCODE_SPI	0x06  /* EEPROM set Write Ena latch */
2386 /* EEPROM reset Write Enable latch */
2387 #define IXGBE_EEPROM_WRDI_OPCODE_SPI	0x04
2388 #define IXGBE_EEPROM_RDSR_OPCODE_SPI	0x05  /* EEPROM read Status reg */
2389 #define IXGBE_EEPROM_WRSR_OPCODE_SPI	0x01  /* EEPROM write Status reg */
2390 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI	0x20  /* EEPROM ERASE 4KB */
2391 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI	0xD8  /* EEPROM ERASE 64KB */
2392 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI	0xDB  /* EEPROM ERASE 256B */
2393 
2394 /* EEPROM Read Register */
2395 #define IXGBE_EEPROM_RW_REG_DATA	16 /* data offset in EEPROM read reg */
2396 #define IXGBE_EEPROM_RW_REG_DONE	2 /* Offset to READ done bit */
2397 #define IXGBE_EEPROM_RW_REG_START	1 /* First bit to start operation */
2398 #define IXGBE_EEPROM_RW_ADDR_SHIFT	2 /* Shift to the address bits */
2399 #define IXGBE_NVM_POLL_WRITE		1 /* Flag for polling for wr complete */
2400 #define IXGBE_NVM_POLL_READ		0 /* Flag for polling for rd complete */
2401 
2402 #define NVM_INIT_CTRL_3		0x38
2403 #define NVM_INIT_CTRL_3_LPLU	0x8
2404 #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2405 #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2406 
2407 #define IXGBE_ETH_LENGTH_OF_ADDRESS	6
2408 
2409 #define IXGBE_EEPROM_PAGE_SIZE_MAX	128
2410 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT	256 /* words rd in burst */
2411 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT	256 /* words wr in burst */
2412 #define IXGBE_EEPROM_CTRL_2		1 /* EEPROM CTRL word 2 */
2413 #define IXGBE_EEPROM_CCD_BIT		2
2414 
2415 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2416 #define IXGBE_EEPROM_GRANT_ATTEMPTS	1000 /* EEPROM attempts to gain grant */
2417 #endif
2418 
2419 /* Number of 5 microseconds we wait for EERD read and
2420  * EERW write to complete */
2421 #define IXGBE_EERD_EEWR_ATTEMPTS	100000
2422 
2423 /* # attempts we wait for flush update to complete */
2424 #define IXGBE_FLUDONE_ATTEMPTS		20000
2425 
2426 #define IXGBE_PCIE_CTRL2		0x5   /* PCIe Control 2 Offset */
2427 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE	0x8   /* Dummy Function Enable */
2428 #define IXGBE_PCIE_CTRL2_LAN_DISABLE	0x2   /* LAN PCI Disable */
2429 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT	0x1   /* LAN Disable Select */
2430 
2431 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET		0x0
2432 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET		0x3
2433 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP		0x1
2434 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS		0x2
2435 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR	(1 << 7)
2436 #define IXGBE_FW_LESM_PARAMETERS_PTR		0x2
2437 #define IXGBE_FW_LESM_STATE_1			0x1
2438 #define IXGBE_FW_LESM_STATE_ENABLED		0x8000 /* LESM Enable bit */
2439 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR	0x4
2440 #define IXGBE_FW_PATCH_VERSION_4		0x7
2441 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR		0x33 /* iSCSI/FCOE block */
2442 #define IXGBE_FCOE_IBA_CAPS_FCOE		0x20 /* FCOE flags */
2443 #define IXGBE_ISCSI_FCOE_BLK_PTR		0x17 /* iSCSI/FCOE block */
2444 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET		0x0 /* FCOE flags */
2445 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE		0x1 /* FCOE flags enable bit */
2446 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR		0x27 /* Alt. SAN MAC block */
2447 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET	0x0 /* Alt SAN MAC capability */
2448 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET	0x1 /* Alt SAN MAC 0 offset */
2449 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET	0x4 /* Alt SAN MAC 1 offset */
2450 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET	0x7 /* Alt WWNN prefix offset */
2451 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET	0x8 /* Alt WWPN prefix offset */
2452 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC	0x0 /* Alt SAN MAC exists */
2453 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN	0x1 /* Alt WWN base exists */
2454 
2455 /* FW header offset */
2456 #define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR	0x4
2457 #define IXGBE_X540_FW_MODULE_MASK			0x7FFF
2458 /* 4KB multiplier */
2459 #define IXGBE_X540_FW_MODULE_LENGTH			0x1000
2460 /* version word 2 (month & day) */
2461 #define IXGBE_X540_FW_PATCH_VERSION_2		0x5
2462 /* version word 3 (silicon compatibility & year) */
2463 #define IXGBE_X540_FW_PATCH_VERSION_3		0x6
2464 /* version word 4 (major & minor numbers) */
2465 #define IXGBE_X540_FW_PATCH_VERSION_4		0x7
2466 
2467 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1	0x4 /* WoL supported on ports 0 & 1 */
2468 #define IXGBE_DEVICE_CAPS_WOL_PORT0	0x8 /* WoL supported on port 0 */
2469 #define IXGBE_DEVICE_CAPS_WOL_MASK	0xC /* Mask for WoL capabilities */
2470 
2471 /* PCI Bus Info */
2472 #define IXGBE_PCI_DEVICE_STATUS		0xAA
2473 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING	0x0020
2474 #define IXGBE_PCI_LINK_STATUS		0xB2
2475 #define IXGBE_PCI_DEVICE_CONTROL2	0xC8
2476 #define IXGBE_PCI_LINK_WIDTH		0x3F0
2477 #define IXGBE_PCI_LINK_WIDTH_1		0x10
2478 #define IXGBE_PCI_LINK_WIDTH_2		0x20
2479 #define IXGBE_PCI_LINK_WIDTH_4		0x40
2480 #define IXGBE_PCI_LINK_WIDTH_8		0x80
2481 #define IXGBE_PCI_LINK_SPEED		0xF
2482 #define IXGBE_PCI_LINK_SPEED_2500	0x1
2483 #define IXGBE_PCI_LINK_SPEED_5000	0x2
2484 #define IXGBE_PCI_LINK_SPEED_8000	0x3
2485 #define IXGBE_PCI_HEADER_TYPE_REGISTER	0x0E
2486 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC	0x80
2487 #define IXGBE_PCI_DEVICE_CONTROL2_16ms	0x0005
2488 
2489 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK	0xf
2490 #define IXGBE_PCIDEVCTRL2_16_32ms_def	0x0
2491 #define IXGBE_PCIDEVCTRL2_50_100us	0x1
2492 #define IXGBE_PCIDEVCTRL2_1_2ms		0x2
2493 #define IXGBE_PCIDEVCTRL2_16_32ms	0x5
2494 #define IXGBE_PCIDEVCTRL2_65_130ms	0x6
2495 #define IXGBE_PCIDEVCTRL2_260_520ms	0x9
2496 #define IXGBE_PCIDEVCTRL2_1_2s		0xa
2497 #define IXGBE_PCIDEVCTRL2_4_8s		0xd
2498 #define IXGBE_PCIDEVCTRL2_17_34s	0xe
2499 
2500 /* Number of 100 microseconds we wait for PCI Express master disable */
2501 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT	800
2502 
2503 /* Check whether address is multicast. This is little-endian specific check.*/
2504 #define IXGBE_IS_MULTICAST(Address) \
2505 		(bool)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
2506 
2507 /* Check whether an address is broadcast. */
2508 #define IXGBE_IS_BROADCAST(Address) \
2509 		((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && \
2510 		(((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
2511 
2512 /* RAH */
2513 #define IXGBE_RAH_VIND_MASK	0x003C0000
2514 #define IXGBE_RAH_VIND_SHIFT	18
2515 #define IXGBE_RAH_AV		0x80000000
2516 #define IXGBE_CLEAR_VMDQ_ALL	0xFFFFFFFF
2517 
2518 /* Header split receive */
2519 #define IXGBE_RFCTL_ISCSI_DIS		0x00000001
2520 #define IXGBE_RFCTL_ISCSI_DWC_MASK	0x0000003E
2521 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT	1
2522 #define IXGBE_RFCTL_RSC_DIS		0x00000020
2523 #define IXGBE_RFCTL_NFSW_DIS		0x00000040
2524 #define IXGBE_RFCTL_NFSR_DIS		0x00000080
2525 #define IXGBE_RFCTL_NFS_VER_MASK	0x00000300
2526 #define IXGBE_RFCTL_NFS_VER_SHIFT	8
2527 #define IXGBE_RFCTL_NFS_VER_2		0
2528 #define IXGBE_RFCTL_NFS_VER_3		1
2529 #define IXGBE_RFCTL_NFS_VER_4		2
2530 #define IXGBE_RFCTL_IPV6_DIS		0x00000400
2531 #define IXGBE_RFCTL_IPV6_XSUM_DIS	0x00000800
2532 #define IXGBE_RFCTL_IPFRSP_DIS		0x00004000
2533 #define IXGBE_RFCTL_IPV6_EX_DIS		0x00010000
2534 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
2535 
2536 /* Transmit Config masks */
2537 #define IXGBE_TXDCTL_ENABLE		0x02000000 /* Ena specific Tx Queue */
2538 #define IXGBE_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wr-bk flushing */
2539 #define IXGBE_TXDCTL_WTHRESH_SHIFT	16 /* shift to WTHRESH bits */
2540 /* Enable short packet padding to 64 bytes */
2541 #define IXGBE_TX_PAD_ENABLE		0x00000400
2542 #define IXGBE_JUMBO_FRAME_ENABLE	0x00000004  /* Allow jumbo frames */
2543 /* This allows for 16K packets + 4k for vlan */
2544 #define IXGBE_MAX_FRAME_SZ		0x40040000
2545 
2546 #define IXGBE_TDWBAL_HEAD_WB_ENABLE	0x1 /* Tx head write-back enable */
2547 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE	0x2 /* Tx seq# write-back enable */
2548 
2549 /* Receive Config masks */
2550 #define IXGBE_RXCTRL_RXEN		0x00000001 /* Enable Receiver */
2551 #define IXGBE_RXCTRL_DMBYPS		0x00000002 /* Desc Monitor Bypass */
2552 #define IXGBE_RXDCTL_ENABLE		0x02000000 /* Ena specific Rx Queue */
2553 #define IXGBE_RXDCTL_SWFLSH		0x04000000 /* Rx Desc wr-bk flushing */
2554 #define IXGBE_RXDCTL_RLPMLMASK		0x00003FFF /* X540 supported only */
2555 #define IXGBE_RXDCTL_RLPML_EN		0x00008000
2556 #define IXGBE_RXDCTL_VME		0x40000000 /* VLAN mode enable */
2557 
2558 #define IXGBE_TSAUXC_EN_CLK		0x00000004
2559 #define IXGBE_TSAUXC_SYNCLK		0x00000008
2560 #define IXGBE_TSAUXC_SDP0_INT		0x00000040
2561 #define IXGBE_TSAUXC_EN_TT0		0x00000001
2562 #define IXGBE_TSAUXC_EN_TT1		0x00000002
2563 #define IXGBE_TSAUXC_ST0		0x00000010
2564 #define IXGBE_TSAUXC_DISABLE_SYSTIME	0x80000000
2565 
2566 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK	0x000000C0
2567 #define IXGBE_TSSDP_TS_SDP0_CLK0	0x00000080
2568 #define IXGBE_TSSDP_TS_SDP0_EN		0x00000100
2569 
2570 #define IXGBE_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
2571 #define IXGBE_TSYNCTXCTL_ENABLED	0x00000010 /* Tx timestamping enabled */
2572 
2573 #define IXGBE_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
2574 #define IXGBE_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
2575 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2	0x00
2576 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1	0x02
2577 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
2578 #define IXGBE_TSYNCRXCTL_TYPE_ALL	0x08
2579 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
2580 #define IXGBE_TSYNCRXCTL_ENABLED	0x00000010 /* Rx Timestamping enabled */
2581 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN	0x00800000 /* Rx Timestamp in Packet */
2582 #define IXGBE_TSYNCRXCTL_TSIP_UP_MASK	0xFF000000 /* Rx Timestamp UP Mask */
2583 
2584 #define IXGBE_TSIM_SYS_WRAP		0x00000001
2585 #define IXGBE_TSIM_TXTS			0x00000002
2586 #define IXGBE_TSIM_TADJ			0x00000080
2587 
2588 #define IXGBE_TSICR_SYS_WRAP		IXGBE_TSIM_SYS_WRAP
2589 #define IXGBE_TSICR_TXTS		IXGBE_TSIM_TXTS
2590 #define IXGBE_TSICR_TADJ		IXGBE_TSIM_TADJ
2591 
2592 #define IXGBE_RXMTRL_V1_CTRLT_MASK	0x000000FF
2593 #define IXGBE_RXMTRL_V1_SYNC_MSG	0x00
2594 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG	0x01
2595 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG	0x02
2596 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG	0x03
2597 #define IXGBE_RXMTRL_V1_MGMT_MSG	0x04
2598 
2599 #define IXGBE_RXMTRL_V2_MSGID_MASK	0x0000FF00
2600 #define IXGBE_RXMTRL_V2_SYNC_MSG	0x0000
2601 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG	0x0100
2602 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG	0x0200
2603 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG	0x0300
2604 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG	0x0800
2605 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG	0x0900
2606 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2607 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG	0x0B00
2608 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG	0x0C00
2609 #define IXGBE_RXMTRL_V2_MGMT_MSG	0x0D00
2610 
2611 #define IXGBE_FCTRL_SBP		0x00000002 /* Store Bad Packet */
2612 #define IXGBE_FCTRL_MPE		0x00000100 /* Multicast Promiscuous Ena*/
2613 #define IXGBE_FCTRL_UPE		0x00000200 /* Unicast Promiscuous Ena */
2614 #define IXGBE_FCTRL_BAM		0x00000400 /* Broadcast Accept Mode */
2615 #define IXGBE_FCTRL_PMCF	0x00001000 /* Pass MAC Control Frames */
2616 #define IXGBE_FCTRL_DPF		0x00002000 /* Discard Pause Frame */
2617 /* Receive Priority Flow Control Enable */
2618 #define IXGBE_FCTRL_RPFCE	0x00004000
2619 #define IXGBE_FCTRL_RFCE	0x00008000 /* Receive Flow Control Ena */
2620 #define IXGBE_MFLCN_PMCF	0x00000001 /* Pass MAC Control Frames */
2621 #define IXGBE_MFLCN_DPF		0x00000002 /* Discard Pause Frame */
2622 #define IXGBE_MFLCN_RPFCE	0x00000004 /* Receive Priority FC Enable */
2623 #define IXGBE_MFLCN_RFCE	0x00000008 /* Receive FC Enable */
2624 #define IXGBE_MFLCN_RPFCE_MASK	0x00000FF4 /* Rx Priority FC bitmap mask */
2625 #define IXGBE_MFLCN_RPFCE_SHIFT	4 /* Rx Priority FC bitmap shift */
2626 
2627 /* Multiple Receive Queue Control */
2628 #define IXGBE_MRQC_RSSEN	0x00000001  /* RSS Enable */
2629 #define IXGBE_MRQC_MRQE_MASK	0xF /* Bits 3:0 */
2630 #define IXGBE_MRQC_RT8TCEN	0x00000002 /* 8 TC no RSS */
2631 #define IXGBE_MRQC_RT4TCEN	0x00000003 /* 4 TC no RSS */
2632 #define IXGBE_MRQC_RTRSS8TCEN	0x00000004 /* 8 TC w/ RSS */
2633 #define IXGBE_MRQC_RTRSS4TCEN	0x00000005 /* 4 TC w/ RSS */
2634 #define IXGBE_MRQC_VMDQEN	0x00000008 /* VMDq2 64 pools no RSS */
2635 #define IXGBE_MRQC_VMDQRSS32EN	0x0000000A /* VMDq2 32 pools w/ RSS */
2636 #define IXGBE_MRQC_VMDQRSS64EN	0x0000000B /* VMDq2 64 pools w/ RSS */
2637 #define IXGBE_MRQC_VMDQRT8TCEN	0x0000000C /* VMDq2/RT 16 pool 8 TC */
2638 #define IXGBE_MRQC_VMDQRT4TCEN	0x0000000D /* VMDq2/RT 32 pool 4 TC */
2639 #define IXGBE_MRQC_L3L4TXSWEN	0x00008000 /* Enable L3/L4 Tx switch */
2640 #define IXGBE_MRQC_RSS_FIELD_MASK	0xFFFF0000
2641 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP	0x00010000
2642 #define IXGBE_MRQC_RSS_FIELD_IPV4	0x00020000
2643 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2644 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX	0x00080000
2645 #define IXGBE_MRQC_RSS_FIELD_IPV6	0x00100000
2646 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP	0x00200000
2647 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP	0x00400000
2648 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP	0x00800000
2649 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2650 #define IXGBE_MRQC_MULTIPLE_RSS		0x00002000
2651 #define IXGBE_MRQC_L3L4TXSWEN		0x00008000
2652 
2653 /* Queue Drop Enable */
2654 #define IXGBE_QDE_ENABLE	0x00000001
2655 #define IXGBE_QDE_HIDE_VLAN	0x00000002
2656 #define IXGBE_QDE_IDX_MASK	0x00007F00
2657 #define IXGBE_QDE_IDX_SHIFT	8
2658 #define IXGBE_QDE_WRITE		0x00010000
2659 #define IXGBE_QDE_READ		0x00020000
2660 
2661 #define IXGBE_TXD_POPTS_IXSM	0x01 /* Insert IP checksum */
2662 #define IXGBE_TXD_POPTS_TXSM	0x02 /* Insert TCP/UDP checksum */
2663 #define IXGBE_TXD_CMD_EOP	0x01000000 /* End of Packet */
2664 #define IXGBE_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
2665 #define IXGBE_TXD_CMD_IC	0x04000000 /* Insert Checksum */
2666 #define IXGBE_TXD_CMD_RS	0x08000000 /* Report Status */
2667 #define IXGBE_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */
2668 #define IXGBE_TXD_CMD_VLE	0x40000000 /* Add VLAN tag */
2669 #define IXGBE_TXD_STAT_DD	0x00000001 /* Descriptor Done */
2670 
2671 #define IXGBE_RXDADV_IPSEC_STATUS_SECP		0x00020000
2672 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2673 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH	0x10000000
2674 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED	0x18000000
2675 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK	0x18000000
2676 /* Multiple Transmit Queue Command Register */
2677 #define IXGBE_MTQC_RT_ENA	0x1 /* DCB Enable */
2678 #define IXGBE_MTQC_VT_ENA	0x2 /* VMDQ2 Enable */
2679 #define IXGBE_MTQC_64Q_1PB	0x0 /* 64 queues 1 pack buffer */
2680 #define IXGBE_MTQC_32VF		0x8 /* 4 TX Queues per pool w/32VF's */
2681 #define IXGBE_MTQC_64VF		0x4 /* 2 TX Queues per pool w/64VF's */
2682 #define IXGBE_MTQC_4TC_4TQ	0x8 /* 4 TC if RT_ENA and VT_ENA */
2683 #define IXGBE_MTQC_8TC_8TQ	0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2684 
2685 /* Receive Descriptor bit definitions */
2686 #define IXGBE_RXD_STAT_DD	0x01 /* Descriptor Done */
2687 #define IXGBE_RXD_STAT_EOP	0x02 /* End of Packet */
2688 #define IXGBE_RXD_STAT_FLM	0x04 /* FDir Match */
2689 #define IXGBE_RXD_STAT_VP	0x08 /* IEEE VLAN Packet */
2690 #define IXGBE_RXDADV_NEXTP_MASK	0x000FFFF0 /* Next Descriptor Index */
2691 #define IXGBE_RXDADV_NEXTP_SHIFT	0x00000004
2692 #define IXGBE_RXD_STAT_UDPCS	0x10 /* UDP xsum calculated */
2693 #define IXGBE_RXD_STAT_L4CS	0x20 /* L4 xsum calculated */
2694 #define IXGBE_RXD_STAT_IPCS	0x40 /* IP xsum calculated */
2695 #define IXGBE_RXD_STAT_PIF	0x80 /* passed in-exact filter */
2696 #define IXGBE_RXD_STAT_CRCV	0x100 /* Speculative CRC Valid */
2697 #define IXGBE_RXD_STAT_OUTERIPCS	0x100 /* Cloud IP xsum calculated */
2698 #define IXGBE_RXD_STAT_VEXT	0x200 /* 1st VLAN found */
2699 #define IXGBE_RXD_STAT_UDPV	0x400 /* Valid UDP checksum */
2700 #define IXGBE_RXD_STAT_DYNINT	0x800 /* Pkt caused INT via DYNINT */
2701 #define IXGBE_RXD_STAT_LLINT	0x800 /* Pkt caused Low Latency Interrupt */
2702 #define IXGBE_RXD_STAT_TSIP	0x08000 /* Time Stamp in packet buffer */
2703 #define IXGBE_RXD_STAT_TS	0x10000 /* Time Stamp */
2704 #define IXGBE_RXD_STAT_SECP	0x20000 /* Security Processing */
2705 #define IXGBE_RXD_STAT_LB	0x40000 /* Loopback Status */
2706 #define IXGBE_RXD_STAT_ACK	0x8000 /* ACK Packet indication */
2707 #define IXGBE_RXD_ERR_CE	0x01 /* CRC Error */
2708 #define IXGBE_RXD_ERR_LE	0x02 /* Length Error */
2709 #define IXGBE_RXD_ERR_PE	0x08 /* Packet Error */
2710 #define IXGBE_RXD_ERR_OSE	0x10 /* Oversize Error */
2711 #define IXGBE_RXD_ERR_USE	0x20 /* Undersize Error */
2712 #define IXGBE_RXD_ERR_TCPE	0x40 /* TCP/UDP Checksum Error */
2713 #define IXGBE_RXD_ERR_IPE	0x80 /* IP Checksum Error */
2714 #define IXGBE_RXDADV_ERR_MASK		0xfff00000 /* RDESC.ERRORS mask */
2715 #define IXGBE_RXDADV_ERR_SHIFT		20 /* RDESC.ERRORS shift */
2716 #define IXGBE_RXDADV_ERR_OUTERIPER	0x04000000 /* CRC IP Header error */
2717 #define IXGBE_RXDADV_ERR_RXE		0x20000000 /* Any MAC Error */
2718 #define IXGBE_RXDADV_ERR_FCEOFE		0x80000000 /* FCEOFe/IPE */
2719 #define IXGBE_RXDADV_ERR_FCERR		0x00700000 /* FCERR/FDIRERR */
2720 #define IXGBE_RXDADV_ERR_FDIR_LEN	0x00100000 /* FDIR Length error */
2721 #define IXGBE_RXDADV_ERR_FDIR_DROP	0x00200000 /* FDIR Drop error */
2722 #define IXGBE_RXDADV_ERR_FDIR_COLL	0x00400000 /* FDIR Collision error */
2723 #define IXGBE_RXDADV_ERR_HBO	0x00800000 /*Header Buffer Overflow */
2724 #define IXGBE_RXDADV_ERR_CE	0x01000000 /* CRC Error */
2725 #define IXGBE_RXDADV_ERR_LE	0x02000000 /* Length Error */
2726 #define IXGBE_RXDADV_ERR_PE	0x08000000 /* Packet Error */
2727 #define IXGBE_RXDADV_ERR_OSE	0x10000000 /* Oversize Error */
2728 #define IXGBE_RXDADV_ERR_USE	0x20000000 /* Undersize Error */
2729 #define IXGBE_RXDADV_ERR_TCPE	0x40000000 /* TCP/UDP Checksum Error */
2730 #define IXGBE_RXDADV_ERR_IPE	0x80000000 /* IP Checksum Error */
2731 #define IXGBE_RXD_VLAN_ID_MASK	0x0FFF  /* VLAN ID is in lower 12 bits */
2732 #define IXGBE_RXD_PRI_MASK	0xE000  /* Priority is in upper 3 bits */
2733 #define IXGBE_RXD_PRI_SHIFT	13
2734 #define IXGBE_RXD_CFI_MASK	0x1000  /* CFI is bit 12 */
2735 #define IXGBE_RXD_CFI_SHIFT	12
2736 
2737 #define IXGBE_RXDADV_STAT_DD		IXGBE_RXD_STAT_DD  /* Done */
2738 #define IXGBE_RXDADV_STAT_EOP		IXGBE_RXD_STAT_EOP /* End of Packet */
2739 #define IXGBE_RXDADV_STAT_FLM		IXGBE_RXD_STAT_FLM /* FDir Match */
2740 #define IXGBE_RXDADV_STAT_VP		IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2741 #define IXGBE_RXDADV_STAT_MASK		0x000fffff /* Stat/NEXTP: bit 0-19 */
2742 #define IXGBE_RXDADV_STAT_FCEOFS	0x00000040 /* FCoE EOF/SOF Stat */
2743 #define IXGBE_RXDADV_STAT_FCSTAT	0x00000030 /* FCoE Pkt Stat */
2744 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH	0x00000000 /* 00: No Ctxt Match */
2745 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP	0x00000010 /* 01: Ctxt w/o DDP */
2746 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP	0x00000020 /* 10: Recv. FCP_RSP */
2747 #define IXGBE_RXDADV_STAT_FCSTAT_DDP	0x00000030 /* 11: Ctxt w/ DDP */
2748 #define IXGBE_RXDADV_STAT_TS		0x00010000 /* IEEE1588 Time Stamp */
2749 #define IXGBE_RXDADV_STAT_TSIP		0x00008000 /* Time Stamp in packet buffer */
2750 
2751 /* PSRTYPE bit definitions */
2752 #define IXGBE_PSRTYPE_TCPHDR	0x00000010
2753 #define IXGBE_PSRTYPE_UDPHDR	0x00000020
2754 #define IXGBE_PSRTYPE_IPV4HDR	0x00000100
2755 #define IXGBE_PSRTYPE_IPV6HDR	0x00000200
2756 #define IXGBE_PSRTYPE_L2HDR	0x00001000
2757 
2758 /* SRRCTL bit definitions */
2759 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT	10 /* so many KBs */
2760 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT	2 /* 64byte resolution (>> 6)
2761 					   * + at bit 8 offset (<< 8)
2762 					   *  = (<< 2)
2763 					   */
2764 #define IXGBE_SRRCTL_RDMTS_SHIFT	22
2765 #define IXGBE_SRRCTL_RDMTS_MASK		0x01C00000
2766 #define IXGBE_SRRCTL_DROP_EN		0x10000000
2767 #define IXGBE_SRRCTL_BSIZEPKT_MASK	0x0000007F
2768 #define IXGBE_SRRCTL_BSIZEHDR_MASK	0x00003F00
2769 #define IXGBE_SRRCTL_DESCTYPE_LEGACY	0x00000000
2770 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2771 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT	0x04000000
2772 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2773 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2774 #define IXGBE_SRRCTL_DESCTYPE_MASK	0x0E000000
2775 
2776 #define IXGBE_RXDPS_HDRSTAT_HDRSP	0x00008000
2777 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK	0x000003FF
2778 
2779 #define IXGBE_RXDADV_RSSTYPE_MASK	0x0000000F
2780 #define IXGBE_RXDADV_PKTTYPE_MASK	0x0000FFF0
2781 #define IXGBE_RXDADV_PKTTYPE_MASK_EX	0x0001FFF0
2782 #define IXGBE_RXDADV_HDRBUFLEN_MASK	0x00007FE0
2783 #define IXGBE_RXDADV_RSCCNT_MASK	0x001E0000
2784 #define IXGBE_RXDADV_RSCCNT_SHIFT	17
2785 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT	5
2786 #define IXGBE_RXDADV_SPLITHEADER_EN	0x00001000
2787 #define IXGBE_RXDADV_SPH		0x8000
2788 
2789 /* RSS Hash results */
2790 #define IXGBE_RXDADV_RSSTYPE_NONE	0x00000000
2791 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
2792 #define IXGBE_RXDADV_RSSTYPE_IPV4	0x00000002
2793 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
2794 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX	0x00000004
2795 #define IXGBE_RXDADV_RSSTYPE_IPV6	0x00000005
2796 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2797 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
2798 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
2799 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2800 
2801 /* RSS Packet Types as indicated in the receive descriptor. */
2802 #define IXGBE_RXDADV_PKTTYPE_NONE	0x00000000
2803 #define IXGBE_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPv4 hdr present */
2804 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPv4 hdr + extensions */
2805 #define IXGBE_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPv6 hdr present */
2806 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPv6 hdr + extensions */
2807 #define IXGBE_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
2808 #define IXGBE_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
2809 #define IXGBE_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
2810 #define IXGBE_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
2811 #define IXGBE_RXDADV_PKTTYPE_GENEVE	0x00000800 /* GENEVE hdr present */
2812 #define IXGBE_RXDADV_PKTTYPE_VXLAN	0x00000800 /* VXLAN hdr present */
2813 #define IXGBE_RXDADV_PKTTYPE_TUNNEL	0x00010000 /* Tunnel type */
2814 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
2815 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
2816 #define IXGBE_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
2817 #define IXGBE_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
2818 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
2819 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
2820 
2821 /* Security Processing bit Indication */
2822 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP		0x00020000
2823 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
2824 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
2825 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
2826 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
2827 
2828 /* Masks to determine if packets should be dropped due to frame errors */
2829 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2830 				IXGBE_RXD_ERR_CE | \
2831 				IXGBE_RXD_ERR_LE | \
2832 				IXGBE_RXD_ERR_PE | \
2833 				IXGBE_RXD_ERR_OSE | \
2834 				IXGBE_RXD_ERR_USE)
2835 
2836 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2837 				IXGBE_RXDADV_ERR_CE | \
2838 				IXGBE_RXDADV_ERR_LE | \
2839 				IXGBE_RXDADV_ERR_PE | \
2840 				IXGBE_RXDADV_ERR_OSE | \
2841 				IXGBE_RXDADV_ERR_USE)
2842 
2843 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599	IXGBE_RXDADV_ERR_RXE
2844 
2845 /* Multicast bit mask */
2846 #define IXGBE_MCSTCTRL_MFE	0x4
2847 
2848 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2849 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE	8
2850 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE	8
2851 #define IXGBE_REQ_TX_BUFFER_GRANULARITY		1024
2852 
2853 /* Vlan-specific macros */
2854 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK	0x0FFF /* VLAN ID in lower 12 bits */
2855 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK	0xE000 /* Priority in upper 3 bits */
2856 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT	0x000D /* Priority in upper 3 of 16 */
2857 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT	IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2858 
2859 /* SR-IOV specific macros */
2860 #define IXGBE_MBVFICR_INDEX(vf_number)	(vf_number >> 4)
2861 #define IXGBE_MBVFICR(_i)		(0x00710 + ((_i) * 4))
2862 #define IXGBE_VFLRE(_i)			(((_i & 1) ? 0x001C0 : 0x00600))
2863 #define IXGBE_VFLREC(_i)		 (0x00700 + ((_i) * 4))
2864 /* Translated register #defines */
2865 #define IXGBE_PVFCTRL(P)	(0x00300 + (4 * (P)))
2866 #define IXGBE_PVFSTATUS(P)	(0x00008 + (0 * (P)))
2867 #define IXGBE_PVFLINKS(P)	(0x042A4 + (0 * (P)))
2868 #define IXGBE_PVFRTIMER(P)	(0x00048 + (0 * (P)))
2869 #define IXGBE_PVFMAILBOX(P)	(0x04C00 + (4 * (P)))
2870 #define IXGBE_PVFRXMEMWRAP(P)	(0x03190 + (0 * (P)))
2871 #define IXGBE_PVTEICR(P)	(0x00B00 + (4 * (P)))
2872 #define IXGBE_PVTEICS(P)	(0x00C00 + (4 * (P)))
2873 #define IXGBE_PVTEIMS(P)	(0x00D00 + (4 * (P)))
2874 #define IXGBE_PVTEIMC(P)	(0x00E00 + (4 * (P)))
2875 #define IXGBE_PVTEIAC(P)	(0x00F00 + (4 * (P)))
2876 #define IXGBE_PVTEIAM(P)	(0x04D00 + (4 * (P)))
2877 #define IXGBE_PVTEITR(P)	(((P) < 24) ? (0x00820 + ((P) * 4)) : \
2878 				 (0x012300 + (((P) - 24) * 4)))
2879 #define IXGBE_PVTIVAR(P)	(0x12500 + (4 * (P)))
2880 #define IXGBE_PVTIVAR_MISC(P)	(0x04E00 + (4 * (P)))
2881 #define IXGBE_PVTRSCINT(P)	(0x12000 + (4 * (P)))
2882 #define IXGBE_VFPBACL(P)	(0x110C8 + (4 * (P)))
2883 #define IXGBE_PVFRDBAL(P)	((P < 64) ? (0x01000 + (0x40 * (P))) \
2884 				 : (0x0D000 + (0x40 * ((P) - 64))))
2885 #define IXGBE_PVFRDBAH(P)	((P < 64) ? (0x01004 + (0x40 * (P))) \
2886 				 : (0x0D004 + (0x40 * ((P) - 64))))
2887 #define IXGBE_PVFRDLEN(P)	((P < 64) ? (0x01008 + (0x40 * (P))) \
2888 				 : (0x0D008 + (0x40 * ((P) - 64))))
2889 #define IXGBE_PVFRDH(P)		((P < 64) ? (0x01010 + (0x40 * (P))) \
2890 				 : (0x0D010 + (0x40 * ((P) - 64))))
2891 #define IXGBE_PVFRDT(P)		((P < 64) ? (0x01018 + (0x40 * (P))) \
2892 				 : (0x0D018 + (0x40 * ((P) - 64))))
2893 #define IXGBE_PVFRXDCTL(P)	((P < 64) ? (0x01028 + (0x40 * (P))) \
2894 				 : (0x0D028 + (0x40 * ((P) - 64))))
2895 #define IXGBE_PVFSRRCTL(P)	((P < 64) ? (0x01014 + (0x40 * (P))) \
2896 				 : (0x0D014 + (0x40 * ((P) - 64))))
2897 #define IXGBE_PVFPSRTYPE(P)	(0x0EA00 + (4 * (P)))
2898 #define IXGBE_PVFTDBAL(P)	(0x06000 + (0x40 * (P)))
2899 #define IXGBE_PVFTDBAH(P)	(0x06004 + (0x40 * (P)))
2900 #define IXGBE_PVFTDLEN(P)	(0x06008 + (0x40 * (P)))
2901 #define IXGBE_PVFTDH(P)		(0x06010 + (0x40 * (P)))
2902 #define IXGBE_PVFTDT(P)		(0x06018 + (0x40 * (P)))
2903 #define IXGBE_PVFTXDCTL(P)	(0x06028 + (0x40 * (P)))
2904 #define IXGBE_PVFTDWBAL(P)	(0x06038 + (0x40 * (P)))
2905 #define IXGBE_PVFTDWBAH(P)	(0x0603C + (0x40 * (P)))
2906 #define IXGBE_PVFDCA_RXCTRL(P)	(((P) < 64) ? (0x0100C + (0x40 * (P))) \
2907 				 : (0x0D00C + (0x40 * ((P) - 64))))
2908 #define IXGBE_PVFDCA_TXCTRL(P)	(0x0600C + (0x40 * (P)))
2909 #define IXGBE_PVFGPRC(x)	(0x0101C + (0x40 * (x)))
2910 #define IXGBE_PVFGPTC(x)	(0x08300 + (0x04 * (x)))
2911 #define IXGBE_PVFGORC_LSB(x)	(0x01020 + (0x40 * (x)))
2912 #define IXGBE_PVFGORC_MSB(x)	(0x0D020 + (0x40 * (x)))
2913 #define IXGBE_PVFGOTC_LSB(x)	(0x08400 + (0x08 * (x)))
2914 #define IXGBE_PVFGOTC_MSB(x)	(0x08404 + (0x08 * (x)))
2915 #define IXGBE_PVFMPRC(x)	(0x0D01C + (0x40 * (x)))
2916 
2917 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2918 		(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2919 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2920 		(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2921 
2922 #define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
2923 		(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2924 #define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
2925 		(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2926 
2927 /* Little Endian defines */
2928 #ifndef __le16
2929 #define __le16  uint16_t
2930 #endif
2931 #ifndef __le32
2932 #define __le32  uint32_t
2933 #endif
2934 #ifndef __le64
2935 #define __le64  uint64_t
2936 
2937 #endif
2938 #ifndef __be16
2939 /* Big Endian defines */
2940 #define __be16  uint16_t
2941 #define __be32  uint32_t
2942 #define __be64  uint64_t
2943 
2944 #endif
2945 enum ixgbe_fdir_pballoc_type {
2946 	IXGBE_FDIR_PBALLOC_NONE = 0,
2947 	IXGBE_FDIR_PBALLOC_64K  = 1,
2948 	IXGBE_FDIR_PBALLOC_128K = 2,
2949 	IXGBE_FDIR_PBALLOC_256K = 3,
2950 };
2951 
2952 /* Flow Director register values */
2953 #define IXGBE_FDIRCTRL_PBALLOC_64K		0x00000001
2954 #define IXGBE_FDIRCTRL_PBALLOC_128K		0x00000002
2955 #define IXGBE_FDIRCTRL_PBALLOC_256K		0x00000003
2956 #define IXGBE_FDIRCTRL_INIT_DONE		0x00000008
2957 #define IXGBE_FDIRCTRL_PERFECT_MATCH		0x00000010
2958 #define IXGBE_FDIRCTRL_REPORT_STATUS		0x00000020
2959 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS	0x00000080
2960 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT		8
2961 #define IXGBE_FDIRCTRL_DROP_Q_MASK		0x00007F00
2962 #define IXGBE_FDIRCTRL_FLEX_SHIFT		16
2963 #define IXGBE_FDIRCTRL_DROP_NO_MATCH		0x00008000
2964 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT		21
2965 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN	0x0001 /* bit 23:21, 001b */
2966 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD		0x0002 /* bit 23:21, 010b */
2967 #define IXGBE_FDIRCTRL_SEARCHLIM		0x00800000
2968 #define IXGBE_FDIRCTRL_FILTERMODE_MASK		0x00E00000
2969 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT		24
2970 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK		0xF0000000
2971 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT	28
2972 
2973 #define IXGBE_FDIRTCPM_DPORTM_SHIFT		16
2974 #define IXGBE_FDIRUDPM_DPORTM_SHIFT		16
2975 #define IXGBE_FDIRIP6M_DIPM_SHIFT		16
2976 #define IXGBE_FDIRM_VLANID			0x00000001
2977 #define IXGBE_FDIRM_VLANP			0x00000002
2978 #define IXGBE_FDIRM_POOL			0x00000004
2979 #define IXGBE_FDIRM_L4P				0x00000008
2980 #define IXGBE_FDIRM_FLEX			0x00000010
2981 #define IXGBE_FDIRM_DIPv6			0x00000020
2982 #define IXGBE_FDIRM_L3P				0x00000040
2983 
2984 #define IXGBE_FDIRIP6M_INNER_MAC	0x03F0 /* bit 9:4 */
2985 #define IXGBE_FDIRIP6M_TUNNEL_TYPE	0x0800 /* bit 11 */
2986 #define IXGBE_FDIRIP6M_TNI_VNI		0xF000 /* bit 15:12 */
2987 #define IXGBE_FDIRIP6M_TNI_VNI_24	0x1000 /* bit 12 */
2988 #define IXGBE_FDIRIP6M_ALWAYS_MASK	0x040F /* bit 10, 3:0 */
2989 
2990 #define IXGBE_FDIRFREE_FREE_MASK		0xFFFF
2991 #define IXGBE_FDIRFREE_FREE_SHIFT		0
2992 #define IXGBE_FDIRFREE_COLL_MASK		0x7FFF0000
2993 #define IXGBE_FDIRFREE_COLL_SHIFT		16
2994 #define IXGBE_FDIRLEN_MAXLEN_MASK		0x3F
2995 #define IXGBE_FDIRLEN_MAXLEN_SHIFT		0
2996 #define IXGBE_FDIRLEN_MAXHASH_MASK		0x7FFF0000
2997 #define IXGBE_FDIRLEN_MAXHASH_SHIFT		16
2998 #define IXGBE_FDIRUSTAT_ADD_MASK		0xFFFF
2999 #define IXGBE_FDIRUSTAT_ADD_SHIFT		0
3000 #define IXGBE_FDIRUSTAT_REMOVE_MASK		0xFFFF0000
3001 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT		16
3002 #define IXGBE_FDIRFSTAT_FADD_MASK		0x00FF
3003 #define IXGBE_FDIRFSTAT_FADD_SHIFT		0
3004 #define IXGBE_FDIRFSTAT_FREMOVE_MASK		0xFF00
3005 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT		8
3006 #define IXGBE_FDIRPORT_DESTINATION_SHIFT	16
3007 #define IXGBE_FDIRVLAN_FLEX_SHIFT		16
3008 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT	15
3009 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT	16
3010 
3011 #define IXGBE_FDIRCMD_CMD_MASK			0x00000003
3012 #define IXGBE_FDIRCMD_CMD_ADD_FLOW		0x00000001
3013 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW		0x00000002
3014 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT	0x00000003
3015 #define IXGBE_FDIRCMD_FILTER_VALID		0x00000004
3016 #define IXGBE_FDIRCMD_FILTER_UPDATE		0x00000008
3017 #define IXGBE_FDIRCMD_IPv6DMATCH		0x00000010
3018 #define IXGBE_FDIRCMD_L4TYPE_UDP		0x00000020
3019 #define IXGBE_FDIRCMD_L4TYPE_TCP		0x00000040
3020 #define IXGBE_FDIRCMD_L4TYPE_SCTP		0x00000060
3021 #define IXGBE_FDIRCMD_IPV6			0x00000080
3022 #define IXGBE_FDIRCMD_CLEARHT			0x00000100
3023 #define IXGBE_FDIRCMD_DROP			0x00000200
3024 #define IXGBE_FDIRCMD_INT			0x00000400
3025 #define IXGBE_FDIRCMD_LAST			0x00000800
3026 #define IXGBE_FDIRCMD_COLLISION			0x00001000
3027 #define IXGBE_FDIRCMD_QUEUE_EN			0x00008000
3028 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT		5
3029 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT		16
3030 #define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT	23
3031 #define IXGBE_FDIRCMD_VT_POOL_SHIFT		24
3032 #define IXGBE_FDIR_INIT_DONE_POLL		10
3033 #define IXGBE_FDIRCMD_CMD_POLL			10
3034 #define IXGBE_FDIRCMD_TUNNEL_FILTER		0x00800000
3035 #define IXGBE_FDIR_DROP_QUEUE			127
3036 
3037 
3038 /* Manageability Host Interface defines */
3039 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH	1792 /* Num of bytes in range */
3040 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH	448 /* Num of dwords in range */
3041 #define IXGBE_HI_COMMAND_TIMEOUT	500 /* Process HI command limit */
3042 #define IXGBE_HI_FLASH_ERASE_TIMEOUT	1000 /* Process Erase command limit */
3043 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT	5000 /* Process Update command limit */
3044 #define IXGBE_HI_FLASH_APPLY_TIMEOUT	0 /* Process Apply command limit */
3045 #define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT	2000 /* Wait up to 2 seconds */
3046 
3047 /* CEM Support */
3048 #define FW_CEM_HDR_LEN			0x4
3049 #define FW_CEM_CMD_DRIVER_INFO		0xDD
3050 #define FW_CEM_CMD_DRIVER_INFO_LEN	0x5
3051 #define FW_CEM_CMD_RESERVED		0X0
3052 #define FW_CEM_UNUSED_VER		0x0
3053 #define FW_CEM_MAX_RETRIES		3
3054 #define FW_CEM_RESP_STATUS_SUCCESS	0x1
3055 #define FW_CEM_DRIVER_VERSION_SIZE	39 /* +9 would send 48 bytes to fw */
3056 #define FW_READ_SHADOW_RAM_CMD		0x31
3057 #define FW_READ_SHADOW_RAM_LEN		0x6
3058 #define FW_WRITE_SHADOW_RAM_CMD		0x33
3059 #define FW_WRITE_SHADOW_RAM_LEN		0xA /* 8 plus 1 WORD to write */
3060 #define FW_SHADOW_RAM_DUMP_CMD		0x36
3061 #define FW_SHADOW_RAM_DUMP_LEN		0
3062 #define FW_DEFAULT_CHECKSUM		0xFF /* checksum always 0xFF */
3063 #define FW_NVM_DATA_OFFSET		3
3064 #define FW_MAX_READ_BUFFER_SIZE		1024
3065 #define FW_DISABLE_RXEN_CMD		0xDE
3066 #define FW_DISABLE_RXEN_LEN		0x1
3067 #define FW_PHY_MGMT_REQ_CMD		0x20
3068 #define FW_PHY_TOKEN_REQ_CMD		0xA
3069 #define FW_PHY_TOKEN_REQ_LEN		2
3070 #define FW_PHY_TOKEN_REQ		0
3071 #define FW_PHY_TOKEN_REL		1
3072 #define FW_PHY_TOKEN_OK			1
3073 #define FW_PHY_TOKEN_RETRY		0x80
3074 #define FW_PHY_TOKEN_DELAY		5	/* milliseconds */
3075 #define FW_PHY_TOKEN_WAIT		5	/* seconds */
3076 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
3077 #define FW_INT_PHY_REQ_CMD		0xB
3078 #define FW_INT_PHY_REQ_LEN		10
3079 #define FW_INT_PHY_REQ_READ		0
3080 #define FW_INT_PHY_REQ_WRITE		1
3081 #define FW_PHY_ACT_REQ_CMD		5
3082 #define FW_PHY_ACT_DATA_COUNT		4
3083 #define FW_PHY_ACT_REQ_LEN		(4 + 4 * FW_PHY_ACT_DATA_COUNT)
3084 #define FW_PHY_ACT_INIT_PHY		1
3085 #define FW_PHY_ACT_SETUP_LINK		2
3086 #define FW_PHY_ACT_LINK_SPEED_10	(1u << 0)
3087 #define FW_PHY_ACT_LINK_SPEED_100	(1u << 1)
3088 #define FW_PHY_ACT_LINK_SPEED_1G	(1u << 2)
3089 #define FW_PHY_ACT_LINK_SPEED_2_5G	(1u << 3)
3090 #define FW_PHY_ACT_LINK_SPEED_5G	(1u << 4)
3091 #define FW_PHY_ACT_LINK_SPEED_10G	(1u << 5)
3092 #define FW_PHY_ACT_LINK_SPEED_20G	(1u << 6)
3093 #define FW_PHY_ACT_LINK_SPEED_25G	(1u << 7)
3094 #define FW_PHY_ACT_LINK_SPEED_40G	(1u << 8)
3095 #define FW_PHY_ACT_LINK_SPEED_50G	(1u << 9)
3096 #define FW_PHY_ACT_LINK_SPEED_100G	(1u << 10)
3097 #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
3098 #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
3099 					  FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
3100 #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
3101 #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX	1u
3102 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX	2u
3103 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
3104 #define FW_PHY_ACT_SETUP_LINK_LP	(1u << 18)
3105 #define FW_PHY_ACT_SETUP_LINK_HP	(1u << 19)
3106 #define FW_PHY_ACT_SETUP_LINK_EEE	(1u << 20)
3107 #define FW_PHY_ACT_SETUP_LINK_AN	(1u << 22)
3108 #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN	(1u << 0)
3109 #define FW_PHY_ACT_GET_LINK_INFO	3
3110 #define FW_PHY_ACT_GET_LINK_INFO_EEE	(1u << 19)
3111 #define FW_PHY_ACT_GET_LINK_INFO_FC_TX	(1u << 20)
3112 #define FW_PHY_ACT_GET_LINK_INFO_FC_RX	(1u << 21)
3113 #define FW_PHY_ACT_GET_LINK_INFO_POWER	(1u << 22)
3114 #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE	(1u << 24)
3115 #define FW_PHY_ACT_GET_LINK_INFO_TEMP	(1u << 25)
3116 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX	(1u << 28)
3117 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX	(1u << 29)
3118 #define FW_PHY_ACT_FORCE_LINK_DOWN	4
3119 #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF	(1u << 0)
3120 #define FW_PHY_ACT_PHY_SW_RESET		5
3121 #define FW_PHY_ACT_PHY_HW_RESET		6
3122 #define FW_PHY_ACT_GET_PHY_INFO		7
3123 #define FW_PHY_ACT_UD_2			0x1002
3124 #define FW_PHY_ACT_UD_2_10G_KR_EEE	(1u << 6)
3125 #define FW_PHY_ACT_UD_2_10G_KX4_EEE	(1u << 5)
3126 #define FW_PHY_ACT_UD_2_1G_KX_EEE	(1u << 4)
3127 #define FW_PHY_ACT_UD_2_10G_T_EEE	(1u << 3)
3128 #define FW_PHY_ACT_UD_2_1G_T_EEE	(1u << 2)
3129 #define FW_PHY_ACT_UD_2_100M_TX_EEE	(1u << 1)
3130 #define FW_PHY_ACT_RETRIES		50
3131 #define FW_PHY_INFO_SPEED_MASK		0xFFFu
3132 #define FW_PHY_INFO_ID_HI_MASK		0xFFFF0000u
3133 #define FW_PHY_INFO_ID_LO_MASK		0x0000FFFFu
3134 
3135 /* Host Interface Command Structures */
3136 
3137 struct ixgbe_hic_hdr {
3138 	uint8_t cmd;
3139 	uint8_t buf_len;
3140 	union {
3141 		uint8_t cmd_resv;
3142 		uint8_t ret_status;
3143 	} cmd_or_resp;
3144 	uint8_t checksum;
3145 } __packed __aligned(4);
3146 
3147 struct ixgbe_hic_hdr2_req {
3148 	uint8_t cmd;
3149 	uint8_t buf_lenh;
3150 	uint8_t buf_lenl;
3151 	uint8_t checksum;
3152 } __packed __aligned(4);
3153 
3154 struct ixgbe_hic_hdr2_rsp {
3155 	uint8_t cmd;
3156 	uint8_t buf_lenl;
3157 	uint8_t buf_lenh_status;	/* 7-5: high bits of buf_len, 4-0: status */
3158 	uint8_t checksum;
3159 } __packed __aligned(4);
3160 
3161 union ixgbe_hic_hdr2 {
3162 	struct ixgbe_hic_hdr2_req req;
3163 	struct ixgbe_hic_hdr2_rsp rsp;
3164 } __packed __aligned(4);
3165 
3166 struct ixgbe_hic_drv_info {
3167 	struct ixgbe_hic_hdr hdr;
3168 	uint8_t port_num;
3169 	uint8_t ver_sub;
3170 	uint8_t ver_build;
3171 	uint8_t ver_min;
3172 	uint8_t ver_maj;
3173 	uint8_t pad; /* end spacing to ensure length is mult. of dword */
3174 	uint16_t pad2; /* end spacing to ensure length is mult. of dword2 */
3175 } __packed __aligned(4);
3176 
3177 struct ixgbe_hic_drv_info2 {
3178 	struct ixgbe_hic_hdr hdr;
3179 	uint8_t port_num;
3180 	uint8_t ver_sub;
3181 	uint8_t ver_build;
3182 	uint8_t ver_min;
3183 	uint8_t ver_maj;
3184 	char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
3185 } __packed __aligned(4);
3186 
3187 /* These need to be dword aligned */
3188 struct ixgbe_hic_read_shadow_ram {
3189 	union ixgbe_hic_hdr2 hdr;
3190 	uint32_t address;
3191 	uint16_t length;
3192 	uint16_t pad2;
3193 	uint16_t data;
3194 	uint16_t pad3;
3195 } __packed __aligned(4);
3196 
3197 struct ixgbe_hic_write_shadow_ram {
3198 	union ixgbe_hic_hdr2 hdr;
3199 	uint32_t address;
3200 	uint16_t length;
3201 	uint16_t pad2;
3202 	uint16_t data;
3203 	uint16_t pad3;
3204 } __packed __aligned(4);
3205 
3206 struct ixgbe_hic_disable_rxen {
3207 	struct ixgbe_hic_hdr hdr;
3208 	uint8_t  port_number;
3209 	uint8_t  pad2;
3210 	uint16_t pad3;
3211 } __packed __aligned(4);
3212 
3213 struct ixgbe_hic_phy_token_req {
3214 	struct ixgbe_hic_hdr hdr;
3215 	uint8_t port_number;
3216 	uint8_t command_type;
3217 	uint16_t pad;
3218 } __packed __aligned(4);
3219 
3220 struct ixgbe_hic_internal_phy_req {
3221 	struct ixgbe_hic_hdr hdr;
3222 	uint8_t port_number;
3223 	uint8_t command_type;
3224 	__be16 address;
3225 	uint16_t rsv1;
3226 	__be32 write_data;
3227 	uint16_t pad;
3228 } __packed __aligned(4);
3229 
3230 struct ixgbe_hic_internal_phy_resp {
3231 	struct ixgbe_hic_hdr hdr;
3232 	__be32 read_data;
3233 } __packed __aligned(4);
3234 
3235 struct ixgbe_hic_phy_activity_req {
3236 	struct ixgbe_hic_hdr hdr;
3237 	uint8_t port_number;
3238 	uint8_t pad;
3239 	__le16 activity_id;
3240 	__be32 data[FW_PHY_ACT_DATA_COUNT];
3241 } __packed __aligned(4);
3242 
3243 struct ixgbe_hic_phy_activity_resp {
3244 	struct ixgbe_hic_hdr hdr;
3245 	__be32 data[FW_PHY_ACT_DATA_COUNT];
3246 } __packed __aligned(4);
3247 
3248 /* Transmit Descriptor - Legacy */
3249 struct ixgbe_legacy_tx_desc {
3250 	uint64_t buffer_addr; /* Address of the descriptor's data buffer */
3251 	union {
3252 		__le32 data;
3253 		struct {
3254 			__le16 length; /* Data buffer length */
3255 			uint8_t cso; /* Checksum offset */
3256 			uint8_t cmd; /* Descriptor control */
3257 		} flags;
3258 	} lower;
3259 	union {
3260 		__le32 data;
3261 		struct {
3262 			uint8_t status; /* Descriptor status */
3263 			uint8_t css; /* Checksum start */
3264 			__le16 vlan;
3265 		} fields;
3266 	} upper;
3267 };
3268 
3269 /* Transmit Descriptor - Advanced */
3270 union ixgbe_adv_tx_desc {
3271 	struct {
3272 		__le64 buffer_addr; /* Address of descriptor's data buf */
3273 		__le32 cmd_type_len;
3274 		__le32 olinfo_status;
3275 	} read;
3276 	struct {
3277 		__le64 rsvd; /* Reserved */
3278 		__le32 nxtseq_seed;
3279 		__le32 status;
3280 	} wb;
3281 };
3282 
3283 /* Receive Descriptor - Legacy */
3284 struct ixgbe_legacy_rx_desc {
3285 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
3286 	__le16 length; /* Length of data DMAed into data buffer */
3287 	__le16 csum; /* Packet checksum */
3288 	uint8_t status;   /* Descriptor status */
3289 	uint8_t errors;   /* Descriptor Errors */
3290 	__le16 vlan;
3291 };
3292 
3293 /* Receive Descriptor - Advanced */
3294 union ixgbe_adv_rx_desc {
3295 	struct {
3296 		__le64 pkt_addr; /* Packet buffer address */
3297 		__le64 hdr_addr; /* Header buffer address */
3298 	} read;
3299 	struct {
3300 		struct {
3301 			union {
3302 				__le32 data;
3303 				struct {
3304 					__le16 pkt_info; /* RSS, Pkt type */
3305 					__le16 hdr_info; /* Splithdr, hdrlen */
3306 				} hs_rss;
3307 			} lo_dword;
3308 			union {
3309 				__le32 rss; /* RSS Hash */
3310 				struct {
3311 					__le16 ip_id; /* IP id */
3312 					__le16 csum; /* Packet Checksum */
3313 				} csum_ip;
3314 			} hi_dword;
3315 		} lower;
3316 		struct {
3317 			__le32 status_error; /* ext status/error */
3318 			__le16 length; /* Packet length */
3319 			__le16 vlan; /* VLAN tag */
3320 		} upper;
3321 	} wb;  /* writeback */
3322 };
3323 
3324 /* Context descriptors */
3325 struct ixgbe_adv_tx_context_desc {
3326 	__le32 vlan_macip_lens;
3327 	__le32 seqnum_seed;
3328 	__le32 type_tucmd_mlhl;
3329 	__le32 mss_l4len_idx;
3330 };
3331 
3332 /* Adv Transmit Descriptor Config Masks */
3333 #define IXGBE_ADVTXD_DTALEN_MASK	0x0000FFFF /* Data buf length(bytes) */
3334 #define IXGBE_ADVTXD_MAC_LINKSEC	0x00040000 /* Insert LinkSec */
3335 #define IXGBE_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 time stamp */
3336 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
3337 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK	0x000001FF /* IPSec ESP length */
3338 #define IXGBE_ADVTXD_DTYP_MASK		0x00F00000 /* DTYP mask */
3339 #define IXGBE_ADVTXD_DTYP_CTXT		0x00200000 /* Adv Context Desc */
3340 #define IXGBE_ADVTXD_DTYP_DATA		0x00300000 /* Adv Data Descriptor */
3341 #define IXGBE_ADVTXD_DCMD_EOP		IXGBE_TXD_CMD_EOP  /* End of Packet */
3342 #define IXGBE_ADVTXD_DCMD_IFCS		IXGBE_TXD_CMD_IFCS /* Insert FCS */
3343 #define IXGBE_ADVTXD_DCMD_RS		IXGBE_TXD_CMD_RS /* Report Status */
3344 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
3345 #define IXGBE_ADVTXD_DCMD_DEXT		IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
3346 #define IXGBE_ADVTXD_DCMD_VLE		IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
3347 #define IXGBE_ADVTXD_DCMD_TSE		0x80000000 /* TCP Seg enable */
3348 #define IXGBE_ADVTXD_STAT_DD		IXGBE_TXD_STAT_DD  /* Descriptor Done */
3349 #define IXGBE_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED pres in WB */
3350 #define IXGBE_ADVTXD_STAT_RSV		0x0000000C /* STA Reserved */
3351 #define IXGBE_ADVTXD_IDX_SHIFT		4 /* Adv desc Index shift */
3352 #define IXGBE_ADVTXD_CC			0x00000080 /* Check Context */
3353 #define IXGBE_ADVTXD_POPTS_SHIFT	8  /* Adv desc POPTS shift */
3354 #define IXGBE_ADVTXD_POPTS_IXSM		(IXGBE_TXD_POPTS_IXSM << \
3355 					 IXGBE_ADVTXD_POPTS_SHIFT)
3356 #define IXGBE_ADVTXD_POPTS_TXSM		(IXGBE_TXD_POPTS_TXSM << \
3357 					 IXGBE_ADVTXD_POPTS_SHIFT)
3358 #define IXGBE_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
3359 #define IXGBE_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
3360 #define IXGBE_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
3361 /* 1st&Last TSO-full iSCSI PDU */
3362 #define IXGBE_ADVTXD_POPTS_ISCO_FULL	0x00001800
3363 #define IXGBE_ADVTXD_POPTS_RSV		0x00002000 /* POPTS Reserved */
3364 #define IXGBE_ADVTXD_PAYLEN_MASK	0x0003FFFF /* Adv desc PAYLEN */
3365 #define IXGBE_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
3366 #define IXGBE_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
3367 #define IXGBE_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
3368 #define IXGBE_ADVTXD_TUCMD_IPV4		0x00000400 /* IP Packet Type: 1=IPv4 */
3369 #define IXGBE_ADVTXD_TUCMD_IPV6		0x00000000 /* IP Packet Type: 0=IPv6 */
3370 #define IXGBE_ADVTXD_TUCMD_L4T_UDP	0x00000000 /* L4 Packet TYPE of UDP */
3371 #define IXGBE_ADVTXD_TUCMD_L4T_TCP	0x00000800 /* L4 Packet TYPE of TCP */
3372 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP	0x00001000 /* L4 Packet TYPE of SCTP */
3373 #define IXGBE_ADVTXD_TUCMD_L4T_RSV	0x00001800 /* RSV L4 Packet TYPE */
3374 #define IXGBE_ADVTXD_TUCMD_MKRREQ	0x00002000 /* req Markers and CRC */
3375 #define IXGBE_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
3376 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3377 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3378 #define IXGBE_ADVTXT_TUCMD_FCOE		0x00008000 /* FCoE Frame Type */
3379 #define IXGBE_ADVTXD_FCOEF_EOF_MASK	(0x3 << 10) /* FC EOF index */
3380 #define IXGBE_ADVTXD_FCOEF_SOF		((1 << 2) << 10) /* FC SOF index */
3381 #define IXGBE_ADVTXD_FCOEF_PARINC	((1 << 3) << 10) /* Rel_Off in F_CTL */
3382 #define IXGBE_ADVTXD_FCOEF_ORIE		((1 << 4) << 10) /* Orientation End */
3383 #define IXGBE_ADVTXD_FCOEF_ORIS		((1 << 5) << 10) /* Orientation Start */
3384 #define IXGBE_ADVTXD_FCOEF_EOF_N	(0x0 << 10) /* 00: EOFn */
3385 #define IXGBE_ADVTXD_FCOEF_EOF_T	(0x1 << 10) /* 01: EOFt */
3386 #define IXGBE_ADVTXD_FCOEF_EOF_NI	(0x2 << 10) /* 10: EOFni */
3387 #define IXGBE_ADVTXD_FCOEF_EOF_A	(0x3 << 10) /* 11: EOFa */
3388 #define IXGBE_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
3389 #define IXGBE_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
3390 
3391 #define IXGBE_ADVTXD_OUTER_IPLEN	16 /* Adv ctxt OUTERIPLEN shift */
3392 #define IXGBE_ADVTXD_TUNNEL_LEN 	24 /* Adv ctxt TUNNELLEN shift */
3393 #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT	16 /* Adv Tx Desc Tunnel Type shift */
3394 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT	17 /* Adv Tx Desc OUTERIPCS Shift */
3395 #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE	1  /* Adv Tx Desc Tunnel Type NVGRE */
3396 /* Adv Tx Desc OUTERIPCS Shift for X550EM_a */
3397 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a	26
3398 /* Autonegotiation advertised speeds */
3399 typedef uint32_t ixgbe_autoneg_advertised;
3400 /* Link speed */
3401 typedef uint32_t ixgbe_link_speed;
3402 #define IXGBE_LINK_SPEED_UNKNOWN	0
3403 #define IXGBE_LINK_SPEED_10_FULL	0x0002
3404 #define IXGBE_LINK_SPEED_100_FULL	0x0008
3405 #define IXGBE_LINK_SPEED_1GB_FULL	0x0020
3406 #define IXGBE_LINK_SPEED_2_5GB_FULL	0x0400
3407 #define IXGBE_LINK_SPEED_5GB_FULL	0x0800
3408 #define IXGBE_LINK_SPEED_10GB_FULL	0x0080
3409 #define IXGBE_LINK_SPEED_82598_AUTONEG	(IXGBE_LINK_SPEED_1GB_FULL | \
3410 					 IXGBE_LINK_SPEED_10GB_FULL)
3411 #define IXGBE_LINK_SPEED_82599_AUTONEG	(IXGBE_LINK_SPEED_100_FULL | \
3412 					 IXGBE_LINK_SPEED_1GB_FULL | \
3413 					 IXGBE_LINK_SPEED_10GB_FULL)
3414 
3415 /* Physical layer type */
3416 typedef uint64_t ixgbe_physical_layer;
3417 #define IXGBE_PHYSICAL_LAYER_UNKNOWN		0
3418 #define IXGBE_PHYSICAL_LAYER_10GBASE_T		0x00001
3419 #define IXGBE_PHYSICAL_LAYER_1000BASE_T		0x00002
3420 #define IXGBE_PHYSICAL_LAYER_100BASE_TX		0x00004
3421 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU	0x00008
3422 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR		0x00010
3423 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM	0x00020
3424 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR		0x00040
3425 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4	0x00080
3426 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4	0x00100
3427 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX	0x00200
3428 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX	0x00400
3429 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR		0x00800
3430 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI	0x01000
3431 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA	0x02000
3432 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX	0x04000
3433 #define IXGBE_PHYSICAL_LAYER_10BASE_T		0x08000
3434 #define IXGBE_PHYSICAL_LAYER_2500BASE_KX	0x10000
3435 #define IXGBE_PHYSICAL_LAYER_1000BASE_LX	0x20000
3436 
3437 /* Flow Control Data Sheet defined values
3438  * Calculation and defines taken from 802.1bb Annex O
3439  */
3440 
3441 /* BitTimes (BT) conversion */
3442 #define IXGBE_BT2KB(BT)		((BT + (8 * 1024 - 1)) / (8 * 1024))
3443 #define IXGBE_B2BT(BT)		(BT * 8)
3444 
3445 /* Calculate Delay to respond to PFC */
3446 #define IXGBE_PFC_D	672
3447 
3448 /* Calculate Cable Delay */
3449 #define IXGBE_CABLE_DC	5556 /* Delay Copper */
3450 #define IXGBE_CABLE_DO	5000 /* Delay Optical */
3451 
3452 /* Calculate Interface Delay X540 */
3453 #define IXGBE_PHY_DC	25600 /* Delay 10G BASET */
3454 #define IXGBE_MAC_DC	8192  /* Delay Copper XAUI interface */
3455 #define IXGBE_XAUI_DC	(2 * 2048) /* Delay Copper Phy */
3456 
3457 #define IXGBE_ID_X540	(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
3458 
3459 /* Calculate Interface Delay 82598, 82599 */
3460 #define IXGBE_PHY_D	12800
3461 #define IXGBE_MAC_D	4096
3462 #define IXGBE_XAUI_D	(2 * 1024)
3463 
3464 #define IXGBE_ID	(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3465 
3466 /* Calculate Delay incurred from higher layer */
3467 #define IXGBE_HD	6144
3468 
3469 /* Calculate PCI Bus delay for low thresholds */
3470 #define IXGBE_PCI_DELAY	10000
3471 
3472 /* Calculate X540 delay value in bit times */
3473 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3474 			((36 * \
3475 			  (IXGBE_B2BT(_max_frame_link) + \
3476 			   IXGBE_PFC_D + \
3477 			   (2 * IXGBE_CABLE_DC) + \
3478 			   (2 * IXGBE_ID_X540) + \
3479 			   IXGBE_HD) / 25 + 1) + \
3480 			 2 * IXGBE_B2BT(_max_frame_tc))
3481 
3482 /* Calculate 82599, 82598 delay value in bit times */
3483 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3484 			((36 * \
3485 			  (IXGBE_B2BT(_max_frame_link) + \
3486 			   IXGBE_PFC_D + \
3487 			   (2 * IXGBE_CABLE_DC) + \
3488 			   (2 * IXGBE_ID) + \
3489 			   IXGBE_HD) / 25 + 1) + \
3490 			 2 * IXGBE_B2BT(_max_frame_tc))
3491 
3492 /* Calculate low threshold delay values */
3493 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3494 			(2 * IXGBE_B2BT(_max_frame_tc) + \
3495 			(36 * IXGBE_PCI_DELAY / 25) + 1)
3496 #define IXGBE_LOW_DV(_max_frame_tc) \
3497 			(2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3498 
3499 /* Software ATR hash keys */
3500 #define IXGBE_ATR_BUCKET_HASH_KEY	0x3DAD14E2
3501 #define IXGBE_ATR_SIGNATURE_HASH_KEY	0x174D3614
3502 
3503 /* Software ATR input stream values and masks */
3504 #define IXGBE_ATR_HASH_MASK		0x7fff
3505 #define IXGBE_ATR_L4TYPE_MASK		0x3
3506 #define IXGBE_ATR_L4TYPE_UDP		0x1
3507 #define IXGBE_ATR_L4TYPE_TCP		0x2
3508 #define IXGBE_ATR_L4TYPE_SCTP		0x3
3509 #define IXGBE_ATR_L4TYPE_IPV6_MASK	0x4
3510 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK	0x10
3511 enum ixgbe_atr_flow_type {
3512 	IXGBE_ATR_FLOW_TYPE_IPV4	= 0x0,
3513 	IXGBE_ATR_FLOW_TYPE_UDPV4	= 0x1,
3514 	IXGBE_ATR_FLOW_TYPE_TCPV4	= 0x2,
3515 	IXGBE_ATR_FLOW_TYPE_SCTPV4	= 0x3,
3516 	IXGBE_ATR_FLOW_TYPE_IPV6	= 0x4,
3517 	IXGBE_ATR_FLOW_TYPE_UDPV6	= 0x5,
3518 	IXGBE_ATR_FLOW_TYPE_TCPV6	= 0x6,
3519 	IXGBE_ATR_FLOW_TYPE_SCTPV6	= 0x7,
3520 	IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4	= 0x10,
3521 	IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4	= 0x11,
3522 	IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4	= 0x12,
3523 	IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4	= 0x13,
3524 	IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6	= 0x14,
3525 	IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6	= 0x15,
3526 	IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6	= 0x16,
3527 	IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6	= 0x17,
3528 };
3529 
3530 /* Flow Director ATR input struct. */
3531 union ixgbe_atr_input {
3532 	/*
3533 	 * Byte layout in order, all values with MSB first:
3534 	 *
3535 	 * vm_pool	- 1 byte
3536 	 * flow_type	- 1 byte
3537 	 * vlan_id	- 2 bytes
3538 	 * src_ip	- 16 bytes
3539 	 * inner_mac	- 6 bytes
3540 	 * cloud_mode	- 2 bytes
3541 	 * tni_vni	- 4 bytes
3542 	 * dst_ip	- 16 bytes
3543 	 * src_port	- 2 bytes
3544 	 * dst_port	- 2 bytes
3545 	 * flex_bytes	- 2 bytes
3546 	 * bkt_hash	- 2 bytes
3547 	 */
3548 	struct {
3549 		uint8_t vm_pool;
3550 		uint8_t flow_type;
3551 		__be16 vlan_id;
3552 		__be32 dst_ip[4];
3553 		__be32 src_ip[4];
3554 		uint8_t inner_mac[6];
3555 		__be16 tunnel_type;
3556 		__be32 tni_vni;
3557 		__be16 src_port;
3558 		__be16 dst_port;
3559 		__be16 flex_bytes;
3560 		__be16 bkt_hash;
3561 	} formatted;
3562 	__be32 dword_stream[14];
3563 };
3564 
3565 /* Flow Director compressed ATR hash input struct */
3566 union ixgbe_atr_hash_dword {
3567 	struct {
3568 		uint8_t vm_pool;
3569 		uint8_t flow_type;
3570 		__be16 vlan_id;
3571 	} formatted;
3572 	__be32 ip;
3573 	struct {
3574 		__be16 src;
3575 		__be16 dst;
3576 	} port;
3577 	__be16 flex_bytes;
3578 	__be32 dword;
3579 };
3580 
3581 
3582 #define IXGBE_MVALS_INIT(m)	\
3583 	IXGBE_CAT(EEC, m),		\
3584 	IXGBE_CAT(FLA, m),		\
3585 	IXGBE_CAT(GRC, m),		\
3586 	IXGBE_CAT(SRAMREL, m),		\
3587 	IXGBE_CAT(FACTPS, m),		\
3588 	IXGBE_CAT(SWSM, m),		\
3589 	IXGBE_CAT(SWFW_SYNC, m),	\
3590 	IXGBE_CAT(FWSM, m),		\
3591 	IXGBE_CAT(SDP0_GPIEN, m),	\
3592 	IXGBE_CAT(SDP1_GPIEN, m),	\
3593 	IXGBE_CAT(SDP2_GPIEN, m),	\
3594 	IXGBE_CAT(EICR_GPI_SDP0, m),	\
3595 	IXGBE_CAT(EICR_GPI_SDP1, m),	\
3596 	IXGBE_CAT(EICR_GPI_SDP2, m),	\
3597 	IXGBE_CAT(CIAA, m),		\
3598 	IXGBE_CAT(CIAD, m),		\
3599 	IXGBE_CAT(I2C_CLK_IN, m),	\
3600 	IXGBE_CAT(I2C_CLK_OUT, m),	\
3601 	IXGBE_CAT(I2C_DATA_IN, m),	\
3602 	IXGBE_CAT(I2C_DATA_OUT, m),	\
3603 	IXGBE_CAT(I2C_DATA_OE_N_EN, m),	\
3604 	IXGBE_CAT(I2C_BB_EN, m),	\
3605 	IXGBE_CAT(I2C_CLK_OE_N_EN, m),	\
3606 	IXGBE_CAT(I2CCTL, m)
3607 
3608 enum ixgbe_mvals {
3609 	IXGBE_MVALS_INIT(_IDX),
3610 	IXGBE_MVALS_IDX_LIMIT
3611 };
3612 
3613 /*
3614  * Unavailable: The FCoE Boot Option ROM is not present in the flash.
3615  * Disabled: Present; boot order is not set for any targets on the port.
3616  * Enabled: Present; boot order is set for at least one target on the port.
3617  */
3618 enum ixgbe_fcoe_boot_status {
3619 	ixgbe_fcoe_bootstatus_disabled = 0,
3620 	ixgbe_fcoe_bootstatus_enabled = 1,
3621 	ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
3622 };
3623 
3624 enum ixgbe_eeprom_type {
3625 	ixgbe_eeprom_uninitialized = 0,
3626 	ixgbe_eeprom_spi,
3627 	ixgbe_flash,
3628 	ixgbe_eeprom_none /* No NVM support */
3629 };
3630 
3631 enum ixgbe_mac_type {
3632 	ixgbe_mac_unknown = 0,
3633 	ixgbe_mac_82598EB,
3634 	ixgbe_mac_82599EB,
3635 	ixgbe_mac_82599_vf,
3636 	ixgbe_mac_X540,
3637 	ixgbe_mac_X540_vf,
3638 	ixgbe_mac_X550,
3639 	ixgbe_mac_X550EM_x,
3640 	ixgbe_mac_X550EM_a,
3641 	ixgbe_mac_X550_vf,
3642 	ixgbe_mac_X550EM_x_vf,
3643 	ixgbe_mac_X550EM_a_vf,
3644 	ixgbe_num_macs
3645 };
3646 
3647 enum ixgbe_phy_type {
3648 	ixgbe_phy_unknown = 0,
3649 	ixgbe_phy_none,
3650 	ixgbe_phy_tn,
3651 	ixgbe_phy_aq,
3652 	ixgbe_phy_x550em_kr,
3653 	ixgbe_phy_x550em_kx4,
3654 	ixgbe_phy_x550em_xfi,
3655 	ixgbe_phy_x550em_ext_t,
3656 	ixgbe_phy_ext_1g_t,
3657 	ixgbe_phy_cu_unknown,
3658 	ixgbe_phy_qt,
3659 	ixgbe_phy_xaui,
3660 	ixgbe_phy_nl,
3661 	ixgbe_phy_sfp_passive_tyco,
3662 	ixgbe_phy_sfp_passive_unknown,
3663 	ixgbe_phy_sfp_active_unknown,
3664 	ixgbe_phy_sfp_avago,
3665 	ixgbe_phy_sfp_ftl,
3666 	ixgbe_phy_sfp_ftl_active,
3667 	ixgbe_phy_sfp_unknown,
3668 	ixgbe_phy_sfp_intel,
3669 	ixgbe_phy_qsfp_passive_unknown,
3670 	ixgbe_phy_qsfp_active_unknown,
3671 	ixgbe_phy_qsfp_intel,
3672 	ixgbe_phy_qsfp_unknown,
3673 	ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
3674 	ixgbe_phy_sgmii,
3675 	ixgbe_phy_fw,
3676 	ixgbe_phy_generic
3677 };
3678 
3679 /*
3680  * SFP+ module type IDs:
3681  *
3682  * ID	Module Type
3683  * =============
3684  * 0	SFP_DA_CU
3685  * 1	SFP_SR
3686  * 2	SFP_LR
3687  * 3	SFP_DA_CU_CORE0 - 82599-specific
3688  * 4	SFP_DA_CU_CORE1 - 82599-specific
3689  * 5	SFP_SR/LR_CORE0 - 82599-specific
3690  * 6	SFP_SR/LR_CORE1 - 82599-specific
3691  */
3692 enum ixgbe_sfp_type {
3693 	ixgbe_sfp_type_da_cu = 0,
3694 	ixgbe_sfp_type_sr = 1,
3695 	ixgbe_sfp_type_lr = 2,
3696 	ixgbe_sfp_type_da_cu_core0 = 3,
3697 	ixgbe_sfp_type_da_cu_core1 = 4,
3698 	ixgbe_sfp_type_srlr_core0 = 5,
3699 	ixgbe_sfp_type_srlr_core1 = 6,
3700 	ixgbe_sfp_type_da_act_lmt_core0 = 7,
3701 	ixgbe_sfp_type_da_act_lmt_core1 = 8,
3702 	ixgbe_sfp_type_1g_cu_core0 = 9,
3703 	ixgbe_sfp_type_1g_cu_core1 = 10,
3704 	ixgbe_sfp_type_1g_sx_core0 = 11,
3705 	ixgbe_sfp_type_1g_sx_core1 = 12,
3706 	ixgbe_sfp_type_1g_lx_core0 = 13,
3707 	ixgbe_sfp_type_1g_lx_core1 = 14,
3708 	ixgbe_sfp_type_not_present = 0xFFFE,
3709 	ixgbe_sfp_type_unknown = 0xFFFF
3710 };
3711 
3712 enum ixgbe_media_type {
3713 	ixgbe_media_type_unknown = 0,
3714 	ixgbe_media_type_fiber,
3715 	ixgbe_media_type_fiber_fixed,
3716 	ixgbe_media_type_fiber_qsfp,
3717 	ixgbe_media_type_copper,
3718 	ixgbe_media_type_backplane,
3719 	ixgbe_media_type_cx4,
3720 	ixgbe_media_type_virtual
3721 };
3722 
3723 /* Flow Control Settings */
3724 enum ixgbe_fc_mode {
3725 	ixgbe_fc_none = 0,
3726 	ixgbe_fc_rx_pause,
3727 	ixgbe_fc_tx_pause,
3728 	ixgbe_fc_full,
3729 	ixgbe_fc_default
3730 };
3731 
3732 /* Smart Speed Settings */
3733 #define IXGBE_SMARTSPEED_MAX_RETRIES	3
3734 enum ixgbe_smart_speed {
3735 	ixgbe_smart_speed_auto = 0,
3736 	ixgbe_smart_speed_on,
3737 	ixgbe_smart_speed_off
3738 };
3739 
3740 /* PCI bus types */
3741 enum ixgbe_bus_type {
3742 	ixgbe_bus_type_unknown = 0,
3743 	ixgbe_bus_type_pci,
3744 	ixgbe_bus_type_pcix,
3745 	ixgbe_bus_type_pci_express,
3746 	ixgbe_bus_type_internal,
3747 	ixgbe_bus_type_reserved
3748 };
3749 
3750 /* PCI bus speeds */
3751 enum ixgbe_bus_speed {
3752 	ixgbe_bus_speed_unknown	= 0,
3753 	ixgbe_bus_speed_33	= 33,
3754 	ixgbe_bus_speed_66	= 66,
3755 	ixgbe_bus_speed_100	= 100,
3756 	ixgbe_bus_speed_120	= 120,
3757 	ixgbe_bus_speed_133	= 133,
3758 	ixgbe_bus_speed_2500	= 2500,
3759 	ixgbe_bus_speed_5000	= 5000,
3760 	ixgbe_bus_speed_8000	= 8000,
3761 	ixgbe_bus_speed_reserved
3762 };
3763 
3764 /* PCI bus widths */
3765 enum ixgbe_bus_width {
3766 	ixgbe_bus_width_unknown	= 0,
3767 	ixgbe_bus_width_pcie_x1	= 1,
3768 	ixgbe_bus_width_pcie_x2	= 2,
3769 	ixgbe_bus_width_pcie_x4	= 4,
3770 	ixgbe_bus_width_pcie_x8	= 8,
3771 	ixgbe_bus_width_32	= 32,
3772 	ixgbe_bus_width_64	= 64,
3773 	ixgbe_bus_width_reserved
3774 };
3775 
3776 struct ixgbe_addr_filter_info {
3777 	uint32_t num_mc_addrs;
3778 	uint32_t rar_used_count;
3779 	uint32_t mta_in_use;
3780 	uint32_t overflow_promisc;
3781 	bool user_set_promisc;
3782 };
3783 
3784 /* Bus parameters */
3785 struct ixgbe_bus_info {
3786 	enum ixgbe_bus_speed speed;
3787 	enum ixgbe_bus_width width;
3788 	enum ixgbe_bus_type type;
3789 
3790 	uint16_t func;
3791 	uint8_t lan_id;
3792 	uint16_t instance_id;
3793 };
3794 
3795 /* Flow control parameters */
3796 struct ixgbe_fc_info {
3797 	uint32_t high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
3798 	uint32_t low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
3799 	uint16_t pause_time; /* Flow Control Pause timer */
3800 	bool send_xon; /* Flow control send XON */
3801 	bool strict_ieee; /* Strict IEEE mode */
3802 	bool disable_fc_autoneg; /* Do not autonegotiate FC */
3803 	bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3804 	enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3805 	enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3806 };
3807 
3808 /* Statistics counters collected by the MAC */
3809 struct ixgbe_hw_stats {
3810 	uint64_t crcerrs;
3811 	uint64_t illerrc;
3812 	uint64_t errbc;
3813 	uint64_t mspdc;
3814 	uint64_t mpctotal;
3815 	uint64_t mpc[8];
3816 	uint64_t mlfc;
3817 	uint64_t mrfc;
3818 	uint64_t rlec;
3819 	uint64_t lxontxc;
3820 	uint64_t lxonrxc;
3821 	uint64_t lxofftxc;
3822 	uint64_t lxoffrxc;
3823 	uint64_t pxontxc[8];
3824 	uint64_t pxonrxc[8];
3825 	uint64_t pxofftxc[8];
3826 	uint64_t pxoffrxc[8];
3827 	uint64_t prc64;
3828 	uint64_t prc127;
3829 	uint64_t prc255;
3830 	uint64_t prc511;
3831 	uint64_t prc1023;
3832 	uint64_t prc1522;
3833 	uint64_t gprc;
3834 	uint64_t bprc;
3835 	uint64_t mprc;
3836 	uint64_t gptc;
3837 	uint64_t gorc;
3838 	uint64_t gotc;
3839 	uint64_t rnbc[8];
3840 	uint64_t ruc;
3841 	uint64_t rfc;
3842 	uint64_t roc;
3843 	uint64_t rjc;
3844 	uint64_t mngprc;
3845 	uint64_t mngpdc;
3846 	uint64_t mngptc;
3847 	uint64_t tor;
3848 	uint64_t tpr;
3849 	uint64_t tpt;
3850 	uint64_t ptc64;
3851 	uint64_t ptc127;
3852 	uint64_t ptc255;
3853 	uint64_t ptc511;
3854 	uint64_t ptc1023;
3855 	uint64_t ptc1522;
3856 	uint64_t mptc;
3857 	uint64_t bptc;
3858 	uint64_t xec;
3859 	uint64_t qprc[16];
3860 	uint64_t qptc[16];
3861 	uint64_t qbrc[16];
3862 	uint64_t qbtc[16];
3863 	uint64_t qprdc[16];
3864 	uint64_t pxon2offc[8];
3865 	uint64_t fdirustat_add;
3866 	uint64_t fdirustat_remove;
3867 	uint64_t fdirfstat_fadd;
3868 	uint64_t fdirfstat_fremove;
3869 	uint64_t fdirmatch;
3870 	uint64_t fdirmiss;
3871 	uint64_t fccrc;
3872 	uint64_t fclast;
3873 	uint64_t fcoerpdc;
3874 	uint64_t fcoeprc;
3875 	uint64_t fcoeptc;
3876 	uint64_t fcoedwrc;
3877 	uint64_t fcoedwtc;
3878 	uint64_t fcoe_noddp;
3879 	uint64_t fcoe_noddp_ext_buff;
3880 	uint64_t ldpcec;
3881 	uint64_t pcrc8ec;
3882 	uint64_t b2ospc;
3883 	uint64_t b2ogprc;
3884 	uint64_t o2bgptc;
3885 	uint64_t o2bspc;
3886 };
3887 
3888 /* forward declaration */
3889 struct ixgbe_hw;
3890 
3891 /* iterator type for walking multicast address lists */
3892 typedef uint8_t* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, uint8_t **mc_addr_ptr,
3893 				  uint32_t *vmdq);
3894 
3895 /* Function pointer table */
3896 struct ixgbe_eeprom_operations {
3897 	int32_t (*init_params)(struct ixgbe_hw *);
3898 	int32_t (*read)(struct ixgbe_hw *, uint16_t, uint16_t *);
3899 	int32_t (*write)(struct ixgbe_hw *, uint16_t, uint16_t);
3900 	int32_t (*validate_checksum)(struct ixgbe_hw *, uint16_t *);
3901 	int32_t (*update_checksum)(struct ixgbe_hw *);
3902 	int32_t (*calc_checksum)(struct ixgbe_hw *);
3903 };
3904 
3905 struct ixgbe_mac_operations {
3906 	int32_t (*init_hw)(struct ixgbe_hw *);
3907 	int32_t (*reset_hw)(struct ixgbe_hw *);
3908 	int32_t (*start_hw)(struct ixgbe_hw *);
3909 	int32_t (*clear_hw_cntrs)(struct ixgbe_hw *);
3910 	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3911 	uint64_t (*get_supported_physical_layer)(struct ixgbe_hw *);
3912 	int32_t (*get_mac_addr)(struct ixgbe_hw *, uint8_t *);
3913 	int32_t (*get_device_caps)(struct ixgbe_hw *, uint16_t *);
3914 	int32_t (*stop_adapter)(struct ixgbe_hw *);
3915 	int32_t (*get_bus_info)(struct ixgbe_hw *);
3916 	int32_t (*negotiate_api_version)(struct ixgbe_hw *, int);
3917 	void (*set_lan_id)(struct ixgbe_hw *);
3918 	int32_t (*read_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t*);
3919 	int32_t (*write_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t);
3920 	int32_t (*setup_sfp)(struct ixgbe_hw *);
3921 	int32_t (*enable_rx_dma)(struct ixgbe_hw *, uint32_t);
3922 	int32_t (*disable_sec_rx_path)(struct ixgbe_hw *);
3923 	int32_t (*enable_sec_rx_path)(struct ixgbe_hw *);
3924 	int32_t (*acquire_swfw_sync)(struct ixgbe_hw *, uint32_t);
3925 	void (*release_swfw_sync)(struct ixgbe_hw *, uint32_t);
3926 	void (*init_swfw_sync)(struct ixgbe_hw *);
3927 	int32_t (*prot_autoc_read)(struct ixgbe_hw *, bool *, uint32_t *);
3928 	int32_t (*prot_autoc_write)(struct ixgbe_hw *, uint32_t, bool);
3929 
3930 	/* Link */
3931 	void (*disable_tx_laser)(struct ixgbe_hw *);
3932 	void (*enable_tx_laser)(struct ixgbe_hw *);
3933 	void (*flap_tx_laser)(struct ixgbe_hw *);
3934 	int32_t (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3935 	int32_t (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3936 	int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3937 	int32_t (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3938 				     bool *);
3939 	void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3940 
3941 	/* LED */
3942 	int32_t (*led_on)(struct ixgbe_hw *, uint32_t);
3943 	int32_t (*led_off)(struct ixgbe_hw *, uint32_t);
3944 	int32_t (*blink_led_start)(struct ixgbe_hw *, uint32_t);
3945 	int32_t (*blink_led_stop)(struct ixgbe_hw *, uint32_t);
3946 
3947 	/* RAR, Multicast, VLAN */
3948 	int32_t (*set_rar)(struct ixgbe_hw *, uint32_t, uint8_t *, uint32_t, uint32_t);
3949 	int32_t (*set_uc_addr)(struct ixgbe_hw *, uint32_t, uint8_t *);
3950 	int32_t (*clear_rar)(struct ixgbe_hw *, uint32_t);
3951 	int32_t (*insert_mac_addr)(struct ixgbe_hw *, uint8_t *, uint32_t);
3952 	int32_t (*set_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t);
3953 	int32_t (*clear_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t);
3954 	int32_t (*init_rx_addrs)(struct ixgbe_hw *);
3955 	int32_t (*update_mc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t,
3956 				   ixgbe_mc_addr_itr, bool clear);
3957 	int32_t (*update_xcast_mode)(struct ixgbe_hw *, int);
3958 	int32_t (*get_link_state)(struct ixgbe_hw *hw, bool *link_state);
3959 	int32_t (*enable_mc)(struct ixgbe_hw *);
3960 	int32_t (*disable_mc)(struct ixgbe_hw *);
3961 	int32_t (*clear_vfta)(struct ixgbe_hw *);
3962 	int32_t (*set_vfta)(struct ixgbe_hw *, uint32_t, uint32_t, bool, bool);
3963 	int32_t (*set_vlvf)(struct ixgbe_hw *, uint32_t, uint32_t, bool, uint32_t *, uint32_t,
3964 			bool);
3965 	int32_t (*set_rlpml)(struct ixgbe_hw *, uint16_t);
3966 	int32_t (*init_uta_tables)(struct ixgbe_hw *);
3967 	void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3968 	void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3969 
3970 	/* Flow Control */
3971 	int32_t (*fc_enable)(struct ixgbe_hw *);
3972 	int32_t (*setup_fc)(struct ixgbe_hw *);
3973 	void (*fc_autoneg)(struct ixgbe_hw *);
3974 
3975 	/* Manageability interface */
3976 	void (*disable_rx)(struct ixgbe_hw *hw);
3977 	void (*enable_rx)(struct ixgbe_hw *hw);
3978 	void (*stop_mac_link_on_d3)(struct ixgbe_hw *);
3979 	void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3980 					   unsigned int);
3981 	int32_t (*dmac_update_tcs)(struct ixgbe_hw *hw);
3982 	int32_t (*dmac_config_tcs)(struct ixgbe_hw *hw);
3983 	int32_t (*dmac_config)(struct ixgbe_hw *hw);
3984 	int32_t (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
3985 	int32_t (*read_iosf_sb_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint32_t *);
3986 	int32_t (*write_iosf_sb_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint32_t);
3987 };
3988 
3989 struct ixgbe_phy_operations {
3990 	int32_t (*identify)(struct ixgbe_hw *);
3991 	int32_t (*identify_sfp)(struct ixgbe_hw *);
3992 	int32_t (*init)(struct ixgbe_hw *);
3993 	int32_t (*reset)(struct ixgbe_hw *);
3994 	int32_t (*read_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t *);
3995 	int32_t (*write_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t);
3996 	int32_t (*read_reg_mdi)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t *);
3997 	int32_t (*write_reg_mdi)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t);
3998 	int32_t (*setup_link)(struct ixgbe_hw *);
3999 	int32_t (*setup_internal_link)(struct ixgbe_hw *);
4000 	int32_t (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
4001 	int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
4002 	int32_t (*get_firmware_version)(struct ixgbe_hw *, uint16_t *);
4003 	int32_t (*read_i2c_byte)(struct ixgbe_hw *, uint8_t, uint8_t, uint8_t *);
4004 	int32_t (*write_i2c_byte)(struct ixgbe_hw *, uint8_t, uint8_t, uint8_t);
4005 	int32_t (*read_i2c_eeprom)(struct ixgbe_hw *, uint8_t , uint8_t *);
4006 	int32_t (*write_i2c_eeprom)(struct ixgbe_hw *, uint8_t, uint8_t);
4007 	void (*i2c_bus_clear)(struct ixgbe_hw *);
4008 	/*depreatced*/
4009 	int32_t (*read_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
4010 	int32_t (*write_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
4011 	int32_t (*read_i2c_combined_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
4012 					      uint16_t *value);
4013 	int32_t (*write_i2c_combined_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
4014 					       uint16_t value);
4015 	/**/
4016 	int32_t (*check_overtemp)(struct ixgbe_hw *);
4017 	int32_t (*set_phy_power)(struct ixgbe_hw *, bool on);
4018 	int32_t (*enter_lplu)(struct ixgbe_hw *);
4019 	int32_t (*handle_lasi)(struct ixgbe_hw *hw);
4020 	int32_t (*read_i2c_byte_unlocked)(struct ixgbe_hw *, uint8_t offset, uint8_t addr,
4021 				      uint8_t *value);
4022 	int32_t (*write_i2c_byte_unlocked)(struct ixgbe_hw *, uint8_t offset, uint8_t addr,
4023 				       uint8_t value);
4024 };
4025 
4026 struct ixgbe_link_operations {
4027 	int32_t (*read_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
4028 	int32_t (*read_link_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
4029 				  uint16_t *val);
4030 	int32_t (*write_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
4031 	int32_t (*write_link_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
4032 				   uint16_t val);
4033 };
4034 
4035 struct ixgbe_link_info {
4036 	struct ixgbe_link_operations ops;
4037 	uint8_t addr;
4038 };
4039 
4040 struct ixgbe_eeprom_info {
4041 	struct ixgbe_eeprom_operations ops;
4042 	enum ixgbe_eeprom_type type;
4043 	uint32_t semaphore_delay;
4044 	uint16_t word_size;
4045 	uint16_t address_bits;
4046 	uint16_t word_page_size;
4047 	uint16_t ctrl_word_3;
4048 };
4049 
4050 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
4051 struct ixgbe_mac_info {
4052 	struct ixgbe_mac_operations ops;
4053 	enum ixgbe_mac_type type;
4054 	uint8_t addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4055 	uint8_t perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4056 #define IXGBE_MAX_MTA			128
4057 	uint32_t mta_shadow[IXGBE_MAX_MTA];
4058 	int32_t mc_filter_type;
4059 	uint32_t mcft_size;
4060 	uint32_t vft_size;
4061 	uint32_t num_rar_entries;
4062 	uint32_t rar_highwater;
4063 	uint32_t rx_pb_size;
4064 	uint32_t max_tx_queues;
4065 	uint32_t max_rx_queues;
4066 	uint32_t orig_autoc;
4067 	bool get_link_status;
4068 	uint32_t orig_autoc2;
4069 	uint16_t max_msix_vectors;
4070 	bool arc_subsystem_valid;
4071 	bool orig_link_settings_stored;
4072 	bool autotry_restart;
4073 	uint8_t flags;
4074 	struct ixgbe_dmac_config dmac_config;
4075 	bool set_lben;
4076 	uint32_t  max_link_up_time;
4077 };
4078 
4079 struct ixgbe_phy_info {
4080 	struct ixgbe_phy_operations ops;
4081 	enum ixgbe_phy_type type;
4082 	uint32_t addr;
4083 	uint32_t id;
4084 	enum ixgbe_sfp_type sfp_type;
4085 	bool sfp_setup_needed;
4086 	uint32_t revision;
4087 	enum ixgbe_media_type media_type;
4088 	uint32_t phy_semaphore_mask;
4089 	bool reset_disable;
4090 	ixgbe_autoneg_advertised autoneg_advertised;
4091 	ixgbe_link_speed speeds_supported;
4092 	ixgbe_link_speed eee_speeds_supported;
4093 	ixgbe_link_speed eee_speeds_advertised;
4094 	enum ixgbe_smart_speed smart_speed;
4095 	bool smart_speed_active;
4096 	bool multispeed_fiber;
4097 	bool reset_if_overtemp;
4098 	bool qsfp_shared_i2c_bus;
4099 	uint32_t nw_mng_if_sel;
4100 };
4101 
4102 #define IXGBE_VFMAILBOX_SIZE	16 /* 16 32 bit words - 64 bytes */
4103 #define IXGBE_MAX_MULTICAST_ADDRESSES_VF  30
4104 
4105 #define IXGBE_VFMAILBOX		0x002FC
4106 #define IXGBE_VFMBMEM		0x00200
4107 
4108 /* Define mailbox register bits */
4109 #define IXGBE_VFMAILBOX_REQ	0x00000001 /* Request for PF Ready bit */
4110 #define IXGBE_VFMAILBOX_ACK	0x00000002 /* Ack PF message received */
4111 #define IXGBE_VFMAILBOX_VFU	0x00000004 /* VF owns the mailbox buffer */
4112 #define IXGBE_VFMAILBOX_PFU	0x00000008 /* PF owns the mailbox buffer */
4113 #define IXGBE_VFMAILBOX_PFSTS	0x00000010 /* PF wrote a message in the MB */
4114 #define IXGBE_VFMAILBOX_PFACK	0x00000020 /* PF ack the previous VF msg */
4115 #define IXGBE_VFMAILBOX_RSTI	0x00000040 /* PF has reset indication */
4116 #define IXGBE_VFMAILBOX_RSTD	0x00000080 /* PF has indicated reset done */
4117 #define IXGBE_VFMAILBOX_R2C_BITS	0x000000B0 /* All read to clear bits */
4118 
4119 #define IXGBE_PFMAILBOX_STS	0x00000001 /* Initiate message send to VF */
4120 #define IXGBE_PFMAILBOX_ACK	0x00000002 /* Ack message recv'd from VF */
4121 #define IXGBE_PFMAILBOX_VFU	0x00000004 /* VF owns the mailbox buffer */
4122 #define IXGBE_PFMAILBOX_PFU	0x00000008 /* PF owns the mailbox buffer */
4123 #define IXGBE_PFMAILBOX_RVFU	0x00000010 /* Reset VFU - used when VF stuck */
4124 
4125 #define IXGBE_PFMBICR_VFREQ_MASK	0x0000FFFF /* bits for VF messages */
4126 #define IXGBE_PFMBICR_VFREQ_VF1		0x00000001 /* bit for VF 1 message */
4127 #define IXGBE_PFMBICR_VFACK_MASK	0xFFFF0000 /* bits for VF acks */
4128 #define IXGBE_PFMBICR_VFACK_VF1		0x00010000 /* bit for VF 1 ack */
4129 
4130 
4131 /* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the
4132  * PF.  The reverse is TRUE if it is IXGBE_PF_*.
4133  * Message results are the value or'd with 0xF0000000
4134  */
4135 #define IXGBE_VT_MSGTYPE_SUCCESS	0x80000000 /* Messages or'd with this
4136 						    * have succeeded
4137 						    */
4138 #define IXGBE_VT_MSGTYPE_FAILURE	0x40000000 /* Messages or'd with this
4139 						    * have failed
4140 						    */
4141 #define IXGBE_VT_MSGTYPE_CTS		0x20000000 /* Indicates that VF is still
4142 						    * clear to send requests
4143 						    */
4144 #define IXGBE_VT_MSGINFO_SHIFT	16
4145 /* bits 23:16 are used for extra info for certain messages */
4146 #define IXGBE_VT_MSGINFO_MASK	(0xFF << IXGBE_VT_MSGINFO_SHIFT)
4147 
4148 /* definitions to support mailbox API version negotiation */
4149 
4150 /*
4151  * each element denotes a version of the API; existing numbers may not
4152  * change; any additions must go at the end
4153  */
4154 enum ixgbe_pfvf_api_rev {
4155 	ixgbe_mbox_api_10,	/* API version 1.0, linux/freebsd VF driver */
4156 	ixgbe_mbox_api_20,	/* API version 2.0, solaris Phase1 VF driver */
4157 	ixgbe_mbox_api_11,	/* API version 1.1, linux/freebsd VF driver */
4158 	ixgbe_mbox_api_12,	/* API version 1.2, linux/freebsd VF driver */
4159 	ixgbe_mbox_api_13,	/* API version 1.3, linux/freebsd VF driver */
4160 	/* API 1.4 is being used in the upstream for IPsec */
4161 	ixgbe_mbox_api_14,	/* API version 1.4, linux/freebsd VF driver */
4162 	ixgbe_mbox_api_15,	/* API version 1.5, linux/freebsd VF driver */
4163 	/* This value should always be last */
4164 	ixgbe_mbox_api_unknown,	/* indicates that API version is not known */
4165 };
4166 
4167 /* mailbox API, legacy requests */
4168 #define IXGBE_VF_RESET		0x01 /* VF requests reset */
4169 #define IXGBE_VF_SET_MAC_ADDR	0x02 /* VF requests PF to set MAC addr */
4170 #define IXGBE_VF_SET_MULTICAST	0x03 /* VF requests PF to set MC addr */
4171 #define IXGBE_VF_SET_VLAN	0x04 /* VF requests PF to set VLAN */
4172 
4173 /* mailbox API, version 1.0 VF requests */
4174 #define IXGBE_VF_SET_LPE	0x05 /* VF requests PF to set VMOLR.LPE */
4175 #define IXGBE_VF_SET_MACVLAN	0x06 /* VF requests PF for unicast filter */
4176 #define IXGBE_VF_API_NEGOTIATE	0x08 /* negotiate API version */
4177 
4178 /* mailbox API, version 1.1 VF requests */
4179 #define IXGBE_VF_GET_QUEUES	0x09 /* get queue configuration */
4180 
4181 /* mailbox API, version 1.2 VF requests */
4182 #define IXGBE_VF_GET_RETA      0x0a    /* VF request for RETA */
4183 #define IXGBE_VF_GET_RSS_KEY	0x0b    /* get RSS key */
4184 #define IXGBE_VF_UPDATE_XCAST_MODE	0x0c
4185 #define IXGBE_VF_GET_LINK_STATE 0x10 /* get vf link state */
4186 
4187 /* mode choices for IXGBE_VF_UPDATE_XCAST_MODE */
4188 enum ixgbevf_xcast_modes {
4189 	IXGBEVF_XCAST_MODE_NONE = 0,
4190 	IXGBEVF_XCAST_MODE_MULTI,
4191 	IXGBEVF_XCAST_MODE_ALLMULTI,
4192 	IXGBEVF_XCAST_MODE_PROMISC,
4193 };
4194 
4195 /* GET_QUEUES return data indices within the mailbox */
4196 #define IXGBE_VF_TX_QUEUES	1	/* number of Tx queues supported */
4197 #define IXGBE_VF_RX_QUEUES	2	/* number of Rx queues supported */
4198 #define IXGBE_VF_TRANS_VLAN	3	/* Indication of port vlan */
4199 #define IXGBE_VF_DEF_QUEUE	4	/* Default queue offset */
4200 
4201 /* length of permanent address message returned from PF */
4202 #define IXGBE_VF_PERMADDR_MSG_LEN	4
4203 /* word in permanent address message with the current multicast type */
4204 #define IXGBE_VF_MC_TYPE_WORD		3
4205 
4206 #define IXGBE_PF_CONTROL_MSG		0x0100 /* PF control message */
4207 
4208 /* mailbox API, version 2.0 VF requests */
4209 #define IXGBE_VF_API_NEGOTIATE		0x08 /* negotiate API version */
4210 #define IXGBE_VF_GET_QUEUES		0x09 /* get queue configuration */
4211 #define IXGBE_VF_ENABLE_MACADDR		0x0A /* enable MAC address */
4212 #define IXGBE_VF_DISABLE_MACADDR	0x0B /* disable MAC address */
4213 #define IXGBE_VF_GET_MACADDRS		0x0C /* get all configured MAC addrs */
4214 #define IXGBE_VF_SET_MCAST_PROMISC	0x0D /* enable multicast promiscuous */
4215 #define IXGBE_VF_GET_MTU		0x0E /* get bounds on MTU */
4216 #define IXGBE_VF_SET_MTU		0x0F /* set a specific MTU */
4217 
4218 /* mailbox API, version 2.0 PF requests */
4219 #define IXGBE_PF_TRANSPARENT_VLAN	0x0101 /* enable transparent vlan */
4220 
4221 #define IXGBE_VF_MBX_INIT_TIMEOUT	2000 /* number of retries on mailbox */
4222 #define IXGBE_VF_MBX_INIT_DELAY		500  /* microseconds between retries */
4223 
4224 #define IXGBE_VF_IRQ_CLEAR_MASK	7
4225 #define IXGBE_VF_MAX_TX_QUEUES	8
4226 #define IXGBE_VF_MAX_RX_QUEUES	8
4227 /* DCB define */
4228 #define IXGBE_VF_MAX_TRAFFIC_CLASS	8
4229 
4230 #define IXGBE_VFCTRL		0x00000
4231 #define IXGBE_VFSTATUS		0x00008
4232 #define IXGBE_VFLINKS		0x00010
4233 #define IXGBE_VFFRTIMER		0x00048
4234 #define IXGBE_VFRXMEMWRAP	0x03190
4235 #define IXGBE_VTEICR		0x00100
4236 #define IXGBE_VTEICS		0x00104
4237 #define IXGBE_VTEIMS		0x00108
4238 #define IXGBE_VTEIMC		0x0010C
4239 #define IXGBE_VTEIAC		0x00110
4240 #define IXGBE_VTEIAM		0x00114
4241 #define IXGBE_VTEITR(x)		(0x00820 + (4 * (x)))
4242 #define IXGBE_VTIVAR(x)		(0x00120 + (4 * (x)))
4243 #define IXGBE_VTIVAR_MISC	0x00140
4244 #define IXGBE_VTRSCINT(x)	(0x00180 + (4 * (x)))
4245 /* define IXGBE_VFPBACL  still says TBD in EAS */
4246 #define IXGBE_VFRDBAL(x)	(0x01000 + (0x40 * (x)))
4247 #define IXGBE_VFRDBAH(x)	(0x01004 + (0x40 * (x)))
4248 #define IXGBE_VFRDLEN(x)	(0x01008 + (0x40 * (x)))
4249 #define IXGBE_VFRDH(x)		(0x01010 + (0x40 * (x)))
4250 #define IXGBE_VFRDT(x)		(0x01018 + (0x40 * (x)))
4251 #define IXGBE_VFRXDCTL(x)	(0x01028 + (0x40 * (x)))
4252 #define IXGBE_VFSRRCTL(x)	(0x01014 + (0x40 * (x)))
4253 #define IXGBE_VFRSCCTL(x)	(0x0102C + (0x40 * (x)))
4254 #define IXGBE_VFPSRTYPE		0x00300
4255 #define IXGBE_VFTDBAL(x)	(0x02000 + (0x40 * (x)))
4256 #define IXGBE_VFTDBAH(x)	(0x02004 + (0x40 * (x)))
4257 #define IXGBE_VFTDLEN(x)	(0x02008 + (0x40 * (x)))
4258 #define IXGBE_VFTDH(x)		(0x02010 + (0x40 * (x)))
4259 #define IXGBE_VFTDT(x)		(0x02018 + (0x40 * (x)))
4260 #define IXGBE_VFTXDCTL(x)	(0x02028 + (0x40 * (x)))
4261 #define IXGBE_VFTDWBAL(x)	(0x02038 + (0x40 * (x)))
4262 #define IXGBE_VFTDWBAH(x)	(0x0203C + (0x40 * (x)))
4263 #define IXGBE_VFDCA_RXCTRL(x)	(0x0100C + (0x40 * (x)))
4264 #define IXGBE_VFDCA_TXCTRL(x)	(0x0200c + (0x40 * (x)))
4265 #define IXGBE_VFGPRC		0x0101C
4266 #define IXGBE_VFGPTC		0x0201C
4267 #define IXGBE_VFGORC_LSB	0x01020
4268 #define IXGBE_VFGORC_MSB	0x01024
4269 #define IXGBE_VFGOTC_LSB	0x02020
4270 #define IXGBE_VFGOTC_MSB	0x02024
4271 #define IXGBE_VFMPRC		0x01034
4272 #define IXGBE_VFMRQC		0x3000
4273 #define IXGBE_VFRSSRK(x)	(0x3100 + ((x) * 4))
4274 #define IXGBE_VFRETA(x)		(0x3200 + ((x) * 4))
4275 
4276 struct ixgbe_mbx_operations {
4277 	void (*init_params)(struct ixgbe_hw *hw);
4278 	void (*release)(struct ixgbe_hw *, uint16_t);
4279 	int32_t  (*read)(struct ixgbe_hw *, uint32_t *, uint16_t,  uint16_t);
4280 	int32_t  (*write)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);
4281 	int32_t  (*read_posted)(struct ixgbe_hw *, uint32_t *, uint16_t,  uint16_t);
4282 	int32_t  (*write_posted)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);
4283 	int32_t  (*check_for_msg)(struct ixgbe_hw *, uint16_t);
4284 	int32_t  (*check_for_ack)(struct ixgbe_hw *, uint16_t);
4285 	int32_t  (*check_for_rst)(struct ixgbe_hw *, uint16_t);
4286 	int32_t  (*clear)(struct ixgbe_hw *, uint16_t);
4287 };
4288 
4289 struct ixgbe_mbx_stats {
4290 	uint32_t msgs_tx;
4291 	uint32_t msgs_rx;
4292 
4293 	uint32_t acks;
4294 	uint32_t reqs;
4295 	uint32_t rsts;
4296 };
4297 
4298 struct ixgbe_mbx_info {
4299 	struct ixgbe_mbx_operations ops;
4300 	struct ixgbe_mbx_stats stats;
4301 	uint32_t timeout;
4302 	uint32_t usec_delay;
4303 	uint32_t vf_mailbox;
4304 	uint16_t size;
4305 };
4306 
4307 struct ixgbe_hw {
4308 	uint8_t *hw_addr;
4309 	void *back;
4310 	struct ixgbe_mac_info mac;
4311 	struct ixgbe_addr_filter_info addr_ctrl;
4312 	struct ixgbe_fc_info fc;
4313 	struct ixgbe_phy_info phy;
4314 	struct ixgbe_link_info link;
4315 	struct ixgbe_eeprom_info eeprom;
4316 	struct ixgbe_bus_info bus;
4317 	struct ixgbe_mbx_info mbx;
4318 	const uint32_t *mvals;
4319 	uint16_t device_id;
4320 	uint16_t vendor_id;
4321 	uint16_t subsystem_device_id;
4322 	uint16_t subsystem_vendor_id;
4323 	uint8_t revision_id;
4324 	bool adapter_stopped;
4325 	int api_version;
4326 	bool force_full_reset;
4327 	bool allow_unsupported_sfp;
4328 	bool wol_enabled;
4329 	bool need_crosstalk_fix;
4330 };
4331 
4332 #define ixgbe_call_func(hw, func, params, error) \
4333 		(func != NULL) ? func params : error
4334 
4335 
4336 /* Error Codes */
4337 #define IXGBE_SUCCESS				0
4338 #define IXGBE_ERR_EEPROM			-1
4339 #define IXGBE_ERR_EEPROM_CHECKSUM		-2
4340 #define IXGBE_ERR_PHY				-3
4341 #define IXGBE_ERR_CONFIG			-4
4342 #define IXGBE_ERR_PARAM				-5
4343 #define IXGBE_ERR_MAC_TYPE			-6
4344 #define IXGBE_ERR_UNKNOWN_PHY			-7
4345 #define IXGBE_ERR_LINK_SETUP			-8
4346 #define IXGBE_ERR_ADAPTER_STOPPED		-9
4347 #define IXGBE_ERR_INVALID_MAC_ADDR		-10
4348 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED		-11
4349 #define IXGBE_ERR_MASTER_REQUESTS_PENDING	-12
4350 #define IXGBE_ERR_INVALID_LINK_SETTINGS		-13
4351 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE		-14
4352 #define IXGBE_ERR_RESET_FAILED			-15
4353 #define IXGBE_ERR_SWFW_SYNC			-16
4354 #define IXGBE_ERR_PHY_ADDR_INVALID		-17
4355 #define IXGBE_ERR_I2C				-18
4356 #define IXGBE_ERR_SFP_NOT_SUPPORTED		-19
4357 #define IXGBE_ERR_SFP_NOT_PRESENT		-20
4358 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT	-21
4359 #define IXGBE_ERR_NO_SAN_ADDR_PTR		-22
4360 #define IXGBE_ERR_FDIR_REINIT_FAILED		-23
4361 #define IXGBE_ERR_EEPROM_VERSION		-24
4362 #define IXGBE_ERR_NO_SPACE			-25
4363 #define IXGBE_ERR_OVERTEMP			-26
4364 #define IXGBE_ERR_FC_NOT_NEGOTIATED		-27
4365 #define IXGBE_ERR_FC_NOT_SUPPORTED		-28
4366 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE	-30
4367 #define IXGBE_ERR_PBA_SECTION			-31
4368 #define IXGBE_ERR_INVALID_ARGUMENT		-32
4369 #define IXGBE_ERR_HOST_INTERFACE_COMMAND	-33
4370 #define IXGBE_ERR_OUT_OF_MEM			-34
4371 #define IXGBE_BYPASS_FW_WRITE_FAILURE		-35
4372 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED		-36
4373 #define IXGBE_ERR_EEPROM_PROTECTED_REGION	-37
4374 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE		-38
4375 #define IXGBE_ERR_FW_RESP_INVALID		-39
4376 #define IXGBE_ERR_TOKEN_RETRY			-40
4377 #define IXGBE_ERR_MBX				-41
4378 #define IXGBE_ERR_MBX_NOMSG			-42
4379 #define IXGBE_ERR_TIMEOUT			-43
4380 
4381 #define IXGBE_NOT_IMPLEMENTED			0x7FFFFFFF
4382 
4383 
4384 #define BYPASS_PAGE_CTL0	0x00000000
4385 #define BYPASS_PAGE_CTL1	0x40000000
4386 #define BYPASS_PAGE_CTL2	0x80000000
4387 #define BYPASS_PAGE_M		0xc0000000
4388 #define BYPASS_WE		0x20000000
4389 
4390 #define BYPASS_AUTO	0x0
4391 #define BYPASS_NOP	0x0
4392 #define BYPASS_NORM	0x1
4393 #define BYPASS_BYPASS	0x2
4394 #define BYPASS_ISOLATE	0x3
4395 
4396 #define BYPASS_EVENT_MAIN_ON	0x1
4397 #define BYPASS_EVENT_AUX_ON	0x2
4398 #define BYPASS_EVENT_MAIN_OFF	0x3
4399 #define BYPASS_EVENT_AUX_OFF	0x4
4400 #define BYPASS_EVENT_WDT_TO	0x5
4401 #define BYPASS_EVENT_USR	0x6
4402 
4403 #define BYPASS_MODE_OFF_M	0x00000003
4404 #define BYPASS_STATUS_OFF_M	0x0000000c
4405 #define BYPASS_AUX_ON_M		0x00000030
4406 #define BYPASS_MAIN_ON_M	0x000000c0
4407 #define BYPASS_MAIN_OFF_M	0x00000300
4408 #define BYPASS_AUX_OFF_M	0x00000c00
4409 #define BYPASS_WDTIMEOUT_M	0x00003000
4410 #define BYPASS_WDT_ENABLE_M	0x00004000
4411 #define BYPASS_WDT_VALUE_M	0x00070000
4412 
4413 #define BYPASS_MODE_OFF_SHIFT	0
4414 #define BYPASS_STATUS_OFF_SHIFT	2
4415 #define BYPASS_AUX_ON_SHIFT	4
4416 #define BYPASS_MAIN_ON_SHIFT	6
4417 #define BYPASS_MAIN_OFF_SHIFT	8
4418 #define BYPASS_AUX_OFF_SHIFT	10
4419 #define BYPASS_WDTIMEOUT_SHIFT	12
4420 #define BYPASS_WDT_ENABLE_SHIFT	14
4421 #define BYPASS_WDT_TIME_SHIFT	16
4422 
4423 #define BYPASS_WDT_1	0x0
4424 #define BYPASS_WDT_1_5	0x1
4425 #define BYPASS_WDT_2	0x2
4426 #define BYPASS_WDT_3	0x3
4427 #define BYPASS_WDT_4	0x4
4428 #define BYPASS_WDT_8	0x5
4429 #define BYPASS_WDT_16	0x6
4430 #define BYPASS_WDT_32	0x7
4431 #define BYPASS_WDT_OFF	0xffff
4432 
4433 #define BYPASS_CTL1_TIME_M	0x01ffffff
4434 #define BYPASS_CTL1_VALID_M	0x02000000
4435 #define BYPASS_CTL1_OFFTRST_M	0x04000000
4436 #define BYPASS_CTL1_WDT_PET_M	0x08000000
4437 
4438 #define BYPASS_CTL1_VALID	0x02000000
4439 #define BYPASS_CTL1_OFFTRST	0x04000000
4440 #define BYPASS_CTL1_WDT_PET	0x08000000
4441 
4442 #define BYPASS_CTL2_DATA_M	0x000000ff
4443 #define BYPASS_CTL2_OFFSET_M	0x0000ff00
4444 #define BYPASS_CTL2_RW_M	0x00010000
4445 #define BYPASS_CTL2_HEAD_M	0x0ff00000
4446 
4447 #define BYPASS_CTL2_OFFSET_SHIFT	8
4448 #define BYPASS_CTL2_HEAD_SHIFT		20
4449 
4450 #define BYPASS_CTL2_RW		0x00010000
4451 
4452 struct ixgbe_bypass_eeprom {
4453 	uint32_t logs;
4454 	uint32_t clear_off;
4455 	uint8_t actions;
4456 };
4457 
4458 #define BYPASS_MAX_LOGS		43
4459 #define BYPASS_LOG_SIZE		5
4460 #define BYPASS_LOG_LINE_SIZE	37
4461 
4462 #define BYPASS_EEPROM_VER_ADD	0x02
4463 
4464 #define BYPASS_LOG_TIME_M	0x01ffffff
4465 #define BYPASS_LOG_TIME_VALID_M	0x02000000
4466 #define BYPASS_LOG_HEAD_M	0x04000000
4467 #define BYPASS_LOG_CLEAR_M	0x08000000
4468 #define BYPASS_LOG_EVENT_M	0xf0000000
4469 #define BYPASS_LOG_ACTION_M	0x03
4470 
4471 #define BYPASS_LOG_EVENT_SHIFT	28
4472 #define BYPASS_LOG_CLEAR_SHIFT	24 /* bit offset */
4473 
4474 #define IXGBE_FUSES0_GROUP(_i)		(0x11158 + ((_i) * 4))
4475 #define IXGBE_FUSES0_300MHZ		(1 << 5)
4476 #define IXGBE_FUSES0_REV_MASK		(3 << 6)
4477 
4478 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)	((P) ? 0x8010 : 0x4010)
4479 #define IXGBE_KRM_LINK_S1(P)		((P) ? 0x8200 : 0x4200)
4480 #define IXGBE_KRM_LINK_CTRL_1(P)	((P) ? 0x820C : 0x420C)
4481 #define IXGBE_KRM_AN_CNTL_1(P)		((P) ? 0x822C : 0x422C)
4482 #define IXGBE_KRM_AN_CNTL_4(P)		((P) ? 0x8238 : 0x4238)
4483 #define IXGBE_KRM_AN_CNTL_8(P)		((P) ? 0x8248 : 0x4248)
4484 #define IXGBE_KRM_PCS_KX_AN(P)		((P) ? 0x9918 : 0x5918)
4485 #define IXGBE_KRM_PCS_KX_AN_LP(P)	((P) ? 0x991C : 0x591C)
4486 #define IXGBE_KRM_SGMII_CTRL(P)		((P) ? 0x82A0 : 0x42A0)
4487 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P)	((P) ? 0x836C : 0x436C)
4488 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)	((P) ? 0x8634 : 0x4634)
4489 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)	((P) ? 0x8638 : 0x4638)
4490 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)	((P) ? 0x8B00 : 0x4B00)
4491 #define IXGBE_KRM_PMD_DFX_BURNIN(P)	((P) ? 0x8E00 : 0x4E00)
4492 #define IXGBE_KRM_PMD_FLX_MASK_ST20(P)	((P) ? 0x9054 : 0x5054)
4493 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)	((P) ? 0x9520 : 0x5520)
4494 #define IXGBE_KRM_RX_ANA_CTL(P)		((P) ? 0x9A00 : 0x5A00)
4495 
4496 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA		~(0x3 << 20)
4497 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR		(1u << 20)
4498 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR		(0x2 << 20)
4499 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN		(1u << 25)
4500 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN		(1u << 26)
4501 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN		(1u << 27)
4502 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M		~(0x7 << 28)
4503 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M		(1u << 28)
4504 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G		(0x2 << 28)
4505 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G		(0x3 << 28)
4506 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN		(0x4 << 28)
4507 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G		(0x7 << 28)
4508 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK		(0x7 << 28)
4509 #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART	(1u << 31)
4510 
4511 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B		(1 << 9)
4512 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS		(1 << 11)
4513 
4514 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK	(0x7 << 8)
4515 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G	(2 << 8)
4516 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G	(4 << 8)
4517 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN		(1 << 12)
4518 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN	(1 << 13)
4519 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ		(1 << 14)
4520 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC		(1 << 15)
4521 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX		(1 << 16)
4522 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR		(1 << 18)
4523 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX		(1 << 24)
4524 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR		(1 << 26)
4525 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE		(1 << 28)
4526 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE		(1 << 29)
4527 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART		(1U << 31)
4528 
4529 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE			(1 << 28)
4530 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE			(1 << 29)
4531 #define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE			(1 << 1)
4532 #define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE			(1 << 2)
4533 #define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE		(1 << 2)
4534 #define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE		(1 << 3)
4535 #define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73		(1 << 29)
4536 #define IXGBE_KRM_AN_CNTL_8_LINEAR			(1 << 0)
4537 #define IXGBE_KRM_AN_CNTL_8_LIMITING			(1 << 1)
4538 
4539 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE		(1 << 10)
4540 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE		(1 << 11)
4541 
4542 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D	(1 << 12)
4543 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D		(1 << 19)
4544 
4545 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN			(1 << 6)
4546 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN		(1 << 15)
4547 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN		(1 << 16)
4548 
4549 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL	(1 << 4)
4550 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS	(1 << 2)
4551 
4552 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK	(0x3 << 16)
4553 
4554 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN	(1 << 1)
4555 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN	(1 << 2)
4556 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN		(1 << 3)
4557 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN		(1U << 31)
4558 
4559 #define IXGBE_SB_IOSF_INDIRECT_CTRL	0x00011144
4560 #define IXGBE_SB_IOSF_INDIRECT_DATA	0x00011148
4561 
4562 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT		0
4563 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK		0xFF
4564 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT	18
4565 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK	\
4566 				(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
4567 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT	20
4568 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK	\
4569 				(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4570 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT	28
4571 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK	0x7
4572 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT		31
4573 #define IXGBE_SB_IOSF_CTRL_BUSY		(1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4574 #define IXGBE_SB_IOSF_TARGET_KR_PHY	0
4575 
4576 #define IXGBE_NW_MNG_IF_SEL		0x00011178
4577 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT	(1u << 1)
4578 #define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE	(1u << 2)
4579 #define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO	(1u << 13)
4580 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M	(1u << 17)
4581 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M	(1u << 18)
4582 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G	(1u << 19)
4583 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G	(1u << 20)
4584 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G	(1u << 21)
4585 #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE	(1u << 25)
4586 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
4587 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
4588 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD	\
4589 				(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
4590 
4591 /* PHY */
4592 #define IXGBE_I2C_EEPROM_DEV_ADDR	0xA0
4593 #define IXGBE_I2C_EEPROM_DEV_ADDR2	0xA2
4594 #define IXGBE_I2C_EEPROM_BANK_LEN	0xFF
4595 
4596 /* EEPROM byte offsets */
4597 #define IXGBE_SFF_IDENTIFIER		0x0
4598 #define IXGBE_SFF_IDENTIFIER_SFP	0x3
4599 #define IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
4600 #define IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
4601 #define IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
4602 #define IXGBE_SFF_1GBE_COMP_CODES	0x6
4603 #define IXGBE_SFF_10GBE_COMP_CODES	0x3
4604 #define IXGBE_SFF_CABLE_TECHNOLOGY	0x8
4605 #define IXGBE_SFF_CABLE_SPEC_COMP	0x3C
4606 #define IXGBE_SFF_SFF_8472_SWAP		0x5C
4607 #define IXGBE_SFF_SFF_8472_COMP		0x5E
4608 #define IXGBE_SFF_SFF_8472_OSCB		0x6E
4609 #define IXGBE_SFF_SFF_8472_ESCB		0x76
4610 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS	0xD
4611 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0	0xA5
4612 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1	0xA6
4613 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2	0xA7
4614 #define IXGBE_SFF_QSFP_CONNECTOR	0x82
4615 #define IXGBE_SFF_QSFP_10GBE_COMP	0x83
4616 #define IXGBE_SFF_QSFP_1GBE_COMP	0x86
4617 #define IXGBE_SFF_QSFP_CABLE_LENGTH	0x92
4618 #define IXGBE_SFF_QSFP_DEVICE_TECH	0x93
4619 
4620 /* Bitmasks */
4621 #define IXGBE_SFF_DA_PASSIVE_CABLE	0x4
4622 #define IXGBE_SFF_DA_ACTIVE_CABLE	0x8
4623 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
4624 #define IXGBE_SFF_1GBASESX_CAPABLE	0x1
4625 #define IXGBE_SFF_1GBASELX_CAPABLE	0x2
4626 #define IXGBE_SFF_1GBASET_CAPABLE	0x8
4627 #define IXGBE_SFF_10GBASESR_CAPABLE	0x10
4628 #define IXGBE_SFF_10GBASELR_CAPABLE	0x20
4629 #define IXGBE_SFF_DA_BAD_HP_CABLE	0x80
4630 #define IXGBE_SFF_SOFT_RS_SELECT_MASK	0x8
4631 #define IXGBE_SFF_SOFT_RS_SELECT_10G	0x8
4632 #define IXGBE_SFF_SOFT_RS_SELECT_1G	0x0
4633 #define IXGBE_SFF_ADDRESSING_MODE	0x4
4634 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE	0x1
4635 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE	0x8
4636 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE	0x23
4637 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL	0x0
4638 #define IXGBE_I2C_EEPROM_READ_MASK	0x100
4639 #define IXGBE_I2C_EEPROM_STATUS_MASK	0x3
4640 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
4641 #define IXGBE_I2C_EEPROM_STATUS_PASS	0x1
4642 #define IXGBE_I2C_EEPROM_STATUS_FAIL	0x2
4643 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
4644 
4645 #define IXGBE_CS4227			0xBE	/* CS4227 address */
4646 #define IXGBE_CS4227_GLOBAL_ID_LSB	0
4647 #define IXGBE_CS4227_GLOBAL_ID_MSB	1
4648 #define IXGBE_CS4227_SCRATCH		2
4649 #define IXGBE_CS4227_GLOBAL_ID_VALUE	0x03E5
4650 #define IXGBE_CS4227_EFUSE_PDF_SKU	0x19F
4651 #define IXGBE_CS4223_SKU_ID		0x0010	/* Quad port */
4652 #define IXGBE_CS4227_SKU_ID		0x0014	/* Dual port */
4653 #define IXGBE_CS4227_RESET_PENDING	0x1357
4654 #define IXGBE_CS4227_RESET_COMPLETE	0x5AA5
4655 #define IXGBE_CS4227_RETRIES		15
4656 #define IXGBE_CS4227_EFUSE_STATUS	0x0181
4657 #define IXGBE_CS4227_LINE_SPARE22_MSB	0x12AD	/* Reg to program speed */
4658 #define IXGBE_CS4227_LINE_SPARE24_LSB	0x12B0	/* Reg to program EDC */
4659 #define IXGBE_CS4227_HOST_SPARE22_MSB	0x1AAD	/* Reg to program speed */
4660 #define IXGBE_CS4227_HOST_SPARE24_LSB	0x1AB0	/* Reg to program EDC */
4661 #define IXGBE_CS4227_EEPROM_STATUS	0x5001
4662 #define IXGBE_CS4227_EEPROM_LOAD_OK	0x0001
4663 #define IXGBE_CS4227_SPEED_1G		0x8000
4664 #define IXGBE_CS4227_SPEED_10G		0
4665 #define IXGBE_CS4227_EDC_MODE_CX1	0x0002
4666 #define IXGBE_CS4227_EDC_MODE_SR	0x0004
4667 #define IXGBE_CS4227_EDC_MODE_DIAG	0x0008
4668 #define IXGBE_CS4227_RESET_HOLD		500	/* microseconds */
4669 #define IXGBE_CS4227_RESET_DELAY	450	/* milliseconds */
4670 #define IXGBE_CS4227_CHECK_DELAY	30	/* milliseconds */
4671 #define IXGBE_PE			0xE0	/* Port expander address */
4672 #define IXGBE_PE_OUTPUT			1	/* Output register offset */
4673 #define IXGBE_PE_CONFIG			3	/* Config register offset */
4674 #define IXGBE_PE_BIT1			(1 << 1)
4675 
4676 /* Flow control defines */
4677 #define IXGBE_TAF_SYM_PAUSE		0x400
4678 #define IXGBE_TAF_ASM_PAUSE		0x800
4679 
4680 /* Bit-shift macros */
4681 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT	24
4682 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT	16
4683 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT	8
4684 
4685 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
4686 #define IXGBE_SFF_VENDOR_OUI_TYCO	0x00407600
4687 #define IXGBE_SFF_VENDOR_OUI_FTL	0x00906500
4688 #define IXGBE_SFF_VENDOR_OUI_AVAGO	0x00176A00
4689 #define IXGBE_SFF_VENDOR_OUI_INTEL	0x001B2100
4690 
4691 /* I2C SDA and SCL timing parameters for standard mode */
4692 #define IXGBE_I2C_T_HD_STA	4
4693 #define IXGBE_I2C_T_LOW		5
4694 #define IXGBE_I2C_T_HIGH	4
4695 #define IXGBE_I2C_T_SU_STA	5
4696 #define IXGBE_I2C_T_HD_DATA	5
4697 #define IXGBE_I2C_T_SU_DATA	1
4698 #define IXGBE_I2C_T_RISE	1
4699 #define IXGBE_I2C_T_FALL	1
4700 #define IXGBE_I2C_T_SU_STO	4
4701 #define IXGBE_I2C_T_BUF		5
4702 
4703 #ifndef IXGBE_SFP_DETECT_RETRIES
4704 #define IXGBE_SFP_DETECT_RETRIES	10
4705 
4706 #endif /* IXGBE_SFP_DETECT_RETRIES */
4707 #define IXGBE_TN_LASI_STATUS_REG	0x9005
4708 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM	0x0008
4709 
4710 /* SFP+ SFF-8472 Compliance */
4711 #define IXGBE_SFF_SFF_8472_UNSUP	0x00
4712 
4713 /* end PHY */
4714 
4715 #endif /* _IXGBE_TYPE_H_ */
4716