1 /* hp2100_cpu.h: HP 2100 CPU definitions 2 3 Copyright (c) 2005-2010, Robert M. Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not 23 be used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 03-Jan-10 RMS Changed declarations of mp_control, mp_mefvv, for VMS compiler 27 15-Jul-08 JDB Rearranged declarations with hp2100_cpu.c and hp2100_defs.h 28 26-Jun-08 JDB Added mp_control to CPU state externals 29 24-Apr-08 JDB Added calc_defer() prototype 30 20-Apr-08 JDB Added DEB_VIS and DEB_SIG debug flags 31 26-Nov-07 JDB Added extern sim_deb, cpu_dev, DEB flags for debug printouts 32 05-Nov-07 JDB Added extern intaddr, mp_viol, mp_mevff, calc_int, dev_ctl, 33 ReadIO, WriteIO for RTE-6/VM microcode support 34 16-Dec-06 JDB Added UNIT_2115 and UNIT_2114 35 16-Oct-06 JDB Moved ReadF to hp2100_cpu1.c 36 26-Sep-06 JDB Added CPU externs for microcode simulators 37 16-Aug-06 JDB Added UNIT_EMA for future RTE-4 EMA microcode 38 Added UNIT_VMA for future RTE-6 VMA and OS microcode 39 Added UNIT_1000_F for future F-Series support 40 09-Aug-06 JDB Added UNIT_DBI for double integer microcode 41 21-Jan-05 JDB Reorganized CPU option flags 42 14-Jan-05 RMS Cloned from hp2100_cpu.c 43 44 CPU models are broken down into family, type, and series to facilitate option 45 validation. Bit 3 encodes the family, bit 2 encodes the type, and bits 1:0 46 encode the series within the type. 47 */ 48 49 #ifndef _HP2100_CPU_H_ 50 #define _HP2100_CPU_H_ 0 51 52 #include <setjmp.h> 53 54 55 /* CPU model definition flags */ 56 57 #define CPU_V_SERIES 0 58 #define CPU_V_TYPE 2 59 #define CPU_V_FAMILY 3 60 61 #define FAMILY_21XX (0 << CPU_V_FAMILY) 62 #define FAMILY_1000 (1 << CPU_V_FAMILY) 63 64 #define TYPE_211X (0 << CPU_V_TYPE) /* 2114, 2115, 2116 */ 65 #define TYPE_2100 (1 << CPU_V_TYPE) /* 2100A, 2100S */ 66 #define TYPE_1000MEF (0 << CPU_V_TYPE) /* 1000-M, 1000-E, 1000-F */ 67 #define TYPE_1000AL (1 << CPU_V_TYPE) /* 1000-L, A600, A700, A900, A990 */ 68 69 #define SERIES_16 (0 << CPU_V_SERIES) /* 211X */ 70 #define SERIES_15 (1 << CPU_V_SERIES) /* 211X */ 71 #define SERIES_14 (2 << CPU_V_SERIES) /* 211X */ 72 #define SERIES_00 (0 << CPU_V_SERIES) /* 2100 */ 73 #define SERIES_M (0 << CPU_V_SERIES) /* 1000 */ 74 #define SERIES_E (1 << CPU_V_SERIES) /* 1000 */ 75 #define SERIES_F (2 << CPU_V_SERIES) /* 1000 */ 76 77 /* CPU unit flags */ 78 79 #define UNIT_M_CPU 017 /* CPU model mask [3:0] */ 80 #define UNIT_M_TYPE 014 /* CPU type mask [3:2] */ 81 #define UNIT_M_FAMILY 010 /* CPU family mask [3:3] */ 82 83 #define UNIT_V_CPU (UNIT_V_UF + 0) /* CPU model bits 0-3 */ 84 #define UNIT_V_EAU (UNIT_V_UF + 4) /* EAU installed */ 85 #define UNIT_V_FP (UNIT_V_UF + 5) /* FP installed */ 86 #define UNIT_V_IOP (UNIT_V_UF + 6) /* IOP installed */ 87 #define UNIT_V_DMS (UNIT_V_UF + 7) /* DMS installed */ 88 #define UNIT_V_FFP (UNIT_V_UF + 8) /* FFP installed */ 89 #define UNIT_V_DBI (UNIT_V_UF + 9) /* DBI installed */ 90 #define UNIT_V_EMA (UNIT_V_UF + 10) /* RTE-4 EMA installed */ 91 #define UNIT_V_VMAOS (UNIT_V_UF + 11) /* RTE-6 VMA/OS installed */ 92 #define UNIT_V_VIS (UNIT_V_UF + 12) /* VIS installed */ 93 #define UNIT_V_SIGNAL (UNIT_V_UF + 13) /* SIGNAL/1000 installed */ 94 /* Future microcode expansion; reuse flags bottom-up if needed */ 95 #define UNIT_V_DS (UNIT_V_UF + 14) /* DS installed */ 96 97 /* Unit models */ 98 99 #define UNIT_MODEL_MASK (UNIT_M_CPU << UNIT_V_CPU) 100 101 #define UNIT_2116 ((FAMILY_21XX | TYPE_211X | SERIES_16) << UNIT_V_CPU) 102 #define UNIT_2115 ((FAMILY_21XX | TYPE_211X | SERIES_15) << UNIT_V_CPU) 103 #define UNIT_2114 ((FAMILY_21XX | TYPE_211X | SERIES_14) << UNIT_V_CPU) 104 #define UNIT_2100 ((FAMILY_21XX | TYPE_2100 | SERIES_00) << UNIT_V_CPU) 105 #define UNIT_1000_M ((FAMILY_1000 | TYPE_1000MEF | SERIES_M) << UNIT_V_CPU) 106 #define UNIT_1000_E ((FAMILY_1000 | TYPE_1000MEF | SERIES_E) << UNIT_V_CPU) 107 #define UNIT_1000_F ((FAMILY_1000 | TYPE_1000MEF | SERIES_F) << UNIT_V_CPU) 108 109 /* Unit types */ 110 111 #define UNIT_TYPE_MASK (UNIT_M_TYPE << UNIT_V_CPU) 112 113 #define UNIT_TYPE_211X ((FAMILY_21XX | TYPE_211X) << UNIT_V_CPU) 114 #define UNIT_TYPE_2100 ((FAMILY_21XX | TYPE_2100) << UNIT_V_CPU) 115 #define UNIT_TYPE_1000 ((FAMILY_1000 | TYPE_1000MEF) << UNIT_V_CPU) 116 117 /* Unit families */ 118 119 #define UNIT_FAMILY_MASK (UNIT_M_FAMILY << UNIT_V_CPU) 120 121 #define UNIT_FAMILY_21XX (FAMILY_21XX << UNIT_V_CPU) 122 #define UNIT_FAMILY_1000 (FAMILY_1000 << UNIT_V_CPU) 123 124 /* Unit accessors */ 125 126 #define UNIT_CPU_MODEL (cpu_unit.flags & UNIT_MODEL_MASK) 127 #define UNIT_CPU_TYPE (cpu_unit.flags & UNIT_TYPE_MASK) 128 #define UNIT_CPU_FAMILY (cpu_unit.flags & UNIT_FAMILY_MASK) 129 130 #define CPU_MODEL_INDEX (UNIT_CPU_MODEL >> UNIT_V_CPU) 131 132 /* Unit features */ 133 134 #define UNIT_EAU (1 << UNIT_V_EAU) 135 #define UNIT_FP (1 << UNIT_V_FP) 136 #define UNIT_IOP (1 << UNIT_V_IOP) 137 #define UNIT_DMS (1 << UNIT_V_DMS) 138 #define UNIT_FFP (1 << UNIT_V_FFP) 139 #define UNIT_DBI (1 << UNIT_V_DBI) 140 #define UNIT_EMA (1 << UNIT_V_EMA) 141 #define UNIT_VMAOS (1 << UNIT_V_VMAOS) 142 #define UNIT_VIS (1 << UNIT_V_VIS) 143 #define UNIT_DS (1 << UNIT_V_DS) 144 #define UNIT_SIGNAL (1 << UNIT_V_SIGNAL) 145 146 #define UNIT_EMA_VMA (UNIT_EMA | UNIT_VMAOS) 147 148 #define UNIT_OPTS (UNIT_EAU | UNIT_FP | UNIT_IOP | \ 149 UNIT_DMS | UNIT_FFP | UNIT_DBI | \ 150 UNIT_EMA | UNIT_VMAOS | \ 151 UNIT_VIS | UNIT_DS | UNIT_SIGNAL) 152 153 /* "Pseudo-option" flags used only for option testing; never set into UNIT structure. */ 154 155 #define UNIT_V_PFAIL (UNIT_V_UF - 1) /* Power fail installed */ 156 #define UNIT_V_DMA (UNIT_V_UF - 2) /* DMA installed */ 157 #define UNIT_V_MP (UNIT_V_UF - 3) /* Memory protect installed */ 158 159 #define UNIT_PFAIL (1 << UNIT_V_PFAIL) 160 #define UNIT_DMA (1 << UNIT_V_DMA) 161 #define UNIT_MP (1 << UNIT_V_MP) 162 163 #define UNIT_NONE 0 /* no options */ 164 165 /* Debug flags */ 166 167 #define DEB_OS (1 << 0) /* RTE-6/VM OS firmware non-TBG processing */ 168 #define DEB_OSTBG (1 << 1) /* RTE-6/VM OS firmware TBG processing */ 169 #define DEB_VMA (1 << 2) /* RTE-6/VM VMA firmware instructions */ 170 #define DEB_EMA (1 << 3) /* RTE-6/VM EMA firmware instructions */ 171 #define DEB_VIS (1 << 4) /* E/F-Series VIS firmware instructions */ 172 #define DEB_SIG (1 << 5) /* F-Series SIGNAL/1000 firmware instructions */ 173 174 /* PC queue. */ 175 176 #define PCQ_SIZE 64 /* must be 2**n */ 177 #define PCQ_MASK (PCQ_SIZE - 1) 178 #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = err_PC 179 180 /* Memory reference instructions */ 181 182 #define I_IA 0100000 /* indirect address */ 183 #define I_AB 0004000 /* A/B select */ 184 #define I_CP 0002000 /* current page */ 185 #define I_DISP 0001777 /* page displacement */ 186 #define I_PAGENO 0076000 /* page number */ 187 188 /* Other instructions */ 189 190 #define I_NMRMASK 0172000 /* non-mrf opcode */ 191 #define I_ASKP 0002000 /* alter/skip */ 192 #define I_IO 0102000 /* I/O */ 193 #define I_CTL 0004000 /* CTL on/off */ 194 #define I_HC 0001000 /* hold/clear */ 195 #define I_DEVMASK 0000077 /* device select code mask */ 196 #define I_GETIOOP(x) (((x) >> 6) & 07) /* I/O sub op */ 197 198 /* Instruction masks */ 199 200 #define I_MRG 0074000 /* MRG instructions */ 201 #define I_MRG_I (I_MRG | I_IA) /* MRG indirect instruction group */ 202 #define I_JSB 0014000 /* JSB instruction */ 203 #define I_JSB_I (I_JSB | I_IA) /* JSB,I instruction */ 204 #define I_JMP 0024000 /* JMP instruction */ 205 #define I_ISZ 0034000 /* ISZ instruction */ 206 207 #define I_IOG 0107700 /* I/O group instruction */ 208 #define I_SFS 0102300 /* SFS instruction */ 209 #define I_STF 0102100 /* STF instruction */ 210 211 /* Memory management */ 212 213 #define VA_N_OFF 10 /* offset width */ 214 #define VA_M_OFF ((1 << VA_N_OFF) - 1) /* offset mask */ 215 #define VA_GETOFF(x) ((x) & VA_M_OFF) 216 #define VA_N_PAG (VA_N_SIZE - VA_N_OFF) /* page width */ 217 #define VA_V_PAG (VA_N_OFF) /* page offset */ 218 #define VA_M_PAG ((1 << VA_N_PAG) - 1) /* page mask */ 219 #define VA_GETPAG(x) (((x) >> VA_V_PAG) & VA_M_PAG) 220 221 /* Maps */ 222 223 #define MAP_NUM 4 /* num maps */ 224 #define MAP_LNT (1 << VA_N_PAG) /* map length */ 225 #define MAP_MASK ((MAP_NUM * MAP_LNT) - 1) 226 #define SMAP 0 /* system map */ 227 #define UMAP (SMAP + MAP_LNT) /* user map */ 228 #define PAMAP (UMAP + MAP_LNT) /* port A map */ 229 #define PBMAP (PAMAP + MAP_LNT) /* port B map */ 230 231 /* DMS map entries */ 232 233 #define MAP_V_RPR 15 /* read prot */ 234 #define MAP_V_WPR 14 /* write prot */ 235 #define RDPROT (1 << MAP_V_RPR) /* read access check */ 236 #define WRPROT (1 << MAP_V_WPR) /* write access check */ 237 #define NOPROT 0 /* no access check */ 238 #define MAP_RSVD 0036000 /* reserved bits */ 239 #define MAP_N_PAG (PA_N_SIZE - VA_N_OFF) /* page width */ 240 #define MAP_V_PAG (VA_N_OFF) 241 #define MAP_M_PAG ((1 << MAP_N_PAG) - 1) 242 #define MAP_GETPAG(x) (((x) & MAP_M_PAG) << MAP_V_PAG) 243 244 /* MEM status register */ 245 246 #define MST_ENBI 0100000 /* MEM enabled at interrupt */ 247 #define MST_UMPI 0040000 /* User map selected at inerrupt */ 248 #define MST_ENB 0020000 /* MEM enabled currently */ 249 #define MST_UMP 0010000 /* User map selected currently */ 250 #define MST_PRO 0004000 /* Protected mode enabled currently */ 251 #define MST_FLT 0002000 /* Base page portion mapped */ 252 #define MST_FENCE 0001777 /* Base page fence */ 253 254 /* MEM violation register */ 255 256 #define MVI_V_RPR 15 /* must be same as */ 257 #define MVI_V_WPR 14 /* MAP_V_xPR */ 258 #define MVI_RPR (1 << MVI_V_RPR) /* rd viol */ 259 #define MVI_WPR (1 << MVI_V_WPR) /* wr viol */ 260 #define MVI_BPG 0020000 /* base page viol */ 261 #define MVI_PRV 0010000 /* priv viol */ 262 #define MVI_MEB 0000200 /* me bus enb @ viol */ 263 #define MVI_MEM 0000100 /* mem enb @ viol */ 264 #define MVI_UMP 0000040 /* usr map @ viol */ 265 #define MVI_PAG 0000037 /* pag sel */ 266 267 /* CPU registers */ 268 269 #define AR ABREG[0] /* A = reg 0 */ 270 #define BR ABREG[1] /* B = reg 1 */ 271 272 extern uint16 ABREG[2]; /* A/B regs (use AR/BR) */ 273 extern uint32 PC; /* P register */ 274 extern uint32 SR; /* S register */ 275 extern uint32 MR; /* M register */ 276 extern uint32 TR; /* T register */ 277 extern uint32 XR; /* X register */ 278 extern uint32 YR; /* Y register */ 279 extern uint32 E; /* E register */ 280 extern uint32 O; /* O register */ 281 282 /* CPU state */ 283 284 extern uint32 err_PC; 285 extern uint32 dms_enb; 286 extern uint32 dms_ump; 287 extern uint32 dms_sr; 288 extern uint32 dms_vr; 289 extern FLIP_FLOP mp_control; 290 extern uint32 mp_fence; 291 extern uint32 mp_viol; 292 extern FLIP_FLOP mp_mevff; 293 extern uint32 iop_sp; 294 extern t_bool ion_defer; 295 extern uint32 intaddr; 296 extern uint16 pcq [PCQ_SIZE]; 297 extern uint32 pcq_p; 298 extern uint32 stop_inst; 299 extern UNIT cpu_unit; 300 extern DEVICE cpu_dev; 301 extern jmp_buf save_env; 302 303 304 /* CPU functions */ 305 306 #define MP_ABORT(va) longjmp (save_env, (va)) 307 308 extern t_stat resolve (uint32 MA, uint32 *addr, uint32 irq); 309 extern uint16 ReadPW (uint32 pa); 310 extern uint8 ReadB (uint32 va); 311 extern uint8 ReadBA (uint32 va); 312 extern uint16 ReadW (uint32 va); 313 extern uint16 ReadWA (uint32 va); 314 extern uint16 ReadIO (uint32 va, uint32 map); 315 extern void WritePW (uint32 pa, uint32 dat); 316 extern void WriteB (uint32 va, uint32 dat); 317 extern void WriteBA (uint32 va, uint32 dat); 318 extern void WriteW (uint32 va, uint32 dat); 319 extern void WriteWA (uint32 va, uint32 dat); 320 extern void WriteIO (uint32 va, uint32 dat, uint32 map); 321 extern t_stat iogrp (uint32 ir, uint32 iotrap); 322 extern uint32 calc_int (void); 323 extern t_bool calc_defer (void); 324 extern void mp_dms_jmp (uint32 va, uint32 plb); 325 extern uint16 dms_rmap (uint32 mapi); 326 extern void dms_wmap (uint32 mapi, uint32 dat); 327 extern void dms_viol (uint32 va, uint32 st); 328 extern uint32 dms_upd_vr (uint32 va); 329 extern uint32 dms_upd_sr (void); 330 331 #endif 332