| /dports/lang/spidermonkey78/firefox-78.9.0/third_party/rust/regalloc/src/linear_scan/ |
| H A D | assign_registers.rs | 409 active: &Vec<IntId>, in match_previous_update_state()
410 inactive: &Vec<IntId>, in match_previous_update_state()
411 expired: &Vec<IntId>, in match_previous_update_state()
412 prev_active: Vec<IntId>, in match_previous_update_state()
531 active: &[IntId], in lazy_compute_inactive()
534 cur_id: IntId, in lazy_compute_inactive()
631 cur_id: IntId, in update_state()
773 id: IntId, in select_naive_reg()
833 id: IntId, in try_allocate_reg()
869 cur_id: IntId, in allocate_blocked_reg()
[all …]
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| H A D | mod.rs | 47 pub(crate) struct IntId(usize); struct
49 impl fmt::Debug for IntId { implementation
332 left_id: IntId, in intersects_with()
333 right_id: IntId, in intersects_with()
446 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
462 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
479 id: IntId, in next_use()
557 id: IntId, in ref_next_use()
628 id: IntId, in last_use()
710 id: IntId, in ref_last_use()
[all …]
|
| H A D | resolve_moves.rs | 20 virtual_intervals: &Vec<IntId>, in run()
399 virtual_intervals: &Vec<IntId>, in find_enclosing_interval()
400 ) -> Option<IntId> { in find_enclosing_interval()
|
| /dports/sysutils/vector/vector-0.10.0/cargo-crates/regalloc-0.0.25/src/linear_scan/ |
| H A D | assign_registers.rs | 71 fn set_active(&mut self, id: IntId) { in set_active()
480 fn next_unhandled(&mut self) -> Option<IntId> { in next_unhandled()
483 fn insert_unhandled(&mut self, id: IntId) { in insert_unhandled()
487 fn spill(&mut self, id: IntId) { in spill()
511 cur_id: IntId, in lazy_compute_inactive()
586 id: IntId, in select_naive_reg()
653 id: IntId, in try_allocate_reg()
698 cur_id: IntId, in allocate_blocked_reg()
900 id: IntId, in find_optimal_split_pos()
1028 id: IntId, in try_split_regs()
[all …]
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| H A D | mod.rs | 131 struct IntId(pub(crate) usize); struct
133 impl fmt::Debug for IntId { implementation
193 id: IntId, in new()
346 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
351 fn set_spill(&mut self, int_id: IntId, slot: SpillSlot) { in set_spill()
360 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
|
| /dports/www/firefox/firefox-99.0/third_party/rust/regalloc/src/linear_scan/ |
| H A D | assign_registers.rs | 71 fn set_active(&mut self, id: IntId) { in set_active()
487 fn next_unhandled(&mut self) -> Option<IntId> { in next_unhandled()
490 fn insert_unhandled(&mut self, id: IntId) { in insert_unhandled()
494 fn spill(&mut self, id: IntId) { in spill()
518 cur_id: IntId, in lazy_compute_inactive()
593 id: IntId, in select_naive_reg()
660 id: IntId, in try_allocate_reg()
705 cur_id: IntId, in allocate_blocked_reg()
907 id: IntId, in find_optimal_split_pos()
1035 id: IntId, in try_split_regs()
[all …]
|
| H A D | mod.rs | 132 struct IntId(pub(crate) usize); struct
134 impl fmt::Debug for IntId { implementation
194 id: IntId, in new()
348 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
353 fn set_spill(&mut self, int_id: IntId, slot: SpillSlot) { in set_spill()
362 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
|
| /dports/mail/thunderbird/thunderbird-91.8.0/third_party/rust/regalloc/src/linear_scan/ |
| H A D | assign_registers.rs | 71 fn set_active(&mut self, id: IntId) { in set_active()
487 fn next_unhandled(&mut self) -> Option<IntId> { in next_unhandled()
490 fn insert_unhandled(&mut self, id: IntId) { in insert_unhandled()
494 fn spill(&mut self, id: IntId) { in spill()
518 cur_id: IntId, in lazy_compute_inactive()
593 id: IntId, in select_naive_reg()
660 id: IntId, in try_allocate_reg()
705 cur_id: IntId, in allocate_blocked_reg()
907 id: IntId, in find_optimal_split_pos()
1035 id: IntId, in try_split_regs()
[all …]
|
| H A D | mod.rs | 132 struct IntId(pub(crate) usize); struct
134 impl fmt::Debug for IntId { implementation
194 id: IntId, in new()
348 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
353 fn set_spill(&mut self, int_id: IntId, slot: SpillSlot) { in set_spill()
362 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
|
| /dports/lang/rust/rustc-1.58.1-src/vendor/regalloc/src/linear_scan/ |
| H A D | assign_registers.rs | 71 fn set_active(&mut self, id: IntId) { in set_active()
487 fn next_unhandled(&mut self) -> Option<IntId> { in next_unhandled()
490 fn insert_unhandled(&mut self, id: IntId) { in insert_unhandled()
494 fn spill(&mut self, id: IntId) { in spill()
518 cur_id: IntId, in lazy_compute_inactive()
593 id: IntId, in select_naive_reg()
660 id: IntId, in try_allocate_reg()
705 cur_id: IntId, in allocate_blocked_reg()
907 id: IntId, in find_optimal_split_pos()
1035 id: IntId, in try_split_regs()
[all …]
|
| H A D | mod.rs | 132 struct IntId(pub(crate) usize); struct
134 impl fmt::Debug for IntId { implementation
194 id: IntId, in new()
348 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
353 fn set_spill(&mut self, int_id: IntId, slot: SpillSlot) { in set_spill()
362 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
|
| /dports/www/firefox-esr/firefox-91.8.0/third_party/rust/regalloc/src/linear_scan/ |
| H A D | assign_registers.rs | 71 fn set_active(&mut self, id: IntId) { in set_active()
487 fn next_unhandled(&mut self) -> Option<IntId> { in next_unhandled()
490 fn insert_unhandled(&mut self, id: IntId) { in insert_unhandled()
494 fn spill(&mut self, id: IntId) { in spill()
518 cur_id: IntId, in lazy_compute_inactive()
593 id: IntId, in select_naive_reg()
660 id: IntId, in try_allocate_reg()
705 cur_id: IntId, in allocate_blocked_reg()
907 id: IntId, in find_optimal_split_pos()
1035 id: IntId, in try_split_regs()
[all …]
|
| H A D | mod.rs | 132 struct IntId(pub(crate) usize); struct
134 impl fmt::Debug for IntId { implementation
194 id: IntId, in new()
348 fn set_reg(&mut self, int_id: IntId, reg: RealReg) { in set_reg()
353 fn set_spill(&mut self, int_id: IntId, slot: SpillSlot) { in set_spill()
362 fn set_child(&mut self, int_id: IntId, child_id: IntId) { in set_child()
|
| /dports/www/grafana8/xorm/ |
| H A D | session_pk_test.go | 17 type IntId struct { struct
18 Id int `xorm:"pk autoincr"`
19 Name string
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY() local
|