1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Wei Lin<wei.w.lin@intel.com>
26 * Yuting Yang<yuting.yang@intel.com>
27 */
28
29 #include "os_interface.h"
30 #include "os_util_debug.h"
31 #include <unistd.h>
32 #include "hw_info.h"
33 #include "fourcc.h"
34 #include <stdlib.h>
35 #include <fcntl.h>
36 #include <errno.h>
37 #include <time.h>
38 #include <string.h>
39
40 #define ALIGN(x, align) (((x) + (align) - 1) & (~((align) -1)))
41
42 #define Y_TILE_WIDTH 128
43 #define Y_TILE_HEIGHT 32
44 #define X_TILE_WIDTH 512
45 #define X_TILE_HEIGHT 8
46
47 #define MI_BATCHBUFFER_END 0x05000000
48
49 static int OpenDevice();
50 static int updatePlatformInfo(PLATFORM * pPlatform);
51 static void getRevId(unsigned short *value);
52
IntelGen_OsAddCommand(PGENOS_COMMAND_BUFFER pCmdBuffer,PCVOID pCmd,DWORD dwCmdSize)53 GENOS_STATUS IntelGen_OsAddCommand(PGENOS_COMMAND_BUFFER pCmdBuffer,
54 PCVOID pCmd, DWORD dwCmdSize)
55 {
56 DWORD dwCmdSizeDwAligned;
57
58 GENOS_OS_ASSERT(pCmdBuffer);
59 GENOS_OS_ASSERT(pCmd);
60
61 dwCmdSizeDwAligned = GENOS_ALIGN_CEIL(dwCmdSize, sizeof(DWORD));
62
63 pCmdBuffer->iOffset += dwCmdSizeDwAligned;
64 pCmdBuffer->iRemaining -= dwCmdSizeDwAligned;
65
66 if (pCmdBuffer->iRemaining < 0) {
67 GENOS_OS_ASSERTMESSAGE("Unable to add command (no space).");
68 return GENOS_STATUS_UNKNOWN;
69 }
70
71 GENOS_SecureMemcpy(pCmdBuffer->pCmdPtr, dwCmdSize, pCmd, dwCmdSize);
72 pCmdBuffer->pCmdPtr += (dwCmdSizeDwAligned / sizeof(DWORD));
73
74 return GENOS_STATUS_SUCCESS;
75 }
76
IntelGen_OsGetCmdBufferSpace(PGENOS_COMMAND_BUFFER pCmdBuffer,DWORD dwCmdSize)77 PVOID IntelGen_OsGetCmdBufferSpace(PGENOS_COMMAND_BUFFER pCmdBuffer,
78 DWORD dwCmdSize)
79 {
80 GENOS_OS_ASSERT(pCmdBuffer);
81
82 if ((pCmdBuffer->iRemaining - (int)dwCmdSize) < 0) {
83 GENOS_OS_ASSERTMESSAGE("Unable to add command (no space).");
84 return NULL;
85 }
86
87 return pCmdBuffer->pCmdPtr;
88 }
89
IntelGen_OsAdjustCmdBufferFreeSpace(PGENOS_COMMAND_BUFFER pCmdBuffer,DWORD dwCmdSize)90 VOID IntelGen_OsAdjustCmdBufferFreeSpace(PGENOS_COMMAND_BUFFER pCmdBuffer,
91 DWORD dwCmdSize)
92 {
93 GENOS_OS_ASSERT(pCmdBuffer);
94 GENOS_OS_ASSERT((dwCmdSize % sizeof(DWORD)) == 0);
95
96 pCmdBuffer->iOffset += dwCmdSize;
97 pCmdBuffer->iRemaining -= dwCmdSize;
98 pCmdBuffer->pCmdPtr += (dwCmdSize / sizeof(DWORD));
99 }
100
IntelGen_OsClear_OsGpuContext(GENOS_CONTEXT * pContext)101 VOID IntelGen_OsClear_OsGpuContext(GENOS_CONTEXT * pContext)
102 {
103 INT iLoop;
104
105 GENOS_OS_FUNCTION_ENTER;
106
107 for (iLoop = 0; iLoop < GENOS_GPU_CONTEXT_MAX; iLoop++) {
108 if (pContext->OsGpuContext[iLoop].pCB != NULL) {
109 GENOS_FreeMemory(pContext->OsGpuContext[iLoop].pCB);
110 pContext->OsGpuContext[iLoop].pCB = NULL;
111 }
112
113 if (pContext->OsGpuContext[iLoop].pAllocationList != NULL) {
114 GENOS_FreeMemory(pContext->
115 OsGpuContext[iLoop].pAllocationList);
116 pContext->OsGpuContext[iLoop].pAllocationList = NULL;
117 }
118
119 if (pContext->OsGpuContext[iLoop].pPatchLocationList) {
120 GENOS_FreeMemory(pContext->OsGpuContext
121 [iLoop].pPatchLocationList);
122 pContext->OsGpuContext[iLoop].pPatchLocationList = NULL;
123 }
124
125 if (pContext->OsGpuContext[iLoop].pResources != NULL) {
126 GENOS_FreeMemory(pContext->
127 OsGpuContext[iLoop].pResources);
128 pContext->OsGpuContext[iLoop].pResources = NULL;
129 }
130
131 if (pContext->OsGpuContext[iLoop].pbWriteMode != NULL) {
132 GENOS_FreeMemory(pContext->
133 OsGpuContext[iLoop].pbWriteMode);
134 pContext->OsGpuContext[iLoop].pbWriteMode = NULL;
135 }
136
137 pContext->OsGpuContext[iLoop].uiMaxNumAllocations = 0;
138 pContext->OsGpuContext[iLoop].uiMaxPatchLocationsize = 0;
139 }
140 }
141
Ctx_GetCommandBuffer(PGENOS_CONTEXT pOsContext,PGENOS_COMMAND_BUFFER pCmdBuffer,INT iSize)142 BOOL Ctx_GetCommandBuffer(PGENOS_CONTEXT pOsContext,
143 PGENOS_COMMAND_BUFFER pCmdBuffer, INT iSize)
144 {
145 BOOL bResult = FALSE;
146 drm_intel_bo *cmd_bo = NULL;
147
148 if (pOsContext == NULL || pCmdBuffer == NULL) {
149 bResult = FALSE;
150 GENOS_OS_ASSERTMESSAGE
151 ("Ctx_GetCommandBuffer:pOsContext == NULL || pCmdBuffer == NULL");
152 goto finish;
153 }
154 cmd_bo =
155 drm_intel_bo_alloc(pOsContext->bufmgr, "Intel GenOS CmdBuf", iSize,
156 4096);
157 if (cmd_bo == NULL) {
158 GENOS_OS_ASSERTMESSAGE("Allocation of command buffer failed.");
159 bResult = FALSE;
160 goto finish;
161 }
162
163 if (drm_intel_bo_map(cmd_bo, 1) != 0) {
164 GENOS_OS_ASSERTMESSAGE("Mapping of command buffer failed.");
165 bResult = FALSE;
166 goto finish;
167 }
168
169 IntelGen_OsResetResource(&pCmdBuffer->OsResource);
170
171 pCmdBuffer->OsResource.Format = Format_Buffer;
172 pCmdBuffer->OsResource.iWidth = cmd_bo->size;
173 pCmdBuffer->OsResource.iHeight = 1;
174 pCmdBuffer->OsResource.iPitch = cmd_bo->size;
175 pCmdBuffer->OsResource.iCount = 1;
176 pCmdBuffer->OsResource.pData = (PBYTE) cmd_bo->virtual;
177 pCmdBuffer->OsResource.TileType = GENOS_TILE_LINEAR;
178 pCmdBuffer->OsResource.bo = cmd_bo;
179 pCmdBuffer->OsResource.bMapped = TRUE;
180
181 pCmdBuffer->pCmdBase = (PDWORD) cmd_bo->virtual;
182 pCmdBuffer->pCmdPtr = (PDWORD) cmd_bo->virtual;
183 pCmdBuffer->iOffset = 0;
184 pCmdBuffer->iRemaining = cmd_bo->size;
185
186 GENOS_ZeroMemory(pCmdBuffer->pCmdBase, cmd_bo->size);
187 bResult = TRUE;
188
189 finish:
190 if ((FALSE == bResult) && (NULL != cmd_bo)) {
191 drm_intel_bo_unreference(cmd_bo);
192 }
193 return bResult;
194 }
195
Ctx_ReturnCommandBuffer(PGENOS_CONTEXT pOsContext,GENOS_GPU_CONTEXT GpuContext,PGENOS_COMMAND_BUFFER pCmdBuffer)196 VOID Ctx_ReturnCommandBuffer(PGENOS_CONTEXT pOsContext,
197 GENOS_GPU_CONTEXT GpuContext,
198 PGENOS_COMMAND_BUFFER pCmdBuffer)
199 {
200 GENOS_OS_GPU_CONTEXT *pOsGpuContext;
201
202 if (pOsContext == NULL || pCmdBuffer == NULL ||
203 IntelGen_OsResourceIsNull(&(pCmdBuffer->OsResource))) {
204 goto finish;
205 }
206 pOsGpuContext = &pOsContext->OsGpuContext[GpuContext];
207
208 pOsGpuContext->pCB->iOffset = pCmdBuffer->iOffset;
209 pOsGpuContext->pCB->iRemaining = pCmdBuffer->iRemaining;
210 pOsGpuContext->pCB->pCmdPtr = pCmdBuffer->pCmdPtr;
211
212 finish:
213 return;
214 }
215
Ctx_FlushCommandBuffer(PGENOS_CONTEXT pOsContext,GENOS_GPU_CONTEXT GpuContext)216 BOOL Ctx_FlushCommandBuffer(PGENOS_CONTEXT pOsContext,
217 GENOS_GPU_CONTEXT GpuContext)
218 {
219 PCOMMAND_BUFFER pCurrCB;
220 BOOL bResult = FALSE;
221 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
222
223 if (pOsContext == NULL) {
224 goto finish;
225 }
226
227 pOsGpuContext = &pOsContext->OsGpuContext[GpuContext];
228 pOsContext->pfnRefresh(pOsContext);
229
230 pOsGpuContext->uiCurrentNumPatchLocations = 0;
231
232 pCurrCB = pOsGpuContext->pCurrentCB;
233 if (pCurrCB->bActive) {
234 goto finish;
235 }
236
237 pCurrCB->bActive = TRUE;
238 bResult = TRUE;
239
240 finish:
241 return bResult;
242 }
243
Ctx_InitCmdBufferPool(PGENOS_CONTEXT pOsContext)244 VOID Ctx_InitCmdBufferPool(PGENOS_CONTEXT pOsContext)
245 {
246 GENOS_OS_FUNCTION_ENTER;
247
248 GENOS_ZeroMemory(&pOsContext->CmdBufferPool,
249 sizeof(CMD_BUFFER_BO_POOL));
250 pOsContext->CmdBufferPool.iFetch = 0;
251 }
252
Ctx_WaitAndReleaseCmdBuffer(PGENOS_CONTEXT pOsContext,INT index)253 HRESULT Ctx_WaitAndReleaseCmdBuffer(PGENOS_CONTEXT pOsContext, INT index)
254 {
255 drm_intel_bo *cmd_bo;
256 HRESULT hr;
257
258 GENOS_OS_FUNCTION_ENTER;
259
260 hr = S_OK;
261
262 if (index < 0 || index >= MAX_CMD_BUF_NUM) {
263 hr = E_FAIL;
264 goto finish;
265 }
266
267 cmd_bo = pOsContext->CmdBufferPool.pCmd_bo[index];
268 if (cmd_bo != NULL) {
269 drm_intel_bo_wait_rendering(cmd_bo);
270 drm_intel_bo_unreference(cmd_bo);
271 pOsContext->CmdBufferPool.pCmd_bo[index] = NULL;
272 }
273
274 finish:
275 return hr;
276 }
277
Ctx_ReleaseCmdBufferPool(PGENOS_CONTEXT pOsContext)278 HRESULT Ctx_ReleaseCmdBufferPool(PGENOS_CONTEXT pOsContext)
279 {
280 INT i;
281 HRESULT hr;
282
283 GENOS_OS_FUNCTION_ENTER;
284
285 hr = S_OK;
286
287 for (i = 0; i < MAX_CMD_BUF_NUM; i++) {
288 GENOS_OS_CHK_HR(Ctx_WaitAndReleaseCmdBuffer(pOsContext, i));
289 }
290
291 finish:
292 return hr;
293 }
294
Ctx_WaitForAvailableCmdBo(PGENOS_CONTEXT pOsContext)295 HRESULT Ctx_WaitForAvailableCmdBo(PGENOS_CONTEXT pOsContext)
296 {
297 INT index;
298 HRESULT hr;
299
300 GENOS_OS_FUNCTION_ENTER;
301
302 hr = S_OK;
303
304 index = pOsContext->CmdBufferPool.iFetch;
305 GENOS_OS_CHK_HR(Ctx_WaitAndReleaseCmdBuffer(pOsContext, index));
306
307 finish:
308 return hr;
309 }
310
Ctx_InsertCmdBufferToPool(PGENOS_CONTEXT pOsContext,drm_intel_bo * bo)311 HRESULT Ctx_InsertCmdBufferToPool(PGENOS_CONTEXT pOsContext, drm_intel_bo * bo)
312 {
313 INT index;
314 HRESULT hr;
315
316 GENOS_OS_FUNCTION_ENTER;
317
318 hr = S_OK;
319
320 GENOS_OS_CHK_HR(Ctx_WaitForAvailableCmdBo(pOsContext));
321
322 index = pOsContext->CmdBufferPool.iFetch;
323
324 pOsContext->CmdBufferPool.pCmd_bo[index] = bo;
325
326 pOsContext->CmdBufferPool.iFetch++;
327 if (pOsContext->CmdBufferPool.iFetch >= MAX_CMD_BUF_NUM) {
328 pOsContext->CmdBufferPool.iFetch = 0;
329 }
330
331 finish:
332 return hr;
333 }
334
Ctx_Refresh(GENOS_CONTEXT * pOsContext)335 BOOL Ctx_Refresh(GENOS_CONTEXT * pOsContext)
336 {
337 return TRUE;
338 }
339
Ctx_Destroy(PGENOS_CONTEXT pOsContext)340 VOID Ctx_Destroy(PGENOS_CONTEXT pOsContext)
341 {
342 PCOMMAND_BUFFER pCurrCB, pNextCB;
343 int i = 0;
344
345 Ctx_ReleaseCmdBufferPool(pOsContext);
346
347 for (i = 0; i < GENOS_GPU_CONTEXT_MAX; i++) {
348 GENOS_FreeMemAndSetNull(pOsContext->OsGpuContext[i].pCB);
349
350 pCurrCB = pOsContext->OsGpuContext[i].pStartCB;
351 for (; (pCurrCB); pCurrCB = pNextCB) {
352 pNextCB = pCurrCB->pNext;
353 GENOS_FreeMemAndSetNull(pCurrCB);
354 }
355 }
356
357 GENOS_FreeMemAndSetNull(pOsContext);
358 }
359
Ctx_InitContext(GENOS_OS_CONTEXT * pContext,PGENOS_CONTEXT pOsDriverContext)360 HRESULT Ctx_InitContext(GENOS_OS_CONTEXT * pContext,
361 PGENOS_CONTEXT pOsDriverContext)
362 {
363 INT iDeviceId;
364 drm_i915_getparam_t gp;
365 HRESULT hr;
366 INT i;
367
368 GENOS_OS_FUNCTION_ENTER;
369
370 hr = S_OK;
371
372 if (pContext == NULL || pOsDriverContext == NULL) {
373 GENOS_OS_ASSERT(FALSE);
374 return E_FAIL;
375 }
376
377 if ((pOsDriverContext->bufmgr != NULL) &&
378 (pOsDriverContext->wDeviceID != 0)) {
379 pContext->bufmgr = pOsDriverContext->bufmgr;
380
381 iDeviceId = pOsDriverContext->wDeviceID;
382 pContext->wDeviceID = iDeviceId;
383 pContext->platform.pchDeviceID = iDeviceId;
384
385 pContext->wRevision = pOsDriverContext->wRevision;
386
387 if (pOsDriverContext->wRevision == -1) {
388 getRevId(&pContext->platform.usRevId);
389 } else {
390 pContext->platform.usRevId = pOsDriverContext->wRevision;
391 }
392 } else {
393 pContext->fd = OpenDevice();
394 if (pContext->fd < 0) {
395 GENOS_OS_ASSERT(FALSE);
396 return E_FAIL;
397 }
398
399 pContext->bufmgr = drm_intel_bufmgr_gem_init(pContext->fd,
400 CMD_BUFFER_SIZE_IN_BYTES);
401 if (pContext->bufmgr == NULL) {
402 GENOS_OS_ASSERT(FALSE);
403 return E_FAIL;
404 }
405
406 memset(&gp, 0, sizeof(gp));
407 gp.param = I915_PARAM_CHIPSET_ID;
408 gp.value = &iDeviceId;
409 hr = drmIoctl(pContext->fd, DRM_IOCTL_I915_GETPARAM, &gp);
410 if ((hr != 0) || (iDeviceId == 0)) {
411 GENOS_OS_ASSERT(FALSE);
412 return E_FAIL;
413
414 }
415 pContext->wDeviceID = iDeviceId;
416 pContext->platform.pchDeviceID = iDeviceId;
417
418 getRevId(&pContext->platform.usRevId);
419 }
420
421 if (FALSE == IS_GEN7_5_PLUS(iDeviceId)) {
422 GENOS_OS_ASSERTMESSAGE
423 ("Platform *NOT* Supported by Current Linux Driver: Only supports: SandyBridge, IvyBridge, HasWell A0/A1/B0 Stepping");
424 return E_FAIL;
425 }
426
427 updatePlatformInfo(&pContext->platform);
428
429 Ctx_InitCmdBufferPool(pContext);
430
431 for (i = 0; i < GENOS_GPU_CONTEXT_MAX; i++) {
432 pContext->OsGpuContext[i].pStartCB = NULL;
433 pContext->OsGpuContext[i].pCurrentCB = NULL;
434 pContext->OsGpuContext[i].bCBFlushed = TRUE;
435 pContext->OsGpuContext[i].uiCommandBufferSize =
436 COMMAND_BUFFER_SIZE;
437 pContext->OsGpuContext[i].pCB = (PGENOS_COMMAND_BUFFER)
438 GENOS_AllocAndZeroMemory(sizeof(GENOS_COMMAND_BUFFER));
439
440 if (NULL == pContext->OsGpuContext[i].pCB) {
441 GENOS_OS_ASSERTMESSAGE("No More Avaliable Memory");
442 hr = E_OUTOFMEMORY;
443 goto finish;
444 }
445 pContext->OsGpuContext[i].pAllocationList = (ALLOCATION_LIST *)
446 GENOS_AllocAndZeroMemory(sizeof(ALLOCATION_LIST) *
447 ALLOCATIONLIST_SIZE);
448 if (NULL == pContext->OsGpuContext[i].pAllocationList) {
449 GENOS_OS_ASSERTMESSAGE
450 ("pContext->OsGpuContext[%d].pAllocationList malloc failed.",
451 i);
452 hr = E_OUTOFMEMORY;
453 goto finish;
454 }
455 pContext->OsGpuContext[i].uiMaxNumAllocations =
456 ALLOCATIONLIST_SIZE;
457
458 pContext->OsGpuContext[i].pPatchLocationList =
459 (PATCHLOCATIONLIST *)
460 GENOS_AllocAndZeroMemory(sizeof(PATCHLOCATIONLIST) *
461 PATCHLOCATIONLIST_SIZE);
462 if (NULL == pContext->OsGpuContext[i].pPatchLocationList) {
463 GENOS_OS_ASSERTMESSAGE
464 ("pContext->OsGpuContext[%d].pPatchLocationList malloc failed.",
465 i);
466 hr = E_OUTOFMEMORY;
467 goto finish;
468 }
469 pContext->OsGpuContext[i].uiMaxPatchLocationsize =
470 PATCHLOCATIONLIST_SIZE;
471
472 pContext->OsGpuContext[i].pResources = (PGENOS_RESOURCE)
473 GENOS_AllocAndZeroMemory(sizeof(GENOS_RESOURCE)
474 * ALLOCATIONLIST_SIZE);
475 if (NULL == pContext->OsGpuContext[i].pResources) {
476 GENOS_OS_ASSERTMESSAGE
477 ("pContext->OsGpuContext[%d].pResources malloc failed.",
478 i);
479 hr = E_OUTOFMEMORY;
480 goto finish;
481 }
482
483 pContext->OsGpuContext[i].pbWriteMode =
484 (BOOL *) GENOS_AllocAndZeroMemory(sizeof(BOOL) *
485 ALLOCATIONLIST_SIZE);
486 if (NULL == pContext->OsGpuContext[i].pbWriteMode) {
487 GENOS_OS_ASSERTMESSAGE
488 ("pContext->OsGpuContext[%d].pbWriteMode malloc failed.",
489 i);
490 hr = E_OUTOFMEMORY;
491 goto finish;
492 }
493 }
494
495 pContext->pfnDestroy = Ctx_Destroy;
496 pContext->pfnGetCommandBuffer = Ctx_GetCommandBuffer;
497 pContext->pfnReturnCommandBuffer = Ctx_ReturnCommandBuffer;
498 pContext->pfnFlushCommandBuffer = Ctx_FlushCommandBuffer;
499 pContext->pfnInsertCmdBufferToPool = Ctx_InsertCmdBufferToPool;
500 pContext->pfnRefresh = Ctx_Refresh;
501
502 finish:
503 if (hr != S_OK)
504 IntelGen_OsClear_OsGpuContext(pContext);
505
506 return hr;
507 }
508
IntelGen_OsGetPlatform(PGENOS_INTERFACE pOsInterface,PLATFORM * pPlatform)509 VOID IntelGen_OsGetPlatform(PGENOS_INTERFACE pOsInterface, PLATFORM * pPlatform)
510 {
511 if (pOsInterface && pPlatform && pOsInterface->pOsContext) {
512 *pPlatform = pOsInterface->pOsContext->platform;
513 }
514 }
515
IntelGen_OsDestroy(PGENOS_INTERFACE pOsInterface,BOOL bDestroyVscVppDeviceTag)516 VOID IntelGen_OsDestroy(PGENOS_INTERFACE pOsInterface,
517 BOOL bDestroyVscVppDeviceTag)
518 {
519 if (pOsInterface &&
520 pOsInterface->pOsContext &&
521 pOsInterface->pOsContext->bFreeContext) {
522 IntelGen_OsClear_OsGpuContext(pOsInterface->pOsContext);
523 pOsInterface->pOsContext->pfnDestroy(pOsInterface->pOsContext);
524 pOsInterface->pOsContext = NULL;
525 }
526 }
527
IntelGen_OsResetOsStates(PGENOS_INTERFACE pOsInterface)528 VOID IntelGen_OsResetOsStates(PGENOS_INTERFACE pOsInterface)
529 {
530 PGENOS_OS_CONTEXT pOsContext;
531 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
532
533 if (pOsInterface == NULL || pOsInterface->pOsContext == NULL) {
534 return;
535 }
536
537 pOsContext = pOsInterface->pOsContext;
538 pOsGpuContext =
539 &pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
540 pOsGpuContext->uiNumAllocations = 0;
541 GENOS_ZeroMemory(pOsGpuContext->pAllocationList,
542 sizeof(ALLOCATION_LIST) *
543 pOsGpuContext->uiMaxNumAllocations);
544 pOsGpuContext->uiCurrentNumPatchLocations = 0;
545 GENOS_ZeroMemory(pOsGpuContext->pPatchLocationList,
546 sizeof(PATCHLOCATIONLIST) *
547 pOsGpuContext->uiMaxPatchLocationsize);
548 pOsGpuContext->uiResCount = 0;
549
550 if ((pOsGpuContext->bCBFlushed == TRUE)
551 && pOsGpuContext->pCB->OsResource.bo) {
552 pOsGpuContext->pCB->OsResource.bo = NULL;
553 }
554 }
555
IntelGen_OsAllocateResource(PGENOS_INTERFACE pOsInterface,PGENOS_ALLOC_GFXRES_PARAMS pParams,PGENOS_RESOURCE pOsResource)556 HRESULT IntelGen_OsAllocateResource(PGENOS_INTERFACE pOsInterface,
557 PGENOS_ALLOC_GFXRES_PARAMS pParams,
558 PGENOS_RESOURCE pOsResource)
559 {
560 CONST CHAR *bufname;
561 INT iSize;
562 INT iHeight;
563 INT iWidth;
564 INT iPitch;
565 unsigned long ulPitch;
566 HRESULT hr;
567 drm_intel_bo *bo;
568 GENOS_TILE_TYPE tileformat;
569 UINT tileformat_linux;
570
571 INT width_align;
572 INT height_align;
573
574 bufname = pParams->pBufName;
575 tileformat_linux = I915_TILING_NONE;
576 hr = S_OK;
577
578 tileformat = pParams->TileType;
579
580 switch (tileformat) {
581 case GENOS_TILE_LINEAR:
582 width_align = 64;
583 height_align = 32;
584 break;
585 case GENOS_TILE_Y:
586 width_align = 128;
587 height_align = 32;
588 break;
589 default:
590 width_align = 16;
591 height_align = 16;
592 }
593
594 iWidth = ALIGN(pParams->dwWidth, width_align);
595 iHeight = ALIGN(pParams->dwHeight, height_align);
596
597 if (NULL == pOsResource) {
598 GENOS_OS_ASSERTMESSAGE("input parameter pOSResource is NULL.");
599 return E_FAIL;
600 }
601
602 switch (pParams->Format) {
603 case Format_Buffer:
604 case Format_RAW:
605 iPitch = iWidth;
606 iSize = iPitch;
607 break;
608 case Format_X8R8G8B8:
609 case Format_A8R8G8B8:
610 case Format_R32F:
611 case Format_R32U:
612 iPitch = 4 * iWidth;
613 iSize = iPitch * iHeight;
614 break;
615 case Format_R5G6B5:
616 case Format_V8U8:
617 case Format_YUY2:
618 case Format_UYVY:
619 case Format_AYUV:
620 case Format_R16U:
621 iPitch = 2 * iWidth;
622 iSize = iPitch * iHeight;
623 break;
624 case Format_AI44:
625 case Format_IA44:
626 case Format_L8:
627 case Format_P8:
628 case Format_A8:
629 case Format_STMM:
630 case Format_R8U:
631 iPitch = iWidth;
632 iSize = iPitch * iHeight;
633 break;
634 case Format_NV12:
635 if (iHeight & 0x1) {
636 hr = E_FAIL;
637 goto finish;
638 }
639 iPitch = iWidth;
640 iSize = iPitch * iHeight * 3 / 2;
641 break;
642 case Format_411P:
643 case Format_422H:
644 case Format_444P:
645 iPitch = iWidth;
646 iSize = iPitch * (3 * iHeight);
647 break;
648 case Format_422V:
649 case Format_IMC3:
650 iPitch = iWidth;
651 iSize = iPitch * (2 * iHeight);
652 break;
653 case Format_YV12:
654 iPitch = iWidth;
655 iSize = iPitch * (3 * iHeight / 2);
656 break;
657 case Format_NV21:
658 case Format_Buffer_2D:
659 default:
660 GENOS_OS_ASSERTMESSAGE("Unsupported format");
661 hr = E_FAIL;
662 goto finish;
663 }
664
665 switch (tileformat) {
666 case GENOS_TILE_Y:
667 tileformat_linux = I915_TILING_Y;
668 break;
669 case GENOS_TILE_X:
670 tileformat_linux = I915_TILING_X;
671 break;
672 default:
673 tileformat_linux = I915_TILING_NONE;
674 }
675
676 iSize = ALIGN(iSize, 4096);
677 if (tileformat_linux == I915_TILING_NONE) {
678 bo = drm_intel_bo_alloc(pOsInterface->pOsContext->bufmgr,
679 bufname, iSize, 4096);
680 } else {
681 bo = drm_intel_bo_alloc_tiled(pOsInterface->pOsContext->bufmgr,
682 bufname, iPitch, iSize / iPitch,
683 1, &tileformat_linux, &ulPitch,
684 0);
685 iPitch = (INT) ulPitch;
686 }
687
688 pOsResource->bMapped = FALSE;
689 if (bo) {
690 pOsResource->Format = pParams->Format;
691 pOsResource->iWidth = pParams->dwWidth;
692 pOsResource->iHeight = iHeight;
693 pOsResource->iPitch = iPitch;
694 pOsResource->iCount = 0;
695 pOsResource->bufname = bufname;
696 pOsResource->bo = bo;
697 pOsResource->TileType = tileformat;
698 pOsResource->pData = (PBYTE) bo->virtual;
699 GENOS_OS_VERBOSEMESSAGE("Alloc %7d bytes (%d x %d resource).",
700 iSize, pParams->dwWidth, iHeight);
701 } else {
702 GENOS_OS_ASSERTMESSAGE
703 ("Fail to Alloc %7d bytes (%d x %d resource).", iSize,
704 pParams->dwWidth, pParams->dwHeight);
705 hr = E_FAIL;
706 }
707
708 finish:
709 return hr;
710 }
711
IntelGen_OsFreeResource(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource)712 VOID IntelGen_OsFreeResource(PGENOS_INTERFACE pOsInterface,
713 PGENOS_RESOURCE pOsResource)
714 {
715 if (pOsResource && pOsResource->bo) {
716 drm_intel_bo_unreference((drm_intel_bo *) (pOsResource->bo));
717 pOsResource->bo = NULL;
718 }
719
720 }
721
IntelGen_OsLockResource(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource,PGENOS_LOCK_PARAMS pLockFlags)722 PVOID IntelGen_OsLockResource(PGENOS_INTERFACE pOsInterface,
723 PGENOS_RESOURCE pOsResource,
724 PGENOS_LOCK_PARAMS pLockFlags)
725 {
726 PVOID pData;
727
728 pData = NULL;
729
730 GENOS_OS_ASSERT(pOsInterface);
731 GENOS_OS_ASSERT(pOsInterface->pOsContext);
732 GENOS_OS_ASSERT(pOsResource);
733
734 if (pOsResource && pOsResource->bo) {
735 drm_intel_bo *bo = pOsResource->bo;
736
737 if (FALSE == pOsResource->bMapped) {
738 if (GFX_IS_PRODUCT
739 (pOsInterface->pOsContext->platform,
740 IGFX_CHERRYVIEW)) {
741 //uncache mapping for the BOs mapped once and then shared in multi-task submissions
742 // it is to W/A GPU hang on CHV when i915.ppgtt = 1 in KMD.
743 drm_intel_gem_bo_map_gtt(bo);
744 } else {
745 if (pOsResource->TileType == GENOS_TILE_LINEAR) {
746 drm_intel_bo_map(bo,
747 (OSKM_LOCKFLAG_WRITEONLY
748 &
749 pLockFlags->WriteOnly));
750 } else {
751 drm_intel_gem_bo_map_gtt(bo);
752 }
753 }
754
755 pOsResource->pData = (PBYTE) bo->virtual;
756 pOsResource->bMapped = TRUE;
757 }
758 pData = pOsResource->pData;
759 }
760
761 GENOS_OS_ASSERT(pData);
762 return pData;
763 }
764
IntelGen_OsUnlockResource(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource)765 HRESULT IntelGen_OsUnlockResource(PGENOS_INTERFACE pOsInterface,
766 PGENOS_RESOURCE pOsResource)
767 {
768 HRESULT hr;
769
770 hr = S_OK;
771
772 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
773 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface->pOsContext);
774 GENOS_OS_CHK_NULL_WITH_HR(pOsResource);
775
776 if (pOsResource->bo) {
777 if (TRUE == pOsResource->bMapped) {
778 if (GFX_IS_PRODUCT
779 (pOsInterface->pOsContext->platform,
780 IGFX_CHERRYVIEW)) {
781 // to be paired with IntelGen_OsLockResource
782 drm_intel_gem_bo_unmap_gtt(pOsResource->bo);
783 } else {
784 if (pOsResource->TileType == GENOS_TILE_LINEAR) {
785 drm_intel_bo_unmap(pOsResource->bo);
786 } else {
787 drm_intel_gem_bo_unmap_gtt
788 (pOsResource->bo);
789 }
790 }
791
792 pOsResource->bo->virtual = NULL;
793 pOsResource->bMapped = FALSE;
794 }
795 pOsResource->pData = NULL;
796 }
797 finish:
798 return hr;
799 }
800
IntelGen_OsSetPatchEntry(PGENOS_INTERFACE pOsInterface,const UINT iAllocationIndex,const UINT ResourceOffset,const UINT PatchOffset)801 HRESULT IntelGen_OsSetPatchEntry(PGENOS_INTERFACE pOsInterface,
802 const UINT iAllocationIndex,
803 const UINT ResourceOffset,
804 const UINT PatchOffset)
805 {
806 PGENOS_OS_CONTEXT pOsContext;
807 GENOS_OS_GPU_CONTEXT *pOsGpuContext;
808 PPATCHLOCATIONLIST pPatchList;
809 HRESULT hr = S_OK;
810
811 pOsContext = pOsInterface->pOsContext;
812 pOsGpuContext =
813 &pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
814 pPatchList = pOsGpuContext->pPatchLocationList;
815
816 pPatchList[pOsGpuContext->uiCurrentNumPatchLocations].AllocationIndex =
817 iAllocationIndex;
818 pPatchList[pOsGpuContext->uiCurrentNumPatchLocations].AllocationOffset =
819 ResourceOffset;
820 pPatchList[pOsGpuContext->uiCurrentNumPatchLocations].PatchOffset =
821 PatchOffset;
822
823 pOsGpuContext->uiCurrentNumPatchLocations++;
824
825 return hr;
826 }
827
IntelGen_OsRegisterResource(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource,BOOL bWrite,BOOL bWritebSetResourceSyncTag)828 HRESULT IntelGen_OsRegisterResource(PGENOS_INTERFACE pOsInterface,
829 PGENOS_RESOURCE pOsResource,
830 BOOL bWrite, BOOL bWritebSetResourceSyncTag)
831 {
832 PGENOS_OS_CONTEXT pOsContext;
833 PGENOS_RESOURCE pResources;
834 UINT uiAllocation;
835 HRESULT hResult = S_OK;
836 GENOS_OS_GPU_CONTEXT *pOsGpuContext;
837
838 GENOS_OS_ASSERT(pOsInterface);
839 GENOS_OS_ASSERT(pOsInterface->pOsContext);
840
841 pOsContext = pOsInterface->pOsContext;
842 pOsGpuContext =
843 &pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
844
845 pResources = pOsGpuContext->pResources;
846 if (NULL == pResources) {
847 GENOS_OS_ASSERTMESSAGE("pResouce is NULL.");
848 return S_OK;
849 }
850 for (uiAllocation = 0;
851 uiAllocation < pOsGpuContext->uiResCount;
852 uiAllocation++, pResources++) {
853 if (pOsResource->bo == pResources->bo)
854 break;
855 }
856 if (uiAllocation < pOsGpuContext->uiMaxNumAllocations) {
857 if (uiAllocation == pOsGpuContext->uiResCount) {
858 pOsGpuContext->uiResCount++;
859 }
860 pOsResource->
861 iAllocationIndex[pOsInterface->CurrentGpuContextOrdinal] =
862 uiAllocation;
863 pOsGpuContext->pResources[uiAllocation] = *pOsResource;
864 pOsGpuContext->pbWriteMode[uiAllocation] |= bWrite;
865 pOsGpuContext->pAllocationList[uiAllocation].hAllocation =
866 &pOsGpuContext->pResources[uiAllocation];
867 pOsGpuContext->pAllocationList[uiAllocation].WriteOperation =
868 bWrite;
869 pOsGpuContext->uiNumAllocations = pOsGpuContext->uiResCount;
870 } else {
871 GENOS_OS_ASSERTMESSAGE("Reached max # registrations.");
872 hResult = E_FAIL;
873 }
874 return hResult;
875 }
876
IntelGen_OsVerifyCommandBufferSize(PGENOS_INTERFACE pOsInterface,DWORD dwRequestedSize)877 HRESULT IntelGen_OsVerifyCommandBufferSize(PGENOS_INTERFACE pOsInterface,
878 DWORD dwRequestedSize)
879 {
880 PGENOS_OS_CONTEXT pOsContext;
881 GENOS_OS_GPU_CONTEXT OsGpuContext;
882
883 GENOS_OS_ASSERT(pOsInterface);
884 GENOS_OS_ASSERT(pOsInterface->pOsContext);
885
886 pOsContext = pOsInterface->pOsContext;
887 OsGpuContext =
888 pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
889
890 if (OsGpuContext.uiCommandBufferSize < dwRequestedSize) {
891 return E_FAIL;
892 }
893
894 return S_OK;
895 }
896
IntelGen_OsResetResourceAllocation(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource)897 VOID IntelGen_OsResetResourceAllocation(PGENOS_INTERFACE pOsInterface,
898 PGENOS_RESOURCE pOsResource)
899 {
900 INT i;
901
902 for (i = 0; i < GENOS_GPU_CONTEXT_MAX; i++) {
903 pOsResource->iAllocationIndex[i] = GENOS_INVALID_ALLOC_INDEX;
904 }
905 }
906
IntelGen_OsGetCommandBuffer(PGENOS_INTERFACE pOsInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)907 HRESULT IntelGen_OsGetCommandBuffer(PGENOS_INTERFACE pOsInterface,
908 PGENOS_COMMAND_BUFFER pCmdBuffer)
909 {
910
911 PGENOS_OS_CONTEXT pOsContext;
912 HRESULT hr = S_OK;
913 GENOS_STATUS eStatus = GENOS_STATUS_SUCCESS;
914 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
915 UINT uiCommandBufferSize;
916
917 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
918 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface->pOsContext);
919 GENOS_OS_CHK_NULL_WITH_HR(pCmdBuffer);
920
921 pOsContext = pOsInterface->pOsContext;
922 pOsGpuContext =
923 &pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
924 uiCommandBufferSize = pOsGpuContext->uiCommandBufferSize;
925
926 if (pOsGpuContext->bCBFlushed == TRUE) {
927 if (pOsContext->pfnGetCommandBuffer(pOsContext,
928 pCmdBuffer,
929 uiCommandBufferSize)) {
930 GENOS_OS_CHK_HR(pOsContext->pfnInsertCmdBufferToPool
931 (pOsContext,
932 pCmdBuffer->OsResource.bo));
933 pOsGpuContext->bCBFlushed = FALSE;
934 eStatus =
935 GENOS_SecureMemcpy(pOsGpuContext->pCB,
936 sizeof(GENOS_COMMAND_BUFFER),
937 pCmdBuffer,
938 sizeof(GENOS_COMMAND_BUFFER));
939 GENOS_OS_CHECK_CONDITION((eStatus !=
940 GENOS_STATUS_SUCCESS),
941 "Failed to copy command buffer",
942 E_FAIL);
943 } else {
944 GENOS_OS_ASSERTMESSAGE
945 ("Failed to activate command buffer.");
946 hr = E_FAIL;
947 goto finish;
948 }
949 }
950
951 GENOS_OS_CHK_HR(pOsInterface->pfnRegisterResource(pOsInterface,
952 &(pOsGpuContext->pCB->
953 OsResource), FALSE,
954 FALSE));
955 eStatus =
956 GENOS_SecureMemcpy(pCmdBuffer, sizeof(GENOS_COMMAND_BUFFER),
957 pOsGpuContext->pCB,
958 sizeof(GENOS_COMMAND_BUFFER));
959 GENOS_OS_CHECK_CONDITION((eStatus != GENOS_STATUS_SUCCESS),
960 "Failed to copy command buffer", E_FAIL);
961
962 finish:
963 return hr;
964 }
965
IntelGen_OsSetIndirectStateSize(PGENOS_INTERFACE pOsInterface,UINT uSize)966 HRESULT IntelGen_OsSetIndirectStateSize(PGENOS_INTERFACE pOsInterface,
967 UINT uSize)
968 {
969 PGENOS_CONTEXT pOsContext;
970 HRESULT hr;
971
972 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
973
974 hr = S_OK;
975
976 pOsContext = pOsInterface->pOsContext;
977 GENOS_OS_CHK_NULL_WITH_HR(pOsContext);
978
979 pOsContext->uIndirectStateSize = uSize;
980
981 finish:
982 return hr;
983 }
984
IntelGen_OsGetIndirectState(PGENOS_INTERFACE pOsInterface,UINT * puOffset,UINT * puSize)985 HRESULT IntelGen_OsGetIndirectState(PGENOS_INTERFACE pOsInterface,
986 UINT * puOffset, UINT * puSize)
987 {
988 PGENOS_CONTEXT pOsContext;
989 GENOS_OS_GPU_CONTEXT OsGpuContext;
990
991 pOsContext = pOsInterface->pOsContext;
992 if (pOsContext) {
993 OsGpuContext =
994 pOsContext->
995 OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
996
997 if (puOffset) {
998 *puOffset =
999 OsGpuContext.uiCommandBufferSize -
1000 pOsContext->uIndirectStateSize;
1001 }
1002
1003 if (puSize) {
1004 *puSize = pOsContext->uIndirectStateSize;
1005 }
1006 }
1007 return S_OK;
1008 }
1009
IntelGen_OsGetResourceAllocationIndex(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pResource)1010 INT IntelGen_OsGetResourceAllocationIndex(PGENOS_INTERFACE pOsInterface,
1011 PGENOS_RESOURCE pResource)
1012 {
1013 GENOS_OS_FUNCTION_ENTER;
1014
1015 if (pResource) {
1016 return (pResource->iAllocationIndex
1017 [pOsInterface->CurrentGpuContextOrdinal]);
1018 }
1019
1020 return GENOS_INVALID_ALLOC_INDEX;
1021
1022 }
1023
IntelGen_OsGetIndirectStatePointer(PGENOS_INTERFACE pOsInterface,PBYTE * pIndirectState)1024 HRESULT IntelGen_OsGetIndirectStatePointer(PGENOS_INTERFACE pOsInterface,
1025 PBYTE * pIndirectState)
1026 {
1027 PGENOS_OS_CONTEXT pOsContext;
1028 GENOS_OS_GPU_CONTEXT OsGpuContext;
1029 HRESULT hr;
1030
1031 GENOS_OS_FUNCTION_ENTER;
1032
1033 hr = E_FAIL;
1034 pOsContext = (pOsInterface) ? pOsInterface->pOsContext : NULL;
1035
1036 if (pOsContext) {
1037 OsGpuContext =
1038 pOsContext->
1039 OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
1040
1041 if (OsGpuContext.pCB && OsGpuContext.pCB->pCmdBase) {
1042 *pIndirectState =
1043 (PBYTE) OsGpuContext.pCB->pCmdBase +
1044 OsGpuContext.uiCommandBufferSize -
1045 pOsContext->uIndirectStateSize;
1046
1047 hr = S_OK;
1048 }
1049 }
1050
1051 return hr;
1052 }
1053
IntelGen_OsReturnCommandBuffer(PGENOS_INTERFACE pOsInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1054 VOID IntelGen_OsReturnCommandBuffer(PGENOS_INTERFACE pOsInterface,
1055 PGENOS_COMMAND_BUFFER pCmdBuffer)
1056 {
1057 PGENOS_OS_CONTEXT pOsContext;
1058
1059 pOsContext = (pOsInterface) ? pOsInterface->pOsContext : NULL;
1060 if (pOsContext == NULL || pCmdBuffer == NULL) {
1061 GENOS_OS_ASSERTMESSAGE("Invalid parameters.");
1062 goto finish;
1063 }
1064
1065 pOsContext->pfnReturnCommandBuffer(pOsContext,
1066 pOsInterface->CurrentGpuContextOrdinal,
1067 pCmdBuffer);
1068
1069 finish:
1070 return;
1071 }
1072
IntelGen_OsSubmitCommandBuffer(PGENOS_INTERFACE pOsInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,BOOL bNullRendering)1073 HRESULT IntelGen_OsSubmitCommandBuffer(PGENOS_INTERFACE pOsInterface,
1074 PGENOS_COMMAND_BUFFER pCmdBuffer,
1075 BOOL bNullRendering)
1076 {
1077 PGENOS_CONTEXT pOsContext;
1078 PGENOS_RESOURCE pResource;
1079 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
1080 GENOS_GPU_CONTEXT GpuContext;
1081 UINT PatchIndex, AllocationIndex;
1082 HRESULT hr;
1083 PPATCHLOCATIONLIST pPatchList, pCurrentPatch;
1084 drm_intel_bo *alloc_bo, *cmd_bo;
1085 INT ResourceOffset, PatchOffset;
1086 DWORD dwBatchBufferEndCmd;
1087 PLATFORM platform;
1088 UINT write_domain;
1089
1090 hr = S_OK;
1091
1092 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
1093
1094 pOsContext = pOsInterface->pOsContext;
1095 GENOS_OS_CHK_NULL_WITH_HR(pOsContext);
1096
1097 GpuContext = pOsInterface->CurrentGpuContextOrdinal;
1098
1099 GENOS_OS_CHK_NULL_WITH_HR(pOsContext->OsGpuContext);
1100 pOsGpuContext = &pOsContext->OsGpuContext[GpuContext];
1101 GENOS_OS_CHK_NULL_WITH_HR(pOsGpuContext);
1102
1103 pPatchList = pOsGpuContext->pPatchLocationList;
1104 GENOS_OS_CHK_NULL_WITH_HR(pPatchList);
1105
1106 pOsInterface->pfnGetPlatform(pOsInterface, &platform);
1107
1108 pOsGpuContext->bCBFlushed = TRUE;
1109 cmd_bo = pCmdBuffer->OsResource.bo;
1110
1111 for (PatchIndex = 0;
1112 PatchIndex < pOsGpuContext->uiCurrentNumPatchLocations;
1113 PatchIndex++) {
1114 pCurrentPatch = &pPatchList[PatchIndex];
1115 GENOS_OS_CHK_NULL_WITH_HR(pCurrentPatch);
1116
1117 AllocationIndex = pCurrentPatch->AllocationIndex;
1118 ResourceOffset = pCurrentPatch->AllocationOffset;
1119 PatchOffset = pCurrentPatch->PatchOffset;
1120
1121 pResource = (PGENOS_RESOURCE)
1122 pOsGpuContext->pAllocationList[AllocationIndex].hAllocation;
1123 GENOS_OS_CHK_NULL_WITH_HR(pResource);
1124
1125 GENOS_OS_ASSERT(pResource->bo);
1126
1127 alloc_bo = (pResource->bo) ? pResource->bo : cmd_bo;
1128
1129 *((DWORD *) ((BYTE *) cmd_bo->virtual + PatchOffset)) =
1130 alloc_bo->offset + ResourceOffset;
1131
1132 if (alloc_bo == cmd_bo) {
1133 write_domain = 0;
1134 } else {
1135 write_domain = I915_GEM_DOMAIN_RENDER;
1136 }
1137 hr = drm_intel_bo_emit_reloc(cmd_bo,
1138 PatchOffset,
1139 alloc_bo,
1140 ResourceOffset, 0x2, write_domain);
1141 if (hr != 0) {
1142 GENOS_OS_ASSERTMESSAGE
1143 ("Error patching alloc_bo = %p, cmd_bo = %p.",
1144 alloc_bo, cmd_bo);
1145 goto finish;
1146 }
1147 }
1148
1149 dwBatchBufferEndCmd = MI_BATCHBUFFER_END;
1150 if (GENOS_FAILED(IntelGen_OsAddCommand(pCmdBuffer,
1151 &dwBatchBufferEndCmd,
1152 sizeof(DWORD)))) {
1153 hr = E_FAIL;
1154 goto finish;
1155 }
1156
1157 drm_intel_bo_unmap(cmd_bo);
1158
1159 if (OSKMGetGpuNode(GpuContext) == I915_EXEC_RENDER) {
1160 {
1161 hr = drm_intel_bo_exec(cmd_bo,
1162 pOsGpuContext->uiCommandBufferSize,
1163 NULL, 0, 0);
1164 }
1165 } else {
1166 hr = drm_intel_bo_mrb_exec(cmd_bo,
1167 pOsGpuContext->uiCommandBufferSize,
1168 NULL,
1169 0, 0, OSKMGetGpuNode(GpuContext));
1170 }
1171
1172 pOsGpuContext->uiNumAllocations = 0;
1173 GENOS_ZeroMemory(pOsGpuContext->pAllocationList,
1174 sizeof(ALLOCATION_LIST) *
1175 pOsGpuContext->uiMaxNumAllocations);
1176 pOsGpuContext->uiCurrentNumPatchLocations = 0;
1177 GENOS_ZeroMemory(pOsGpuContext->pPatchLocationList,
1178 sizeof(PATCHLOCATIONLIST) *
1179 pOsGpuContext->uiMaxPatchLocationsize);
1180 pOsGpuContext->uiResCount = 0;
1181
1182 finish:
1183 return hr;
1184 }
1185
IntelGen_OsResizeCommandBufferAndPatchList(PGENOS_INTERFACE pOsInterface,DWORD dwRequestedCommandBufferSize,DWORD dwRequestedPatchListSize)1186 HRESULT IntelGen_OsResizeCommandBufferAndPatchList(PGENOS_INTERFACE
1187 pOsInterface,
1188 DWORD
1189 dwRequestedCommandBufferSize,
1190 DWORD
1191 dwRequestedPatchListSize)
1192 {
1193 PGENOS_CONTEXT pOsContext;
1194 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
1195 PPATCHLOCATIONLIST pNewPatchList;
1196 HRESULT hr;
1197
1198 GENOS_OS_FUNCTION_ENTER;
1199
1200 GENOS_OS_ASSERT(pOsInterface);
1201 GENOS_OS_ASSERT(pOsInterface->pOsContext);
1202
1203 hr = S_OK;
1204
1205 pOsContext = pOsInterface->pOsContext;
1206 pOsGpuContext =
1207 &(pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal]);
1208
1209 pOsGpuContext->uiCommandBufferSize =
1210 ALIGN(dwRequestedCommandBufferSize, 8);
1211
1212 if (dwRequestedPatchListSize > pOsGpuContext->uiMaxPatchLocationsize) {
1213 pNewPatchList = (PPATCHLOCATIONLIST)
1214 realloc(pOsGpuContext->pPatchLocationList,
1215 sizeof(PATCHLOCATIONLIST) *
1216 dwRequestedPatchListSize);
1217 if (NULL == pNewPatchList) {
1218 GENOS_OS_ASSERTMESSAGE
1219 ("pOsGpuContext->pPatchLocationList realloc failed.");
1220 hr = E_FAIL;
1221 goto finish;
1222 }
1223
1224 pOsGpuContext->pPatchLocationList = pNewPatchList;
1225
1226 GENOS_ZeroMemory((pOsGpuContext->pPatchLocationList +
1227 pOsGpuContext->uiMaxPatchLocationsize),
1228 sizeof(PATCHLOCATIONLIST) *
1229 (dwRequestedPatchListSize -
1230 pOsGpuContext->uiMaxPatchLocationsize));
1231 pOsGpuContext->uiMaxPatchLocationsize =
1232 dwRequestedPatchListSize;
1233 }
1234
1235 finish:
1236 return hr;
1237 }
1238
IntelGen_OsResizeCommandBuffer(PGENOS_INTERFACE pOsInterface,DWORD dwRequestedSize)1239 HRESULT IntelGen_OsResizeCommandBuffer(PGENOS_INTERFACE pOsInterface,
1240 DWORD dwRequestedSize)
1241 {
1242 PGENOS_CONTEXT pOsContext;
1243 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
1244 GENOS_GPU_CONTEXT GpuContext;
1245 HRESULT hr;
1246
1247 hr = S_OK;
1248
1249 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
1250 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface->pOsContext);
1251
1252 pOsContext =
1253 &pOsInterface->pOsContext[pOsInterface->CurrentGpuContextOrdinal];
1254 GENOS_OS_CHK_NULL_WITH_HR(pOsContext);
1255
1256 GpuContext = pOsInterface->CurrentGpuContextOrdinal;
1257
1258 GENOS_OS_CHK_NULL_WITH_HR(pOsContext->OsGpuContext);
1259 pOsGpuContext = &pOsContext->OsGpuContext[GpuContext];
1260 GENOS_OS_CHK_NULL_WITH_HR(pOsGpuContext);
1261
1262 pOsGpuContext->uiCommandBufferSize = dwRequestedSize;
1263
1264 finish:
1265 return hr;
1266 }
1267
IntelGen_OsFmt_OsToGen(GENOS_OS_FORMAT format)1268 GENOS_FORMAT IntelGen_OsFmt_OsToGen(GENOS_OS_FORMAT format)
1269 {
1270 switch ((INT) format) {
1271 case GFX_DDIFMT_A8B8G8R8:
1272 return Format_A8R8G8B8;
1273 case GFX_DDIFMT_X8B8G8R8:
1274 return Format_X8R8G8B8;
1275 case GFX_DDIFMT_R32F:
1276 return Format_R32F;
1277 case GFX_DDIFMT_A8R8G8B8:
1278 return Format_A8R8G8B8;
1279 case GFX_DDIFMT_X8R8G8B8:
1280 return Format_X8R8G8B8;
1281 case GFX_DDIFMT_R5G6B5:
1282 return Format_R5G6B5;
1283 case GFX_DDIFMT_YUY2:
1284 return Format_YUY2;
1285 case GFX_DDIFMT_P8:
1286 return Format_P8;
1287 case GFX_DDIFMT_A8P8:
1288 return Format_A8P8;
1289 case GFX_DDIFMT_A8:
1290 return Format_A8;
1291 case GFX_DDIFMT_L8:
1292 return Format_L8;
1293 case GFX_DDIFMT_A4L4:
1294 return Format_A4L4;
1295 case GFX_DDIFMT_A8L8:
1296 return Format_A8L8;
1297 case GFX_DDIFMT_V8U8:
1298 return Format_V8U8;
1299 case (GFX_DDIFORMAT) FOURCC_YVYU:
1300 return Format_YVYU;
1301 case (GFX_DDIFORMAT) FOURCC_UYVY:
1302 return Format_UYVY;
1303 case (GFX_DDIFORMAT) FOURCC_VYUY:
1304 return Format_VYUY;
1305 case (GFX_DDIFORMAT) FOURCC_AYUV:
1306 return Format_AYUV;
1307 case (GFX_DDIFORMAT) FOURCC_NV12:
1308 return Format_NV12;
1309 case (GFX_DDIFORMAT) FOURCC_NV21:
1310 return Format_NV21;
1311 case (GFX_DDIFORMAT) FOURCC_NV11:
1312 return Format_NV11;
1313 case (GFX_DDIFORMAT) FOURCC_P208:
1314 return Format_P208;
1315 case (GFX_DDIFORMAT) FOURCC_IMC1:
1316 return Format_IMC1;
1317 case (GFX_DDIFORMAT) FOURCC_IMC2:
1318 return Format_IMC2;
1319 case (GFX_DDIFORMAT) FOURCC_IMC3:
1320 return Format_IMC3;
1321 case (GFX_DDIFORMAT) FOURCC_IMC4:
1322 return Format_IMC4;
1323 case (GFX_DDIFORMAT) FOURCC_I420:
1324 return Format_I420;
1325 case (GFX_DDIFORMAT) FOURCC_IYUV:
1326 return Format_IYUV;
1327 case (GFX_DDIFORMAT) FOURCC_YV12:
1328 return Format_YV12;
1329 case (GFX_DDIFORMAT) FOURCC_YVU9:
1330 return Format_YVU9;
1331 case (GFX_DDIFORMAT) FOURCC_AI44:
1332 return Format_AI44;
1333 case (GFX_DDIFORMAT) FOURCC_IA44:
1334 return Format_IA44;
1335 case (GFX_DDIFORMAT) FOURCC_400P:
1336 return Format_400P;
1337 case (GFX_DDIFORMAT) FOURCC_411P:
1338 return Format_411P;
1339 case (GFX_DDIFORMAT) FOURCC_422H:
1340 return Format_422H;
1341 case (GFX_DDIFORMAT) FOURCC_422V:
1342 return Format_422V;
1343 case (GFX_DDIFORMAT) FOURCC_444P:
1344 return Format_444P;
1345 case (GFX_DDIFORMAT) FOURCC_RGBP:
1346 return Format_RGBP;
1347 case (GFX_DDIFORMAT) FOURCC_BGRP:
1348 return Format_BGRP;
1349 default:
1350 return Format_Invalid;
1351 }
1352 }
1353
IntelGen_OsFmt_GenToOs(GENOS_FORMAT format)1354 GENOS_OS_FORMAT IntelGen_OsFmt_GenToOs(GENOS_FORMAT format)
1355 {
1356 switch (format) {
1357 case Format_A8R8G8B8:
1358 return (GENOS_OS_FORMAT) GFX_DDIFMT_A8R8G8B8;
1359 case Format_X8R8G8B8:
1360 return (GENOS_OS_FORMAT) GFX_DDIFMT_X8R8G8B8;
1361 case Format_R32U:
1362 return (GENOS_OS_FORMAT) GFX_DDIFMT_R32F;
1363 case Format_R32F:
1364 return (GENOS_OS_FORMAT) GFX_DDIFMT_R32F;
1365 case Format_R5G6B5:
1366 return (GENOS_OS_FORMAT) GFX_DDIFMT_R5G6B5;
1367 case Format_YUY2:
1368 return (GENOS_OS_FORMAT) GFX_DDIFMT_YUY2;
1369 case Format_P8:
1370 return (GENOS_OS_FORMAT) GFX_DDIFMT_P8;
1371 case Format_A8P8:
1372 return (GENOS_OS_FORMAT) GFX_DDIFMT_A8P8;
1373 case Format_A8:
1374 return (GENOS_OS_FORMAT) GFX_DDIFMT_A8;
1375 case Format_L8:
1376 return (GENOS_OS_FORMAT) GFX_DDIFMT_L8;
1377 case Format_A4L4:
1378 return (GENOS_OS_FORMAT) GFX_DDIFMT_A4L4;
1379 case Format_A8L8:
1380 return (GENOS_OS_FORMAT) GFX_DDIFMT_A8L8;
1381 case Format_V8U8:
1382 return (GENOS_OS_FORMAT) GFX_DDIFMT_V8U8;
1383 case Format_YVYU:
1384 return (GENOS_OS_FORMAT) FOURCC_YVYU;
1385 case Format_UYVY:
1386 return (GENOS_OS_FORMAT) FOURCC_UYVY;
1387 case Format_VYUY:
1388 return (GENOS_OS_FORMAT) FOURCC_VYUY;
1389 case Format_AYUV:
1390 return (GENOS_OS_FORMAT) FOURCC_AYUV;
1391 case Format_NV12:
1392 return (GENOS_OS_FORMAT) FOURCC_NV12;
1393 case Format_NV21:
1394 return (GENOS_OS_FORMAT) FOURCC_NV21;
1395 case Format_NV11:
1396 return (GENOS_OS_FORMAT) FOURCC_NV11;
1397 case Format_P208:
1398 return (GENOS_OS_FORMAT) FOURCC_P208;
1399 case Format_IMC1:
1400 return (GENOS_OS_FORMAT) FOURCC_IMC1;
1401 case Format_IMC2:
1402 return (GENOS_OS_FORMAT) FOURCC_IMC2;
1403 case Format_IMC3:
1404 return (GENOS_OS_FORMAT) FOURCC_IMC3;
1405 case Format_IMC4:
1406 return (GENOS_OS_FORMAT) FOURCC_IMC4;
1407 case Format_I420:
1408 return (GENOS_OS_FORMAT) FOURCC_I420;
1409 case Format_IYUV:
1410 return (GENOS_OS_FORMAT) FOURCC_IYUV;
1411 case Format_YV12:
1412 return (GENOS_OS_FORMAT) FOURCC_YV12;
1413 case Format_YVU9:
1414 return (GENOS_OS_FORMAT) FOURCC_YVU9;
1415 case Format_AI44:
1416 return (GENOS_OS_FORMAT) FOURCC_AI44;
1417 case Format_IA44:
1418 return (GENOS_OS_FORMAT) FOURCC_IA44;
1419 case Format_400P:
1420 return (GENOS_OS_FORMAT) FOURCC_400P;
1421 case Format_411P:
1422 return (GENOS_OS_FORMAT) FOURCC_411P;
1423 case Format_422H:
1424 return (GENOS_OS_FORMAT) FOURCC_422H;
1425 case Format_422V:
1426 return (GENOS_OS_FORMAT) FOURCC_422V;
1427 case Format_444P:
1428 return (GENOS_OS_FORMAT) FOURCC_444P;
1429 case Format_RGBP:
1430 return (GENOS_OS_FORMAT) FOURCC_RGBP;
1431 case Format_BGRP:
1432 return (GENOS_OS_FORMAT) FOURCC_BGRP;
1433 case Format_STMM:
1434 return (GENOS_OS_FORMAT) GFX_DDIFMT_P8;
1435 default:
1436 return (GENOS_OS_FORMAT) GFX_DDIFMT_UNKNOWN;
1437 }
1438 }
1439
IntelGen_OsSleepMs(PGENOS_INTERFACE pOsInterface,DWORD dwWaitMs)1440 VOID IntelGen_OsSleepMs(PGENOS_INTERFACE pOsInterface, DWORD dwWaitMs)
1441 {
1442 usleep(dwWaitMs);
1443 }
1444
IntelGen_OsResetCommandBuffer(PGENOS_INTERFACE pOsInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1445 HRESULT IntelGen_OsResetCommandBuffer(PGENOS_INTERFACE pOsInterface,
1446 PGENOS_COMMAND_BUFFER pCmdBuffer)
1447 {
1448 PGENOS_OS_CONTEXT pOsContext;
1449 PGENOS_OS_GPU_CONTEXT pOsGpuContext;
1450
1451 GENOS_OS_FUNCTION_ENTER;
1452
1453 pOsContext = pOsInterface->pOsContext;
1454 pOsGpuContext =
1455 &pOsContext->OsGpuContext[pOsInterface->CurrentGpuContextOrdinal];
1456
1457 pOsGpuContext->bCBFlushed = TRUE;
1458
1459 return S_OK;
1460 }
1461
IntelGen_OsAllocUserptr(PGENOS_CONTEXT pOsContext,const char * name,void * addr,uint32_t tilingMode,uint32_t stride,unsigned long size,unsigned long flags)1462 static void* IntelGen_OsAllocUserptr(PGENOS_CONTEXT pOsContext,
1463 const char *name,
1464 void *addr,
1465 uint32_t tilingMode,
1466 uint32_t stride,
1467 unsigned long size,
1468 unsigned long flags)
1469 {
1470 return drm_intel_bo_alloc_userptr(pOsContext->bufmgr,
1471 name, addr, tilingMode,
1472 stride, size, flags);
1473 }
1474
IntelGen_OsInitInterface(PGENOS_INTERFACE pOsInterface,PGENOS_CONTEXT pOsDriverContext)1475 HRESULT IntelGen_OsInitInterface(PGENOS_INTERFACE pOsInterface,
1476 PGENOS_CONTEXT pOsDriverContext)
1477 {
1478 PGENOS_OS_CONTEXT pOsContext;
1479 HRESULT hr;
1480
1481 GENOS_OS_FUNCTION_ENTER;
1482
1483 pOsContext = NULL;
1484 hr = S_OK;
1485
1486 GENOS_OS_NORMALMESSAGE("mm:IntelGen_OsInitInterface called.");
1487
1488 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface);
1489 GENOS_OS_CHK_NULL_WITH_HR(pOsDriverContext);
1490
1491 pOsContext = (PGENOS_OS_CONTEXT)
1492 GENOS_AllocAndZeroMemory(sizeof(GENOS_OS_CONTEXT));
1493 if (pOsContext == NULL) {
1494 GENOS_OS_ASSERTMESSAGE("Unable to allocate memory.");
1495 hr = E_OUTOFMEMORY;
1496 goto finish;
1497 }
1498 hr = Ctx_InitContext(pOsContext, pOsDriverContext);
1499 if (S_OK != hr) {
1500 GENOS_OS_ASSERTMESSAGE("Unable to initialize context.");
1501 goto finish;
1502 }
1503
1504 pOsContext->bFreeContext = TRUE;
1505 pOsInterface->OS = GENOS_OS_LINUX;
1506 pOsInterface->pOsContext = pOsContext;
1507 pOsInterface->bUsesPatchList = TRUE;
1508 pOsInterface->bUsesGfxAddress = FALSE;
1509 pOsInterface->bNoParsingAssistanceInKmd = TRUE;
1510 pOsInterface->bUsesCmdBufHeaderInResize = FALSE;
1511 pOsInterface->bUsesCmdBufHeader = FALSE;
1512 pOsInterface->dwNumNalUnitBytesIncluded =
1513 GENOS_NAL_UNIT_LENGTH - GENOS_NAL_UNIT_STARTCODE_LENGTH;
1514
1515 drm_intel_bufmgr_gem_enable_reuse(pOsContext->bufmgr);
1516
1517 pOsInterface->pfnGetPlatform = IntelGen_OsGetPlatform;
1518 pOsInterface->pfnDestroy = IntelGen_OsDestroy;
1519
1520 pOsInterface->pfnResetOsStates = IntelGen_OsResetOsStates;
1521 pOsInterface->pfnAllocateResource = IntelGen_OsAllocateResource;
1522 pOsInterface->pfnFreeResource = IntelGen_OsFreeResource;
1523 pOsInterface->pfnLockResource = IntelGen_OsLockResource;
1524 pOsInterface->pfnUnlockResource = IntelGen_OsUnlockResource;
1525 pOsInterface->pfnRegisterResource = IntelGen_OsRegisterResource;
1526 pOsInterface->pfnResetResourceAllocationIndex =
1527 IntelGen_OsResetResourceAllocation;
1528 pOsInterface->pfnGetResourceAllocationIndex =
1529 IntelGen_OsGetResourceAllocationIndex;
1530 pOsInterface->pfnGetCommandBuffer = IntelGen_OsGetCommandBuffer;
1531 pOsInterface->pfnResetCommandBuffer = IntelGen_OsResetCommandBuffer;
1532 pOsInterface->pfnReturnCommandBuffer = IntelGen_OsReturnCommandBuffer;
1533 pOsInterface->pfnSubmitCommandBuffer = IntelGen_OsSubmitCommandBuffer;
1534 pOsInterface->pfnVerifyCommandBufferSize =
1535 IntelGen_OsVerifyCommandBufferSize;
1536 pOsInterface->pfnResizeCommandBufferAndPatchList =
1537 IntelGen_OsResizeCommandBufferAndPatchList;
1538 pOsInterface->pfnFmt_OsToGen = IntelGen_OsFmt_OsToGen;
1539 pOsInterface->pfnFmt_GenToOs = IntelGen_OsFmt_GenToOs;
1540 pOsInterface->pfnSetIndirectStateSize = IntelGen_OsSetIndirectStateSize;
1541 pOsInterface->pfnGetIndirectState = IntelGen_OsGetIndirectState;
1542 pOsInterface->pfnGetIndirectStatePointer =
1543 IntelGen_OsGetIndirectStatePointer;
1544 pOsInterface->pfnSetPatchEntry = IntelGen_OsSetPatchEntry;
1545 pOsInterface->pfnAllocUserptr = IntelGen_OsAllocUserptr;
1546
1547 pOsInterface->pfnSleepMs = IntelGen_OsSleepMs;
1548
1549 hr = S_OK;
1550
1551 finish:
1552 if (S_OK != hr && NULL != pOsContext) {
1553 if (pOsContext->fd >= 0) {
1554 close(pOsContext->fd);
1555 }
1556 GENOS_FreeMemAndSetNull(pOsContext);
1557 }
1558 return hr;
1559 }
1560
IntelGen_OsResourceIsNull(PGENOS_RESOURCE pOsResource)1561 BOOL IntelGen_OsResourceIsNull(PGENOS_RESOURCE pOsResource)
1562 {
1563 GENOS_OS_ASSERT(pOsResource);
1564
1565 return ((pOsResource->bo == NULL));
1566 }
1567
IntelGen_OsResetResource(PGENOS_RESOURCE pOsResource)1568 VOID IntelGen_OsResetResource(PGENOS_RESOURCE pOsResource)
1569 {
1570 INT i;
1571
1572 GENOS_OS_FUNCTION_ENTER;
1573
1574 GENOS_OS_ASSERT(pOsResource);
1575
1576 GENOS_ZeroMemory(pOsResource, sizeof(GENOS_RESOURCE));
1577 pOsResource->Format = Format_None;
1578 for (i = 0; i < GENOS_GPU_CONTEXT_MAX; i++) {
1579 pOsResource->iAllocationIndex[i] = GENOS_INVALID_ALLOC_INDEX;
1580 }
1581 }
1582
IntelGen_OsWaitOnResource(PGENOS_INTERFACE pOsInterface,PGENOS_RESOURCE pOsResource)1583 HRESULT IntelGen_OsWaitOnResource(PGENOS_INTERFACE pOsInterface,
1584 PGENOS_RESOURCE pOsResource)
1585 {
1586 HRESULT hr;
1587 GENOS_LOCK_PARAMS LockFlags;
1588
1589 GENOS_OS_ASSERT(pOsInterface);
1590 GENOS_OS_ASSERT(pOsResource);
1591 GENOS_OS_ASSERT(pOsInterface->pOsContext);
1592
1593 hr = S_OK;
1594
1595 GENOS_ZeroMemory(&LockFlags, sizeof(GENOS_LOCK_PARAMS));
1596
1597 LockFlags.WriteOnly = 1;
1598
1599 GENOS_OS_CHK_NULL_WITH_HR(pOsInterface->pfnLockResource(pOsInterface,
1600 pOsResource,
1601 &LockFlags));
1602
1603 GENOS_OS_CHK_HR(pOsInterface->pfnUnlockResource
1604 (pOsInterface, pOsResource));
1605
1606 finish:
1607 return hr;
1608 }
1609
IntelGen_OsInitInterfaceComp(PGENOS_INTERFACE pOsInterface,PGENOS_CONTEXT pOsDriverContext,GENOS_COMPONENT component)1610 HRESULT IntelGen_OsInitInterfaceComp(PGENOS_INTERFACE pOsInterface,
1611 PGENOS_CONTEXT pOsDriverContext,
1612 GENOS_COMPONENT component)
1613 {
1614 HRESULT hr = E_FAIL;
1615
1616 pOsInterface->pfnWaitOnResource = IntelGen_OsWaitOnResource;
1617 hr = IntelGen_OsInitInterface(pOsInterface, pOsDriverContext);
1618
1619 return hr;
1620 }
1621
OsToGenTileType(UINT type)1622 GENOS_TILE_TYPE OsToGenTileType(UINT type)
1623 {
1624 switch (type) {
1625 case I915_TILING_NONE:
1626 return GENOS_TILE_LINEAR;
1627 case I915_TILING_X:
1628 return GENOS_TILE_X;
1629 case I915_TILING_Y:
1630 return GENOS_TILE_Y;
1631 default:
1632 return GENOS_TILE_INVALID;
1633 }
1634 };
1635
1636 #define PATH_MAX 256
FindDeviceNum(const char * name)1637 static int FindDeviceNum(const char *name)
1638 {
1639 int fd = -1;
1640 char path[PATH_MAX];
1641 char bpo[64];
1642 drmVersionPtr version;
1643 int num;
1644
1645 snprintf(bpo, sizeof(bpo), "%s_bpo", name);
1646
1647 for (num = 0; num < 32; num++) {
1648 sprintf(path, "/dev/dri/card%d", num);
1649 if ((fd = open(path, O_RDWR)) >= 0) {
1650 if ((version = drmGetVersion(fd))) {
1651 if (!(strcmp(version->name, name) &&
1652 strcmp(version->name, bpo))) {
1653 drmFreeVersion(version);
1654 close(fd);
1655 break;
1656 }
1657 drmFreeVersion(version);
1658 }
1659 close(fd);
1660 }
1661 }
1662 return num;
1663 }
1664
OpenDevice()1665 static int OpenDevice()
1666 {
1667 int num = FindDeviceNum("i915");
1668 int fd = -1;
1669 char path[PATH_MAX];
1670 sprintf(path, "/dev/dri/renderD%d", 128 + num);
1671 fd = open(path, O_RDWR);
1672 if (fd < 0) {
1673 sprintf(path, "/dev/dri/card%d", num);
1674 fd = open(path, O_RDWR);
1675 }
1676 return fd;
1677 }
1678
platform_setTypeAndFamily(PLATFORM * pPlatform,const PLATFORM_TYPE platformType,const PRODUCT_FAMILY productFamily,const GFXCORE_FAMILY displayFamily,const GFXCORE_FAMILY renderFamily)1679 static inline void platform_setTypeAndFamily(PLATFORM * pPlatform,
1680 const PLATFORM_TYPE platformType,
1681 const PRODUCT_FAMILY productFamily,
1682 const GFXCORE_FAMILY displayFamily,
1683 const GFXCORE_FAMILY renderFamily)
1684 {
1685 GENOS_OS_ASSERT(pPlatform);
1686
1687 pPlatform->ePlatformType = platformType;
1688 pPlatform->eProductFamily = productFamily;
1689 pPlatform->ePCHProductFamily = PCH_UNKNOWN;
1690 pPlatform->eDisplayCoreFamily = displayFamily;
1691 pPlatform->eRenderCoreFamily = renderFamily;
1692 }
1693
updatePlatformInfo(PLATFORM * pPlatform)1694 static int updatePlatformInfo(PLATFORM * pPlatform)
1695 {
1696 if (!pPlatform) {
1697 return -EINVAL;
1698 }
1699
1700 const unsigned int uDeviceID = pPlatform->pchDeviceID;
1701
1702 switch (uDeviceID) {
1703 /* HSW DESKTOP */
1704 case IHSW_CL_DESK_GT1_DEV_ID:
1705 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1706 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1707 IGFX_GEN7_5_CORE);
1708 pPlatform->GtType = GTTYPE_GT1;
1709 break;
1710 case IHSW_GTH_DESK_DEVICE_F0_ID:
1711 case IHSW_GTM_DESK_DEVICE_F0_ID:
1712 case IHSW_GTL_DESK_DEVICE_F0_ID:
1713 case IHSW_DESK_DEV_F0_ID:
1714 case IHSW_DESK_DEV_F0_M_ID:
1715 case IHSW_DESK_DEV_F0_H_ID:
1716 case IHSW_CL_DESK_GT2_DEV_ID:
1717 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1718 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1719 IGFX_GEN7_5_CORE);
1720 pPlatform->GtType = GTTYPE_GT2;
1721 break;
1722 case IHSW_CRW_DESK_GT2_DEV_ID:
1723 case IHSW_CRW_DESK_GT3_DEV_ID:
1724 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1725 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1726 IGFX_GEN7_5_CORE);
1727 pPlatform->GtType = GTTYPE_GT3;
1728 break;
1729
1730 /* HSW MOBILE */
1731 case IHSW_CL_MOBL_GT1_DEV_ID:
1732 case IHSW_ULT_MOBL_GT1_DEV_ID:
1733 case IHSW_ULX_MOBL_GT1_DEV_ID:
1734 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1735 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1736 IGFX_GEN7_5_CORE);
1737 pPlatform->GtType = GTTYPE_GT1;
1738 break;
1739 case IHSW_MOBL_DEV_F0_ID:
1740 case IHSW_MOBL_DEV_F0_M_ID:
1741 case IHSW_MOBL_DEV_F0_H_ID:
1742 case IHSW_VA_DEV_F0_ID:
1743 case IHSW_MOBL_DEVICE_F0_ID:
1744 case IHSW_CL_MOBL_GT2_DEV_ID:
1745 case IHSW_ULT_MOBL_GT2_DEV_ID:
1746 case IHSW_ULX_MOBL_GT2_DEV_ID:
1747 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1748 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1749 IGFX_GEN7_5_CORE);
1750 pPlatform->GtType = GTTYPE_GT2;
1751 break;
1752 case IHSW_ULT_MOBL_GT3_DEV_ID:
1753 case IHSW_ULT_MRKT_GT3_DEV_ID:
1754 case IHSW_CRW_MOBL_GT2_DEV_ID:
1755 case IHSW_CRW_MOBL_GT3_DEV_ID:
1756 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1757 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1758 IGFX_GEN7_5_CORE);
1759 pPlatform->GtType = GTTYPE_GT3;
1760 break;
1761 /* HSW SERVER */
1762 case IHSW_CL_SERV_GT1_DEV_ID:
1763 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1764 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1765 IGFX_GEN7_5_CORE);
1766 pPlatform->GtType = GTTYPE_GT1;
1767 break;
1768 case IHSW_CL_SERV_GT2_DEV_ID:
1769 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1770 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1771 IGFX_GEN7_5_CORE);
1772 pPlatform->GtType = GTTYPE_GT2;
1773 break;
1774 case IHSW_CRW_SERV_GT3_DEV_ID:
1775 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1776 IGFX_HASWELL, IGFX_GEN7_5_CORE,
1777 IGFX_GEN7_5_CORE);
1778 pPlatform->GtType = GTTYPE_GT3;
1779 break;
1780
1781 case IBDW_GT0_DESK_DEVICE_F0_ID:
1782 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1783 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1784 IGFX_GEN8_CORE);
1785 pPlatform->GtType = GTTYPE_GT0;
1786 break;
1787 case IBDW_GT1_SERV_DEVICE_F0_ID:
1788 case IBDW_GT1_WRK_DEVICE_F0_ID:
1789 case IBDW_GT1_ULX_DEVICE_F0_ID:
1790 case IBDW_GT1_RSVD_DEVICE_F0_ID:
1791 case IBDW_GT1_DESK_DEVICE_F0_ID:
1792 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1793 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1794 IGFX_GEN8_CORE);
1795 pPlatform->GtType = GTTYPE_GT1;
1796 break;
1797 case IBDW_GT2_DESK_DEVICE_F0_ID:
1798 case IBDW_GT2_RSVD_DEVICE_F0_ID:
1799 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1800 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1801 IGFX_GEN8_CORE);
1802 pPlatform->GtType = GTTYPE_GT2;
1803 break;
1804 case IBDW_GT1_HALO_MOBL_DEVICE_F0_ID:
1805 case IBDW_GT1_ULT_MOBL_DEVICE_F0_ID:
1806 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1807 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1808 IGFX_GEN8_CORE);
1809 pPlatform->GtType = GTTYPE_GT1;
1810 break;
1811 case IBDW_GT2_HALO_MOBL_DEVICE_F0_ID:
1812 case IBDW_GT2_ULT_MOBL_DEVICE_F0_ID:
1813 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1814 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1815 IGFX_GEN8_CORE);
1816 pPlatform->GtType = GTTYPE_GT2;
1817 break;
1818 case IBDW_GT2_SERV_DEVICE_F0_ID:
1819 case IBDW_GT2_WRK_DEVICE_F0_ID:
1820 case IBDW_GT2_ULX_DEVICE_F0_ID:
1821 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1822 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1823 IGFX_GEN8_CORE);
1824 pPlatform->GtType = GTTYPE_GT2;
1825 break;
1826 case IBDW_GT3_ULT_MOBL_DEVICE_F0_ID:
1827 case IBDW_GT3_HALO_MOBL_DEVICE_F0_ID:
1828 case IBDW_GT3_ULT25W_MOBL_DEVICE_F0_ID:
1829 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1830 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1831 IGFX_GEN8_CORE);
1832 pPlatform->GtType = GTTYPE_GT3;
1833 break;
1834 case IBDW_GT3_SERV_DEVICE_F0_ID:
1835 case IBDW_GT3_WRK_DEVICE_F0_ID:
1836 case IBDW_GT3_ULX_DEVICE_F0_ID:
1837 case IBDW_GT3_DESK_DEVICE_F0_ID:
1838 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1839 IGFX_BROADWELL, IGFX_GEN7_5_CORE,
1840 IGFX_GEN8_CORE);
1841 pPlatform->GtType = GTTYPE_GT3;
1842 break;
1843 case ICHV_MOBL_DEVICE_F0_ID:
1844 case ICHV_PLUS_MOBL_DEVICE_F0_ID:
1845 case ICHV_DESK_DEVICE_F0_ID:
1846 case ICHV_PLUS_DESK_DEVICE_F0_ID:
1847 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1848 IGFX_CHERRYVIEW, IGFX_GEN5_CORE,
1849 IGFX_GEN8_CORE);
1850 pPlatform->GtType = GTTYPE_GT1;
1851 break;
1852
1853 case ISKL_GT0_DESK_DEVICE_F0_ID:
1854 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1855 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1856 IGFX_GEN9_CORE);
1857 pPlatform->GtType = GTTYPE_GT0;
1858 break;
1859 case ISKL_GT1_DESK_DEVICE_F0_ID:
1860 case ISKL_GT1_DT_DEVICE_F0_ID:
1861 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1862 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1863 IGFX_GEN9_CORE);
1864 pPlatform->GtType = GTTYPE_GT1;
1865 break;
1866 case ISKL_GT2_DESK_DEVICE_F0_ID:
1867 case ISKL_GT2_DT_DEVICE_F0_ID:
1868 case ISKL_GT2_WRK_DEVICE_F0_ID:
1869 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1870 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1871 IGFX_GEN9_CORE);
1872 pPlatform->GtType = GTTYPE_GT2;
1873 break;
1874 case ISKL_GT3_DESK_DEVICE_F0_ID:
1875 case ISKL_GT3_ULT_DEVICE_F0_ID:
1876 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1877 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1878 IGFX_GEN9_CORE);
1879 pPlatform->GtType = GTTYPE_GT3;
1880 break;
1881 case ISKL_GT4_DESK_DEVICE_F0_ID:
1882 case ISKL_GT4_DT_DEVICE_F0_ID:
1883 platform_setTypeAndFamily(pPlatform, PLATFORM_DESKTOP,
1884 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1885 IGFX_GEN9_CORE);
1886 pPlatform->GtType = GTTYPE_GT4;
1887 break;
1888 case ISKL_GT2_ULT_DEVICE_F0_ID:
1889 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1890 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1891 IGFX_GEN9_CORE);
1892 pPlatform->GtType = GTTYPE_GT2;
1893 break;
1894 case ISKL_GT2_ULX_DEVICE_F0_ID:
1895 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1896 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1897 IGFX_GEN9_CORE);
1898 pPlatform->GtType = GTTYPE_GT2;
1899 break;
1900 case ISKL_GT1_ULT_DEVICE_F0_ID:
1901 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1902 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1903 IGFX_GEN9_CORE);
1904 pPlatform->GtType = GTTYPE_GT1;
1905 break;
1906 case ISKL_GT1_ULX_DEVICE_F0_ID:
1907 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1908 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1909 IGFX_GEN9_CORE);
1910 pPlatform->GtType = GTTYPE_GT1;
1911 break;
1912 case ISKL_GT1_5_ULT_DEVICE_F0_ID:
1913 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1914 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1915 IGFX_GEN9_CORE);
1916 pPlatform->GtType = GTTYPE_GT1_5;
1917 break;
1918 case ISKL_GT1_5_ULX_DEVICE_F0_ID:
1919 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1920 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1921 IGFX_GEN9_CORE);
1922 pPlatform->GtType = GTTYPE_GT1_5;
1923 break;
1924 case ISKL_GT0_MOBL_DEVICE_F0_ID:
1925 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1926 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1927 IGFX_GEN9_CORE);
1928 pPlatform->GtType = GTTYPE_GT0;
1929 break;
1930 case ISKL_GT1_HALO_MOBL_DEVICE_F0_ID:
1931 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1932 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1933 IGFX_GEN9_CORE);
1934 pPlatform->GtType = GTTYPE_GT1;
1935 break;
1936 case ISKL_GT2_HALO_MOBL_DEVICE_F0_ID:
1937 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1938 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1939 IGFX_GEN9_CORE);
1940 pPlatform->GtType = GTTYPE_GT2;
1941 break;
1942 case ISKL_GT3_HALO_MOBL_DEVICE_F0_ID:
1943 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1944 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1945 IGFX_GEN9_CORE);
1946 pPlatform->GtType = GTTYPE_GT3;
1947 break;
1948 case ISKL_GT4_HALO_MOBL_DEVICE_F0_ID:
1949 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1950 IGFX_SKYLAKE, IGFX_GEN9_CORE,
1951 IGFX_GEN9_CORE);
1952 pPlatform->GtType = GTTYPE_GT4;
1953 break;
1954
1955 case IBXT_GT_3x6_DEVICE_ID:
1956 case IBXT_PRO_3x6_DEVICE_ID:
1957 case IBXT_PRO_12EU_3x6_DEVICE_ID:
1958 case IBXT_P_3x6_DEVICE_ID:
1959 case IBXT_P_12EU_3x6_DEVICE_ID:
1960 platform_setTypeAndFamily(pPlatform, PLATFORM_MOBILE,
1961 IGFX_BROXTON, IGFX_GEN9_CORE,
1962 IGFX_GEN9_CORE);
1963 pPlatform->GtType = GTTYPE_GTA;
1964 break;
1965
1966 case IKBL_GT1_5_DT_DEVICE_F0_ID:
1967 case IKBL_GT1_5_ULT_DEVICE_F0_ID:
1968 case IKBL_GT1_5_ULX_DEVICE_F0_ID:
1969 platform_setTypeAndFamily(pPlatform, PLATFORM_ALL,
1970 IGFX_KABYLAKE, IGFX_GEN9_CORE,
1971 IGFX_GEN9_CORE);
1972 pPlatform->GtType = GTTYPE_GT1_5;
1973 break;
1974
1975 case IKBL_GT2_ULT_DEVICE_F0_ID:
1976 case IKBL_GT2_ULX_DEVICE_F0_ID:
1977 case IKBL_GT2_DT_DEVICE_F0_ID:
1978 case IKBL_GT2F_ULT_DEVICE_F0_ID:
1979 case IKBL_GT2_HALO_DEVICE_F0_ID:
1980 case IKBL_GT2_SERV_DEVICE_F0_ID:
1981 case IKBL_GT2_WRK_DEVICE_F0_ID:
1982 platform_setTypeAndFamily(pPlatform, PLATFORM_ALL,
1983 IGFX_KABYLAKE, IGFX_GEN9_CORE,
1984 IGFX_GEN9_CORE);
1985 pPlatform->GtType = GTTYPE_GT2;
1986 break;
1987 case IKBL_GT4_HALO_DEVICE_F0_ID:
1988 case IKBL_GT4_DT_DEVICE_F0_ID:
1989 case IKBL_GT4_SERV_DEVICE_F0_ID:
1990 case IKBL_GT4_WRK_DEVICE_F0_ID:
1991 platform_setTypeAndFamily(pPlatform, PLATFORM_ALL,
1992 IGFX_KABYLAKE, IGFX_GEN9_CORE,
1993 IGFX_GEN9_CORE);
1994 pPlatform->GtType = GTTYPE_GT4;
1995 break;
1996 case IKBL_GT1_ULT_DEVICE_F0_ID:
1997 case IKBL_GT1_ULX_DEVICE_F0_ID:
1998 case IKBL_GT1_DT_DEVICE_F0_ID:
1999 case IKBL_GT1_HALO_DEVICE_F0_ID:
2000 case IKBL_GT1_SERV_DEVICE_F0_ID:
2001 platform_setTypeAndFamily(pPlatform, PLATFORM_ALL,
2002 IGFX_KABYLAKE, IGFX_GEN9_CORE,
2003 IGFX_GEN9_CORE);
2004 pPlatform->GtType = GTTYPE_GT1;
2005 break;
2006 case IKBL_GT3_ULT_DEVICE_F0_ID:
2007 case IKBL_GT3_HALO_DEVICE_F0_ID:
2008 case IKBL_GT3_SERV_DEVICE_F0_ID:
2009 platform_setTypeAndFamily(pPlatform, PLATFORM_ALL,
2010 IGFX_KABYLAKE, IGFX_GEN9_CORE,
2011 IGFX_GEN9_CORE);
2012 pPlatform->GtType = GTTYPE_GT3;
2013 break;
2014
2015 default:
2016 GENOS_OS_ASSERTMESSAGE("Unrecognized device ID %04X",
2017 uDeviceID);
2018 return -ENODEV;
2019 }
2020
2021 pPlatform->usRevId = pPlatform->usRevId;
2022 pPlatform->usRevId_PCH = pPlatform->usRevId_PCH;
2023 pPlatform->ePlatformType = pPlatform->ePlatformType;
2024
2025 return 0;
2026 }
2027
getRevId(unsigned short * value)2028 static void getRevId(unsigned short *value)
2029 {
2030 #define PCI_REVID 8
2031 FILE *fp;
2032 CHAR config_data[16];
2033
2034 fp = fopen("/sys/devices/pci0000:00/0000:00:02.0/config", "r");
2035
2036 if (fp) {
2037 if (fread(config_data, 1, 16, fp))
2038 *value = config_data[PCI_REVID];
2039 else
2040 *value = 2; /* assume it is at least B-steping */
2041 fclose(fp);
2042 } else {
2043 *value = 2; /* assume it is at least B-steping */
2044 }
2045
2046 return;
2047 }
2048