1 //
2 // JERRY Core
3 //
4 // Originally by David Raingeard
5 // GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS)
6 // Cleanups/rewrites/fixes by James Hammons
7 //
8 // JLH = James Hammons <jlhamm@acm.org>
9 //
10 // WHO WHEN WHAT
11 // --- ---------- -----------------------------------------------------------
12 // JLH 11/25/2009 Major rewrite of memory subsystem and handlers
13 //
14
15 // ------------------------------------------------------------
16 // JERRY REGISTERS (Mapped by Aaron Giles)
17 // ------------------------------------------------------------
18 // F10000-F13FFF R/W xxxxxxxx xxxxxxxx Jerry
19 // F10000 W xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
20 // F10002 W xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
21 // F10004 W xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
22 // F10008 W xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
23 // F10010 W ------xx xxxxxxxx CLK1 - processor clock divider
24 // F10012 W ------xx xxxxxxxx CLK2 - video clock divider
25 // F10014 W -------- --xxxxxx CLK3 - chroma clock divider
26 // F10020 R/W ---xxxxx ---xxxxx JINTCTRL - interrupt control register
27 // W ---x---- -------- (J_SYNCLR - clear synchronous serial intf ints)
28 // W ----x--- -------- (J_ASYNCLR - clear asynchronous serial intf ints)
29 // W -----x-- -------- (J_TIM2CLR - clear timer 2 [tempo] interrupts)
30 // W ------x- -------- (J_TIM1CLR - clear timer 1 [sample] interrupts)
31 // W -------x -------- (J_EXTCLR - clear external interrupts)
32 // R/W -------- ---x---- (J_SYNENA - enable synchronous serial intf ints)
33 // R/W -------- ----x--- (J_ASYNENA - enable asynchronous serial intf ints)
34 // R/W -------- -----x-- (J_TIM2ENA - enable timer 2 [tempo] interrupts)
35 // R/W -------- ------x- (J_TIM1ENA - enable timer 1 [sample] interrupts)
36 // R/W -------- -------x (J_EXTENA - enable external interrupts)
37 // F10030 R/W -------- xxxxxxxx ASIDATA - asynchronous serial data
38 // F10032 W -x------ -xxxxxxx ASICTRL - asynchronous serial control
39 // W -x------ -------- (TXBRK - transmit break)
40 // W -------- -x------ (CLRERR - clear error)
41 // W -------- --x----- (RINTEN - enable receiver interrupts)
42 // W -------- ---x---- (TINTEN - enable transmitter interrupts)
43 // W -------- ----x--- (RXIPOL - receiver input polarity)
44 // W -------- -----x-- (TXOPOL - transmitter output polarity)
45 // W -------- ------x- (PAREN - parity enable)
46 // W -------- -------x (ODD - odd parity select)
47 // F10032 R xxx-xxxx x-xxxxxx ASISTAT - asynchronous serial status
48 // R x------- -------- (ERROR - OR of PE,FE,OE)
49 // R -x------ -------- (TXBRK - transmit break)
50 // R --x----- -------- (SERIN - serial input)
51 // R ----x--- -------- (OE - overrun error)
52 // R -----x-- -------- (FE - framing error)
53 // R ------x- -------- (PE - parity error)
54 // R -------x -------- (TBE - transmit buffer empty)
55 // R -------- x------- (RBF - receive buffer full)
56 // R -------- ---x---- (TINTEN - enable transmitter interrupts)
57 // R -------- ----x--- (RXIPOL - receiver input polarity)
58 // R -------- -----x-- (TXOPOL - transmitter output polarity)
59 // R -------- ------x- (PAREN - parity enable)
60 // R -------- -------x (ODD - odd parity)
61 // F10034 R/W xxxxxxxx xxxxxxxx ASICLK - asynchronous serial interface clock
62 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
63 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
64 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
65 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
66 // ------------------------------------------------------------
67 // F14000-F17FFF R/W xxxxxxxx xxxxxxxx Joysticks and GPIO0-5
68 // F14000 R xxxxxxxx xxxxxxxx JOYSTICK - read joystick state
69 // F14000 W x------- xxxxxxxx JOYSTICK - latch joystick output
70 // W x------- -------- (enable joystick outputs)
71 // W -------- xxxxxxxx (joystick output data)
72 // F14002 R xxxxxxxx xxxxxxxx JOYBUTS - button register
73 // F14800-F14FFF R/W xxxxxxxx xxxxxxxx GPI00 - reserved (CD-ROM? no.)
74 // F15000-F15FFF R/W xxxxxxxx xxxxxxxx GPI01 - reserved
75 // F16000-F16FFF R/W xxxxxxxx xxxxxxxx GPI02 - reserved
76 // F17000-F177FF R/W xxxxxxxx xxxxxxxx GPI03 - reserved
77 // F17800-F17BFF R/W xxxxxxxx xxxxxxxx GPI04 - reserved
78 // F17C00-F17FFF R/W xxxxxxxx xxxxxxxx GPI05 - reserved
79 // ------------------------------------------------------------
80 // F18000-F1FFFF R/W xxxxxxxx xxxxxxxx Jerry DSP
81 // F1A100 R/W xxxxxxxx xxxxxxxx D_FLAGS - DSP flags register
82 // R/W x------- -------- (DMAEN - DMA enable)
83 // R/W -x------ -------- (REGPAGE - register page)
84 // W --x----- -------- (D_EXT0CLR - clear external interrupt 0)
85 // W ---x---- -------- (D_TIM2CLR - clear timer 2 interrupt)
86 // W ----x--- -------- (D_TIM1CLR - clear timer 1 interrupt)
87 // W -----x-- -------- (D_I2SCLR - clear I2S interrupt)
88 // W ------x- -------- (D_CPUCLR - clear CPU interrupt)
89 // R/W -------x -------- (D_EXT0ENA - enable external interrupt 0)
90 // R/W -------- x------- (D_TIM2ENA - enable timer 2 interrupt)
91 // R/W -------- -x------ (D_TIM1ENA - enable timer 1 interrupt)
92 // R/W -------- --x----- (D_I2SENA - enable I2S interrupt)
93 // R/W -------- ---x---- (D_CPUENA - enable CPU interrupt)
94 // R/W -------- ----x--- (IMASK - interrupt mask)
95 // R/W -------- -----x-- (NEGA_FLAG - ALU negative)
96 // R/W -------- ------x- (CARRY_FLAG - ALU carry)
97 // R/W -------- -------x (ZERO_FLAG - ALU zero)
98 // F1A102 R/W -------- ------xx D_FLAGS - upper DSP flags
99 // R/W -------- ------x- (D_EXT1ENA - enable external interrupt 1)
100 // R/W -------- -------x (D_EXT1CLR - clear external interrupt 1)
101 // F1A104 W -------- ----xxxx D_MTXC - matrix control register
102 // W -------- ----x--- (MATCOL - column/row major)
103 // W -------- -----xxx (MATRIX3-15 - matrix width)
104 // F1A108 W ----xxxx xxxxxx-- D_MTXA - matrix address register
105 // F1A10C W -------- -----x-x D_END - data organization register
106 // W -------- -----x-- (BIG_INST - big endian instruction fetch)
107 // W -------- -------x (BIG_IO - big endian I/O)
108 // F1A110 R/W xxxxxxxx xxxxxxxx D_PC - DSP program counter
109 // F1A114 R/W xxxxxxxx xx-xxxxx D_CTRL - DSP control/status register
110 // R xxxx---- -------- (VERSION - DSP version code)
111 // R/W ----x--- -------- (BUS_HOG - hog the bus!)
112 // R/W -----x-- -------- (D_EXT0LAT - external interrupt 0 latch)
113 // R/W ------x- -------- (D_TIM2LAT - timer 2 interrupt latch)
114 // R/W -------x -------- (D_TIM1LAT - timer 1 interrupt latch)
115 // R/W -------- x------- (D_I2SLAT - I2S interrupt latch)
116 // R/W -------- -x------ (D_CPULAT - CPU interrupt latch)
117 // R/W -------- ---x---- (SINGLE_GO - single step one instruction)
118 // R/W -------- ----x--- (SINGLE_STEP - single step mode)
119 // R/W -------- -----x-- (FORCEINT0 - cause interrupt 0 on GPU)
120 // R/W -------- ------x- (CPUINT - send GPU interrupt to CPU)
121 // R/W -------- -------x (DSPGO - enable DSP execution)
122 // F1A116 R/W -------- -------x D_CTRL - upper DSP control/status register
123 // R/W -------- -------x (D_EXT1LAT - external interrupt 1 latch)
124 // F1A118-F1A11B W xxxxxxxx xxxxxxxx D_MOD - modulo instruction mask
125 // F1A11C-F1A11F R xxxxxxxx xxxxxxxx D_REMAIN - divide unit remainder
126 // F1A11C W -------- -------x D_DIVCTRL - divide unit control
127 // W -------- -------x (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide)
128 // F1A120-F1A123 R xxxxxxxx xxxxxxxx D_MACHI - multiply & accumulate high bits
129 // F1A148 W xxxxxxxx xxxxxxxx R_DAC - right transmit data
130 // F1A14C W xxxxxxxx xxxxxxxx L_DAC - left transmit data
131 // F1A150 W -------- xxxxxxxx SCLK - serial clock frequency
132 // F1A150 R -------- ------xx SSTAT
133 // R -------- ------x- (left - no description)
134 // R -------- -------x (WS - word strobe status)
135 // F1A154 W -------- --xxxx-x SMODE - serial mode
136 // W -------- --x----- (EVERYWORD - interrupt on MSB of every word)
137 // W -------- ---x---- (FALLING - interrupt on falling edge)
138 // W -------- ----x--- (RISING - interrupt of rising edge)
139 // W -------- -----x-- (WSEN - enable word strobes)
140 // W -------- -------x (INTERNAL - enables serial clock)
141 // ------------------------------------------------------------
142 // F1B000-F1CFFF R/W xxxxxxxx xxxxxxxx Local DSP RAM
143 // ------------------------------------------------------------
144 // F1D000 R xxxxxxxx xxxxxxxx ROM_TRI - triangle wave
145 // F1D200 R xxxxxxxx xxxxxxxx ROM_SINE - full sine wave
146 // F1D400 R xxxxxxxx xxxxxxxx ROM_AMSINE - amplitude modulated sine wave
147 // F1D600 R xxxxxxxx xxxxxxxx ROM_12W - sine wave and second order harmonic
148 // F1D800 R xxxxxxxx xxxxxxxx ROM_CHIRP16 - chirp
149 // F1DA00 R xxxxxxxx xxxxxxxx ROM_NTRI - traingle wave with noise
150 // F1DC00 R xxxxxxxx xxxxxxxx ROM_DELTA - spike
151 // F1DE00 R xxxxxxxx xxxxxxxx ROM_NOISE - white noise
152 // ------------------------------------------------------------
153
154 #include "jerry.h"
155
156 #include <string.h> // For memcpy
157 #include "cdrom.h"
158 #include "dac.h"
159 #include "dsp.h"
160 #include "eeprom.h"
161 #include "event.h"
162 #include "jaguar.h"
163 #include "joystick.h"
164 #include "log.h"
165 #include "m68000/m68kinterface.h"
166 #include "memtrack.h"
167 #include "settings.h"
168 #include "tom.h"
169 #include "wavetable.h"
170
171 //Note that 44100 Hz requires samples every 22.675737 usec.
172
173 uint8_t jerry_ram_8[0x10000];
174
175 uint8_t analog_x, analog_y;
176
177 static uint32_t JERRYPIT1Prescaler;
178 static uint32_t JERRYPIT1Divider;
179 static uint32_t JERRYPIT2Prescaler;
180 static uint32_t JERRYPIT2Divider;
181 static int32_t jerry_timer_1_counter;
182 static int32_t jerry_timer_2_counter;
183
184 int32_t JERRYI2SInterruptTimer = -1;
185 uint32_t jerryI2SCycles;
186 uint32_t jerryIntPending;
187
188 static uint16_t jerryInterruptMask = 0;
189 static uint16_t jerryPendingInterrupt = 0;
190
191 // Private function prototypes
192
193 void JERRYResetPIT1(void);
194 void JERRYResetPIT2(void);
195 void JERRYResetI2S(void);
196
197 void JERRYPIT1Callback(void);
198 void JERRYPIT2Callback(void);
199 void JERRYI2SCallback(void);
200
201
JERRYResetI2S(void)202 void JERRYResetI2S(void)
203 {
204 *sclk = 8;
205 JERRYI2SInterruptTimer = -1;
206 }
207
208
JERRYResetPIT1(void)209 void JERRYResetPIT1(void)
210 {
211 RemoveCallback(JERRYPIT1Callback);
212
213 if (JERRYPIT1Prescaler | JERRYPIT1Divider)
214 {
215 double usecs = (float)(JERRYPIT1Prescaler + 1) * (float)(JERRYPIT1Divider + 1) * RISC_CYCLE_IN_USEC;
216 SetCallbackTime(JERRYPIT1Callback, usecs, EVENT_JERRY);
217 }
218 }
219
220
JERRYResetPIT2(void)221 void JERRYResetPIT2(void)
222 {
223 RemoveCallback(JERRYPIT2Callback);
224
225 if (JERRYPIT1Prescaler | JERRYPIT1Divider)
226 {
227 double usecs = (float)(JERRYPIT2Prescaler + 1) * (float)(JERRYPIT2Divider + 1) * RISC_CYCLE_IN_USEC;
228 SetCallbackTime(JERRYPIT2Callback, usecs, EVENT_JERRY);
229 }
230 }
231
232
233 // This is the cause of the regressions in Cybermorph and Missile Command 3D...
234 // Solution: Probably have to check the DSP enable bit before sending these thru.
JERRYPIT1Callback(void)235 void JERRYPIT1Callback(void)
236 {
237 if (TOMIRQEnabled(IRQ_DSP))
238 {
239 if (jerryInterruptMask & IRQ2_TIMER1) // CPU Timer 1 IRQ
240 {
241 // Not sure, but I think we don't generate another IRQ if one's already going...
242 // But this seems to work... :-/
243 jerryPendingInterrupt |= IRQ2_TIMER1;
244 m68k_set_irq(2); // Generate 68K IPL 2
245 }
246 }
247
248 DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE); // This does the 'IRQ enabled' checking...
249 JERRYResetPIT1();
250 }
251
252
JERRYPIT2Callback(void)253 void JERRYPIT2Callback(void)
254 {
255 if (TOMIRQEnabled(IRQ_DSP))
256 {
257 if (jerryInterruptMask & IRQ2_TIMER2) // CPU Timer 2 IRQ
258 {
259 jerryPendingInterrupt |= IRQ2_TIMER2;
260 m68k_set_irq(2); // Generate 68K IPL 2
261 }
262 }
263
264 DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE); // This does the 'IRQ enabled' checking...
265 JERRYResetPIT2();
266 }
267
268
JERRYI2SCallback(void)269 void JERRYI2SCallback(void)
270 {
271 // We don't have to divide the RISC clock rate by this--the reason is a bit
272 // convoluted. Will put explanation here later...
273 // What's needed here is to find the ratio of the frequency to the number of clock cycles
274 // in one second. For example, if the sample rate is 44100, we divide the clock rate by
275 // this: 26590906 / 44100 = 602 cycles.
276 // Which means, every 602 cycles that go by we have to generate an interrupt.
277 jerryI2SCycles = 32 * (2 * (*sclk + 1));
278
279 // If INTERNAL flag is set, then JERRY's SCLK is master
280 if (*smode & SMODE_INTERNAL)
281 {
282 double usecs;
283
284 // This does the 'IRQ enabled' checking...
285 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
286 // double usecs = (float)jerryI2SCycles * RISC_CYCLE_IN_USEC;
287 //this fix is almost enough to fix timings in tripper, but not quite enough...
288 usecs = (float)jerryI2SCycles * (vjs.hardwareTypeNTSC ? RISC_CYCLE_IN_USEC : RISC_CYCLE_PAL_IN_USEC);
289 SetCallbackTime(JERRYI2SCallback, usecs, EVENT_JERRY);
290 }
291 else
292 {
293 // JERRY is slave to external word clock
294
295 //Note that 44100 Hz requires samples every 22.675737 usec.
296 //When JERRY is slave to the word clock, we need to do interrupts either at 44.1K
297 //sample rate or at a 88.2K sample rate (11.332... usec).
298
299 if (ButchIsReadyToSend())//Not sure this is right spot to check...
300 {
301 // return GetWordFromButchSSI(offset, who);
302 SetSSIWordsXmittedFromButch();
303 DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE);
304 }
305
306 SetCallbackTime(JERRYI2SCallback, 22.675737, EVENT_JERRY);
307 }
308 }
309
310
JERRYInit(void)311 void JERRYInit(void)
312 {
313 JoystickInit();
314 MTInit();
315 memcpy(&jerry_ram_8[0xD000], waveTableROM, 0x1000);
316
317 JERRYPIT1Prescaler = 0xFFFF;
318 JERRYPIT2Prescaler = 0xFFFF;
319 JERRYPIT1Divider = 0xFFFF;
320 JERRYPIT2Divider = 0xFFFF;
321 jerryInterruptMask = 0x0000;
322 jerryPendingInterrupt = 0x0000;
323
324 DACInit();
325 }
326
327
JERRYReset(void)328 void JERRYReset(void)
329 {
330 JoystickReset();
331 EepromReset();
332 MTReset();
333 JERRYResetI2S();
334
335 memset(jerry_ram_8, 0x00, 0xD000); // Don't clear out the Wavetable ROM...!
336 JERRYPIT1Prescaler = 0xFFFF;
337 JERRYPIT2Prescaler = 0xFFFF;
338 JERRYPIT1Divider = 0xFFFF;
339 JERRYPIT2Divider = 0xFFFF;
340 jerry_timer_1_counter = 0;
341 jerry_timer_2_counter = 0;
342 jerryInterruptMask = 0x0000;
343 jerryPendingInterrupt = 0x0000;
344
345 DACReset();
346 }
347
348
JERRYDone(void)349 void JERRYDone(void)
350 {
351 WriteLog("JERRY: M68K Interrupt control ($F10020) = %04X\n", GET16(jerry_ram_8, 0x20));
352 JoystickDone();
353 DACDone();
354 EepromDone();
355 MTDone();
356 }
357
358
JERRYIRQEnabled(int irq)359 bool JERRYIRQEnabled(int irq)
360 {
361 // Read the word @ $F10020
362 return jerryInterruptMask & irq;
363 }
364
365
JERRYSetPendingIRQ(int irq)366 void JERRYSetPendingIRQ(int irq)
367 {
368 // This is the shadow of INT (it's a split RO/WO register)
369 jerryPendingInterrupt |= irq;
370 }
371
372
373 //
374 // JERRY byte access (read)
375 //
JERRYReadByte(uint32_t offset,uint32_t who)376 uint8_t JERRYReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/)
377 {
378 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
379 return DSPReadByte(offset, who);
380 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
381 return DSPReadByte(offset, who);
382 // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
383 else if (offset >= 0xF1A148 && offset <= 0xF1A153)
384 return DACReadByte(offset, who);
385 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
386 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
387 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
388 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
389 else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
390 {
391 /* Unhandled timer read (BYTE) */
392 }
393 else if (offset >= 0xF14000 && offset <= 0xF14003)
394 {
395 uint16_t value = JoystickReadWord(offset & 0xFE);
396
397 if (offset & 0x01)
398 value &= 0xFF;
399 else
400 value >>= 8;
401
402 // This is wrong, should only have the lowest bit from $F14001
403 return value | EepromReadByte(offset);
404 }
405 else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
406 return EepromReadByte(offset);
407
408 return jerry_ram_8[offset & 0xFFFF];
409 }
410
411
412 //
413 // JERRY word access (read)
414 //
JERRYReadWord(uint32_t offset,uint32_t who)415 uint16_t JERRYReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/)
416 {
417
418 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
419 return DSPReadWord(offset, who);
420 else if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF)
421 return DSPReadWord(offset, who);
422 // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...)
423 else if (offset >= 0xF1A148 && offset <= 0xF1A153)
424 return DACReadWord(offset, who);
425 // F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler
426 // F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider
427 // F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler
428 // F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider
429 else if ((offset >= 0xF10036) && (offset <= 0xF1003D))
430 {
431 /* Unhandled timer read (WORD) */
432 }
433 else if (offset == 0xF10020)
434 return jerryPendingInterrupt;
435 else if (offset == 0xF14000)
436 return (JoystickReadWord(offset) & 0xFFFE) | EepromReadWord(offset);
437 else if ((offset >= 0xF14002) && (offset < 0xF14003))
438 return JoystickReadWord(offset);
439 else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
440 return EepromReadWord(offset);
441
442 offset &= 0xFFFF; // Prevent crashing...!
443 return ((uint16_t)jerry_ram_8[offset+0] << 8) | jerry_ram_8[offset+1];
444 }
445
446
447 //
448 // JERRY byte access (write)
449 //
JERRYWriteByte(uint32_t offset,uint8_t data,uint32_t who)450 void JERRYWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/)
451 {
452 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
453 {
454 DSPWriteByte(offset, data, who);
455 return;
456 }
457 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
458 {
459 DSPWriteByte(offset, data, who);
460 return;
461 }
462 // SCLK ($F1A150--8 bits wide)
463 //NOTE: This should be taken care of in DAC...
464 // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
465 else if (offset >= 0xF1A148 && offset <= 0xF1A157)
466 {
467 DACWriteByte(offset, data, who);
468 return;
469 }
470 else if (offset >= 0xF10000 && offset <= 0xF10007)
471 {
472 /* Unhandled timer write (BYTE) */
473 return;
474 }
475 // JERRY -> 68K interrupt enables/latches (need to be handled!)
476 else if (offset >= 0xF10020 && offset <= 0xF10021)//WAS:23)
477 {
478 if (offset == 0xF10020)
479 {
480 // Clear pending interrupts...
481 jerryPendingInterrupt &= ~data;
482 }
483 else if (offset == 0xF10021)
484 jerryInterruptMask = data;
485 }
486 else if ((offset >= 0xF14000) && (offset <= 0xF14003))
487 {
488 JoystickWriteWord(offset & 0xFE, (uint16_t)data);
489 EepromWriteByte(offset, data);
490 return;
491 }
492 else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF))
493 {
494 EepromWriteByte(offset, data);
495 return;
496 }
497
498 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
499 if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
500 return;
501
502 jerry_ram_8[offset & 0xFFFF] = data;
503 }
504
505
506 //
507 // JERRY word access (write)
508 //
JERRYWriteWord(uint32_t offset,uint16_t data,uint32_t who)509 void JERRYWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/)
510 {
511 if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20))
512 {
513 DSPWriteWord(offset, data, who);
514 return;
515 }
516 else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000))
517 {
518 DSPWriteWord(offset, data, who);
519 return;
520 }
521 //NOTE: This should be taken care of in DAC...
522 // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...)
523 else if (offset >= 0xF1A148 && offset <= 0xF1A156)
524 {
525 DACWriteWord(offset, data, who);
526 return;
527 }
528 else if (offset >= 0xF10000 && offset <= 0xF10007)
529 {
530 switch(offset & 0x07)
531 {
532 case 0:
533 JERRYPIT1Prescaler = data;
534 JERRYResetPIT1();
535 break;
536 case 2:
537 JERRYPIT1Divider = data;
538 JERRYResetPIT1();
539 break;
540 case 4:
541 JERRYPIT2Prescaler = data;
542 JERRYResetPIT2();
543 break;
544 case 6:
545 JERRYPIT2Divider = data;
546 JERRYResetPIT2();
547 }
548 // Need to handle (unaligned) cases???
549
550 return;
551 }
552 // JERRY -> 68K interrupt enables/latches (need to be handled!)
553 else if (offset >= 0xF10020 && offset <= 0xF10022)
554 {
555 jerryInterruptMask = data & 0xFF;
556 jerryPendingInterrupt &= ~(data >> 8);
557 return;
558 }
559 else if (offset >= 0xF14000 && offset < 0xF14003)
560 {
561 JoystickWriteWord(offset, data);
562 EepromWriteWord(offset, data);
563 return;
564 }
565 else if (offset >= 0xF14000 && offset <= 0xF1A0FF)
566 {
567 EepromWriteWord(offset, data);
568 return;
569 }
570
571 //Need to protect write attempts to Wavetable ROM (F1D000-FFF)
572 if (offset >= 0xF1D000 && offset <= 0xF1DFFF)
573 return;
574
575 jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF;
576 jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF;
577 }
578
579
JERRYGetPIT1Frequency(void)580 int JERRYGetPIT1Frequency(void)
581 {
582 int systemClockFrequency = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL);
583 return systemClockFrequency / ((JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1));
584 }
585
586
JERRYGetPIT2Frequency(void)587 int JERRYGetPIT2Frequency(void)
588 {
589 int systemClockFrequency = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL);
590 return systemClockFrequency / ((JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1));
591 }
592
593