1 /* $OpenBSD: jmb.c,v 1.11 2024/05/24 06:02:58 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #include <sys/param.h>
20 #include <sys/systm.h>
21 #include <sys/device.h>
22
23 #include <dev/pci/pcireg.h>
24 #include <dev/pci/pcivar.h>
25 #include <dev/pci/pcidevs.h>
26
27 /* JMicron registers */
28 #define JM_PCI_CTL0 0x40 /* control register 0 */
29 #define JM_PCI_CTL0_ROM_EN (1<<31) /* External Option ROM */
30 #define JM_PCI_CTL0_IDWR_EN (1<<30) /* Device ID Write */
31 #define JM_PCI_CTL0_MSI64_EN (1<<25) /* 64bit MSI Addr Mode */
32 #define JM_PCI_CTL0_MSI_EN (1<<24) /* MSI Addr Mode */
33 #define JM_PCI_CTL0_IDEDMA_CFG (1<<23) /* PCIIDE DMA Chan Cfg */
34 #define JM_PCI_CTL0_PCIIDE_CS (1<<22) /* PCIIDE channels Swap */
35 #define JM_PCI_CTL0_SATA_PS (1<<21) /* SATA channel M/S swap */
36 #define JM_PCI_CTL0_AHCI_PS (1<<20) /* SATA AHCI ports swap */
37 #define JM_PCI_CTL0_F1_SUBCLASS_M 0xc0000 /* subclass for func 1 */
38 #define JM_PCI_CTL0_F0_SUBCLASS_M 0x30000 /* subclass for func 0 */
39 #define JM_PCI_CTL0_SUBCLASS_IDE 0x0 /* IDE Controller */
40 #define JM_PCI_CTL0_SUBCLASS_RAID 0x1 /* RAID Controller */
41 #define JM_PCI_CTL0_SUBCLASS_AHCI 0x2 /* AHCI Controller */
42 #define JM_PCI_CTL0_SUBCLASS_OTHER 0x3 /* Other Mass Storage */
43 #define JM_PCI_CTL0_F1_SUBCLASS(_m) ((_m)<<18) /* subclass for func 1 */
44 #define JM_PCI_CTL0_F0_SUBCLASS(_m) ((_m)<<16) /* subclass for func 0 */
45 #define JM_PCI_CTL0_SATA1_AHCI (1<<15) /* SATA port 1 AHCI enable */
46 #define JM_PCI_CTL0_SATA1_IDE (1<<14) /* SATA port 1 IDE enable */
47 #define JM_PCI_CTL0_SATA0_AHCI (1<<13) /* SATA port 0 AHCI enable */
48 #define JM_PCI_CTL0_SATA0_IDE (1<<12) /* SATA port 0 PCIIDE enable */
49 #define JM_PCI_CTL0_AHCI_F1 (1<<9) /* AHCI on function 1 */
50 #define JM_PCI_CTL0_AHCI_EN (1<<8) /* ACHI enable */
51 #define JM_PCI_CTL0_PATA0_RST (1<<6) /* PATA port 0 reset */
52 #define JM_PCI_CTL0_PATA0_EN (1<<5) /* PATA port 0 enable */
53 #define JM_PCI_CTL0_PATA0_SEC (1<<4) /* PATA 0 enable on 2nd chan */
54 #define JM_PCI_CTL0_PATA0_40P (1<<3) /* PATA 0 40pin cable */
55 #define JM_PCI_CTL0_PCIIDE_F1 (1<<1) /* PCIIDE on function 1 */
56 #define JM_PCI_CTL0_PATA0_PRI (1<<0) /* PATA 0 enable on 1st chan */
57
58 #define JM_PCI_CTL5 0x80 /* control register 8 */
59 #define JM_PCI_CTL5_PATA1_PRI (1<<24) /* force PATA 1 on chan0 */
60
61 int jmb_match(struct device *, void *, void *);
62 void jmb_attach(struct device *, struct device *, void *);
63 int jmb_print(void *, const char *);
64
65 struct jmb_softc {
66 struct device sc_dev;
67 };
68
69 const struct cfattach jmb_ca = {
70 sizeof(struct jmb_softc),
71 jmb_match,
72 jmb_attach,
73 config_detach_children
74 };
75
76 struct cfdriver jmb_cd = {
77 NULL, "jmb", DV_DULL
78 };
79
80 static const struct pci_matchid jmb_devices[] = {
81 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB360 },
82 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB361 },
83 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB362 },
84 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB363 },
85 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB365 },
86 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB366 },
87 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB368 }
88 };
89
90 int
jmb_match(struct device * parent,void * match,void * aux)91 jmb_match(struct device *parent, void *match, void *aux)
92 {
93 struct pci_attach_args *pa = aux;
94
95 return (pci_matchbyid(pa, jmb_devices,
96 sizeof(jmb_devices) / sizeof(jmb_devices[0])) * 3);
97 }
98
99 void
jmb_attach(struct device * parent,struct device * self,void * aux)100 jmb_attach(struct device *parent, struct device *self, void *aux)
101 {
102 struct pci_attach_args *pa = aux, jpa;
103 u_int32_t ctl0, ctl5;
104 int sata = 0, pata = 0;
105
106 ctl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0);
107 ctl5 = pci_conf_read(pa->pa_pc, pa->pa_tag, JM_PCI_CTL5);
108
109 /* configure sata bits if it is on this function */
110 if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_AHCI_F1) ? 1 : 0)) {
111 ctl0 &= ~(JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_IDE |
112 JM_PCI_CTL0_SATA0_AHCI | JM_PCI_CTL0_SATA1_IDE |
113 JM_PCI_CTL0_SATA1_AHCI);
114
115 switch (PCI_PRODUCT(pa->pa_id)) {
116 case PCI_PRODUCT_JMICRON_JMB360:
117 case PCI_PRODUCT_JMICRON_JMB361:
118 case PCI_PRODUCT_JMICRON_JMB362:
119 case PCI_PRODUCT_JMICRON_JMB363:
120 case PCI_PRODUCT_JMICRON_JMB365:
121 case PCI_PRODUCT_JMICRON_JMB366:
122 /* enable AHCI */
123 ctl0 |= JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_AHCI |
124 JM_PCI_CTL0_SATA1_AHCI;
125 sata = 1;
126 break;
127 }
128 }
129
130 /* configure pata bits if it is on this function */
131 if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_PCIIDE_F1) ? 1 : 0)) {
132 ctl0 &= ~(JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG);
133 ctl5 &= ~JM_PCI_CTL5_PATA1_PRI;
134
135 switch (PCI_PRODUCT(pa->pa_id)) {
136 case PCI_PRODUCT_JMICRON_JMB366:
137 case PCI_PRODUCT_JMICRON_JMB365:
138 /* wire the second PATA port in the right place */
139 ctl5 |= JM_PCI_CTL5_PATA1_PRI;
140 /* FALLTHROUGH */
141 case PCI_PRODUCT_JMICRON_JMB363:
142 case PCI_PRODUCT_JMICRON_JMB361:
143 case PCI_PRODUCT_JMICRON_JMB368:
144 ctl0 |= JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG;
145 pata = 1;
146 break;
147 }
148 }
149
150 pci_conf_write(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0, ctl0);
151 pci_conf_write(pa->pa_pc, pa->pa_tag, JM_PCI_CTL5, ctl5);
152
153 printf("\n");
154
155 jpa = *pa;
156
157 if (sata) {
158 /* tweak the class to look like ahci, then try to attach it */
159 jpa.pa_class = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) |
160 (PCI_SUBCLASS_MASS_STORAGE_SATA << PCI_SUBCLASS_SHIFT) |
161 (0x01 << PCI_INTERFACE_SHIFT); /* AHCI_PCI_INTERFACE */
162 config_found(self, &jpa, jmb_print);
163 }
164
165 if (pata) {
166 /* set things up for pciide */
167 jpa.pa_class = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) |
168 (PCI_SUBCLASS_MASS_STORAGE_IDE << PCI_SUBCLASS_SHIFT) |
169 (0x85 << PCI_INTERFACE_SHIFT);
170 config_found(self, &jpa, jmb_print);
171 }
172 }
173
174 int
jmb_print(void * aux,const char * pnp)175 jmb_print(void *aux, const char *pnp)
176 {
177 struct pci_attach_args *pa = aux;
178 char devinfo[256];
179
180 if (pnp != NULL) {
181 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo,
182 sizeof(devinfo));
183 printf("%s at %s", devinfo, pnp);
184 }
185
186 return (UNCONF);
187 }
188