1 /* 2 * JTAG_defs.h 3 * 4 * <FILEBRIEF> 5 * 6 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the 19 * distribution. 20 * 21 * Neither the name of Texas Instruments Incorporated nor the names of 22 * its contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /*========================================================================*\ 39 | | 40 | MSP430.h | 41 | | 42 | This file contains the JTAG instruction and control bit definitions for | 43 | the MSP430 | 44 |--------------------------------------------------------------------------| 45 | Project: MSP430 JTAG interfcae | 46 | Developed using: MS Visual C++ 5.0 | 47 |--------------------------------------------------------------------------| 48 | Version: 1.2.0 | 49 | Initial Version: 20 / 07 / 02 | 50 | Last Change: 01 / 22 / 04 | 51 |--------------------------------------------------------------------------| 52 | Version history: | 53 | Version: 1.1.5 | 54 | 12/02/2003 UPSF Added mirrowed JTAG-instr. table for uC execution | 55 | 12/02/2003 UPSF Changed JMP_$ to JMP_D | 56 | 22/02/2003 UPSF Renamed IEx, I2C and ADC10 Register definitions | 57 | Version: 1.1.5.8 | 58 | 16.03.2004 UPSF Changed Register Names to xxx_Address | 59 | Version: 1.2.0.1 | 60 | 19.08.2004 UPSF Added FCTL1_ADDRESS definition | 61 | 01.10.2004 UPSF Added FCTLx_ADDRESS, LOCKA_BIT definition | 62 | Version: 2.1.4.13 | 63 | 19.08.2004 UPSF Added MOVA_IMM_PC definition | 64 | Version: 2.1.4.20 | 65 | 02.09.2005 WLUT Added IR_EMEX_DATA_EXCHANGE32 instruction definition | 66 | Expandedn BPMASK_DONTCARE definition to 32bit | 67 | Version: 2.3.4.0 | 68 | 24.04.2008 WLUT Added definitions for 5xx support | 69 | | 70 |--------------------------------------------------------------------------| 71 | Designed 2002 by Texas Instruments | 72 \*========================================================================*/ 73 74 /*------------------------------------------------------------------------*\ 75 | Remarks: | 76 | | 77 \*------------------------------------------------------------------------*/ 78 79 #ifndef _JTAG_defs_H_ 80 #define _JTAG_defs_H_ 81 82 // #defines. ------------------------------------------------------------------ 83 #define FUSECHECK_DELAY 50 84 85 #define JTAGVERSION 0x89 86 #define JTAGVERSION8D 0x8D 87 #define JTAGVERSION91 0x91 88 #define JTAGVERSION95 0x95 89 #define JTAGVERSION98 0x98 90 #define JTAGVERSION99 0x99 91 92 #define F_BYTE 8 93 #define F_WORD 16 94 #define F_ADDR 20 95 #define F_LONG 32 96 #define F_LONG_LONG 64 97 98 #define SBW1200KHz 0x800A 99 #define SBW600KHz 0x600A 100 #define SBW400KHz 0x400A 101 #define SBW200KHz 0x200A 102 #define SBW100KHz 0x100A 103 104 #define JTAG15MHz 1 105 #define JTAG8MHz 2 106 #define JTAG4MHz 4 107 #define JTAG2MHz 8 108 #define JTAG1MHz 16 109 #define JTAG500KHz 32 110 #define JTAG250KHz 64 111 #define JTAG750KHz 128 112 113 #define RSTLOW_SBW 0 114 #define RSTLOW_JTAG 1 115 #define RSTHIGH_SBW 2 116 #define RSTHIGH_JTAG 3 117 118 #define SAFE_PC_ADDRESS (0x00000004ul) 119 120 /*--------------------------start if uController_uif--------------------------*/ 121 122 // Instructions to access the Emex registers 123 #define IR_EMEX_DATA_EXCHANGE 0x90 // 09 124 #define IR_EMEX_READ_TRIGGER 0x50 // 0A 125 #define IR_EMEX_READ_CONTROL 0xD0 // 0B 126 #define IR_EMEX_WRITE_CONTROL 0x30 // 0C 127 #define IR_EMEX_DATA_EXCHANGE32 0xB0 128 129 #define IR_TEST_REG 0x54 // 2A //Select the 32-bit JTAG test register 130 #define IR_TEST_3V_REG 0xF4 // 16 bit 3 volt test reg 131 // Instructions for the address register 132 #define IR_ADDR_HIGH_BYTE 0x81 // 81 133 #define IR_ADDR_LOW_BYTE 0x41 // 82 134 #define IR_ADDR_16BIT 0xC1 // 83 135 #define IR_ADDR_CAPTURE 0x21 // 84 136 #define IR_DATA_TO_ADDR 0xA1 // 85 137 #define IR_CAPTURE_CPU_REG 0x61 // 86 138 #define IR_DEVICE_ID 0xE1 // 87 139 140 // Instructions for the data register 141 #define IR_DATA_16BIT 0x82 // 41 142 #define IR_DATA_CAPTURE 0x42 // 42 143 #define IR_DATA_QUICK 0xC2 // 43 144 #define IR_DATA_PSA 0x22 // 44 145 #define IR_DATA_16BIT_OPT 0xA2 // 45 146 #define IR_SHIFT_OUT_PSA 0x62 // 46 147 #define IR_DTA 0xE2 // 47 148 149 // Instructions for the breakpoint logic 150 #define IR_BP_CNTL_16BIT 0x90 // 09 151 #define IR_BP_CNTL_CAPTURE 0x50 // 0A 152 #define IR_BP1_16BIT 0xD0 // 0B 153 #define IR_BP1_CAPTURE 0x30 // 0C 154 #define IR_BP2_16BIT 0xB0 // 0D 155 #define IR_BP2_CAPTURE 0x70 // 0E 156 157 // Instructions for the FLASH register 158 #define IR_FLASH_16BIT_UPDATE 0x98 // 19 159 #define IR_FLASH_CAPTURE 0x58 // 1A 160 #define IR_FLASH_16BIT_IN 0xD8 // 1B 161 #define IR_FLASH_UPDATE 0x38 // 1C 162 // Bits of the FLASH register 163 #define FLASH_SESEL1 0x0080 164 #define FLASH_TMR 0x0800 165 166 // Instructions for the control signal register 167 #define IR_CNTRL_SIG_HIGH_BYTE 0x88 // 11 168 #define IR_CNTRL_SIG_LOW_BYTE 0x48 // 12 169 #define IR_CNTRL_SIG_16BIT 0xC8 // 13 170 #define IR_CNTRL_SIG_CAPTURE 0x28 // 14 171 #define IR_CNTRL_SIG_RELEASE 0xA8 // 15 172 #define IR_COREIP_ID 0xE8 // 17 173 #define IR_JSTATE_ID 0x46 // 62 174 175 // Bits of the control signal register 176 #define CNTRL_SIG_READ 0x0001 177 #define CNTRL_SIG_CPU_HALT 0x0002 178 #define CNTRL_SIG_INTR_REQ 0x0004 179 #define CNTRL_SIG_HALT_JTAG 0x0008 180 #define CNTRL_SIG_BYTE 0x0010 181 #define CNTRL_SIG_CPU_OFF 0x0020 182 #define CNTRL_SIG_MCLKON 0x0040 183 #define CNTRL_SIG_INSTRLOAD 0x0080 184 #define CNTRL_SIG_TMODE 0x0100 185 #define CNTRL_SIG_TCE 0x0200 186 #define CNTRL_SIG_TCE1 0x0400 187 #define CNTRL_SIG_PUC 0x0800 188 #define CNTRL_SIG_CPU 0x1000 189 #define CNTRL_SIG_TAGFUNCSAT 0x2000 190 #define CNTRL_SIG_SWITCH 0x4000 191 #define CNTRL_SIG_STOP_SEL 0x8000 192 #define CNTRL_SIG_CPUSUSP (0x0001<<8) 193 #define CNTRL_SIG_CPUOFF (0x0001<<5) 194 #define CNTRL_SIG_INTREQ (0x0001<<2) 195 #define CNTRL_SIG_HALT (0x0001<<1) 196 197 // Instructions for the fuse control 198 #define IR_CNTRL 0x84 // 21 199 #define IR_PREPARE_BLOW 0x44 // 22 200 #define IR_EX_BLOW 0x24 // 24 201 202 // Instructions for the configuration fuse register 203 #define IR_CONFIG_FUSES 0x94 // 29 204 205 // Instructions for the control of the Embedded Signal Processing Cell 206 #define IR_DUAL_8BIT 0x8C // 31 207 #define IR_DUAL_CAPTURE 0x4C // 32 208 #define IR_SELECT_MAIN 0xCC // 33 209 #define IR_SELECT_ESP 0x2C // 34 210 211 // Bypass instruction 212 #define IR_BYPASS 0xFF 213 214 // Accept Key Instruction for SPMA devices 215 #define IR_ACCEPT_KEY 0x9A // 59 216 217 #define IR_JMB_EXCHANGE 0x86 // 61 218 #define IR_JMB_WRITE_32BIT_MODE 0x11 219 #define IR_TDO_EVENT 0x26 // 64 220 #define IR_TDO_EVENT_CTL 0xA6 // 65 221 222 #define EEMEV 0x0100 223 // Registers in the EMEX logic 224 #define MX_WRITE 0 // Write offset 225 #define MX_READ 1 // Read offset 226 227 // Breakpoint block 228 // EMEX address = BP number * Block size + Register offset + R/W offset 229 // Note: In Volker's new EEM documentation, this block is called the Memory Bus Trigger 230 #define MX_BLKSIZE 8 // Block size 231 #define MX_BP 0x0000 // Breakpoint value offset 232 #define MX_CNTRL 0x0002 // Control offset 233 #define MX_MASK 0x0004 // Mask offset 234 #define MX_COMB 0x0006 // Combination offset 235 236 // Control block 237 #define MX_EEMVER 0x0087 238 #define MX_CPUSTOP 0x0080 239 #define MX_GENCNTRL 0x0082 240 #define MX_GCLKCTRL 0x0088 241 #define MX_MCLKCNTL0 0x008A 242 #define MX_TRIGFLAG 0x008E 243 244 // Settings of the Breakpoint block Control register 245 #define BPCNTRL_MAB 0x0000 246 #define BPCNTRL_MDB 0x0001 247 #define BPCNTRL_RW_DISABLE 0x0000 248 #define BPCNTRL_RW_ENABLE 0x0020 249 #define BPCNTRL_EQ 0x0000 250 #define BPCNTRL_GE 0x0008 251 #define BPCNTRL_LE 0x0010 252 #define BPCNTRL_FREE 0x0018 253 #define BPCNTRL_DMA_DISABLE 0x0000 254 #define BPCNTRL_DMA_ENABLE 0x0040 255 // With BPCNTRL_DMA_DISABLE and BPCNTRL_RW_DISABLE 256 #define BPCNTRL_IF 0x0000 257 #define BPCNTRL_IFHOLD 0x0002 258 #define BPCNTRL_NIF 0x0004 259 #define BPCNTRL_BOTH 0x0006 260 // With BPCNTRL_DMA_DISABLE and BPCNTRL_RW_ENABLE 261 #define BPCNTRL_NIF_READ 0x0000 262 #define BPCNTRL_NIF_WRITE 0x0002 263 #define BPCNTRL_READ 0x0004 264 #define BPCNTRL_WRITE 0x0006 265 // Special consideration for future data breakpoints and the F12x2: 266 // - Must handle DMA access (Bit 6 of control register) 267 // - Read/Write Enable (Bit 5 of control register) is not implemented in the F12x2 268 // With BPCNTRL_DMA_ENABLE and BPCNTRL_RW_DISABLE 269 #define BPCNTRL_NIF_NDMA 0x0000 270 #define BPCNTRL_DMA 0x0002 271 #define BPCNTRL_NDMA 0x0004 272 #define BPCNTRL_WRITE_NDMA 0x0006 273 // With BPCNTRL_DMA_ENABLE and BPCNTRL_RW_ENABLE 274 #define BPCNTRL_NIF_READ_NDMA 0x0000 275 #define BPCNTRL_READ_NDMA 0x0002 276 #define BPCNTRL_READ_DMA 0x0004 277 #define BPCNTRL_WRITE_DMA 0x0006 278 279 // Settings of the Breakpoint block Mask register 280 #define BPMASK_WORD 0x0000 281 #define BPMASK_HIGHBYTE 0x00FF 282 #define BPMASK_LOWBYTE 0xFF00 283 #define BPMASK_DONTCARE 0xFFFFFFFF 284 285 // MSP430_Debug.h contains definitions for the following: 286 // Bits of the Control block General Control register 287 // Bits of the Control block General Clock Control register (F41x) 288 // Bits of the Control block General Clock Control register (F43x/F44x) 289 290 // Bits of the device Status register (R2) 291 #define STATUS_REG_C 0x0001 292 #define STATUS_REG_Z 0x0002 293 #define STATUS_REG_N 0x0004 294 #define STATUS_REG_GIE 0x0008 295 #define STATUS_REG_CPUOFF 0x0010 296 #define STATUS_REG_OSCOFF 0x0020 297 #define STATUS_REG_SCG0 0x0040 298 #define STATUS_REG_SCG1 0x0080 299 #define STATUS_REG_V 0x0100 300 301 #define WDTCTL_ADDRESS 0x120 // Watchdog Timer control register address for 1xx/2xx/4xx family 302 #define WDTPW_DEF 0x5a // Watchdog Timer password. 303 #define WDTHOLD_DEF 0x80 // Watchdog Timer hold. 304 #define WDTSSEL_ACLK 0x03 // Watchdog Timer Clock Source 305 #define SYSBSLC_ADDRESS 0x182 // SYS Module Bootstrap Loader control register address 306 #ifndef SYSBSLPE 307 #define SYSBSLPE 0x8000 // SYS - BSL Memory protection enalbed 308 #endif 309 310 #define FLASHPW_DEF 0xa5 // Flash password. 311 312 // MSP430 Instructions. 313 #define JMP_OPCODE 0x3C00 // JMP OPCODE 314 #define JMP_D 0x3fff // JMP $ 315 #define JMP_D_2 0x3ffe // JMP $-2 316 #define JMP_D_4 0x3ffd // JMP $-4 317 #define BIS_B_IMM_1 0xd3d2 // BIS.B #1, 318 #define BIC_B_IMM_1 0xc3d2 // BIC.B #1, 319 #define MOV_IMM_PC 0x4030 // MOV #<val>,PC 320 #define MOVA_IMM_PC 0x0080 // MOVA #<val>,PC 321 #define MOVA_IMM_SP 0x0180 // MOVA #<val>,SP 322 #define MOVA_R14_ABS 0x0E60 // MOVA R14,&abs 323 #define MOVA_R15_ABS 0x0F60 // MOVA R15,&abs 324 325 // MSP430 Address. 326 #define IE1_ADDRESS 0x0000 327 #define IE2_ADDRESS 0x0001 328 329 #define ADC10DTC0_ADDRESS 0x0048 330 #define ADC10CTL0_ADDRESS 0x01b0 331 #define ADC10CTL1_ADDRESS 0x01b2 332 333 #define I2CCTL_ADDRESS 0x0070 334 #define I2CTCTL_ADDRESS 0x0071 335 #define I2CDR_ADDRESS 0x0076 336 337 #define FCTL1_ADDRESS 0x0128 338 #define FCTL2_ADDRESS 0x012A 339 #define FCTL3_ADDRESS 0x012C // FCTL3 register address for 1xx/2xx/4xx families 340 #define LOCKA_BIT 0x0040 341 342 #define BYTE_REG_START_ADDR 0x0000 343 #define WORD_REG_START_ADDR 0x0100 344 #define LAST_PERIPHERAL_ADDR 0x01ff 345 //#define DATA_START_ADDR 0x0200 346 //#define DATA_END_ADDR 0 x09ff 347 // ROM address (for use in work-around to RAM-corrupted-during-JTAG-access bug). 348 #define ROM_ADDR 0x0c04 349 #define FLASH_START_ADDR 0x1000 350 //#define FLASH_END_ADDR 0xffff 351 352 #define MAIN_SEGMENT_SIZE 512 // Segments are normally 512 bytes in size. 353 #define FIRST_60K_SEGMENT_SIZE 256 // However, the first segment of 60K devices is 256 bytes in size. 354 //#define INFO_SEGMENT_SIZE 128 // And Information segments are 128 bytes in size. 355 356 //JMB DR Requests 357 #define DR_JMB_PASSWORD_EXCHANGE_REQUEST 0x1E1E 358 #define MAGIC_PATTERN 0xA55A 359 360 361 //******************************************************************************************************** 362 // MSP432 363 //******************************************************************************************************** 364 // General purpose definitions 365 #define READ 0x1 366 #define WRITE 0x0 367 #define MAX_RETRY 40 368 #define ACK 0x2 369 #define SWD_ACK 0x1 370 371 #define DAPABORT 0x01 372 #define STKCMPCLR 0x02 373 #define STKERRCLR 0x04 374 #define WDERRCLR 0x08 375 #define ORUNERRCLR 0x10 376 377 // JTAG Instruction Register definitions 378 #define IR4_ABORT 0x8 // Used to force an AP abort 379 #define IR4_DPACC 0xA // DP IR dpacc 380 #define IR4_APACC 0xB // AP IR apacc 381 #define IR4_IDCODE 0xE // JTAG-DP TAP identification 382 #define IR4_BYPASS 0xF // Bypasses the device, by providing a direct path between DBGTDI and DBGTDO. 383 384 // Debug Port register addresses 385 #define DP_DPIDR 0x00 // DP architecture register 386 #define DP_CTRL_STAT 0x04 // Control & Status 387 #define DP_SELECT 0x08 // Select Register (JTAG R/W & SW W) 388 #define DP_RDBUFF 0x0C // Read Buffer (Read Only) 389 390 // CTRL_STAT register bits 391 #define DP_CTRL_STAT_CSYSPWRUPACK 0x80000000 392 #define DP_CTRL_STAT_CSYSPWRUPREQ 0x40000000 393 #define DP_CTRL_STAT_CDBGPWRUPACK 0x20000000 394 #define DP_CTRL_STAT_CDBGPWRUPREQ 0x10000000 395 #define DP_CTRL_STAT_CDBGRSTACK 0x08000000 396 #define DP_CTRL_STAT_CDBGRSTREQ 0x04000000 397 #define DP_CTRL_STAT_WDATAERR 0x00000080 398 #define DP_CTRL_STAT_STICKYERR 0x00000020 399 #define DP_CTRL_STAT_STICKYCMP 0x00000010 400 #define DP_CTRL_STAT_STICKYORUN 0x00000002 401 402 // Access Port register addresses 403 #define AP_CSW 0x00 // Control/Status word 404 #define AP_TAR 0x04 // Transfer Address Register 405 #define AP_DRW 0x0C // Data Read/Write Register 406 #define AP_BD0 0x10 // Banked data 0 407 #define AP_BD1 0x14 // Banked data 1 408 #define AP_BD2 0x18 // Banked data 2 409 #define AP_BD3 0x1C // Banked data 3 410 #define AP_CFG 0xF4 // Configuration register 411 #define AP_BASE 0xF8 // Debug Base Address register 412 #define AP_IDR 0xFC // Indentification register 413 414 // CSW bits 415 #define AP_CSW_SIZE_MASK 0x0000000F 416 #define AP_CSW_SIZE_8BIT 0x00000000 // Byte 8-bit transfer mode 417 #define AP_CSW_SIZE_16BIT 0x00000001 // Halfword 16-bit transfer mode 418 #define AP_CSW_SIZE_32BIT 0x00000002 // Word 32-bit transfer mode 419 420 #define AP_CSW_ADDRINC_MASK 0x00000030 421 #define AP_CSW_ADDRINC_OFF 0x00000000 // Auto-increment off 422 #define AP_CSW_ADDRINC_SINGLE 0x00000010 // Increment single 423 #define AP_CSW_ADDRINC_PACKED 0x00000020 // Increment packed 424 425 #define AP_CSW_MODE_MASK 0x00000F00 426 #define AP_CSW_MODE_BASIC 0x00000000 // Basic mode 427 #define AP_CSW_MODE_BARRIER 0x00000001 // Barrier mode 428 429 // SCS Register offsets 430 #define AIRCR (0xe000e000 + 0x00000D0C) // Application Interrupt and Reset Control Register 431 #define DFSR (0xe000e000 + 0x00000D30) // Debug Fault Status Register 432 #define DHCSR (0xe000e000 + 0x00000DF0) // Debug Halting Control and Status Register 433 #define DCRSR (0xe000e000 + 0x00000DF4) // Debug Core Register Selector Register 434 #define DCRDR (0xe000e000 + 0x00000DF8) // Debug Core Register Data Register 435 #define DEMCR (0xe000e000 + 0x00000DFC) // Debug Exception and Monitor Control Register 436 #define SCB_SCR (0xe000e000 + +0x00000D00 + 0x10) // System Control Register 437 438 #define SCB_SCR_SLEEPONEXIT_Msk 0x00000002 439 440 //DEMCR regs 441 #define xPSR_REG 0x10 442 #define MSP_SP 0x11 443 #define PSP_SP 0x12 444 #define spec_REG 0x14 445 446 // AIRCR bits 447 #define VECTKEY 0x05FA0000 // Vector Key. 0x05FA must be written anytime this register 448 // is written, otherwise the write is ignored (no bits are 449 // changed in the register). 450 #define VECTKEYSTAT 0xFFFF0000 // Reads as 0xFA05. 451 #define SYSRESETREQ 0x00000004 // Writing this bit 1 will cause a signal to be asserted to the external system to indicate a reset is requested. 452 #define VECTCLRACTIVE 0x00000002 // Clears all active state information for fixed and configurable exceptions. This bit self-clears. 453 #define VECTRESET 0x00000001 // Local system reset 454 455 // DFSR bits 456 #define EXTERNAL 0x00000010 // An asynchronous exception generated due to the assertion of EDBGRQ. 457 #define VCATCH 0x00000008 // Vector catch triggered. Corresponding FSR will contain the primary cause of the exception. 458 #define DWTTRAP 0x00000004 // Data Watchpoint and Trace trap. Indicates that the core halted due to at least one DWT trap event. 459 #define BKPT 0x00000002 // BKPT instruction executed or breakpoint match in FPB. 460 #define HALTED 0x00000001 // Halt request, including step debug command. Stopped on next instruction. 461 462 // DHCSR bits 463 #define DBGKEY 0xA05F0000 // Debug Key. The value 0xA05F must be written to enable write 464 // accesses to bits [15:0], otherwise the write access will be ignored. 465 #define S_RESET_ST 0x02000000 // Core reset since the last time this bit was read. This is a sticky bit, which clears on read. 466 #define S_RETIRE_ST 0x01000000 // Instruction has completed (retired) since last read. This is a sticky bit, which clears on read. 467 // This bit can be used to determine if the core is stalled on a load/store or fetch. 468 #define S_LOCKUP 0x00080000 // Core is locked up due to an unrecoverable exception. 469 #define S_SLEEP 0x00040000 // Core is sleeping. Must set the C_HALT bit to gain control, or wait for an interrupt 470 // (WFI instruction response) to wake-up the system. 471 #define S_HALT 0x00020000 // Core is in Debug state. 472 #define S_REGRDY 0x00010000 // A handshake flag. The bit is cleared to �0� on a write to the 473 // Debug Core Register Selector Register and is set to �1� when 474 // the transfer to/from the Debug Core Register Data Register is complete. 475 #define C_SNAPSTALL 0x00000020 // If the core is stalled on a load/store operation (see S_RETIRE_ST), setting this bit will break 476 // the stall and force the instruction to complete. This bit can only be set if C_DEBUGEN and C_HALT are set, 477 // and S_RETIRE_ST is clear. The bus state is UNPREDICTABLE when C_SNAPSTALL is set. 478 #define C_MASKINTS 0x00000008 // Mask PendSV, SysTick and external configurable interrupts when debug is enabled. The bit does not affect NMI. When 479 // C_DEBUGEN==0, this bit is UNKNOWN. 480 #define C_STEP 0x00000004 // Step the core. 481 #define C_HALT 0x00000002 // Halt the core. 482 #define C_DEBUGEN 0x00000001 // Enable halting debug. 483 484 // DCRSR bits 485 #define REG_WnR 0x00010000 // Write = 1, Read = 0 486 487 // DEMCR bits 488 #define TRCENA 0x01000000 // Global enable for all features configured and controlled by the DWT and ITM blocks. 489 #define MON_REQ 0x00080000 // A DebugMonitor semaphore bit. 490 #define MON_STEP 0x00040000 // When MON_EN is set, this bit is used to step the core. 491 #define MON_PEND 0x00020000 // Pend the DebugMonitor exception to activate when priority allows. 492 #define MON_EN 0x00010000 // Enable the DebugMonitor exception. 493 #define VC_HARDERR 0x00000400 // Debug trap on a HardFault exception. 494 #define VC_INTERR 0x00000200 // Debug trap on a fault occurring during an exception entry or return sequence. 495 #define VC_BUSERR 0x00000100 // Debug trap on a BusFault exception. 496 #define VC_STATERR 0x00000080 // Debug trap on a UsageFault exception due to a state information error (for example an UNDEFINED instruction). 497 #define VC_CHKERR 0x00000040 // Debug trap on a UsageFault exception due to a checking error (for example an alignment check error). 498 #define VC_NOCPERR 0x00000020 // Debug trap on a UsageFault access to a Coprocessor. 499 #define VC_MMERR 0x00000010 // Debug trap on a MemManage exception. 500 #define VC_CORERESET 0x00000001 // Reset Vector Catch. Halt a running system when a Local Reset occurs. 501 502 // FPB definitions 503 #define FP_CTRL (armConfigSettings.fpbBase + 0x00000000) // FlashPatch control 504 #define FP_REMAP (armConfigSettings.fpbBase + 0x00000004) // FlashPatch remapping address 505 #define FP_COMP(i) (armConfigSettings.fpbBase + 0x00000008 + i * 4) // FlashPatch comparator (i) control 506 507 // FP_CTRL bits 508 #define KEY 0x00000002 509 #define ENABLE 0x00000001 510 511 // JTAG Instruction Register definitions 512 #define ABORT (0x8) // Used to force an AP abort 513 #define DPACC (0xA) // DP IR dpacc 514 #define APACC (0xB) // AP IR apacc 515 #define IDCODE (0xE) // JTAG-DP TAP identification 516 #define BYPASS (0xF) // Bypasses the device, by providing a direct path between DBGTDI and DBGTDO. 517 518 // DP_SELECT Register bits 519 #define DP_SELECT_APBANKSEL_MASK (0x000000F0) // APBANKSEL Mask 520 #define DP_SELECT_APSEL_MASK (0xFF000000) // APBANKSEL Mask 521 522 // SWD register access 523 #define SWD_AP (1) 524 #define SWD_DP (0) 525 526 // SWD register access 527 #define SWD_AP (1) 528 #define SWD_DP (0) 529 530 #endif /* _JTAG_defs_H_ */ 531