xref: /netbsd/sys/arch/arm/include/arm32/pmap.h (revision 68e04e53)
1 /*	$NetBSD: pmap.h,v 1.175 2023/04/24 16:32:54 martin Exp $	*/
2 
3 /*
4  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Copyright (c) 1994,1995 Mark Brinicombe.
40  * All rights reserved.
41  *
42  * Redistribution and use in source and binary forms, with or without
43  * modification, are permitted provided that the following conditions
44  * are met:
45  * 1. Redistributions of source code must retain the above copyright
46  *    notice, this list of conditions and the following disclaimer.
47  * 2. Redistributions in binary form must reproduce the above copyright
48  *    notice, this list of conditions and the following disclaimer in the
49  *    documentation and/or other materials provided with the distribution.
50  * 3. All advertising materials mentioning features or use of this software
51  *    must display the following acknowledgement:
52  *	This product includes software developed by Mark Brinicombe
53  * 4. The name of the author may not be used to endorse or promote products
54  *    derived from this software without specific prior written permission.
55  *
56  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
57  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
58  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
60  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
61  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
63  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
64  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
65  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66  */
67 
68 #ifndef	_ARM32_PMAP_H_
69 #define	_ARM32_PMAP_H_
70 
71 #ifdef _KERNEL
72 
73 #include <arm/cpuconf.h>
74 #include <arm/arm32/pte.h>
75 #ifndef _LOCORE
76 #if defined(_KERNEL_OPT)
77 #include "opt_arm32_pmap.h"
78 #include "opt_multiprocessor.h"
79 #endif
80 #include <arm/cpufunc.h>
81 #include <arm/locore.h>
82 
83 #include <uvm/uvm_object.h>
84 
85 #include <uvm/pmap/pmap_devmap.h>
86 #include <uvm/pmap/pmap_pvt.h>
87 #endif
88 
89 #ifdef ARM_MMU_EXTENDED
90 #define	PMAP_HWPAGEWALKER		1
91 #define	PMAP_TLB_MAX			1
92 #if PMAP_TLB_MAX > 1
93 #define	PMAP_TLB_NEED_SHOOTDOWN		1
94 #endif
95 #define	PMAP_TLB_FLUSH_ASID_ON_RESET	arm_has_tlbiasid_p
96 #define	PMAP_TLB_NUM_PIDS		256
97 #define	cpu_set_tlb_info(ci, ti)        ((void)((ci)->ci_tlb_info = (ti)))
98 #if PMAP_TLB_MAX > 1
99 #define	cpu_tlb_info(ci)		((ci)->ci_tlb_info)
100 #else
101 #define	cpu_tlb_info(ci)		(&pmap_tlb0_info)
102 #endif
103 #define	pmap_md_tlb_asid_max()		(PMAP_TLB_NUM_PIDS - 1)
104 #include <uvm/pmap/tlb.h>
105 #include <uvm/pmap/pmap_tlb.h>
106 
107 /*
108  * If we have an EXTENDED MMU and the address space is split evenly between
109  * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
110  * user and kernel address spaces.
111  */
112 #if (KERNEL_BASE & 0x80000000) == 0
113 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000
114 #endif
115 #endif  /* ARM_MMU_EXTENDED */
116 
117 /*
118  * a pmap describes a processes' 4GB virtual address space.  this
119  * virtual address space can be broken up into 4096 1MB regions which
120  * are described by L1 PTEs in the L1 table.
121  *
122  * There is a line drawn at KERNEL_BASE.  Everything below that line
123  * changes when the VM context is switched.  Everything above that line
124  * is the same no matter which VM context is running.  This is achieved
125  * by making the L1 PTEs for those slots above KERNEL_BASE reference
126  * kernel L2 tables.
127  *
128  * The basic layout of the virtual address space thus looks like this:
129  *
130  *	0xffffffff
131  *	.
132  *	.
133  *	.
134  *	KERNEL_BASE
135  *	--------------------
136  *	.
137  *	.
138  *	.
139  *	0x00000000
140  */
141 
142 /*
143  * The number of L2 descriptor tables which can be tracked by an l2_dtable.
144  * A bucket size of 16 provides for 16MB of contiguous virtual address
145  * space per l2_dtable. Most processes will, therefore, require only two or
146  * three of these to map their whole working set.
147  */
148 #define	L2_BUCKET_XLOG2	(L1_S_SHIFT)
149 #define	L2_BUCKET_XSIZE	(1 << L2_BUCKET_XLOG2)
150 #define	L2_BUCKET_LOG2	4
151 #define	L2_BUCKET_SIZE	(1 << L2_BUCKET_LOG2)
152 
153 /*
154  * Given the above "L2-descriptors-per-l2_dtable" constant, the number
155  * of l2_dtable structures required to track all possible page descriptors
156  * mappable by an L1 translation table is given by the following constants:
157  */
158 #define	L2_LOG2		(32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2))
159 #define	L2_SIZE		(1 << L2_LOG2)
160 
161 /*
162  * tell MI code that the cache is virtually-indexed.
163  * ARMv6 is physically-tagged but all others are virtually-tagged.
164  */
165 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
166 #define	PMAP_CACHE_VIPT
167 #else
168 #define	PMAP_CACHE_VIVT
169 #endif
170 
171 #ifndef _LOCORE
172 
173 #ifndef ARM_MMU_EXTENDED
174 struct l1_ttable;
175 struct l2_dtable;
176 
177 /*
178  * Track cache/tlb occupancy using the following structure
179  */
180 union pmap_cache_state {
181 	struct {
182 		union {
183 			uint8_t csu_cache_b[2];
184 			uint16_t csu_cache;
185 		} cs_cache_u;
186 
187 		union {
188 			uint8_t csu_tlb_b[2];
189 			uint16_t csu_tlb;
190 		} cs_tlb_u;
191 	} cs_s;
192 	uint32_t cs_all;
193 };
194 #define	cs_cache_id	cs_s.cs_cache_u.csu_cache_b[0]
195 #define	cs_cache_d	cs_s.cs_cache_u.csu_cache_b[1]
196 #define	cs_cache	cs_s.cs_cache_u.csu_cache
197 #define	cs_tlb_id	cs_s.cs_tlb_u.csu_tlb_b[0]
198 #define	cs_tlb_d	cs_s.cs_tlb_u.csu_tlb_b[1]
199 #define	cs_tlb		cs_s.cs_tlb_u.csu_tlb
200 
201 /*
202  * Assigned to cs_all to force cacheops to work for a particular pmap
203  */
204 #define	PMAP_CACHE_STATE_ALL	0xffffffffu
205 #endif /* !ARM_MMU_EXTENDED */
206 
207 
208 #define	DEVMAP_ALIGN(a)	((a) & ~L1_S_OFFSET)
209 #define	DEVMAP_SIZE(s)	roundup2((s), L1_S_SIZE)
210 #define	DEVMAP_FLAGS	PMAP_DEV
211 
212 /*
213  * The pmap structure itself
214  */
215 struct pmap {
216 	kmutex_t		pm_lock;
217 	u_int			pm_refs;
218 #ifndef ARM_HAS_VBAR
219 	pd_entry_t		*pm_pl1vec;
220 	pd_entry_t		pm_l1vec;
221 #endif
222 	struct l2_dtable	*pm_l2[L2_SIZE];
223 	struct pmap_statistics	pm_stats;
224 	LIST_ENTRY(pmap)	pm_list;
225 	bool			pm_remove_all;
226 #ifdef ARM_MMU_EXTENDED
227 	pd_entry_t		*pm_l1;
228 	paddr_t			pm_l1_pa;
229 #ifdef MULTIPROCESSOR
230 	kcpuset_t		*pm_onproc;
231 	kcpuset_t		*pm_active;
232 #if PMAP_TLB_MAX > 1
233 	u_int			pm_shootdown_pending;
234 #endif
235 #endif
236 	struct pmap_asid_info	pm_pai[PMAP_TLB_MAX];
237 #else
238 	struct l1_ttable	*pm_l1;
239 	union pmap_cache_state	pm_cstate;
240 	uint8_t			pm_domain;
241 	bool			pm_activated;
242 #endif
243 };
244 
245 struct pmap_kernel {
246 	struct pmap		kernel_pmap;
247 };
248 
249 /*
250  * Physical / virtual address structure. In a number of places (particularly
251  * during bootstrapping) we need to keep track of the physical and virtual
252  * addresses of various pages
253  */
254 typedef struct pv_addr {
255 	SLIST_ENTRY(pv_addr) pv_list;
256 	paddr_t pv_pa;
257 	vaddr_t pv_va;
258 	vsize_t pv_size;
259 	uint8_t pv_cache;
260 	uint8_t pv_prot;
261 } pv_addr_t;
262 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t;
263 
264 extern pv_addrqh_t pmap_freeq;
265 extern pv_addr_t kernelstack;
266 extern pv_addr_t abtstack;
267 extern pv_addr_t fiqstack;
268 extern pv_addr_t irqstack;
269 extern pv_addr_t undstack;
270 extern pv_addr_t idlestack;
271 extern pv_addr_t systempage;
272 extern pv_addr_t kernel_l1pt;
273 #if defined(EFI_RUNTIME)
274 extern pv_addr_t efirt_l1pt;
275 #endif
276 
277 #ifdef ARM_MMU_EXTENDED
278 extern bool arm_has_tlbiasid_p;	/* also in <arm/locore.h> */
279 #endif
280 
281 /*
282  * Determine various modes for PTEs (user vs. kernel, cacheable
283  * vs. non-cacheable).
284  */
285 #define	PTE_KERNEL	0
286 #define	PTE_USER	1
287 #define	PTE_NOCACHE	0
288 #define	PTE_CACHE	1
289 #define	PTE_PAGETABLE	2
290 #define	PTE_DEV		3
291 
292 /*
293  * Flags that indicate attributes of pages or mappings of pages.
294  *
295  * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
296  * page.  PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
297  * pv_entry's for each page.  They live in the same "namespace" so
298  * that we can clear multiple attributes at a time.
299  *
300  * Note the "non-cacheable" flag generally means the page has
301  * multiple mappings in a given address space.
302  */
303 #define	PVF_MOD		0x01		/* page is modified */
304 #define	PVF_REF		0x02		/* page is referenced */
305 #define	PVF_WIRED	0x04		/* mapping is wired */
306 #define	PVF_WRITE	0x08		/* mapping is writable */
307 #define	PVF_EXEC	0x10		/* mapping is executable */
308 #ifdef PMAP_CACHE_VIVT
309 #define	PVF_UNC		0x20		/* mapping is 'user' non-cacheable */
310 #define	PVF_KNC		0x40		/* mapping is 'kernel' non-cacheable */
311 #define	PVF_NC		(PVF_UNC|PVF_KNC)
312 #endif
313 #ifdef PMAP_CACHE_VIPT
314 #define	PVF_NC		0x20		/* mapping is 'kernel' non-cacheable */
315 #define	PVF_MULTCLR	0x40		/* mapping is multi-colored */
316 #endif
317 #define	PVF_COLORED	0x80		/* page has or had a color */
318 #define	PVF_KENTRY	0x0100		/* page entered via pmap_kenter_pa */
319 #define	PVF_KMPAGE	0x0200		/* page is used for kmem */
320 #define	PVF_DIRTY	0x0400		/* page may have dirty cache lines */
321 #define	PVF_KMOD	0x0800		/* unmanaged page is modified  */
322 #define	PVF_KWRITE	(PVF_KENTRY|PVF_WRITE)
323 #define	PVF_DMOD	(PVF_MOD|PVF_KMOD|PVF_KMPAGE)
324 
325 /*
326  * Commonly referenced structures
327  */
328 extern int		arm_poolpage_vmfreelist;
329 
330 /*
331  * Macros that we need to export
332  */
333 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
334 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
335 
336 #define	pmap_is_modified(pg)	\
337 	(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
338 #define	pmap_is_referenced(pg)	\
339 	(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
340 #define	pmap_is_page_colored_p(md)	\
341 	(((md)->pvh_attrs & PVF_COLORED) != 0)
342 
343 #define	pmap_copy(dp, sp, da, l, sa)	/* nothing */
344 
345 #define	pmap_phys_address(ppn)		(arm_ptob((ppn)))
346 u_int arm32_mmap_flags(paddr_t);
347 #define	ARM32_MMAP_WRITECOMBINE		0x40000000
348 #define	ARM32_MMAP_CACHEABLE		0x20000000
349 #define	ARM_MMAP_WRITECOMBINE		ARM32_MMAP_WRITECOMBINE
350 #define	ARM_MMAP_CACHEABLE		ARM32_MMAP_CACHEABLE
351 #define	pmap_mmap_flags(ppn)		arm32_mmap_flags(ppn)
352 
353 #define	PMAP_PTE			0x10000000 /* kenter_pa */
354 #define	PMAP_DEV			0x20000000 /* kenter_pa */
355 #define	PMAP_DEV_SO			0x40000000 /* kenter_pa */
356 #define	PMAP_DEV_MASK			(PMAP_DEV | PMAP_DEV_SO)
357 
358 /*
359  * Functions that we need to export
360  */
361 void	pmap_procwr(struct proc *, vaddr_t, int);
362 bool	pmap_remove_all(pmap_t);
363 bool	pmap_extract(pmap_t, vaddr_t, paddr_t *);
364 
365 #define	PMAP_NEED_PROCWR
366 #define	PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
367 #define	PMAP_ENABLE_PMAP_KMPAGE	/* enable the PMAP_KMPAGE flag */
368 
369 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
370 #define	PMAP_PREFER(hint, vap, sz, td)	pmap_prefer((hint), (vap), (td))
371 void	pmap_prefer(vaddr_t, vaddr_t *, int);
372 #endif
373 
374 #ifdef ARM_MMU_EXTENDED
375 int	pmap_maxproc_set(int);
376 struct pmap *
377 	pmap_efirt(void);
378 #endif
379 
380 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
381 
382 /* Functions we use internally. */
383 #ifdef PMAP_STEAL_MEMORY
384 void	pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *);
385 void	pmap_boot_pageadd(pv_addr_t *);
386 vaddr_t	pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *);
387 #endif
388 void	pmap_bootstrap(vaddr_t, vaddr_t);
389 
390 struct pmap *
391 	pmap_efirt(void);
392 void	pmap_activate_efirt(void);
393 void	pmap_deactivate_efirt(void);
394 
395 void	pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
396 int	pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
397 int	pmap_prefetchabt_fixup(void *);
398 bool	pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
399 bool	pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
400 bool	pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
401 
402 void	pmap_postinit(void);
403 
404 void	vector_page_setprot(int);
405 
406 /* Bootstrapping routines. */
407 void	pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
408 void	pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
409 vsize_t	pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
410 void	pmap_unmap_chunk(vaddr_t, vaddr_t, vsize_t);
411 void	pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
412 
413 vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
414 
415 /*
416  * Special page zero routine for use by the idle loop (no cache cleans).
417  */
418 bool	pmap_pageidlezero(paddr_t);
419 #define	PMAP_PAGEIDLEZERO(pa)	pmap_pageidlezero((pa))
420 
421 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
422 /*
423  * For the pmap, this is a more useful way to map a direct mapped page.
424  * It returns either the direct-mapped VA or the VA supplied if it can't
425  * be direct mapped.
426  */
427 vaddr_t	pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t);
428 #endif
429 
430 /*
431  * used by dumpsys to record the PA of the L1 table
432  */
433 uint32_t pmap_kernel_L1_addr(void);
434 /*
435  * The current top of kernel VM
436  */
437 extern vaddr_t	pmap_curmaxkvaddr;
438 
439 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
440 /*
441  * Ending VA of direct mapped memory (usually KERNEL_VM_BASE).
442  */
443 extern vaddr_t pmap_directlimit;
444 #endif
445 
446 /*
447  * Useful macros and constants
448  */
449 
450 /* Virtual address to page table entry */
451 static inline pt_entry_t *
vtopte(vaddr_t va)452 vtopte(vaddr_t va)
453 {
454 	pd_entry_t *pdep;
455 	pt_entry_t *ptep;
456 
457 	KASSERT(trunc_page(va) == va);
458 
459 	if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
460 		return (NULL);
461 	return (ptep);
462 }
463 
464 /*
465  * Virtual address to physical address
466  */
467 static inline paddr_t
vtophys(vaddr_t va)468 vtophys(vaddr_t va)
469 {
470 	paddr_t pa;
471 
472 	if (pmap_extract(pmap_kernel(), va, &pa) == false)
473 		return (0);	/* XXXSCW: Panic? */
474 
475 	return (pa);
476 }
477 
478 /*
479  * The new pmap ensures that page-tables are always mapping Write-Thru.
480  * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
481  * on every change.
482  *
483  * Unfortunately, not all CPUs have a write-through cache mode.  So we
484  * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
485  * and if there is the chance for PTE syncs to be needed, we define
486  * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
487  * the code.
488  */
489 extern int pmap_needs_pte_sync;
490 #if defined(_KERNEL_OPT)
491 /*
492  * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a
493  * single MMU type is selected.
494  *
495  * StrongARM SA-1 caches do not have a write-through mode.  So, on these,
496  * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs.
497  * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs.
498  *
499  * Use run time evaluation for all other cases.
500  *
501  */
502 #if (ARM_NMMUS == 1)
503 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0)
504 #define	PMAP_INCLUDE_PTE_SYNC
505 #define	PMAP_NEEDS_PTE_SYNC	1
506 #elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0)
507 #define	PMAP_NEEDS_PTE_SYNC	0
508 #endif
509 #endif
510 #endif /* _KERNEL_OPT */
511 
512 /*
513  * Provide a fallback in case we were not able to determine it at
514  * compile-time.
515  */
516 #ifndef PMAP_NEEDS_PTE_SYNC
517 #define	PMAP_NEEDS_PTE_SYNC	pmap_needs_pte_sync
518 #define	PMAP_INCLUDE_PTE_SYNC
519 #endif
520 
521 static inline void
pmap_ptesync(pt_entry_t * ptep,size_t cnt)522 pmap_ptesync(pt_entry_t *ptep, size_t cnt)
523 {
524 	if (PMAP_NEEDS_PTE_SYNC) {
525 		cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
526 #ifdef SHEEVA_L2_CACHE
527 		cpu_sdcache_wb_range((vaddr_t)ptep, -1,
528 		    cnt * sizeof(pt_entry_t));
529 #endif
530 	}
531 	dsb(sy);
532 }
533 
534 #define	PDE_SYNC(pdep)			pmap_ptesync((pdep), 1)
535 #define	PDE_SYNC_RANGE(pdep, cnt)	pmap_ptesync((pdep), (cnt))
536 #define	PTE_SYNC(ptep)			pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE)
537 #define	PTE_SYNC_RANGE(ptep, cnt)	pmap_ptesync((ptep), (cnt))
538 
539 #define	l1pte_valid_p(pde)	((pde) != 0)
540 #define	l1pte_section_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_S)
541 #define	l1pte_supersection_p(pde) (l1pte_section_p(pde)	\
542 				&& ((pde) & L1_S_V6_SUPER) != 0)
543 #define	l1pte_page_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_C)
544 #define	l1pte_fpage_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_F)
545 #define	l1pte_pa(pde)		((pde) & L1_C_ADDR_MASK)
546 #define	l1pte_index(v)		((vaddr_t)(v) >> L1_S_SHIFT)
547 
548 static inline void
l1pte_setone(pt_entry_t * pdep,pt_entry_t pde)549 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde)
550 {
551 	*pdep = pde;
552 }
553 
554 static inline void
l1pte_set(pt_entry_t * pdep,pt_entry_t pde)555 l1pte_set(pt_entry_t *pdep, pt_entry_t pde)
556 {
557 	*pdep = pde;
558 	if (l1pte_page_p(pde)) {
559 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep);
560 		for (int k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) {
561 			pde += L2_T_SIZE;
562 			pdep[k] = pde;
563 		}
564 	} else if (l1pte_supersection_p(pde)) {
565 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep);
566 		for (int k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) {
567 			pdep[k] = pde;
568 		}
569 	}
570 }
571 
572 #define	l2pte_index(v)		((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT))
573 #define	l2pte_valid_p(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
574 #define	l2pte_pa(pte)		((pte) & L2_S_FRAME)
575 #define	l1pte_lpage_p(pte)	(((pte) & L2_TYPE_MASK) == L2_TYPE_L)
576 #define	l2pte_minidata_p(pte)	(((pte) & \
577 				 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
578 				 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
579 
580 static inline void
l2pte_set(pt_entry_t * ptep,pt_entry_t pte,pt_entry_t opte)581 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
582 {
583 	if (l1pte_lpage_p(pte)) {
584 		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
585 		for (int k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) {
586 			*ptep++ = pte;
587 		}
588 	} else {
589 		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
590 		for (int k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) {
591 			KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte);
592 			*ptep++ = pte;
593 			pte += L2_S_SIZE;
594 			if (opte)
595 				opte += L2_S_SIZE;
596 		}
597 	}
598 }
599 
600 static inline void
l2pte_reset(pt_entry_t * ptep)601 l2pte_reset(pt_entry_t *ptep)
602 {
603 	KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
604 	*ptep = 0;
605 	for (int k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
606 		ptep[k] = 0;
607 	}
608 }
609 
610 /* L1 and L2 page table macros */
611 #define	pmap_pde_v(pde)		l1pte_valid(*(pde))
612 #define	pmap_pde_section(pde)	l1pte_section_p(*(pde))
613 #define	pmap_pde_supersection(pde)	l1pte_supersection_p(*(pde))
614 #define	pmap_pde_page(pde)	l1pte_page_p(*(pde))
615 #define	pmap_pde_fpage(pde)	l1pte_fpage_p(*(pde))
616 
617 #define	pmap_pte_v(pte)		l2pte_valid_p(*(pte))
618 #define	pmap_pte_pa(pte)	l2pte_pa(*(pte))
619 
620 static inline uint32_t
pte_value(pt_entry_t pte)621 pte_value(pt_entry_t pte)
622 {
623 	return pte;
624 }
625 
626 static inline bool
pte_valid_p(pt_entry_t pte)627 pte_valid_p(pt_entry_t pte)
628 {
629 
630 	return l2pte_valid_p(pte);
631 }
632 
633 
634 /* Size of the kernel part of the L1 page table */
635 #define	KERNEL_PD_SIZE	\
636 	(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
637 
638 void	bzero_page(vaddr_t);
639 void	bcopy_page(vaddr_t, vaddr_t);
640 
641 #ifdef FPU_VFP
642 void	bzero_page_vfp(vaddr_t);
643 void	bcopy_page_vfp(vaddr_t, vaddr_t);
644 #endif
645 
646 /************************* ARM MMU configuration *****************************/
647 
648 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
649 void	pmap_copy_page_generic(paddr_t, paddr_t);
650 void	pmap_zero_page_generic(paddr_t);
651 
652 void	pmap_pte_init_generic(void);
653 #if defined(CPU_ARM8)
654 void	pmap_pte_init_arm8(void);
655 #endif
656 #if defined(CPU_ARM9)
657 void	pmap_pte_init_arm9(void);
658 #endif /* CPU_ARM9 */
659 #if defined(CPU_ARM10)
660 void	pmap_pte_init_arm10(void);
661 #endif /* CPU_ARM10 */
662 #if defined(CPU_ARM11)	/* ARM_MMU_V6 */
663 void	pmap_pte_init_arm11(void);
664 #endif /* CPU_ARM11 */
665 #if defined(CPU_ARM11MPCORE)	/* ARM_MMU_V6 */
666 void	pmap_pte_init_arm11mpcore(void);
667 #endif
668 #if ARM_MMU_V6 == 1
669 void	pmap_pte_init_armv6(void);
670 #endif /* ARM_MMU_V6 */
671 #if ARM_MMU_V7 == 1
672 void	pmap_pte_init_armv7(void);
673 #endif /* ARM_MMU_V7 */
674 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
675 
676 #if ARM_MMU_SA1 == 1
677 void	pmap_pte_init_sa1(void);
678 #endif /* ARM_MMU_SA1 == 1 */
679 
680 #if ARM_MMU_XSCALE == 1
681 void	pmap_copy_page_xscale(paddr_t, paddr_t);
682 void	pmap_zero_page_xscale(paddr_t);
683 
684 void	pmap_pte_init_xscale(void);
685 
686 void	xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
687 
688 #define	PMAP_UAREA(va)		pmap_uarea(va)
689 void	pmap_uarea(vaddr_t);
690 #endif /* ARM_MMU_XSCALE == 1 */
691 
692 extern pt_entry_t		pte_l1_s_nocache_mode;
693 extern pt_entry_t		pte_l2_l_nocache_mode;
694 extern pt_entry_t		pte_l2_s_nocache_mode;
695 
696 extern pt_entry_t		pte_l1_s_cache_mode;
697 extern pt_entry_t		pte_l2_l_cache_mode;
698 extern pt_entry_t		pte_l2_s_cache_mode;
699 
700 extern pt_entry_t		pte_l1_s_cache_mode_pt;
701 extern pt_entry_t		pte_l2_l_cache_mode_pt;
702 extern pt_entry_t		pte_l2_s_cache_mode_pt;
703 
704 extern pt_entry_t		pte_l1_s_wc_mode;
705 extern pt_entry_t		pte_l2_l_wc_mode;
706 extern pt_entry_t		pte_l2_s_wc_mode;
707 
708 extern pt_entry_t		pte_l1_s_cache_mask;
709 extern pt_entry_t		pte_l2_l_cache_mask;
710 extern pt_entry_t		pte_l2_s_cache_mask;
711 
712 extern pt_entry_t		pte_l1_s_prot_u;
713 extern pt_entry_t		pte_l1_s_prot_w;
714 extern pt_entry_t		pte_l1_s_prot_ro;
715 extern pt_entry_t		pte_l1_s_prot_mask;
716 
717 extern pt_entry_t		pte_l2_s_prot_u;
718 extern pt_entry_t		pte_l2_s_prot_w;
719 extern pt_entry_t		pte_l2_s_prot_ro;
720 extern pt_entry_t		pte_l2_s_prot_mask;
721 
722 extern pt_entry_t		pte_l2_l_prot_u;
723 extern pt_entry_t		pte_l2_l_prot_w;
724 extern pt_entry_t		pte_l2_l_prot_ro;
725 extern pt_entry_t		pte_l2_l_prot_mask;
726 
727 extern pt_entry_t		pte_l1_ss_proto;
728 extern pt_entry_t		pte_l1_s_proto;
729 extern pt_entry_t		pte_l1_c_proto;
730 extern pt_entry_t		pte_l2_s_proto;
731 
732 extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
733 extern void (*pmap_zero_page_func)(paddr_t);
734 
735 #endif /* !_LOCORE */
736 
737 /*****************************************************************************/
738 
739 #define	KERNEL_PID		0	/* The kernel uses ASID 0 */
740 
741 /*
742  * Definitions for MMU domains
743  */
744 #define	PMAP_DOMAINS		15	/* 15 'user' domains (1-15) */
745 #define	PMAP_DOMAIN_KERNEL	0	/* The kernel pmap uses domain #0 */
746 
747 #ifdef ARM_MMU_EXTENDED
748 #define	PMAP_DOMAIN_USER	1	/* User pmaps use domain #1 */
749 #define	DOMAIN_DEFAULT		((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | (DOMAIN_CLIENT << (PMAP_DOMAIN_USER*2)))
750 #else
751 #define	DOMAIN_DEFAULT		((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)))
752 #endif
753 
754 /*
755  * These macros define the various bit masks in the PTE.
756  *
757  * We use these macros since we use different bits on different processor
758  * models.
759  */
760 #define	L1_S_PROT_U_generic	(L1_S_AP(AP_U))
761 #define	L1_S_PROT_W_generic	(L1_S_AP(AP_W))
762 #define	L1_S_PROT_RO_generic	(0)
763 #define	L1_S_PROT_MASK_generic	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
764 
765 #define	L1_S_PROT_U_xscale	(L1_S_AP(AP_U))
766 #define	L1_S_PROT_W_xscale	(L1_S_AP(AP_W))
767 #define	L1_S_PROT_RO_xscale	(0)
768 #define	L1_S_PROT_MASK_xscale	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
769 
770 #define	L1_S_PROT_U_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
771 #define	L1_S_PROT_W_armv6	(L1_S_AP(AP_W))
772 #define	L1_S_PROT_RO_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
773 #define	L1_S_PROT_MASK_armv6	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
774 
775 #define	L1_S_PROT_U_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
776 #define	L1_S_PROT_W_armv7	(L1_S_AP(AP_W))
777 #define	L1_S_PROT_RO_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
778 #define	L1_S_PROT_MASK_armv7	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
779 
780 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
781 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
782 #define	L1_S_CACHE_MASK_armv6	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
783 #define	L1_S_CACHE_MASK_armv6n	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
784 #define	L1_S_CACHE_MASK_armv7	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
785 
786 #define	L2_L_PROT_U_generic	(L2_AP(AP_U))
787 #define	L2_L_PROT_W_generic	(L2_AP(AP_W))
788 #define	L2_L_PROT_RO_generic	(0)
789 #define	L2_L_PROT_MASK_generic	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
790 
791 #define	L2_L_PROT_U_xscale	(L2_AP(AP_U))
792 #define	L2_L_PROT_W_xscale	(L2_AP(AP_W))
793 #define	L2_L_PROT_RO_xscale	(0)
794 #define	L2_L_PROT_MASK_xscale	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
795 
796 #define	L2_L_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
797 #define	L2_L_PROT_W_armv6n	(L2_AP0(AP_W))
798 #define	L2_L_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
799 #define	L2_L_PROT_MASK_armv6n	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
800 
801 #define	L2_L_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
802 #define	L2_L_PROT_W_armv7	(L2_AP0(AP_W))
803 #define	L2_L_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
804 #define	L2_L_PROT_MASK_armv7	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
805 
806 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
807 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
808 #define	L2_L_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
809 #define	L2_L_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
810 #define	L2_L_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
811 
812 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
813 #define	L2_S_PROT_W_generic	(L2_AP(AP_W))
814 #define	L2_S_PROT_RO_generic	(0)
815 #define	L2_S_PROT_MASK_generic	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
816 
817 #define	L2_S_PROT_U_xscale	(L2_AP0(AP_U))
818 #define	L2_S_PROT_W_xscale	(L2_AP0(AP_W))
819 #define	L2_S_PROT_RO_xscale	(0)
820 #define	L2_S_PROT_MASK_xscale	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
821 
822 #define	L2_S_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
823 #define	L2_S_PROT_W_armv6n	(L2_AP0(AP_W))
824 #define	L2_S_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
825 #define	L2_S_PROT_MASK_armv6n	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
826 
827 #define	L2_S_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
828 #define	L2_S_PROT_W_armv7	(L2_AP0(AP_W))
829 #define	L2_S_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
830 #define	L2_S_PROT_MASK_armv7	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
831 
832 #define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
833 #define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X))
834 #define	L2_XS_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX))
835 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
836 #define	L2_S_CACHE_MASK_armv6c	L2_XS_CACHE_MASK_armv6
837 #else
838 #define	L2_S_CACHE_MASK_armv6c	L2_S_CACHE_MASK_generic
839 #endif
840 #define	L2_S_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
841 #define	L2_S_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
842 
843 
844 #define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
845 #define	L1_S_PROTO_xscale	(L1_TYPE_S)
846 #define	L1_S_PROTO_armv6	(L1_TYPE_S)
847 #define	L1_S_PROTO_armv7	(L1_TYPE_S)
848 
849 #define	L1_SS_PROTO_generic	0
850 #define	L1_SS_PROTO_xscale	0
851 #define	L1_SS_PROTO_armv6	(L1_TYPE_S | L1_S_V6_SS)
852 #define	L1_SS_PROTO_armv7	(L1_TYPE_S | L1_S_V6_SS)
853 
854 #define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
855 #define	L1_C_PROTO_xscale	(L1_TYPE_C)
856 #define	L1_C_PROTO_armv6	(L1_TYPE_C)
857 #define	L1_C_PROTO_armv7	(L1_TYPE_C)
858 
859 #define	L2_L_PROTO		(L2_TYPE_L)
860 
861 #define	L2_S_PROTO_generic	(L2_TYPE_S)
862 #define	L2_S_PROTO_xscale	(L2_TYPE_XS)
863 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
864 #define	L2_S_PROTO_armv6c	(L2_TYPE_XS)    /* XP=0, extended small page */
865 #else
866 #define	L2_S_PROTO_armv6c	(L2_TYPE_S)	/* XP=0, subpage APs */
867 #endif
868 #ifdef ARM_MMU_EXTENDED
869 #define	L2_S_PROTO_armv6n	(L2_TYPE_S|L2_XS_XN)
870 #else
871 #define	L2_S_PROTO_armv6n	(L2_TYPE_S)	/* with XP=1 */
872 #endif
873 #ifdef ARM_MMU_EXTENDED
874 #define	L2_S_PROTO_armv7	(L2_TYPE_S|L2_XS_XN)
875 #else
876 #define	L2_S_PROTO_armv7	(L2_TYPE_S)
877 #endif
878 
879 /*
880  * User-visible names for the ones that vary with MMU class.
881  */
882 
883 #if ARM_NMMUS > 1
884 /* More than one MMU class configured; use variables. */
885 #define	L1_S_PROT_U		pte_l1_s_prot_u
886 #define	L1_S_PROT_W		pte_l1_s_prot_w
887 #define	L1_S_PROT_RO		pte_l1_s_prot_ro
888 #define	L1_S_PROT_MASK		pte_l1_s_prot_mask
889 
890 #define	L2_S_PROT_U		pte_l2_s_prot_u
891 #define	L2_S_PROT_W		pte_l2_s_prot_w
892 #define	L2_S_PROT_RO		pte_l2_s_prot_ro
893 #define	L2_S_PROT_MASK		pte_l2_s_prot_mask
894 
895 #define	L2_L_PROT_U		pte_l2_l_prot_u
896 #define	L2_L_PROT_W		pte_l2_l_prot_w
897 #define	L2_L_PROT_RO		pte_l2_l_prot_ro
898 #define	L2_L_PROT_MASK		pte_l2_l_prot_mask
899 
900 #define	L1_S_CACHE_MASK		pte_l1_s_cache_mask
901 #define	L2_L_CACHE_MASK		pte_l2_l_cache_mask
902 #define	L2_S_CACHE_MASK		pte_l2_s_cache_mask
903 
904 #define	L1_SS_PROTO		pte_l1_ss_proto
905 #define	L1_S_PROTO		pte_l1_s_proto
906 #define	L1_C_PROTO		pte_l1_c_proto
907 #define	L2_S_PROTO		pte_l2_s_proto
908 
909 #define	pmap_copy_page(s, d)	(*pmap_copy_page_func)((s), (d))
910 #define	pmap_zero_page(d)	(*pmap_zero_page_func)((d))
911 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
912 #define	L1_S_PROT_U		L1_S_PROT_U_generic
913 #define	L1_S_PROT_W		L1_S_PROT_W_generic
914 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
915 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
916 
917 #define	L2_S_PROT_U		L2_S_PROT_U_generic
918 #define	L2_S_PROT_W		L2_S_PROT_W_generic
919 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
920 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
921 
922 #define	L2_L_PROT_U		L2_L_PROT_U_generic
923 #define	L2_L_PROT_W		L2_L_PROT_W_generic
924 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
925 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
926 
927 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
928 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
929 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
930 
931 #define	L1_SS_PROTO		L1_SS_PROTO_generic
932 #define	L1_S_PROTO		L1_S_PROTO_generic
933 #define	L1_C_PROTO		L1_C_PROTO_generic
934 #define	L2_S_PROTO		L2_S_PROTO_generic
935 
936 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
937 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
938 #elif ARM_MMU_V6N != 0
939 #define	L1_S_PROT_U		L1_S_PROT_U_armv6
940 #define	L1_S_PROT_W		L1_S_PROT_W_armv6
941 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv6
942 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv6
943 
944 #define	L2_S_PROT_U		L2_S_PROT_U_armv6n
945 #define	L2_S_PROT_W		L2_S_PROT_W_armv6n
946 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv6n
947 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv6n
948 
949 #define	L2_L_PROT_U		L2_L_PROT_U_armv6n
950 #define	L2_L_PROT_W		L2_L_PROT_W_armv6n
951 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv6n
952 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv6n
953 
954 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6n
955 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6n
956 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv6n
957 
958 /*
959  * These prototypes make writeable mappings, while the other MMU types
960  * make read-only mappings.
961  */
962 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
963 #define	L1_S_PROTO		L1_S_PROTO_armv6
964 #define	L1_C_PROTO		L1_C_PROTO_armv6
965 #define	L2_S_PROTO		L2_S_PROTO_armv6n
966 
967 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
968 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
969 #elif ARM_MMU_V6C != 0
970 #define	L1_S_PROT_U		L1_S_PROT_U_generic
971 #define	L1_S_PROT_W		L1_S_PROT_W_generic
972 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
973 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
974 
975 #define	L2_S_PROT_U		L2_S_PROT_U_generic
976 #define	L2_S_PROT_W		L2_S_PROT_W_generic
977 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
978 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
979 
980 #define	L2_L_PROT_U		L2_L_PROT_U_generic
981 #define	L2_L_PROT_W		L2_L_PROT_W_generic
982 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
983 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
984 
985 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
986 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
987 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
988 
989 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
990 #define	L1_S_PROTO		L1_S_PROTO_generic
991 #define	L1_C_PROTO		L1_C_PROTO_generic
992 #define	L2_S_PROTO		L2_S_PROTO_generic
993 
994 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
995 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
996 #elif ARM_MMU_XSCALE == 1
997 #define	L1_S_PROT_U		L1_S_PROT_U_generic
998 #define	L1_S_PROT_W		L1_S_PROT_W_generic
999 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
1000 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
1001 
1002 #define	L2_S_PROT_U		L2_S_PROT_U_xscale
1003 #define	L2_S_PROT_W		L2_S_PROT_W_xscale
1004 #define	L2_S_PROT_RO		L2_S_PROT_RO_xscale
1005 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
1006 
1007 #define	L2_L_PROT_U		L2_L_PROT_U_generic
1008 #define	L2_L_PROT_W		L2_L_PROT_W_generic
1009 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
1010 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
1011 
1012 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
1013 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
1014 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
1015 
1016 #define	L1_SS_PROTO		L1_SS_PROTO_xscale
1017 #define	L1_S_PROTO		L1_S_PROTO_xscale
1018 #define	L1_C_PROTO		L1_C_PROTO_xscale
1019 #define	L2_S_PROTO		L2_S_PROTO_xscale
1020 
1021 #define	pmap_copy_page(s, d)	pmap_copy_page_xscale((s), (d))
1022 #define	pmap_zero_page(d)	pmap_zero_page_xscale((d))
1023 #elif ARM_MMU_V7 == 1
1024 #define	L1_S_PROT_U		L1_S_PROT_U_armv7
1025 #define	L1_S_PROT_W		L1_S_PROT_W_armv7
1026 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv7
1027 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv7
1028 
1029 #define	L2_S_PROT_U		L2_S_PROT_U_armv7
1030 #define	L2_S_PROT_W		L2_S_PROT_W_armv7
1031 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv7
1032 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv7
1033 
1034 #define	L2_L_PROT_U		L2_L_PROT_U_armv7
1035 #define	L2_L_PROT_W		L2_L_PROT_W_armv7
1036 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv7
1037 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv7
1038 
1039 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv7
1040 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv7
1041 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv7
1042 
1043 /*
1044  * These prototypes make writeable mappings, while the other MMU types
1045  * make read-only mappings.
1046  */
1047 #define	L1_SS_PROTO		L1_SS_PROTO_armv7
1048 #define	L1_S_PROTO		L1_S_PROTO_armv7
1049 #define	L1_C_PROTO		L1_C_PROTO_armv7
1050 #define	L2_S_PROTO		L2_S_PROTO_armv7
1051 
1052 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
1053 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
1054 #endif /* ARM_NMMUS > 1 */
1055 
1056 /*
1057  * Macros to set and query the write permission on page descriptors.
1058  */
1059 #define	l1pte_set_writable(pte)	(((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W)
1060 #define	l1pte_set_readonly(pte)	(((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO)
1061 
1062 #define	l2pte_set_writable(pte)	(((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W)
1063 #define	l2pte_set_readonly(pte)	(((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO)
1064 
1065 #define	l2pte_writable_p(pte)	(((pte) & L2_S_PROT_W) == L2_S_PROT_W && \
1066 				 (L2_S_PROT_RO == 0 || \
1067 				  ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO))
1068 
1069 /*
1070  * These macros return various bits based on kernel/user and protection.
1071  * Note that the compiler will usually fold these at compile time.
1072  */
1073 
1074 #define	L1_S_PROT(ku, pr)	(					   \
1075 	(((ku) == PTE_USER) ? 						   \
1076 	    L1_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)	   \
1077 	: 								   \
1078 	    (((L1_S_PROT_RO && 						   \
1079 		((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \
1080 		    L1_S_PROT_RO : L1_S_PROT_W)))			   \
1081     )
1082 
1083 #define	L2_L_PROT(ku, pr)	(					   \
1084 	(((ku) == PTE_USER) ?						   \
1085 	    L2_L_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)	   \
1086 	:								   \
1087 	    (((L2_L_PROT_RO && 						   \
1088 		((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \
1089 		    L2_L_PROT_RO : L2_L_PROT_W)))			   \
1090     )
1091 
1092 #define	L2_S_PROT(ku, pr)	(					   \
1093 	(((ku) == PTE_USER) ?						   \
1094 	    L2_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)	   \
1095 	:								   \
1096 	    (((L2_S_PROT_RO &&						   \
1097 		((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \
1098 		    L2_S_PROT_RO : L2_S_PROT_W)))			   \
1099     )
1100 
1101 /*
1102  * Macros to test if a mapping is mappable with an L1 SuperSection,
1103  * L1 Section, or an L2 Large Page mapping.
1104  */
1105 #define	L1_SS_MAPPABLE_P(va, pa, size)					\
1106 	((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE)
1107 
1108 #define	L1_S_MAPPABLE_P(va, pa, size)					\
1109 	((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
1110 
1111 #define	L2_L_MAPPABLE_P(va, pa, size)					\
1112 	((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
1113 
1114 #define	PMAP_MAPSIZE1	L2_L_SIZE
1115 #define	PMAP_MAPSIZE2	L1_S_SIZE
1116 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
1117 #define	PMAP_MAPSIZE3	L1_SS_SIZE
1118 #endif
1119 
1120 #ifndef _LOCORE
1121 /*
1122  * Hooks for the pool allocator.
1123  */
1124 #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
1125 extern paddr_t physical_start, physical_end;
1126 #ifdef PMAP_NEED_ALLOC_POOLPAGE
1127 struct vm_page *arm_pmap_alloc_poolpage(int);
1128 #define	PMAP_ALLOC_POOLPAGE	arm_pmap_alloc_poolpage
1129 #endif
1130 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
1131 vaddr_t	pmap_map_poolpage(paddr_t);
1132 paddr_t	pmap_unmap_poolpage(vaddr_t);
1133 #define	PMAP_MAP_POOLPAGE(pa)	pmap_map_poolpage(pa)
1134 #define	PMAP_UNMAP_POOLPAGE(va)	pmap_unmap_poolpage(va)
1135 #endif
1136 
1137 #define	__HAVE_PMAP_PV_TRACK	1
1138 
1139 void pmap_pv_protect(paddr_t, vm_prot_t);
1140 
1141 struct pmap_page {
1142 	SLIST_HEAD(,pv_entry) pvh_list;		/* pv_entry list */
1143 	int pvh_attrs;				/* page attributes */
1144 	u_int uro_mappings;
1145 	u_int urw_mappings;
1146 	union {
1147 		u_short s_mappings[2];	/* Assume kernel count <= 65535 */
1148 		u_int i_mappings;
1149 	} k_u;
1150 };
1151 
1152 /*
1153  * pmap-specific data store in the vm_page structure.
1154  */
1155 #define	__HAVE_VM_PAGE_MD
1156 struct vm_page_md {
1157 	struct pmap_page pp;
1158 #define	pvh_list	pp.pvh_list
1159 #define	pvh_attrs	pp.pvh_attrs
1160 #define	uro_mappings	pp.uro_mappings
1161 #define	urw_mappings	pp.urw_mappings
1162 #define	kro_mappings	pp.k_u.s_mappings[0]
1163 #define	krw_mappings	pp.k_u.s_mappings[1]
1164 #define	k_mappings	pp.k_u.i_mappings
1165 };
1166 
1167 #define	PMAP_PAGE_TO_MD(ppage) container_of((ppage), struct vm_page_md, pp)
1168 
1169 /*
1170  * Set the default color of each page.
1171  */
1172 #if ARM_MMU_V6 > 0
1173 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1174 	(pg)->mdpage.pvh_attrs = VM_PAGE_TO_PHYS(pg) & arm_cache_prefer_mask
1175 #else
1176 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1177 	(pg)->mdpage.pvh_attrs = 0
1178 #endif
1179 
1180 #define	VM_MDPAGE_INIT(pg)						\
1181 do {									\
1182 	SLIST_INIT(&(pg)->mdpage.pvh_list);				\
1183 	VM_MDPAGE_PVH_ATTRS_INIT(pg);					\
1184 	(pg)->mdpage.uro_mappings = 0;					\
1185 	(pg)->mdpage.urw_mappings = 0;					\
1186 	(pg)->mdpage.k_mappings = 0;					\
1187 } while (/*CONSTCOND*/0)
1188 
1189 #ifndef	__BSD_PTENTRY_T__
1190 #define	__BSD_PTENTRY_T__
1191 typedef uint32_t pt_entry_t;
1192 #define	PRIxPTE		PRIx32
1193 #endif
1194 
1195 #endif /* !_LOCORE */
1196 
1197 #endif /* _KERNEL */
1198 
1199 #endif	/* _ARM32_PMAP_H_ */
1200