1 /* $NetBSD: pte.h,v 1.19 2014/10/29 10:59:48 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_PTE_H_ 39 #define _ARM_PTE_H_ 40 41 /* 42 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 43 * architecture versions used an optional off-CPU memory controller 44 * to perform address translation). 45 * 46 * The ARM MMU consists of a TLB and translation table walking logic. 47 * There is typically one TLB per memory interface (or, put another 48 * way, one TLB per software-visible cache). 49 * 50 * The ARM MMU is capable of mapping memory in the following chunks: 51 * 52 * 16M SuperSections (L1 table, ARMv6+) 53 * 54 * 1M Sections (L1 table) 55 * 56 * 64K Large Pages (L2 table) 57 * 58 * 4K Small Pages (L2 table) 59 * 60 * 1K Tiny Pages (L2 table) 61 * 62 * There are two types of L2 tables: Coarse Tables and Fine Tables (not 63 * available on ARMv6+). Coarse Tables can map Large and Small Pages. 64 * Fine Tables can map Tiny Pages. 65 * 66 * Coarse Tables can define 4 Subpages within Large and Small pages. 67 * Subpages define different permissions for each Subpage within 68 * a Page. ARMv6 format Coarse Tables have no subpages. 69 * 70 * Coarse Tables are 1K in length. Fine tables are 4K in length. 71 * 72 * The Translation Table Base register holds the pointer to the 73 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 74 * aligned to a 16K boundary. Each entry in the L1 Table maps 75 * 1M of virtual address space, either via a Section mapping or 76 * via an L2 Table. 77 * 78 * ARMv6+ has a second TTBR register which can be used if any of the 79 * upper address bits are non-zero (think kernel). For NetBSD, this 80 * would be 1 upper bit splitting user/kernel in a 2GB/2GB split. 81 * This would also reduce the size of the L1 Table to 8K. 82 * 83 * In addition, the Fast Context Switching Extension (FCSE) is available 84 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 85 * TLB/cache flushes on context switch by use of a smaller address space 86 * and a "process ID" that modifies the virtual address before being 87 * presented to the translation logic. 88 */ 89 90 #ifndef _LOCORE 91 typedef uint32_t pd_entry_t; /* L1 table entry */ 92 typedef uint32_t pt_entry_t; /* L2 table entry */ 93 #endif /* _LOCORE */ 94 95 #define L1_SS_SIZE 0x01000000 /* 16M */ 96 #define L1_SS_OFFSET (L1_SS_SIZE - 1) 97 #define L1_SS_FRAME (~L1_SS_OFFSET) 98 #define L1_SS_SHIFT 24 99 100 #define L1_S_SIZE 0x00100000 /* 1M */ 101 #define L1_S_OFFSET (L1_S_SIZE - 1) 102 #define L1_S_FRAME (~L1_S_OFFSET) 103 #define L1_S_SHIFT 20 104 105 #define L2_L_SIZE 0x00010000 /* 64K */ 106 #define L2_L_OFFSET (L2_L_SIZE - 1) 107 #define L2_L_FRAME (~L2_L_OFFSET) 108 #define L2_L_SHIFT 16 109 110 #define L2_S_SEGSIZE (PAGE_SIZE * L2_S_SIZE / 4) 111 #define L2_S_SIZE 0x00001000 /* 4K */ 112 #define L2_S_OFFSET (L2_S_SIZE - 1) 113 #define L2_S_FRAME (~L2_S_OFFSET) 114 #define L2_S_SHIFT 12 115 116 #define L2_T_SIZE 0x00000400 /* 1K */ 117 #define L2_T_OFFSET (L2_T_SIZE - 1) 118 #define L2_T_FRAME (~L2_T_OFFSET) 119 #define L2_T_SHIFT 10 120 121 /* 122 * The NetBSD VM implementation only works on whole pages (4K), 123 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 124 * (16K L1 table, 1K L2 table). 125 * 126 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 127 * table. 128 */ 129 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 130 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 131 132 #define L1_TABLE_SIZE 0x4000 /* 16K */ 133 #define L2_TABLE_SIZE 0x1000 /* 4K */ 134 /* 135 * The new pmap deals with the 1KB coarse L2 tables by 136 * allocating them from a pool. Until every port has been converted, 137 * keep the old L2_TABLE_SIZE define lying around. Converted ports 138 * should use L2_TABLE_SIZE_REAL until then. 139 */ 140 #define L1_TABLE_SIZE_REAL 0x4000 /* 16K */ 141 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 142 143 /* 144 * ARM L1 Descriptors 145 */ 146 147 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 148 #define L1_TYPE_C 0x01 /* Coarse L2 */ 149 #define L1_TYPE_S 0x02 /* Section */ 150 #define L1_TYPE_F 0x03 /* Fine L2 */ 151 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 152 153 /* L1 Section Descriptor */ 154 #define L1_S_B 0x00000004 /* bufferable Section */ 155 #define L1_S_C 0x00000008 /* cacheable Section */ 156 #define L1_S_IMP 0x00000010 /* implementation defined */ 157 #define L1_S_DOM(x) ((x) << 5) /* domain */ 158 #define L1_S_DOM_MASK L1_S_DOM(0xf) 159 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 160 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 161 162 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 163 #define L1_S_XS_TEX(x) ((x) << 12) /* Type Extension */ 164 #define L1_S_V6_TEX(x) L1_S_XS_TEX(x) 165 #define L1_S_V6_P 0x00000200 /* ECC enable for this section */ 166 #define L1_S_V6_SUPER 0x00040000 /* ARMv6 SuperSection (16MB) bit */ 167 #define L1_S_V6_XN L1_S_IMP /* ARMv6 eXecute Never */ 168 #define L1_S_V6_APX 0x00008000 /* ARMv6 AP eXtension */ 169 #define L1_S_V6_S 0x00010000 /* ARMv6 Shared */ 170 #define L1_S_V6_nG 0x00020000 /* ARMv6 not-Global */ 171 #define L1_S_V6_SS 0x00040000 /* ARMv6 SuperSection */ 172 #define L1_S_V6_NS 0x00080000 /* ARMv6 Not Secure */ 173 174 /* L1 Coarse Descriptor */ 175 #define L1_C_IMP0 0x00000004 /* implementation defined */ 176 #define L1_C_IMP1 0x00000008 /* implementation defined */ 177 #define L1_C_IMP2 0x00000010 /* implementation defined */ 178 #define L1_C_DOM(x) ((x) << 5) /* domain */ 179 #define L1_C_DOM_MASK L1_C_DOM(0xf) 180 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 181 182 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 183 #define L1_C_V6_P 0x00000200 /* ECC enable for this section */ 184 185 /* L1 Fine Descriptor */ 186 #define L1_F_IMP0 0x00000004 /* implementation defined */ 187 #define L1_F_IMP1 0x00000008 /* implementation defined */ 188 #define L1_F_IMP2 0x00000010 /* implementation defined */ 189 #define L1_F_DOM(x) ((x) << 5) /* domain */ 190 #define L1_F_DOM_MASK L1_F_DOM(0xf) 191 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 192 193 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 194 195 /* 196 * ARM L2 Descriptors 197 */ 198 199 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 200 #define L2_TYPE_L 0x01 /* Large Page */ 201 #define L2_TYPE_S 0x02 /* Small Page */ 202 #define L2_TYPE_T 0x03 /* Tiny Page (not armv7) */ 203 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 204 205 /* 206 * This L2 Descriptor type is available on XScale processors 207 * when using a Coarse L1 Descriptor. The Extended Small 208 * Descriptor has the same format as the XScale Tiny Descriptor, 209 * but describes a 4K page, rather than a 1K page. 210 * For V6 MMU, this is used when XP bit is cleared. 211 */ 212 #define L2_TYPE_XS 0x03 /* XScale/ARMv6 Extended Small Page */ 213 214 #define L2_B 0x00000004 /* Bufferable page */ 215 #define L2_C 0x00000008 /* Cacheable page */ 216 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 217 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 218 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 219 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 220 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 221 222 #define L2_XS_L_TEX(x) ((x) << 12) /* Type Extension */ 223 #define L2_XS_T_TEX(x) ((x) << 6) /* Type Extension */ 224 #define L2_XS_XN 0x00000001 /* ARMv6 eXecute Never (when XP=1) */ 225 #define L2_XS_APX 0x00000200 /* ARMv6 AP eXtension */ 226 #define L2_XS_S 0x00000400 /* ARMv6 Shared */ 227 #define L2_XS_nG 0x00000800 /* ARMv6 Not-Global */ 228 #define L2_V6_L_TEX L2_XS_L_TEX 229 #define L2_V6_XS_TEX L2_XS_T_TEX 230 #define L2_XS_L_XN 0x00008000 /* ARMv6 eXecute Never */ 231 232 233 /* 234 * Access Permissions for L1 and L2 Descriptors. 235 */ 236 #define AP_W 0x01 /* writable */ 237 #define AP_U 0x02 /* user */ 238 239 /* 240 * Access Permissions for L1 and L2 of ARMv6 with XP=1 and ARMv7 241 */ 242 #define AP_R 0x01 /* readable */ 243 #define AP_RO 0x20 /* read-only (L2_XS_APX >> 4) */ 244 245 /* 246 * Short-hand for common AP_* constants. 247 * 248 * Note: These values assume the S (System) bit is set and 249 * the R (ROM) bit is clear in CP15 register 1. 250 */ 251 #define AP_KR 0x00 /* kernel read */ 252 #define AP_KRW 0x01 /* kernel read/write */ 253 #define AP_KRWUR 0x02 /* kernel read/write user read */ 254 #define AP_KRWURW 0x03 /* kernel read/write user read/write */ 255 256 /* 257 * Note: These values assume the S (System) and the R (ROM) bits are clear and 258 * the XP (eXtended page table) bit is set in CP15 register 1. ARMv6 only. 259 */ 260 #define APX_KR(APX) (APX|0x01) /* kernel read */ 261 #define APX_KRUR(APX) (APX|0x02) /* kernel read user read */ 262 #define APX_KRW(APX) ( 0x01) /* kernel read/write */ 263 #define APX_KRWUR(APX) ( 0x02) /* kernel read/write user read */ 264 #define APX_KRWURW(APX) ( 0x03) /* kernel read/write user read/write */ 265 266 /* 267 * Note: These values are for the simplified access permissions model 268 * of ARMv7. Assumes that AFE is clear in CP15 register 1. 269 * Also used for ARMv6 with XP bit set. 270 */ 271 #define AP7_KR 0x21 /* kernel read */ 272 #define AP7_KRUR 0x23 /* kernel read user read */ 273 #define AP7_KRW 0x01 /* kernel read/write */ 274 #define AP7_KRWURW 0x03 /* kernel read/write user read/write */ 275 276 /* 277 * Domain Types for the Domain Access Control Register. 278 */ 279 #define DOMAIN_FAULT 0x00 /* no access */ 280 #define DOMAIN_CLIENT 0x01 /* client */ 281 #define DOMAIN_RESERVED 0x02 /* reserved */ 282 #define DOMAIN_MANAGER 0x03 /* manager */ 283 284 /* 285 * Type Extension bits for XScale processors. 286 * 287 * Behavior of C and B when X == 0: 288 * 289 * C B Cacheable Bufferable Write Policy Line Allocate Policy 290 * 0 0 N N - - 291 * 0 1 N Y - - 292 * 1 0 Y Y Write-through Read Allocate 293 * 1 1 Y Y Write-back Read Allocate 294 * 295 * Behavior of C and B when X == 1: 296 * C B Cacheable Bufferable Write Policy Line Allocate Policy 297 * 0 0 - - - - DO NOT USE 298 * 0 1 N Y - - 299 * 1 0 Mini-Data - - - 300 * 1 1 Y Y Write-back R/W Allocate 301 */ 302 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 303 304 /* 305 * Type Extension bits for ARM V6 and V7 MMU 306 * 307 * TEX C B Shared 308 * 000 0 0 Strong order yes 309 * 000 0 1 Shared device yes 310 * 000 1 0 Outer and Inner write through, no write alloc S-bit 311 * 000 1 1 Outer and Inner write back, no write alloc S-bit 312 * 001 0 0 Outer and Inner non-cacheable S-bit 313 * 001 0 1 reserved 314 * 001 1 0 reserved 315 * 001 1 1 Outer and Inner write back, write alloc S-bit 316 * 010 0 0 Non-shared device no 317 * 010 0 1 reserved 318 * 010 1 X reserved 319 * 011 X X reserved 320 * 1BB A A BB for inner, AA for outer S-bit 321 * 322 * BB inner cache 323 * 0 0 Non-cacheable 324 * 0 1 Write back, write alloc 325 * 1 0 Write through, no write alloc 326 * 1 1 Write back, no write alloc 327 * 328 * AA outer cache 329 * 0 0 Non-cacheable 330 * 0 1 Write back, write alloc 331 * 1 0 Write through, no write alloc 332 * 1 1 Write back, no write alloc 333 */ 334 335 #define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */ 336 337 #endif /* _ARM_PTE_H_ */ 338