1 /* $OpenBSD: asm.h,v 1.19 2017/06/23 09:55:10 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1990,1991,1994 The University of Utah and 5 * the Computer Systems Laboratory (CSL). All rights reserved. 6 * 7 * Permission to use, copy, modify and distribute this software is hereby 8 * granted provided that (1) source code retains these copyright, permission, 9 * and disclaimer notices, and (2) redistributions including binaries 10 * reproduce the notices in supporting documentation, and (3) all advertising 11 * materials mentioning features or use of this software display the following 12 * acknowledgement: ``This product includes software developed by the 13 * Computer Systems Laboratory at the University of Utah.'' 14 * 15 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 16 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 17 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 20 * improvements that they make and grant CSL redistribution rights. 21 * 22 * Utah $Hdr: asm.h 1.8 94/12/14$ 23 */ 24 25 #ifndef _MACHINE_ASM_H_ 26 #define _MACHINE_ASM_H_ 27 28 /* 29 * hppa assembler definitions 30 */ 31 32 /* 33 * Hardware General Registers 34 */ 35 r0 .reg %r0 36 r1 .reg %r1 37 r2 .reg %r2 38 r3 .reg %r3 39 r4 .reg %r4 40 r5 .reg %r5 41 r6 .reg %r6 42 r7 .reg %r7 43 r8 .reg %r8 44 r9 .reg %r9 45 r10 .reg %r10 46 r11 .reg %r11 47 r12 .reg %r12 48 r13 .reg %r13 49 r14 .reg %r14 50 r15 .reg %r15 51 r16 .reg %r16 52 r17 .reg %r17 53 r18 .reg %r18 54 r19 .reg %r19 55 r20 .reg %r20 56 r21 .reg %r21 57 r22 .reg %r22 58 r23 .reg %r23 59 r24 .reg %r24 60 r25 .reg %r25 61 r26 .reg %r26 62 r27 .reg %r27 63 r28 .reg %r28 64 r29 .reg %r29 65 r30 .reg %r30 66 r31 .reg %r31 67 68 /* 69 * Hardware Space Registers 70 */ 71 sr0 .reg %sr0 72 sr1 .reg %sr1 73 sr2 .reg %sr2 74 sr3 .reg %sr3 75 sr4 .reg %sr4 76 sr5 .reg %sr5 77 sr6 .reg %sr6 78 sr7 .reg %sr7 79 80 /* 81 * Hardware Floating Point Registers 82 */ 83 fr0 .reg %fr0 84 fr1 .reg %fr1 85 fr2 .reg %fr2 86 fr3 .reg %fr3 87 fr4 .reg %fr4 88 fr5 .reg %fr5 89 fr6 .reg %fr6 90 fr7 .reg %fr7 91 fr8 .reg %fr8 92 fr9 .reg %fr9 93 fr10 .reg %fr10 94 fr11 .reg %fr11 95 fr12 .reg %fr12 96 fr13 .reg %fr13 97 fr14 .reg %fr14 98 fr15 .reg %fr15 99 fr16 .reg %fr16 100 fr17 .reg %fr17 101 fr18 .reg %fr18 102 fr19 .reg %fr19 103 fr20 .reg %fr20 104 fr21 .reg %fr21 105 fr22 .reg %fr22 106 fr23 .reg %fr23 107 fr24 .reg %fr24 108 fr25 .reg %fr25 109 fr26 .reg %fr26 110 fr27 .reg %fr27 111 fr28 .reg %fr28 112 fr29 .reg %fr29 113 fr30 .reg %fr30 114 fr31 .reg %fr31 115 116 /* 117 * Hardware Control Registers 118 */ 119 cr0 .reg %cr0 120 cr8 .reg %cr8 121 cr9 .reg %cr9 122 cr10 .reg %cr10 123 cr11 .reg %cr11 124 cr12 .reg %cr12 125 cr13 .reg %cr13 126 cr14 .reg %cr14 127 cr15 .reg %cr15 128 cr16 .reg %cr16 129 cr17 .reg %cr17 130 cr18 .reg %cr18 131 cr19 .reg %cr19 132 cr20 .reg %cr20 133 cr21 .reg %cr21 134 cr22 .reg %cr22 135 cr23 .reg %cr23 136 cr24 .reg %cr24 137 cr25 .reg %cr25 138 cr26 .reg %cr26 139 cr27 .reg %cr27 140 cr28 .reg %cr28 141 cr29 .reg %cr29 142 cr30 .reg %cr30 143 cr31 .reg %cr31 144 145 rctr .reg %cr0 146 pidr1 .reg %cr8 147 pidr2 .reg %cr9 148 ccr .reg %cr10 149 sar .reg %cr11 150 pidr3 .reg %cr12 151 pidr4 .reg %cr13 152 iva .reg %cr14 153 eiem .reg %cr15 154 itmr .reg %cr16 155 pcsq .reg %cr17 156 pcoq .reg %cr18 157 iir .reg %cr19 158 isr .reg %cr20 159 ior .reg %cr21 160 ipsw .reg %cr22 161 eirr .reg %cr23 162 tr0 .reg %cr24 163 vtop .reg %cr25 164 tr1 .reg %cr25 165 tr2 .reg %cr26 166 tr3 .reg %cr27 167 tr4 .reg %cr28 168 tr5 .reg %cr29 169 tr6 .reg %cr30 170 tr7 .reg %cr31 171 172 /* 173 * Calling Convention 174 */ 175 rp .reg %r2 176 arg3 .reg %r23 177 arg2 .reg %r24 178 arg1 .reg %r25 179 arg0 .reg %r26 180 dp .reg %r27 181 ret0 .reg %r28 182 ret1 .reg %r29 183 sl .reg %r29 184 sp .reg %r30 185 186 /* 187 * Temporary registers 188 */ 189 t1 .reg %r22 190 t2 .reg %r21 191 t3 .reg %r20 192 t4 .reg %r19 193 194 /* 195 * Temporary space registers 196 */ 197 ts1 .reg %sr2 198 199 /* 200 * Space Registers - SW Conventions 201 */ 202 sret .reg %sr1 ; return value 203 sarg .reg %sr1 ; argument 204 205 /* 206 * Floating Point Registers - SW Conventions 207 */ 208 farg0 .reg %fr5 209 farg1 .reg %fr6 210 farg2 .reg %fr7 211 farg3 .reg %fr8 212 fret .reg %fr4 213 214 /* 215 * Temporary floating point registers 216 */ 217 tf1 .reg %fr11 218 tf2 .reg %fr10 219 tf3 .reg %fr9 220 tf4 .reg %fr8 221 222 #ifdef __STDC__ 223 #define __CONCAT(a,b) a ## b 224 #else 225 #define __CONCAT(a,b) a/**/b 226 #endif 227 228 #if defined(PROF) || defined(GPROF) 229 #define _PROF_PROLOGUE !\ 230 1: !\ 231 stw rp, HPPA_FRAME_CRP(sr0,sp) !\ 232 stw arg0, HPPA_FRAME_ARG(0)(sr0,sp) !\ 233 stw arg1, HPPA_FRAME_ARG(1)(sr0,sp) !\ 234 stw arg2, HPPA_FRAME_ARG(2)(sr0,sp) !\ 235 stw arg3, HPPA_FRAME_ARG(3)(sr0,sp) !\ 236 ldo HPPA_FRAME_SIZE(sp), sp !\ 237 copy rp, arg0 !\ 238 bl 2f, arg1 !\ 239 depi 0, 31, 2, arg1 !\ 240 2: !\ 241 bl _mcount, rp !\ 242 ldo 1b - 2b(arg1), arg1 !\ 243 ldo -HPPA_FRAME_SIZE(sp), sp !\ 244 ldw HPPA_FRAME_ARG(3)(sr0,sp), arg3 !\ 245 ldw HPPA_FRAME_ARG(2)(sr0,sp), arg2 !\ 246 ldw HPPA_FRAME_ARG(1)(sr0,sp), arg1 !\ 247 ldw HPPA_FRAME_ARG(0)(sr0,sp), arg0 !\ 248 ldw HPPA_FRAME_CRP(sr0,sp) ,rp 249 #else 250 #define _PROF_PROLOGUE 251 #endif 252 253 #define LEAF_ENTRY(x) ! .text ! .align 4 !\ 254 .export x, entry ! .label x ! .proc !\ 255 .callinfo frame=0,no_calls,save_rp !\ 256 .entry ! _PROF_PROLOGUE 257 258 #define ENTRY(x,n) ! .text ! .align 4 !\ 259 .export x, entry ! .label x ! .proc !\ 260 .callinfo frame=n,calls, save_rp, save_sp !\ 261 .entry ! _PROF_PROLOGUE 262 263 #define ALTENTRY(x) ! .export x, entry ! .label x 264 #define EXIT(x) ! .exit ! .procend ! .size x, .-x 265 266 #define BSS(n,s) ! .data ! .label n ! .comm s 267 268 #define STRONG_ALIAS(alias,sym) ! .global alias ! .set alias, sym 269 #define WEAK_ALIAS(alias,sym) ! .weak alias ! .set alias, sym 270 271 #endif /* _MACHINE_ASM_H_ */ 272