1 /* $OpenBSD: cache_loongson3.c,v 1.2 2016/01/05 05:27:54 visa Exp $ */
2
3 /*
4 * Copyright (c) 2014 Miodrag Vallat.
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Cache handling code for Loongson 3A and compatible processors
21 * (including Loongson 2Gq)
22 */
23
24 #include <sys/param.h>
25 #include <sys/systm.h>
26
27 #include <mips64/cache.h>
28 #include <machine/cpu.h>
29
30 #include <uvm/uvm_extern.h>
31
32 void
Loongson3_ConfigCache(struct cpu_info * ci)33 Loongson3_ConfigCache(struct cpu_info *ci)
34 {
35 mips64r2_ConfigCache(ci);
36
37 ci->ci_SyncCache = Loongson3_SyncCache;
38 ci->ci_InvalidateICache = Loongson3_InvalidateICache;
39 ci->ci_InvalidateICachePage = Loongson3_InvalidateICachePage;
40 ci->ci_SyncICache = Loongson3_SyncICache;
41 ci->ci_SyncDCachePage = Loongson3_SyncDCachePage;
42 ci->ci_HitSyncDCachePage = Loongson3_SyncDCachePage;
43 ci->ci_HitSyncDCache = Loongson3_HitSyncDCache;
44 ci->ci_HitInvalidateDCache = Loongson3_HitInvalidateDCache;
45 ci->ci_IOSyncDCache = Loongson3_IOSyncDCache;
46 }
47
48 /*
49 * Writeback and invalidate all caches.
50 */
51 void
Loongson3_SyncCache(struct cpu_info * ci)52 Loongson3_SyncCache(struct cpu_info *ci)
53 {
54 mips_sync();
55 }
56
57 /*
58 * Invalidate I$ for the given range.
59 */
60 void
Loongson3_InvalidateICache(struct cpu_info * ci,vaddr_t va,size_t sz)61 Loongson3_InvalidateICache(struct cpu_info *ci, vaddr_t va, size_t sz)
62 {
63 /* nothing to do */
64 }
65
66 /*
67 * Register a given page for I$ invalidation.
68 */
69 void
Loongson3_InvalidateICachePage(struct cpu_info * ci,vaddr_t va)70 Loongson3_InvalidateICachePage(struct cpu_info *ci, vaddr_t va)
71 {
72 /* nothing to do */
73 }
74
75 /*
76 * Perform postponed I$ invalidation.
77 */
78 void
Loongson3_SyncICache(struct cpu_info * ci)79 Loongson3_SyncICache(struct cpu_info *ci)
80 {
81 /* nothing to do */
82 }
83
84 /*
85 * Writeback D$ for the given page.
86 */
87 void
Loongson3_SyncDCachePage(struct cpu_info * ci,vaddr_t va,paddr_t pa)88 Loongson3_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
89 {
90 /* nothing to do */
91 }
92
93 /*
94 * Writeback D$ for the given range. Range is expected to be currently
95 * mapped, allowing the use of `Hit' operations. This is less aggressive
96 * than using `Index' operations.
97 */
98
99 void
Loongson3_HitSyncDCache(struct cpu_info * ci,vaddr_t va,size_t sz)100 Loongson3_HitSyncDCache(struct cpu_info *ci, vaddr_t va, size_t sz)
101 {
102 /* nothing to do */
103 }
104
105 /*
106 * Invalidate D$ for the given range. Range is expected to be currently
107 * mapped, allowing the use of `Hit' operations. This is less aggressive
108 * than using `Index' operations.
109 */
110
111 void
Loongson3_HitInvalidateDCache(struct cpu_info * ci,vaddr_t va,size_t sz)112 Loongson3_HitInvalidateDCache(struct cpu_info *ci, vaddr_t va, size_t sz)
113 {
114 /* nothing to do */
115 }
116
117 /*
118 * Backend for bus_dmamap_sync(). Enforce coherency of the given range
119 * by performing the necessary cache writeback and/or invalidate
120 * operations.
121 */
122 void
Loongson3_IOSyncDCache(struct cpu_info * ci,vaddr_t va,size_t sz,int how)123 Loongson3_IOSyncDCache(struct cpu_info *ci, vaddr_t va, size_t sz, int how)
124 {
125 switch (how) {
126 case CACHE_SYNC_R:
127 break;
128 case CACHE_SYNC_X:
129 case CACHE_SYNC_W:
130 mips_sync(); /* XXX necessary? */
131 break;
132 }
133 }
134