| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/ |
| H A D | ppc4xx-mal.h | 33 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 497 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu60/qemu-6.0.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 498 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu42/qemu-4.2.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 739 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/ppc/ |
| H A D | ppc4xx_devs.c | 742 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu-utils/qemu-4.2.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 739 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu5/qemu-5.2.0/hw/ppc/ |
| H A D | ppc4xx_devs.c | 738 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/ppc/ |
| H A D | ppc4xx_devs.c | 738 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/ppc/ |
| H A D | ppc4xx_devs.c | 738 MAL0_TXCASR = 0x184, enumerator
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/ |
| H A D | ppc405.h | 541 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|
| H A D | ppc440.h | 641 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ macro
|