1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 QLogic Corporation. All rights reserved. 24 */ 25 26 #ifndef _QLGE_HW_H 27 #define _QLGE_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define ISP_SCHULTZ 0x8000 34 35 #define MB_REG_COUNT 8 36 #define MB_DATA_REG_COUNT (MB_REG_COUNT-1) 37 38 39 #define QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ) 40 41 /* 42 * Data bit definitions. 43 */ 44 #define BIT_0 0x1 45 #define BIT_1 0x2 46 #define BIT_2 0x4 47 #define BIT_3 0x8 48 #define BIT_4 0x10 49 #define BIT_5 0x20 50 #define BIT_6 0x40 51 #define BIT_7 0x80 52 #define BIT_8 0x100 53 #define BIT_9 0x200 54 #define BIT_10 0x400 55 #define BIT_11 0x800 56 #define BIT_12 0x1000 57 #define BIT_13 0x2000 58 #define BIT_14 0x4000 59 #define BIT_15 0x8000 60 #define BIT_16 0x10000 61 #define BIT_17 0x20000 62 #define BIT_18 0x40000 63 #define BIT_19 0x80000 64 #define BIT_20 0x100000 65 #define BIT_21 0x200000 66 #define BIT_22 0x400000 67 #define BIT_23 0x800000 68 #define BIT_24 0x1000000 69 #define BIT_25 0x2000000 70 #define BIT_26 0x4000000 71 #define BIT_27 0x8000000 72 #define BIT_28 0x10000000 73 #define BIT_29 0x20000000 74 #define BIT_30 0x40000000 75 #define BIT_31 0x80000000 76 77 typedef struct ql_stats 78 { 79 uint32_t intr_type; 80 /* software statics */ 81 uint32_t intr; 82 uint64_t speed; 83 uint32_t duplex; 84 uint32_t media; 85 /* TX */ 86 uint64_t obytes; 87 uint64_t opackets; 88 uint32_t nocarrier; 89 uint32_t defer; 90 /* RX */ 91 uint64_t rbytes; 92 uint64_t rpackets; 93 uint32_t norcvbuf; 94 uint32_t frame_too_long; 95 uint32_t crc; 96 ulong_t multircv; 97 ulong_t brdcstrcv; 98 uint32_t errrcv; 99 uint32_t frame_too_short; 100 /* statics by hw */ 101 uint32_t errxmt; 102 uint32_t frame_err; 103 ulong_t multixmt; 104 ulong_t brdcstxmt; 105 uint32_t phy_addr; 106 uint32_t jabber_err; 107 108 }ql_stats_t; 109 110 111 #define ETHERNET_CRC_SIZE 4 112 113 /* 114 * Register Definitions... 115 */ 116 #define MAILBOX_COUNT 16 117 /* System Register 0x00 */ 118 #define PROC_ADDR_RDY BIT_31 119 #define PROC_ADDR_R BIT_30 120 #define PROC_ADDR_ERR BIT_29 121 #define PROC_ADDR_DA BIT_28 122 #define PROC_ADDR_FUNC0_MBI 0x00001180 123 #define PROC_ADDR_FUNC0_MBO (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT) 124 #define PROC_ADDR_FUNC0_CTL 0x000011a1 125 #define PROC_ADDR_FUNC2_MBI 0x00001280 126 #define PROC_ADDR_FUNC2_MBO (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT) 127 #define PROC_ADDR_FUNC2_CTL 0x000012a1 128 #define PROC_ADDR_MPI_RISC 0x00000000 129 #define PROC_ADDR_MDE 0x00010000 130 #define PROC_ADDR_REGBLOCK 0x00020000 131 #define PROC_ADDR_RISC_REG 0x00030000 132 133 134 /* System Register 0x08 */ 135 #define SYSTEM_EFE_FAE 0x3u 136 #define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16) 137 enum { 138 SYS_EFE = (1 << 0), 139 SYS_FAE = (1 << 1), 140 SYS_MDC = (1 << 2), 141 SYS_DST = (1 << 3), 142 SYS_DWC = (1 << 4), 143 SYS_EVW = (1 << 5), 144 SYS_OMP_DLY_MASK = 0x3f000000, 145 /* 146 * There are no values defined as of edit #15. 147 */ 148 SYS_ODI = (1 << 14) 149 }; 150 151 /* 152 * Reset/Failover Register (RST_FO) bit definitions. 153 */ 154 155 #define RST_FO_TFO (1 << 0) 156 #define RST_FO_RR_MASK 0x00060000 157 #define RST_FO_RR_CQ_CAM 0x00000000 158 #define RST_FO_RR_DROP 0x00000001 159 #define RST_FO_RR_DQ 0x00000002 160 #define RST_FO_RR_RCV_FUNC_CQ 0x00000003 161 #define RST_FO_FRB BIT_12 162 #define RST_FO_MOP BIT_13 163 #define RST_FO_REG BIT_14 164 #define RST_FO_FR 0x8000u 165 166 /* 167 * Function Specific Control Register (FSC) bit definitions. 168 */ 169 enum { 170 FSC_DBRST_MASK = 0x00070000, 171 FSC_DBRST_256 = 0x00000000, 172 FSC_DBRST_512 = 0x00000001, 173 FSC_DBRST_768 = 0x00000002, 174 FSC_DBRST_1024 = 0x00000003, 175 FSC_DBL_MASK = 0x00180000, 176 FSC_DBL_DBRST = 0x00000000, 177 FSC_DBL_MAX_PLD = 0x00000008, 178 FSC_DBL_MAX_BRST = 0x00000010, 179 FSC_DBL_128_BYTES = 0x00000018, 180 FSC_EC = (1 << 5), 181 FSC_EPC_MASK = 0x00c00000, 182 FSC_EPC_INBOUND = (1 << 6), 183 FSC_EPC_OUTBOUND = (1 << 7), 184 FSC_VM_PAGESIZE_MASK = 0x07000000, 185 FSC_VM_PAGE_2K = 0x00000100, 186 FSC_VM_PAGE_4K = 0x00000200, 187 FSC_VM_PAGE_8K = 0x00000300, 188 FSC_VM_PAGE_64K = 0x00000600, 189 FSC_SH = (1 << 11), 190 FSC_DSB = (1 << 12), 191 FSC_STE = (1 << 13), 192 FSC_FE = (1 << 15) 193 }; 194 195 /* 196 * Host Command Status Register (CSR) bit definitions. 197 */ 198 #define CSR_ERR_STS_MASK 0x0000003f 199 /* 200 * There are no valued defined as of edit #15. 201 */ 202 #define CSR_RR BIT_8 203 #define CSR_HRI BIT_9 204 #define CSR_RP BIT_10 205 #define CSR_CMD_PARM_SHIFT 22 206 #define CSR_CMD_NOP 0x00000000 207 #define CSR_CMD_SET_RST 0x1000000 208 #define CSR_CMD_CLR_RST 0x20000000 209 #define CSR_CMD_SET_PAUSE 0x30000000 210 #define CSR_CMD_CLR_PAUSE 0x40000000 211 #define CSR_CMD_SET_H2R_INT 0x50000000 212 #define CSR_CMD_CLR_H2R_INT 0x60000000 213 #define CSR_CMD_PAR_EN 0x70000000 214 #define CSR_CMD_SET_BAD_PAR 0x80000000u 215 #define CSR_CMD_CLR_BAD_PAR 0x90000000u 216 #define CSR_CMD_CLR_R2PCI_INT 0xa0000000u 217 218 /* 219 * Configuration Register (CFG) bit definitions. 220 */ 221 enum { 222 CFG_LRQ = (1 << 0), 223 CFG_DRQ = (1 << 1), 224 CFG_LR = (1 << 2), 225 CFG_DR = (1 << 3), 226 CFG_LE = (1 << 5), 227 CFG_LCQ = (1 << 6), 228 CFG_DCQ = (1 << 7), 229 CFG_Q_SHIFT = 8, 230 CFG_Q_MASK = 0x7f000000 231 }; 232 233 /* 234 * Status Register (STS) bit definitions. 235 */ 236 enum { 237 STS_FE = (1 << 0), 238 STS_PI = (1 << 1), 239 STS_PL0 = (1 << 2), 240 STS_PL1 = (1 << 3), 241 STS_PI0 = (1 << 4), 242 STS_PI1 = (1 << 5), 243 STS_FUNC_ID_MASK = 0x000000c0, 244 STS_FUNC_ID_SHIFT = 6, 245 STS_F0E = (1 << 8), 246 STS_F1E = (1 << 9), 247 STS_F2E = (1 << 10), 248 STS_F3E = (1 << 11), 249 STS_NFE = (1 << 12) 250 }; 251 252 /* 253 * Register (REV_ID) bit definitions. 254 */ 255 enum { 256 REV_ID_MASK = 0x0000000f, 257 REV_ID_NICROLL_SHIFT = 0, 258 REV_ID_NICREV_SHIFT = 4, 259 REV_ID_XGROLL_SHIFT = 8, 260 REV_ID_XGREV_SHIFT = 12, 261 REV_ID_CHIPREV_SHIFT = 28 262 }; 263 264 /* 265 * Force ECC Error Register (FRC_ECC_ERR) bit definitions. 266 */ 267 enum { 268 FRC_ECC_ERR_VW = (1 << 12), 269 FRC_ECC_ERR_VB = (1 << 13), 270 FRC_ECC_ERR_NI = (1 << 14), 271 FRC_ECC_ERR_NO = (1 << 15), 272 FRC_ECC_PFE_SHIFT = 16, 273 FRC_ECC_ERR_DO = (1 << 18), 274 FRC_ECC_P14 = (1 << 19) 275 }; 276 277 /* 278 * Error Status Register (ERR_STS) bit definitions. 279 */ 280 enum { 281 ERR_STS_NOF = (1 << 0), 282 ERR_STS_NIF = (1 << 1), 283 ERR_STS_DRP = (1 << 2), 284 ERR_STS_XGP = (1 << 3), 285 ERR_STS_FOU = (1 << 4), 286 ERR_STS_FOC = (1 << 5), 287 ERR_STS_FOF = (1 << 6), 288 ERR_STS_FIU = (1 << 7), 289 ERR_STS_FIC = (1 << 8), 290 ERR_STS_FIF = (1 << 9), 291 ERR_STS_MOF = (1 << 10), 292 ERR_STS_TA = (1 << 11), 293 ERR_STS_MA = (1 << 12), 294 ERR_STS_MPE = (1 << 13), 295 ERR_STS_SCE = (1 << 14), 296 ERR_STS_STE = (1 << 15), 297 ERR_STS_FOW = (1 << 16), 298 ERR_STS_UE = (1 << 17), 299 ERR_STS_MCH = (1 << 26), 300 ERR_STS_LOC_SHIFT = 27 301 }; 302 303 /* 304 * Semaphore Register (SEM) bit definitions. 305 */ 306 /* 307 * Example: 308 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT) 309 */ 310 #define SEM_CLEAR 0 311 #define SEM_SET 1 312 #define SEM_FORCE 3 313 #define SEM_XGMAC0_SHIFT 0 314 #define SEM_XGMAC1_SHIFT 2 315 #define SEM_ICB_SHIFT 4 316 #define SEM_MAC_ADDR_SHIFT 6 317 #define SEM_FLASH_SHIFT 8 318 #define SEM_PROBE_SHIFT 10 319 #define SEM_RT_IDX_SHIFT 12 320 #define SEM_PROC_REG_SHIFT 14 321 #define SEM_XGMAC0_MASK 0x00030000 322 #define SEM_XGMAC1_MASK 0x000c0000 323 #define SEM_ICB_MASK 0x00300000 324 #define SEM_MAC_ADDR_MASK 0x00c00000 325 #define SEM_FLASH_MASK 0x03000000 326 #define SEM_PROBE_MASK 0x0c000000 327 #define SEM_RT_IDX_MASK 0x30000000 328 #define SEM_PROC_REG_MASK 0xc0000000 329 330 /* 331 * Stop CQ Processing Register (CQ_STOP) bit definitions. 332 */ 333 enum { 334 CQ_STOP_QUEUE_MASK = (0x007f0000), 335 CQ_STOP_TYPE_MASK = (0x03000000), 336 CQ_STOP_TYPE_START = 0x00000100, 337 CQ_STOP_TYPE_STOP = 0x00000200, 338 CQ_STOP_TYPE_READ = 0x00000300, 339 CQ_STOP_EN = (1 << 15) 340 }; 341 342 /* 343 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions. 344 */ 345 #define MAC_ADDR_IDX_SHIFT 4 346 #define MAC_ADDR_TYPE_SHIFT 16 347 #define MAC_ADDR_TYPE_MASK 0x000f0000 348 #define MAC_ADDR_TYPE_CAM_MAC 0x00000000 349 #define MAC_ADDR_TYPE_MULTI_MAC 0x00010000 350 #define MAC_ADDR_TYPE_VLAN 0x00020000 351 #define MAC_ADDR_TYPE_MULTI_FLTR 0x00030000 352 #define MAC_ADDR_TYPE_FC_MAC 0x00040000 353 #define MAC_ADDR_TYPE_MGMT_MAC 0x00050000 354 #define MAC_ADDR_TYPE_MGMT_VLAN 0x00060000 355 #define MAC_ADDR_TYPE_MGMT_V4 0x00070000 356 #define MAC_ADDR_TYPE_MGMT_V6 0x00080000 357 #define MAC_ADDR_TYPE_MGMT_TU_DP 0x00090000 358 #define MAC_ADDR_ADR BIT_25 359 #define MAC_ADDR_RS BIT_26 360 #define MAC_ADDR_E BIT_27 361 #define MAC_ADDR_MR BIT_30 362 #define MAC_ADDR_MW BIT_31 363 #define MAX_MULTICAST_HW_SIZE 32 364 365 /* 366 * MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions. 367 */ 368 #define SPLT_HDR_EP BIT_31 369 370 /* 371 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions. 372 */ 373 enum { 374 NIC_RCV_CFG_PPE = (1 << 0), 375 NIC_RCV_CFG_VLAN_MASK = 0x00060000, 376 NIC_RCV_CFG_VLAN_ALL = 0x00000000, 377 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002, 378 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004, 379 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006, 380 NIC_RCV_CFG_RV = (1 << 3), 381 NIC_RCV_CFG_DFQ_MASK = (0x7f000000), 382 NIC_RCV_CFG_DFQ_SHIFT = 8, 383 NIC_RCV_CFG_DFQ = 0 /* HARDCODE default queue to 0. */ 384 }; 385 386 /* 387 * Routing Index Register (RT_IDX) bit definitions. 388 */ 389 #define RT_IDX_IDX_SHIFT 8 390 #define RT_IDX_TYPE_MASK 0x000f0000 391 #define RT_IDX_TYPE_RT 0x00000000 392 #define RT_IDX_TYPE_RT_INV 0x00010000 393 #define RT_IDX_TYPE_NICQ 0x00020000 394 #define RT_IDX_TYPE_NICQ_INV 0x00030000 395 #define RT_IDX_DST_MASK 0x00700000 396 #define RT_IDX_DST_RSS 0x00000000 397 #define RT_IDX_DST_CAM_Q 0x00100000 398 #define RT_IDX_DST_COS_Q 0x00200000 399 #define RT_IDX_DST_DFLT_Q 0x00300000 400 #define RT_IDX_DST_DEST_Q 0x00400000 401 #define RT_IDX_RS BIT_26 402 #define RT_IDX_E BIT_27 403 #define RT_IDX_MR BIT_30 404 #define RT_IDX_MW BIT_31 405 406 /* Nic Queue format - type 2 bits */ 407 #define RT_IDX_BCAST 1 408 #define RT_IDX_MCAST BIT_1 409 #define RT_IDX_MCAST_MATCH BIT_2 410 #define RT_IDX_MCAST_REG_MATCH BIT_3 411 #define RT_IDX_MCAST_HASH_MATCH BIT_4 412 #define RT_IDX_FC_MACH BIT_5 413 #define RT_IDX_ETH_FCOE BIT_6 414 #define RT_IDX_CAM_HIT BIT_7 415 #define RT_IDX_CAM_BIT0 BIT_8 416 #define RT_IDX_CAM_BIT1 BIT_9 417 #define RT_IDX_VLAN_TAG BIT_10 418 #define RT_IDX_VLAN_MATCH BIT_11 419 #define RT_IDX_VLAN_FILTER BIT_12 420 #define RT_IDX_ETH_SKIP1 BIT_13 421 #define RT_IDX_ETH_SKIP2 BIT_14 422 #define RT_IDX_BCAST_MCAST_MATCH BIT_15 423 #define RT_IDX_802_3 BIT_16 424 #define RT_IDX_LLDP BIT_17 425 #define RT_IDX_UNUSED018 BIT_18 426 #define RT_IDX_UNUSED019 BIT_19 427 #define RT_IDX_UNUSED20 BIT_20 428 #define RT_IDX_UNUSED21 BIT_21 429 #define RT_IDX_ERR BIT_22 430 #define RT_IDX_VALID BIT_23 431 #define RT_IDX_TU_CSUM_ERR BIT_24 432 #define RT_IDX_IP_CSUM_ERR BIT_25 433 #define RT_IDX_MAC_ERR BIT_26 434 #define RT_IDX_RSS_TCP6 BIT_27 435 #define RT_IDX_RSS_TCP4 BIT_28 436 #define RT_IDX_RSS_IPV6 BIT_29 437 #define RT_IDX_RSS_IPV4 BIT_30 438 #define RT_IDX_RSS_MATCH BIT_31 439 440 /* Hierarchy for the NIC Queue Mask */ 441 enum { 442 RT_IDX_ALL_ERR_SLOT = 0, 443 RT_IDX_MAC_ERR_SLOT = 0, 444 RT_IDX_IP_CSUM_ERR_SLOT = 1, 445 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, 446 RT_IDX_BCAST_SLOT = 3, 447 RT_IDX_MCAST_MATCH_SLOT = 4, 448 RT_IDX_ALLMULTI_SLOT = 5, 449 RT_IDX_UNUSED6_SLOT = 6, 450 RT_IDX_UNUSED7_SLOT = 7, 451 RT_IDX_RSS_MATCH_SLOT = 8, 452 RT_IDX_RSS_IPV4_SLOT = 8, 453 RT_IDX_RSS_IPV6_SLOT = 9, 454 RT_IDX_RSS_TCP4_SLOT = 10, 455 RT_IDX_RSS_TCP6_SLOT = 11, 456 RT_IDX_CAM_HIT_SLOT = 12, 457 RT_IDX_UNUSED013 = 13, 458 RT_IDX_UNUSED014 = 14, 459 RT_IDX_PROMISCUOUS_SLOT = 15, 460 RT_IDX_MAX_SLOTS = 16 461 }; 462 463 enum { 464 CAM_OUT_ROUTE_FC = 0, 465 CAM_OUT_ROUTE_NIC = 1, 466 CAM_OUT_FUNC_SHIFT = 2, 467 CAM_OUT_RV = (1 << 4), 468 CAM_OUT_SH = (1 << 15), 469 CAM_OUT_CQ_ID_SHIFT = 5 470 }; 471 472 /* Reset/Failover Register 0C */ 473 #define FUNCTION_RESET 0x8000u 474 #define FUNCTION_RESET_MASK (FUNCTION_RESET<<16) 475 476 /* Function Specific Control Register 0x10 */ 477 #define FSC_MASK (0x97ffu << 16) 478 #define FSC_FE 0x8000 479 480 /* Configuration Register 0x28 */ 481 #define LOAD_LCQ 0x40 482 #define LOAD_LCQ_MASK (0x7F40u << 16) 483 #define LOAD_ICB_ERR 0x20 484 #define LOAD_LRQ 0x01 485 #define LOAD_LRQ_MASK (0x7F01u << 16) 486 487 #define FN0_NET 0 488 #define FN1_NET 1 489 #define FN0_FC 2 490 #define FN1_FC 3 491 492 /* 493 * Semaphore Register (SEM) bit definitions. 494 */ 495 #define SEM_CLEAR 0 496 #define SEM_SET 1 497 #define SEM_FORCE 3 498 #define SEM_XGMAC0_SHIFT 0 499 #define SEM_XGMAC1_SHIFT 2 500 #define SEM_ICB_SHIFT 4 501 #define SEM_MAC_ADDR_SHIFT 6 502 #define SEM_FLASH_SHIFT 8 503 #define SEM_PROBE_SHIFT 10 504 #define SEM_RT_IDX_SHIFT 12 505 #define SEM_PROC_REG_SHIFT 14 506 #define SEM_XGMAC0_MASK 0x00030000 507 #define SEM_XGMAC1_MASK 0x000c0000 508 #define SEM_ICB_MASK 0x00300000 509 #define SEM_MAC_ADDR_MASK 0x00c00000 510 #define SEM_FLASH_MASK 0x03000000 511 #define SEM_PROBE_MASK 0x0c000000 512 #define SEM_RT_IDX_MASK 0x30000000 513 #define SEM_PROC_REG_MASK 0xc0000000 514 515 /* System Register 0x08 */ 516 #define SYSTEM_EFE_FAE 0x3u 517 #define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16) 518 519 /* Interrupt Status Register-1 0x3C */ 520 #define CQ_0_NOT_EMPTY BIT_0 521 #define CQ_1_NOT_EMPTY BIT_1 522 #define CQ_2_NOT_EMPTY BIT_2 523 #define CQ_3_NOT_EMPTY BIT_3 524 #define CQ_4_NOT_EMPTY BIT_4 525 #define CQ_5_NOT_EMPTY BIT_5 526 #define CQ_6_NOT_EMPTY BIT_6 527 #define CQ_7_NOT_EMPTY BIT_7 528 #define CQ_8_NOT_EMPTY BIT_8 529 #define CQ_9_NOT_EMPTY BIT_9 530 #define CQ_10_NOT_EMPTY BIT_10 531 #define CQ_11_NOT_EMPTY BIT_11 532 #define CQ_12_NOT_EMPTY BIT_12 533 #define CQ_13_NOT_EMPTY BIT_13 534 #define CQ_14_NOT_EMPTY BIT_14 535 #define CQ_15_NOT_EMPTY BIT_15 536 #define CQ_16_NOT_EMPTY BIT_16 537 /* Processor Address Register 0x00 */ 538 #define PROCESSOR_ADDRESS_RDY (0x8000u<<16) 539 #define PROCESSOR_ADDRESS_READ (0x4000u<<16) 540 /* Host Command/Status Register 0x14 */ 541 #define HOST_CMD_SET_RISC_RESET 0x10000000u 542 #define HOST_CMD_CLEAR_RISC_RESET 0x20000000u 543 #define HOST_CMD_SET_RISC_PAUSE 0x30000000u 544 #define HOST_CMD_RELEASE_RISC_PAUSE 0x40000000u 545 #define HOST_CMD_SET_RISC_INTR 0x50000000u 546 #define HOST_CMD_CLEAR_RISC_INTR 0x60000000u 547 #define HOST_CMD_SET_PARITY_ENABLE 0x70000000u 548 #define HOST_CMD_FORCE_BAD_PARITY 0x80000000u 549 #define HOST_CMD_RELEASE_BAD_PARITY 0x90000000u 550 #define HOST_CMD_CLEAR_RISC_TO_HOST_INTR 0xA0000000u 551 #define HOST_TO_MPI_INTR_NOT_DONE 0x200 552 553 #define RISC_RESET BIT_8 554 #define RISC_PAUSED BIT_10 555 /* Semaphor Register 0x64 */ 556 #define QL_SEM_BITS_BASE_CODE 0x1u 557 #define QL_PORT0_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE) 558 #define QL_PORT1_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE << 2) 559 #define QL_ICB_ACCESS_ADDRESS_SEM_BITS (QL_SEM_BITS_BASE_CODE << 4) 560 #define QL_MAC_PROTOCOL_SEM_BITS (QL_SEM_BITS_BASE_CODE << 6) 561 #define QL_FLASH_SEM_BITS (QL_SEM_BITS_BASE_CODE << 8) 562 #define QL_PROBE_MUX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 10) 563 #define QL_ROUTING_INDEX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 12) 564 #define QL_PROCESSOR_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14) 565 #define QL_NIC_RECV_CONFIG_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14) 566 567 #define QL_SEM_MASK_BASE_CODE 0x30000u 568 #define QL_PORT0_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE) 569 #define QL_PORT1_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE << 2) 570 #define QL_ICB_ACCESS_ADDRESS_SEM_MASK (QL_SEM_MASK_BASE_CODE << 4) 571 #define QL_MAC_PROTOCOL_SEM_MASK (QL_SEM_MASK_BASE_CODE << 6) 572 #define QL_FLASH_SEM_MASK (QL_SEM_MASK_BASE_CODE << 8) 573 #define QL_PROBE_MUX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 10) 574 #define QL_ROUTING_INDEX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 12) 575 #define QL_PROCESSOR_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14) 576 #define QL_NIC_RECV_CONFIG_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14) 577 578 /* XGMAC Address Register 0x78 */ 579 #define XGMAC_ADDRESS_RDY (0x8000u<<16) 580 #define XGMAC_ADDRESS_READ_TRANSACT (0x4000u<<16) 581 #define XGMAC_ADDRESS_ACCESS_ERROR (0x2000u<<16) 582 583 /* XGMAC Register Set */ 584 #define REG_XGMAC_GLOBAL_CONFIGURATION 0x108 585 #define GLOBAL_CONFIG_JUMBO_MODE 0x40 586 587 #define REG_XGMAC_MAC_TX_CONFIGURATION 0x10C 588 #define XGMAC_MAC_TX_ENABLE 0x02 589 590 #define REG_XGMAC_MAC_RX_CONFIGURATION 0x110 591 #define XGMAC_MAC_RX_ENABLE 0x02 592 593 #define REG_XGMAC_FLOW_CONTROL 0x11C 594 595 #define REG_XGMAC_MAC_TX_PARAM 0x134 596 #define REG_XGMAC_MAC_RX_PARAM 0x138 597 598 #define REG_XGMAC_MAC_TX_PKTS 0x200 599 #define REG_XGMAC_MAC_TX_OCTETS 0x208 600 #define REG_XGMAC_MAC_TX_MULTCAST_PKTS 0x210 601 #define REG_XGMAC_MAC_TX_BROADCAST_PKTS 0x218 602 #define REG_XGMAC_MAC_TX_PAUSE_PKTS 0x230 603 604 #define REG_XGMAC_MAC_RX_OCTETS 0x300 605 #define REG_XGMAC_MAC_RX_OCTETS_OK 0x308 606 #define REG_XGMAC_MAC_RX_PKTS 0x310 607 #define REG_XGMAC_MAC_RX_PKTS_OK 0x318 608 #define REG_XGMAC_MAC_RX_BROADCAST_PKTS 0x320 609 #define REG_XGMAC_MAC_RX_MULTCAST_PKTS 0x328 610 #define REG_XGMAC_MAC_RX_JABBER_PKTS 0x348 611 #define REG_XGMAC_MAC_FCS_ERR 0x360 612 #define REG_XGMAC_MAC_ALIGN_ERR 0x368 613 #define REG_XGMAC_MAC_RX_SYM_ERR 0x370 614 #define REG_XGMAC_MAC_RX_INT_ERR 0x378 615 #define REG_XGMAC_MAC_RX_PAUSE_PKTS 0x388 616 #define REG_XGMAC_MAC_PHY_ADDR 0x430 617 #define REG_XGMAC_MAC_RX_FIFO_DROPS 0x5B8 618 619 620 /* MAC Protocol Address Index Register Set 0xA8 */ 621 #define MAC_PROTOCOL_ADDRESS_INDEX_MW (0x8000u<<16) 622 #define MAC_PROTOCOL_ADDRESS_ENABLE (1 << 27) 623 #define MAC_PROTOCOL_TYPE_CAM_MAC (0x0) 624 #define MAC_PROTOCOL_TYPE_MULTICAST (0x10000u) 625 626 /* NIC Receive Configuration Register 0xD4 */ 627 #define RECV_CONFIG_DEFAULT_Q_MASK (0x7F000000u) 628 #define RECV_CONFIG_VTAG_REMOVAL_MASK (0x80000u) 629 #define RECV_CONFIG_VTAG_RV 0x08 630 631 /* 632 * 10G MAC Address Register (XGMAC_ADDR) bit definitions. 633 */ 634 #define XGMAC_ADDR_RDY (1 << 31) 635 #define XGMAC_ADDR_R (1 << 30) 636 #define XGMAC_ADDR_XME (1 << 29) 637 638 #define PAUSE_SRC_LO 0x00000100 639 #define PAUSE_SRC_HI 0x00000104 640 #define GLOBAL_CFG 0x00000108 641 #define GLOBAL_CFG_RESET (1 << 0) 642 #define GLOBAL_CFG_JUMBO (1 << 6) 643 #define GLOBAL_CFG_TX_STAT_EN (1 << 10) 644 #define GLOBAL_CFG_RX_STAT_EN (1 << 11) 645 #define TX_CFG 0x0000010c 646 #define TX_CFG_RESET (1 << 0) 647 #define TX_CFG_EN (1 << 1) 648 #define TX_CFG_PREAM (1 << 2) 649 #define RX_CFG 0x00000110 650 #define RX_CFG_RESET (1 << 0) 651 #define RX_CFG_EN (1 << 1) 652 #define RX_CFG_PREAM (1 << 2) 653 #define FLOW_CTL 0x0000011c 654 #define PAUSE_OPCODE 0x00000120 655 #define PAUSE_TIMER 0x00000124 656 #define PAUSE_FRM_DEST_LO 0x00000128 657 #define PAUSE_FRM_DEST_HI 0x0000012c 658 #define MAC_TX_PARAMS 0x00000134 659 #define MAC_TX_PARAMS_JUMBO (1 << 31) 660 #define MAC_TX_PARAMS_SIZE_SHIFT 16 661 #define MAC_RX_PARAMS 0x00000138 662 #define MAC_SYS_INT 0x00000144 663 #define MAC_SYS_INT_MASK 0x00000148 664 #define MAC_MGMT_INT 0x0000014c 665 #define MAC_MGMT_IN_MASK 0x00000150 666 #define EXT_ARB_MODE 0x000001fc 667 #define TX_PKTS 0x00000200 668 #define TX_PKTS_LO 0x00000204 669 #define TX_BYTES 0x00000208 670 #define TX_BYTES_LO 0x0000020C 671 #define TX_MCAST_PKTS 0x00000210 672 #define TX_MCAST_PKTS_LO 0x00000214 673 #define TX_BCAST_PKTS 0x00000218 674 #define TX_BCAST_PKTS_LO 0x0000021C 675 #define TX_UCAST_PKTS 0x00000220 676 #define TX_UCAST_PKTS_LO 0x00000224 677 #define TX_CTL_PKTS 0x00000228 678 #define TX_CTL_PKTS_LO 0x0000022c 679 #define TX_PAUSE_PKTS 0x00000230 680 #define TX_PAUSE_PKTS_LO 0x00000234 681 #define TX_64_PKT 0x00000238 682 #define TX_64_PKT_LO 0x0000023c 683 #define TX_65_TO_127_PKT 0x00000240 684 #define TX_65_TO_127_PKT_LO 0x00000244 685 #define TX_128_TO_255_PKT 0x00000248 686 #define TX_128_TO_255_PKT_LO 0x0000024c 687 #define TX_256_511_PKT 0x00000250 688 #define TX_256_511_PKT_LO 0x00000254 689 #define TX_512_TO_1023_PKT 0x00000258 690 #define TX_512_TO_1023_PKT_LO 0x0000025c 691 #define TX_1024_TO_1518_PKT 0x00000260 692 #define TX_1024_TO_1518_PKT_LO 0x00000264 693 #define TX_1519_TO_MAX_PKT 0x00000268 694 #define TX_1519_TO_MAX_PKT_LO 0x0000026c 695 #define TX_UNDERSIZE_PKT 0x00000270 696 #define TX_UNDERSIZE_PKT_LO 0x00000274 697 #define TX_OVERSIZE_PKT 0x00000278 698 #define TX_OVERSIZE_PKT_LO 0x0000027c 699 #define RX_HALF_FULL_DET 0x000002a0 700 #define TX_HALF_FULL_DET_LO 0x000002a4 701 #define RX_OVERFLOW_DET 0x000002a8 702 #define TX_OVERFLOW_DET_LO 0x000002ac 703 #define RX_HALF_FULL_MASK 0x000002b0 704 #define TX_HALF_FULL_MASK_LO 0x000002b4 705 #define RX_OVERFLOW_MASK 0x000002b8 706 #define TX_OVERFLOW_MASK_LO 0x000002bc 707 #define STAT_CNT_CTL 0x000002c0 708 #define STAT_CNT_CTL_CLEAR_TX (1 << 0) /* Control */ 709 #define STAT_CNT_CTL_CLEAR_RX (1 << 1) /* Control */ 710 #define AUX_RX_HALF_FULL_DET 0x000002d0 711 #define AUX_TX_HALF_FULL_DET 0x000002d4 712 #define AUX_RX_OVERFLOW_DET 0x000002d8 713 #define AUX_TX_OVERFLOW_DET 0x000002dc 714 #define AUX_RX_HALF_FULL_MASK 0x000002f0 715 #define AUX_TX_HALF_FULL_MASK 0x000002f4 716 #define AUX_RX_OVERFLOW_MASK 0x000002f8 717 #define AUX_TX_OVERFLOW_MASK 0x000002fc 718 #define RX_BYTES 0x00000300 719 #define RX_BYTES_LO 0x00000304 720 #define RX_BYTES_OK 0x00000308 721 #define RX_BYTES_OK_LO 0x0000030c 722 #define RX_PKTS 0x00000310 723 #define RX_PKTS_LO 0x00000314 724 #define RX_PKTS_OK 0x00000318 725 #define RX_PKTS_OK_LO 0x0000031c 726 #define RX_BCAST_PKTS 0x00000320 727 #define RX_BCAST_PKTS_LO 0x00000324 728 #define RX_MCAST_PKTS 0x00000328 729 #define RX_MCAST_PKTS_LO 0x0000032c 730 #define RX_UCAST_PKTS 0x00000330 731 #define RX_UCAST_PKTS_LO 0x00000334 732 #define RX_UNDERSIZE_PKTS 0x00000338 733 #define RX_UNDERSIZE_PKTS_LO 0x0000033c 734 #define RX_OVERSIZE_PKTS 0x00000340 735 #define RX_OVERSIZE_PKTS_LO 0x00000344 736 #define RX_JABBER_PKTS 0x00000348 737 #define RX_JABBER_PKTS_LO 0x0000034c 738 #define RX_UNDERSIZE_FCERR_PKTS 0x00000350 739 #define RX_UNDERSIZE_FCERR_PKTS_LO 0x00000354 740 #define RX_DROP_EVENTS 0x00000358 741 #define RX_DROP_EVENTS_LO 0x0000035c 742 #define RX_FCERR_PKTS 0x00000360 743 #define RX_FCERR_PKTS_LO 0x00000364 744 #define RX_ALIGN_ERR 0x00000368 745 #define RX_ALIGN_ERR_LO 0x0000036c 746 #define RX_SYMBOL_ERR 0x00000370 747 #define RX_SYMBOL_ERR_LO 0x00000374 748 #define RX_MAC_ERR 0x00000378 749 #define RX_MAC_ERR_LO 0x0000037c 750 #define RX_CTL_PKTS 0x00000380 751 #define RX_CTL_PKTS_LO 0x00000384 752 #define RX_PAUSE_PKTS 0x00000388 753 #define RX_PAUSE_PKTS_LO 0x0000038c 754 #define RX_64_PKTS 0x00000390 755 #define RX_64_PKTS_LO 0x00000394 756 #define RX_65_TO_127_PKTS 0x00000398 757 #define RX_65_TO_127_PKTS_LO 0x0000039c 758 #define RX_128_255_PKTS 0x000003a0 759 #define RX_128_255_PKTS_LO 0x000003a4 760 #define RX_256_511_PKTS 0x000003a8 761 #define RX_256_511_PKTS_LO 0x000003ac 762 #define RX_512_TO_1023_PKTS 0x000003b0 763 #define RX_512_TO_1023_PKTS_LO 0x000003b4 764 #define RX_1024_TO_1518_PKTS 0x000003b8 765 #define RX_1024_TO_1518_PKTS_LO 0x000003bc 766 #define RX_1519_TO_MAX_PKTS 0x000003c0 767 #define RX_1519_TO_MAX_PKTS_LO 0x000003c4 768 #define RX_LEN_ERR_PKTS 0x000003c8 769 #define RX_LEN_ERR_PKTS_LO 0x000003cc 770 #define MDIO_TX_DATA 0x00000400 771 #define MDIO_RX_DATA 0x00000410 772 #define MDIO_CMD 0x00000420 773 #define MDIO_PHY_ADDR 0x00000430 774 #define MDIO_PORT 0x00000440 775 #define MDIO_STATUS 0x00000450 776 #define TX_CBFC_PAUSE_FRAMES0 0x00000500 777 #define TX_CBFC_PAUSE_FRAMES0_LO 0x00000504 778 #define TX_CBFC_PAUSE_FRAMES1 0x00000508 779 #define TX_CBFC_PAUSE_FRAMES1_LO 0x0000050C 780 #define TX_CBFC_PAUSE_FRAMES2 0x00000510 781 #define TX_CBFC_PAUSE_FRAMES2_LO 0x00000514 782 #define TX_CBFC_PAUSE_FRAMES3 0x00000518 783 #define TX_CBFC_PAUSE_FRAMES3_LO 0x0000051C 784 #define TX_CBFC_PAUSE_FRAMES4 0x00000520 785 #define TX_CBFC_PAUSE_FRAMES4_LO 0x00000524 786 #define TX_CBFC_PAUSE_FRAMES5 0x00000528 787 #define TX_CBFC_PAUSE_FRAMES5_LO 0x0000052C 788 #define TX_CBFC_PAUSE_FRAMES6 0x00000530 789 #define TX_CBFC_PAUSE_FRAMES6_LO 0x00000534 790 #define TX_CBFC_PAUSE_FRAMES7 0x00000538 791 #define TX_CBFC_PAUSE_FRAMES7_LO 0x0000053C 792 #define TX_FCOE_PKTS 0x00000540 793 #define TX_FCOE_PKTS_LO 0x00000544 794 #define TX_MGMT_PKTS 0x00000548 795 #define TX_MGMT_PKTS_LO 0x0000054C 796 #define RX_CBFC_PAUSE_FRAMES0 0x00000568 797 #define RX_CBFC_PAUSE_FRAMES0_LO 0x0000056C 798 #define RX_CBFC_PAUSE_FRAMES1 0x00000570 799 #define RX_CBFC_PAUSE_FRAMES1_LO 0x00000574 800 #define RX_CBFC_PAUSE_FRAMES2 0x00000578 801 #define RX_CBFC_PAUSE_FRAMES2_LO 0x0000057C 802 #define RX_CBFC_PAUSE_FRAMES3 0x00000580 803 #define RX_CBFC_PAUSE_FRAMES3_LO 0x00000584 804 #define RX_CBFC_PAUSE_FRAMES4 0x00000588 805 #define RX_CBFC_PAUSE_FRAMES4_LO 0x0000058C 806 #define RX_CBFC_PAUSE_FRAMES5 0x00000590 807 #define RX_CBFC_PAUSE_FRAMES5_LO 0x00000594 808 #define RX_CBFC_PAUSE_FRAMES6 0x00000598 809 #define RX_CBFC_PAUSE_FRAMES6_LO 0x0000059C 810 #define RX_CBFC_PAUSE_FRAMES7 0x000005A0 811 #define RX_CBFC_PAUSE_FRAMES7_LO 0x000005A4 812 #define RX_FCOE_PKTS 0x000005A8 813 #define RX_FCOE_PKTS_LO 0x000005AC 814 #define RX_MGMT_PKTS 0x000005B0 815 #define RX_MGMT_PKTS_LO 0x000005B4 816 #define RX_NIC_FIFO_DROP 0x000005B8 817 #define RX_NIC_FIFO_DROP_LO 0x000005BC 818 #define RX_FCOE_FIFO_DROP 0x000005C0 819 #define RX_FCOE_FIFO_DROP_LO 0x000005C4 820 #define RX_MGMT_FIFO_DROP 0x000005C8 821 #define RX_MGMT_FIFO_DROP_LO 0x000005CC 822 #define RX_PKTS_PRIORITY0 0x00000600 823 #define RX_PKTS_PRIORITY0_LO 0x00000604 824 #define RX_PKTS_PRIORITY1 0x00000608 825 #define RX_PKTS_PRIORITY1_LO 0x0000060C 826 #define RX_PKTS_PRIORITY2 0x00000610 827 #define RX_PKTS_PRIORITY2_LO 0x00000614 828 #define RX_PKTS_PRIORITY3 0x00000618 829 #define RX_PKTS_PRIORITY3_LO 0x0000061C 830 #define RX_PKTS_PRIORITY4 0x00000620 831 #define RX_PKTS_PRIORITY4_LO 0x00000624 832 #define RX_PKTS_PRIORITY5 0x00000628 833 #define RX_PKTS_PRIORITY5_LO 0x0000062C 834 #define RX_PKTS_PRIORITY6 0x00000630 835 #define RX_PKTS_PRIORITY6_LO 0x00000634 836 #define RX_PKTS_PRIORITY7 0x00000638 837 #define RX_PKTS_PRIORITY7_LO 0x0000063C 838 #define RX_OCTETS_PRIORITY0 0x00000640 839 #define RX_OCTETS_PRIORITY0_LO 0x00000644 840 #define RX_OCTETS_PRIORITY1 0x00000648 841 #define RX_OCTETS_PRIORITY1_LO 0x0000064C 842 #define RX_OCTETS_PRIORITY2 0x00000650 843 #define RX_OCTETS_PRIORITY2_LO 0x00000654 844 #define RX_OCTETS_PRIORITY3 0x00000658 845 #define RX_OCTETS_PRIORITY3_LO 0x0000065C 846 #define RX_OCTETS_PRIORITY4 0x00000660 847 #define RX_OCTETS_PRIORITY4_LO 0x00000664 848 #define RX_OCTETS_PRIORITY5 0x00000668 849 #define RX_OCTETS_PRIORITY5_LO 0x0000066C 850 #define RX_OCTETS_PRIORITY6 0x00000670 851 #define RX_OCTETS_PRIORITY6_LO 0x00000674 852 #define RX_OCTETS_PRIORITY7 0x00000678 853 #define RX_OCTETS_PRIORITY7_LO 0x0000067C 854 #define TX_PKTS_PRIORITY0 0x00000680 855 #define TX_PKTS_PRIORITY0_LO 0x00000684 856 #define TX_PKTS_PRIORITY1 0x00000688 857 #define TX_PKTS_PRIORITY1_LO 0x0000068C 858 #define TX_PKTS_PRIORITY2 0x00000690 859 #define TX_PKTS_PRIORITY2_LO 0x00000694 860 #define TX_PKTS_PRIORITY3 0x00000698 861 #define TX_PKTS_PRIORITY3_LO 0x0000069C 862 #define TX_PKTS_PRIORITY4 0x000006A0 863 #define TX_PKTS_PRIORITY4_LO 0x000006A4 864 #define TX_PKTS_PRIORITY5 0x000006A8 865 #define TX_PKTS_PRIORITY5_LO 0x000006AC 866 #define TX_PKTS_PRIORITY6 0x000006B0 867 #define TX_PKTS_PRIORITY6_LO 0x000006B4 868 #define TX_PKTS_PRIORITY7 0x000006B8 869 #define TX_PKTS_PRIORITY7_LO 0x000006BC 870 #define TX_OCTETS_PRIORITY0 0x000006C0 871 #define TX_OCTETS_PRIORITY0_LO 0x000006C4 872 #define TX_OCTETS_PRIORITY1 0x000006C8 873 #define TX_OCTETS_PRIORITY1_LO 0x000006CC 874 #define TX_OCTETS_PRIORITY2 0x000006D0 875 #define TX_OCTETS_PRIORITY2_LO 0x000006D4 876 #define TX_OCTETS_PRIORITY3 0x000006D8 877 #define TX_OCTETS_PRIORITY3_LO 0x000006DC 878 #define TX_OCTETS_PRIORITY4 0x000006E0 879 #define TX_OCTETS_PRIORITY4_LO 0x000006E4 880 #define TX_OCTETS_PRIORITY5 0x000006E8 881 #define TX_OCTETS_PRIORITY5_LO 0x000006EC 882 #define TX_OCTETS_PRIORITY6 0x000006F0 883 #define TX_OCTETS_PRIORITY6_LO 0x000006F4 884 #define TX_OCTETS_PRIORITY7 0x000006F8 885 #define TX_OCTETS_PRIORITY7_LO 0x000006FC 886 #define RX_DISCARD_PRIORITY0 0x00000700 887 #define RX_DISCARD_PRIORITY0_LO 0x00000704 888 #define RX_DISCARD_PRIORITY1 0x00000708 889 #define RX_DISCARD_PRIORITY1_LO 0x0000070C 890 #define RX_DISCARD_PRIORITY2 0x00000710 891 #define RX_DISCARD_PRIORITY2_LO 0x00000714 892 #define RX_DISCARD_PRIORITY3 0x00000718 893 #define RX_DISCARD_PRIORITY3_LO 0x0000071C 894 #define RX_DISCARD_PRIORITY4 0x00000720 895 #define RX_DISCARD_PRIORITY4_LO 0x00000724 896 #define RX_DISCARD_PRIORITY5 0x00000728 897 #define RX_DISCARD_PRIORITY5_LO 0x0000072C 898 #define RX_DISCARD_PRIORITY6 0x00000730 899 #define RX_DISCARD_PRIORITY6_LO 0x00000734 900 #define RX_DISCARD_PRIORITY7 0x00000738 901 #define RX_DISCARD_PRIORITY7_LO 0x0000073C 902 903 904 #define CQ0_ID 0x0 905 #define NIC_CORE 0x1 906 /* Routing Index Register 0xE4 */ 907 #define ROUTING_INDEX_MW BIT_31 908 #define ROUTING_INDEX_DEFAULT_ENABLE_MASK (0x8320000u) 909 #define ROUTING_INDEX_DEFAULT_DISABLE_MASK (0x0320000u) 910 911 /* Routing Data Register 0xE8 */ 912 #define ROUTE_AS_CAM_HIT 0x80 913 #define ROUTE_AS_BCAST_MCAST_MATCH 0x8000u 914 #define ROUTE_AS_VALID_PKT 0x800000u /* promiscuous mode? */ 915 916 enum { 917 ROUTING_MASK_INDEX_CAM_HIT, 918 ROUTING_MASK_INDEX_BCAST_MCAST_MATCH, 919 ROUTING_MASK_INDEX_VALID_PKT, 920 ROUTING_MASK_INDEX_TOTAL 921 }; 922 923 #define ROUTING_MASK_INDEX_MAX 16 924 /* 925 * General definitions... 926 */ 927 928 /* 929 * Below are a number compiler switches for controlling driver behavior. 930 * Some are not supported under certain conditions and are notated as such. 931 */ 932 933 /* MTU & Frame Size stuff */ 934 #define JUMBO_MTU 9000 935 #define NORMAL_FRAME_SIZE 2500 /* ETHERMTU,1500 */ 936 #define JUMBO_FRAME_SIZE 9600 937 #define LRG_BUF_NORMAL_SIZE NORMAL_FRAME_SIZE 938 #define LRG_BUF_JUMBO_SIZE JUMBO_FRAME_SIZE 939 #define VLAN_ID_LEN 2 940 #define VLAN_HEADER_LEN sizeof (struct ether_vlan_header) /* 18 */ 941 #define ETHER_HEADER_LEN sizeof (struct ether_header) /* 14 */ 942 943 #define NUM_TX_RING_ENTRIES (1024) 944 #define NUM_RX_RING_ENTRIES (1024) 945 946 #define NUM_SMALL_BUFFERS (1024) 947 #define NUM_LARGE_BUFFERS (1024) 948 949 #define RX_TX_RING_SHADOW_SPACE 2 /* 1st one is wqicb and 2nd for cqicb */ 950 #define BUF_Q_PTR_SPACE ((((NUM_SMALL_BUFFERS * sizeof (uint64_t)) \ 951 / VM_PAGE_SIZE) + 1) + \ 952 (((NUM_LARGE_BUFFERS * sizeof (uint64_t)) \ 953 / VM_PAGE_SIZE) + 1)) 954 955 #define MAX_CQ 128 956 #define DFLT_RX_COALESCE_WAIT 90 /* usec wait for coalescing */ 957 #define DFLT_RX_INTER_FRAME_WAIT 30 /* max interframe-wait for */ 958 /* coalescing */ 959 #define DFLT_TX_COALESCE_WAIT 90 /* usec wait for coalescing */ 960 #define DFLT_TX_INTER_FRAME_WAIT 30 /* max interframe-wait for */ 961 /* coalescing */ 962 #define DFLT_RX_COALESCE_WAIT_JUMBO 40 /* usec wait for coalescing */ 963 #define DFLT_RX_INTER_FRAME_WAIT_JUMBO 10 /* max interframe-wait for */ 964 /* coalescing */ 965 #define DFLT_TX_COALESCE_WAIT_JUMBO 40 /* usec wait for coalescing */ 966 #define DFLT_TX_INTER_FRAME_WAIT_JUMBO 10 /* max interframe-wait for */ 967 /* coalescing */ 968 #define DFLT_PAYLOAD_COPY_THRESH 6 /* must be at least 6 usec */ 969 970 #define UDELAY_COUNT 3 971 #define UDELAY_DELAY 10 972 973 #define MAX_RX_RINGS 128 974 #define MAX_TX_RINGS 16 975 976 /* 977 * Large & Small Buffers for Receives 978 */ 979 struct lrg_buf_q_entry { 980 uint32_t addr0_lower; 981 #define IAL_LAST_ENTRY 0x00000001 982 #define IAL_CONT_ENTRY 0x00000002 983 #define IAL_FLAG_MASK 0x00000003 984 uint32_t addr0_upper; 985 }; 986 987 struct bufq_addr_element { 988 uint32_t addr_low; 989 uint32_t addr_high; 990 }; 991 992 #define QL_NO_RESET 0 993 #define QL_DO_RESET 1 994 995 /* Link must be in one of these states */ 996 enum link_state_t { 997 LS_DOWN, 998 LS_UP 999 }; 1000 1001 /* qlge->flags definitions. */ 1002 #define INTERRUPTS_ENABLED BIT_0 1003 #define ADAPTER_ERROR BIT_1 1004 1005 #define ADAPTER_SUSPENDED BIT_8 1006 1007 /* 1008 * ISP PCI Configuration Register Set structure definitions. 1009 */ 1010 typedef volatile struct 1011 { 1012 volatile uint16_t vendor_id; 1013 volatile uint16_t device_id; 1014 volatile uint16_t command; 1015 volatile uint16_t status; 1016 volatile uint8_t revision; 1017 volatile uint8_t prog_class; 1018 volatile uint8_t sub_class; 1019 volatile uint8_t base_class; 1020 volatile uint8_t cache_line_size; 1021 volatile uint8_t latency_timer; 1022 volatile uint8_t header_type; 1023 volatile uint32_t io_base_address; 1024 volatile uint32_t pci_cntl_reg_set_mem_base_address_lower; 1025 volatile uint32_t pci_cntl_reg_set_mem_base_address_upper; 1026 volatile uint32_t pci_doorbell_mem_base_address_lower; 1027 volatile uint32_t pci_doorbell_mem_base_address_upper; 1028 1029 volatile uint16_t sub_vendor_id; 1030 volatile uint16_t sub_device_id; 1031 volatile uint32_t expansion_rom; 1032 volatile uint8_t intr_line; 1033 volatile uint8_t intr_pin; 1034 volatile uint8_t min_grant; 1035 volatile uint8_t max_latency; 1036 volatile uint16_t pcie_device_control; 1037 volatile uint16_t link_status; 1038 volatile uint16_t msi_msg_control; 1039 volatile uint16_t msi_x_msg_control; 1040 1041 } pci_cfg_t; 1042 1043 1044 /* 1045 * 1046 * Schultz Control Registers Index 1047 * 1048 */ 1049 #define REG_PROCESSOR_ADDR 0x00 1050 #define REG_PROCESSOR_DATA 0x04 1051 #define REG_SYSTEM 0x08 1052 #define REG_RESET_FAILOVER 0x0C 1053 #define REG_FUNCTION_SPECIFIC_CONTROL 0x10 1054 #define REG_HOST_CMD_STATUS 0x14 1055 #define REG_ICB_RID 0x1C 1056 #define REG_ICB_ACCESS_ADDRESS_LOWER 0x20 1057 #define REG_ICB_ACCESS_ADDRESS_UPPER 0x24 1058 #define REG_CONFIGURATION 0x28 1059 1060 #define INTR_EN_INTR_MASK 0x007f0000 1061 #define INTR_EN_TYPE_MASK 0x03000000 1062 #define INTR_EN_TYPE_ENABLE 0x00000100 1063 #define INTR_EN_TYPE_DISABLE 0x00000200 1064 #define INTR_EN_TYPE_READ 0x00000300 1065 #define INTR_EN_IHD 0x00002000 1066 #define INTR_EN_IHD_MASK (INTR_EN_IHD << 16) 1067 #define INTR_EN_EI 0x00004000 1068 #define INTR_EN_EN 0x00008000 1069 1070 #define REG_STATUS 0x30 1071 #define REG_INTERRUPT_ENABLE 0x34 1072 #define REG_INTERRUPT_MASK 0x38 1073 #define REG_INTERRUPT_STATUS_1 0x3C 1074 1075 #define REG_ERROR_STATUS 0x54 1076 1077 #define REG_SEMAPHORE 0x64 1078 1079 #define REG_XGMAC_ADDRESS 0x78 1080 #define REG_XGMAC_DATA 0x7C 1081 #define REG_NIC_ENHANCED_TX_SCHEDULE 0x80 1082 #define REG_CNA_ENHANCED_TX_SCHEDULE 0x84 1083 #define REG_FLASH_ADDRESS 0x88 1084 #define REG_FLASH_DATA 0x8C 1085 1086 #define REG_STOP_CQ_PROCESSING 0x90 1087 #define REG_PAGE_TABLE_RID 0x94 1088 #define REG_WQ_PAGE_TABLE_BASE_ADDR_LOWER 0x98 1089 #define REG_WQ_PAGE_TABLE_BASE_ADDR_UPPER 0x9C 1090 #define REG_CQ_PAGE_TABLE_BASE_ADDR_LOWER 0xA0 1091 #define REG_CQ_PAGE_TABLE_BASE_ADDR_UPPER 0xA4 1092 #define REG_MAC_PROTOCOL_ADDRESS_INDEX 0xA8 1093 #define REG_MAC_PROTOCOL_DATA 0xAC 1094 #define REG_SPLIT_HEADER 0xC0 1095 #define REG_NIC_RECEIVE_CONFIGURATION 0xD4 1096 1097 #define REG_MGMT_RCV_CFG 0xE0 1098 #define REG_ROUTING_INDEX 0xE4 1099 #define REG_ROUTING_DATA 0xE8 1100 #define REG_RSVD7 0xEC 1101 #define REG_XG_SERDES_ADDR 0xF0 1102 #define REG_XG_SERDES_DATA 0xF4 1103 #define REG_PRB_MX_ADDR 0xF8 1104 #define REG_PRB_MX_DATA 0xFC 1105 1106 #define INTR_MASK_PI 0x00000001 1107 #define INTR_MASK_HL0 0x00000002 1108 #define INTR_MASK_LH0 0x00000004 1109 #define INTR_MASK_HL1 0x00000008 1110 #define INTR_MASK_LH1 0x00000010 1111 #define INTR_MASK_SE 0x00000020 1112 #define INTR_MASK_LSC 0x00000040 1113 #define INTR_MASK_MC 0x00000080 1114 #define INTR_MASK_LINK_IRQS = (INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC) 1115 1116 /* Interrupt Enable Register 0x34 */ 1117 #define INTR_ENABLED 0x8000 1118 #define GLOBAL_ENABLE_INTR 0x4000 1119 #define ENABLE_MSI_MULTI_INTR 0x2000 1120 #define ONE_INTR_MASK 0x3FF0000u 1121 #define ENABLE_INTR 0x0100 1122 #define DISABLE_INTR 0x0200 1123 #define VERIFY_INTR_ENABLED 0x0300 1124 #define ISP_ENABLE_INTR(qlge) ql_put32(qlge, \ 1125 REG_INTERRUPT_ENABLE,\ 1126 (ONE_INTR_MASK | ENABLE_INTR)) 1127 #define ISP_DISABLE_INTR(qlge) ql_put32(qlge, \ 1128 REG_INTERRUPT_ENABLE, \ 1129 (ONE_INTR_MASK | DISABLE_INTR)) 1130 #define ISP_ENABLE_PI_INTR(qlge) ql_put32(qlge, \ 1131 REG_INTERRUPT_MASK, (BIT_16|1)) 1132 #define ISP_DISABLE_PI_INTR(qlge) ql_put32(qlge, \ 1133 REG_INTERRUPT_MASK, BIT_16) 1134 1135 #define ISP_ENABLE_GLOBAL_INTRS(qlge) { \ 1136 ql_put32(qlge, REG_INTERRUPT_ENABLE, \ 1137 (0x40000000u | GLOBAL_ENABLE_INTR)); \ 1138 qlge->flags |= INTERRUPTS_ENABLED; \ 1139 } 1140 #define ISP_DISABLE_GLOBAL_INTRS(qlge) { \ 1141 ql_put32(qlge, \ 1142 REG_INTERRUPT_ENABLE, (0x40000000u)); \ 1143 qlge->flags &= ~INTERRUPTS_ENABLED; \ 1144 } 1145 #define REQ_Q_VALID 0x10 1146 #define RSP_Q_VALID 0x10 1147 1148 /* 1149 * Mailbox Registers 1150 */ 1151 #define MPI_REG 0x1002 1152 #define NUM_MAILBOX_REGS 16 1153 #define FUNC_0_IN_MAILBOX_0_REG_OFFSET 0x1180 1154 #define FUNC_0_OUT_MAILBOX_0_REG_OFFSET 0x1190 1155 #define FUNC_1_IN_MAILBOX_0_REG_OFFSET 0x1280 1156 #define FUNC_1_OUT_MAILBOX_0_REG_OFFSET 0x1290 1157 1158 /* 1159 * Control Register Set definitions. 1160 */ 1161 typedef volatile struct 1162 { 1163 volatile uint32_t processor_address; /* 0x00 */ 1164 volatile uint32_t processor_data; /* 0x04 */ 1165 volatile uint32_t system_data; /* 0x08 */ 1166 volatile uint32_t reset_failover; /* 0x0C */ 1167 1168 volatile uint32_t function_specific_control; /* 0x10 */ 1169 volatile uint32_t host_command_status; /* 0x14 */ 1170 volatile uint32_t led; /* 0x18 */ 1171 volatile uint32_t icb_rid; /* 0x1c */ 1172 1173 volatile uint32_t idb_access_address_low; /* 0x20 */ 1174 volatile uint32_t idb_access_address_high; /* 0x24 */ 1175 volatile uint32_t configuration; /* 0x28 */ 1176 volatile uint32_t bios_base; /* 0x2C */ 1177 1178 volatile uint32_t status; /* 0x30 */ 1179 volatile uint32_t interrupt_enable; /* 0x34 */ 1180 volatile uint32_t interrupt_mask; /* 0x38 */ 1181 volatile uint32_t interrupt_status_1; /* 0x3c */ 1182 1183 volatile uint32_t interrupt_status_2; /* 0x40 */ 1184 volatile uint32_t interrupt_status_3; /* 0x44 */ 1185 volatile uint32_t interrupt_status_4; /* 0x48 */ 1186 volatile uint32_t rev_id; /* 0x4c */ 1187 1188 volatile uint32_t force_ecc_error; /* 0x50 */ 1189 volatile uint32_t error_status; /* 0x54 */ 1190 volatile uint32_t internal_ram_debug_address; /* 0x58 */ 1191 volatile uint32_t internal_ram_data; /* 0x5c */ 1192 1193 volatile uint32_t correctable_ecc_error; /* 0x60 */ 1194 volatile uint32_t semaphore; /* 0x64 */ 1195 1196 volatile uint32_t gpio1; /* 0x68 */ 1197 volatile uint32_t gpio2; /* 0x6c */ 1198 1199 volatile uint32_t gpio3; /* 0x70 */ 1200 volatile uint32_t reserved1; /* 0x74 */ 1201 volatile uint32_t xgmac_address; /* 0x78 */ 1202 volatile uint32_t xgmac_data; /* 0x7c */ 1203 1204 volatile uint32_t nic_enhanced_tx_schedule; /* 0x80 */ 1205 volatile uint32_t cna_enhanced_tx_schedule; /* 0x84 */ 1206 volatile uint32_t flash_address; /* 0x88 */ 1207 volatile uint32_t flash_data; /* 0x8c */ 1208 1209 volatile uint32_t stop_cq; /* 0x90 */ 1210 volatile uint32_t page_table_rid; /* 0x94 */ 1211 volatile uint32_t wq_page_table_base_address_lower; /* 0x98 */ 1212 volatile uint32_t wq_page_table_base_address_upper; /* 0x9c */ 1213 1214 volatile uint32_t cq_page_table_base_address_lower; /* 0xA0 */ 1215 volatile uint32_t cq_page_table_base_address_upper; /* 0xA4 */ 1216 volatile uint32_t mac_protocol_address_index; /* 0xA8 */ 1217 volatile uint32_t mac_protocol_data; /* 0xAc */ 1218 1219 volatile uint32_t cos_default_cq_reg1; /* 0xB0 */ 1220 volatile uint32_t cos_default_cq_reg2; /* 0xB4 */ 1221 volatile uint32_t ethertype_skip_reg1; /* 0xB8 */ 1222 volatile uint32_t ethertype_skip_reg2; /* 0xBC */ 1223 1224 volatile uint32_t split_header; /* 0xC0 */ 1225 volatile uint32_t fcoe_pause_threshold; /* 0xC4 */ 1226 volatile uint32_t nic_pause_threshold; /* 0xC8 */ 1227 volatile uint32_t fc_ethertype; /* 0xCC */ 1228 1229 volatile uint32_t fcoe_recv_configuration; /* 0xD0 */ 1230 volatile uint32_t nic_recv_configuration; /* 0xD4 */ 1231 volatile uint32_t cos_tags_in_fcoe_fifo; /* 0xD8 */ 1232 volatile uint32_t cos_tags_in_nic_fifo; /* 0xDc */ 1233 1234 volatile uint32_t mgmt_recv_configuration; /* 0xE0 */ 1235 volatile uint32_t routing_index; /* 0xE4 */ 1236 volatile uint32_t routing_data; /* 0xE8 */ 1237 volatile uint32_t reserved2; /* 0xEc */ 1238 1239 volatile uint32_t xg_serdes_address; /* 0xF0 */ 1240 volatile uint32_t xg_serdes_data; /* 0xF4 */ 1241 volatile uint32_t probe_mux_address; /* 0xF8 */ 1242 volatile uint32_t probe_mux_read_data; /* 0xFc */ 1243 1244 #define INTR_PENDING (uint32_t)(CSR_COMPLETION_INTR) 1245 1246 } dev_reg_t; 1247 1248 typedef volatile struct 1249 { 1250 volatile uint32_t doorbell_reg_address[256]; /* 0x00 */ 1251 } dev_doorbell_reg_t; 1252 1253 #define SET_RMASK(val) ((val & 0xffff) | (val << 16)) 1254 #define CLR_RMASK(val) (0 | (val << 16)) 1255 1256 /* 1257 * DMA registers read only 1258 */ 1259 typedef volatile struct 1260 { 1261 volatile uint32_t req_q_out; 1262 volatile uint32_t rsp_q_in; 1263 1264 } iop_dmaregs_t; 1265 1266 #define DMAREGS_SIZE (sizeof (iop_dmaregs_t)) 1267 #define DUMMY_SIZE (32*1024) 1268 1269 #ifdef QL_DEBUG 1270 typedef struct crash_record { 1271 uint16_t fw_major_version; /* 00 - 01 */ 1272 uint16_t fw_minor_version; /* 02 - 03 */ 1273 uint16_t fw_patch_version; /* 04 - 05 */ 1274 uint16_t fw_build_version; /* 06 - 07 */ 1275 1276 uint8_t build_date[16]; /* 08 - 17 */ 1277 uint8_t build_time[16]; /* 18 - 27 */ 1278 uint8_t build_user[16]; /* 28 - 37 */ 1279 uint8_t card_serial_num[16]; /* 38 - 47 */ 1280 1281 uint32_t time_of_crash_in_secs; /* 48 - 4B */ 1282 uint32_t time_of_crash_in_ms; /* 4C - 4F */ 1283 1284 uint16_t outb_risc_sd_num_frames; /* 50 - 51 */ 1285 uint16_t oap_sd_length; /* 52 - 53 */ 1286 uint16_t iap_sd_num_frames; /* 54 - 55 */ 1287 uint16_t inb_risc_sd_length; /* 56 - 57 */ 1288 1289 uint8_t reserved[28]; /* 58 - 7F */ 1290 1291 uint8_t outb_risc_reg_dump[256]; /* 80 -17F */ 1292 uint8_t inb_risc_reg_dump[256]; /* 180 -27F */ 1293 uint8_t inb_outb_risc_stack_dump[1]; /* 280 - ??? */ 1294 } crash_record_t; 1295 #endif 1296 1297 /* 1298 * I/O register access macros 1299 * #if QL_DEBUG & 1 1300 */ 1301 1302 #define RD_REG_BYTE(qlge, addr) \ 1303 ddi_get8(qlge->dev_handle, (uint8_t *)addr) 1304 #define RD_REG_DWORD(qlge, addr) \ 1305 ddi_get32(qlge->dev_handle, (uint32_t *)addr) 1306 #define WRT_REG_BYTE(qlge, addr, data) \ 1307 ddi_put8(qlge->dev_handle, (uint8_t *)addr, data) 1308 #define WRT_REG_WORD(qlge, addr, data) \ 1309 ddi_put16(qlge->dev_handle, (uint16_t *)addr, data) 1310 #define WRT_REG_DWORD(qlge, addr, data) \ 1311 ddi_put32(qlge->dev_handle, (uint32_t *)addr, data) 1312 1313 /* 1314 * QLGE-specific ioctls ... 1315 */ 1316 #define QLA_IOC ((((('Q' << 8) + 'L') << 8) + 'A') << 8) 1317 1318 /* 1319 * Definition of ioctls commands 1320 */ 1321 #define QLA_PCI_STATUS (QLA_IOC|1) /* Read all PCI registers */ 1322 1323 #define QLA_WRITE_REG (QLA_IOC|3) 1324 #define QLA_READ_PCI_REG (QLA_IOC|4) 1325 #define QLA_WRITE_PCI_REG (QLA_IOC|5) 1326 #define QLA_GET_DBGLEAVEL (QLA_IOC|6) 1327 #define QLA_SET_DBGLEAVEL (QLA_IOC|7) 1328 #define QLA_READ_CONTRL_REGISTERS (QLA_IOC|8) 1329 1330 #define QLA_MANUAL_READ_FLASH (QLA_IOC|9) 1331 #define QLA_MANUAL_WRITE_FLASH (QLA_IOC|10) 1332 #define QLA_SUPPORTED_DUMP_TYPES (QLA_IOC|11) 1333 #define QLA_GET_BINARY_CORE_DUMP (QLA_IOC|12) 1334 #define QLA_TRIGGER_SYS_ERROR_EVENT (QLA_IOC|13) 1335 1336 #define QLA_READ_FLASH (QLA_IOC|15) 1337 #define QLA_WRITE_FLASH (QLA_IOC|16) 1338 #define QLA_READ_VPD (QLA_IOC|17) 1339 #define QLA_GET_PROP (QLA_IOC|18) 1340 #define QLA_SHOW_REGION (QLA_IOC|19) 1341 #define QLA_LIST_ADAPTER_INFO (QLA_IOC|20) 1342 #define QLA_READ_FW_IMAGE (QLA_IOC|21) 1343 #define QLA_WRITE_FW_IMAGE_HEADERS (QLA_IOC|22) 1344 1345 #define QLA_CONTINUE_COPY_IN (QLA_IOC|29) 1346 #define QLA_CONTINUE_COPY_OUT (QLA_IOC|30) 1347 #define QLA_SOFT_RESET (QLA_IOC|31) 1348 1349 #define QLA_IOCTL_CMD_FIRST QLA_PCI_STATUS 1350 #define QLA_IOCTL_CMD_LAST QLA_SOFT_RESET 1351 1352 /* Solaris IOCTL can copy in&out up to 1024 bytes each time */ 1353 #define IOCTL_BUFFER_SIZE 1024 1354 #define IOCTL_MAX_BUF_SIZE (IOCTL_BUFFER_SIZE*512) /* 512k */ 1355 1356 typedef struct ioctl_header_info { 1357 uint8_t version; 1358 uint8_t reserved; 1359 uint8_t option[2]; 1360 uint16_t expected_trans_times; 1361 uint16_t payload_length; 1362 uint32_t total_length; 1363 } ioctl_header_info_t; 1364 1365 #define IOCTL_HEADER_LEN sizeof (ioctl_header_info_t) 1366 #define IOCTL_MAX_DATA_LEN (IOCTL_BUFFER_SIZE - IOCTL_HEADER_LEN) 1367 1368 struct ql_pci_reg { 1369 uint16_t addr; /* register number [0..ff] */ 1370 uint16_t value; /* data to write/data read */ 1371 }; 1372 1373 struct ql_device_reg { 1374 uint32_t addr; /* address to write/data read */ 1375 uint32_t value; /* data to write/data read */ 1376 }; 1377 1378 struct ql_flash_io_info { 1379 uint32_t addr; /* register number [0..ff] */ 1380 uint32_t size; /* number of data to write/data read */ 1381 }; 1382 1383 struct qlnic_mpi_version_info { 1384 uint32_t fw_version; 1385 uint32_t phy_version; 1386 }; 1387 1388 struct qlnic_link_status_info { 1389 uint32_t link_status_info; 1390 uint32_t additional_info; 1391 uint32_t network_hw_info; 1392 uint32_t dcbx_frame_counters_info; 1393 uint32_t change_counters_info; 1394 }; 1395 1396 struct qlnic_prop_info { 1397 struct qlnic_mpi_version_info mpi_version; /* MPI Version */ 1398 uint32_t fw_state; /* MPI state */ 1399 struct qlnic_link_status_info link_status; /* Link Status */ 1400 }; 1401 1402 typedef struct ql_adapter_info { 1403 uint32_t pci_binding; /* /bus/dev/func number per IEEE 1277 format */ 1404 uint16_t vendor_id; 1405 uint16_t device_id; 1406 uint16_t sub_vendor_id; 1407 uint16_t sub_device_id; 1408 struct ether_addr cur_addr; 1409 } ql_adapter_info_t; 1410 1411 #define DUMP_DESCRIPTION_HEADER_SIGNATURE 0x42535451 /* "QTSB" */ 1412 typedef struct ql_dump_header { 1413 uint32_t signature; /* QTSB */ 1414 uint8_t version; 1415 uint8_t length; 1416 uint8_t num_dumps; 1417 uint8_t reserved; 1418 uint32_t time_stamp_lo; 1419 uint32_t time_stamp_hi; 1420 } ql_dump_header_t; 1421 1422 #define DUMP_IMAGE_HEADER_SIGNATURE 0x504D4451 /* "QDMP" */ 1423 1424 typedef struct ql_dump_image_header { 1425 uint32_t signature; /* QDMP */ 1426 uint8_t version; 1427 uint8_t header_length; 1428 uint16_t checksum; 1429 uint32_t data_type; 1430 #define DUMP_TYPE_CORE_DUMP 1 1431 #define DUMP_TYPE_REGISTER_DUMP 2 1432 #define DUMP_TYPE_DRIVER_DUMP 3 1433 uint32_t data_length; 1434 } ql_dump_image_header_t; 1435 1436 /* utility request */ 1437 #define DUMP_REQUEST_CORE BIT_1 1438 #define DUMP_REQUEST_REGISTER BIT_2 1439 #define DUMP_REQUEST_DRIVER BIT_3 1440 1441 #define DUMP_REQUEST_ALL BIT_7 1442 1443 #define DUMP_DESCRIPTION_FOOTER_SIGNATURE 0x45535451 /* "QTSE" */ 1444 typedef struct ql_dump_footer { 1445 uint32_t signature; /* QTSE */ 1446 uint8_t version; 1447 uint8_t length; 1448 uint16_t reserved; 1449 uint32_t time_stamp_lo; 1450 uint32_t time_stamp_hi; 1451 } ql_dump_footer_t; 1452 1453 1454 /* 1455 * Solaris qlnic exit status. 1456 */ 1457 #define QN_ERR_BASE 0x30000000 1458 #define QN_ERR_OK QN_ERR_BASE | 0 /* Success */ 1459 #define QN_ERR_NOT_SUPPORTED QN_ERR_BASE | 1 /* Command not supported */ 1460 #define QN_ERR_INVALID_PARAM QN_ERR_BASE | 2 /* Invalid parameter */ 1461 #define QN_ERR_WRONG_NO_PARAM QN_ERR_BASE | 3 /* Wrong number of parameters */ 1462 #define QN_ERR_FILE_NOT_FOUND QN_ERR_BASE | 4 /* File not found */ 1463 #define QN_ERR_FILE_READ_ERR QN_ERR_BASE | 5 /* File read err */ 1464 #define QN_ERR_FILE_WRITE_ERR QN_ERR_BASE | 6 /* File write err */ 1465 #define QN_ERR_NO_MEMORY QN_ERR_BASE | 7 /* No Memory */ 1466 1467 #define FLT_REGION_FDT 0x1A 1468 #define ISP_8100_FDT_ADDR 0x360000 1469 #define ISP_8100_FDT_SIZE 0x80 1470 1471 #define FLT_REGION_FLT 0x1C 1472 #define ISP_8100_FLT_ADDR 0x361000 1473 #define ISP_8100_FLT_SIZE 0x1000 1474 1475 #define FLT_REGION_NIC_BOOT_CODE 0x2E 1476 #define ISP_8100_NIC_BOOT_CODE_ADDR 0x0 1477 #define ISP_8100_NIC_BOOT_CODE_SIZE 0x80000 1478 1479 #define FLT_REGION_MPI_FW_USE 0x42 1480 #define ISP_8100_MPI_FW_USE_ADDR 0xF0000 1481 #define ISP_8100_MPI_FW_USE_SIZE 0x10000 1482 1483 #define FLT_REGION_MPI_RISC_FW 0x40 1484 #define ISP_8100_MPI_RISC_FW_ADDR 0x100000 1485 #define ISP_8100_MPI_RISC_FW_SIZE 0x10000 1486 1487 #define FLT_REGION_VPD0 0x2C 1488 #define ISP_8100_VPD0_ADDR 0x140000 1489 #define ISP_8100_VPD0_SIZE 0x200 1490 1491 #define FLT_REGION_NIC_PARAM0 0x46 1492 #define ISP_8100_NIC_PARAM0_ADDR 0x140200 1493 #define ISP_8100_NIC_PARAM0_SIZE 0x200 1494 1495 #define FLT_REGION_VPD1 0x2D 1496 #define ISP_8100_VPD1_ADDR 0x140400 1497 #define ISP_8100_VPD1_SIZE 0x200 1498 1499 #define FLT_REGION_NIC_PARAM1 0x47 1500 #define ISP_8100_NIC_PARAM1_ADDR 0x140600 1501 #define ISP_8100_NIC_PARAM1_SIZE 0x200 1502 1503 #define FLT_REGION_MPI_CFG 0x41 1504 #define ISP_8100_MPI_CFG_ADDR 0x150000 1505 #define ISP_8100_MPI_CFG_SIZE 0x10000 1506 1507 #define FLT_REGION_EDC_PHY_FW 0x45 1508 #define ISP_8100_EDC_PHY_FW_ADDR 0x170000 1509 #define ISP_8100_EDC_PHY_FW_SIZE 0x20000 1510 1511 #define FLT_REGION_FC_BOOT_CODE 0x07 1512 #define ISP_8100_FC_BOOT_CODE_ADDR 0x200000 1513 #define ISP_8100_FC_BOOT_CODE_SIZE 0x80000 1514 1515 #define FLT_REGION_FC_FW 0x01 1516 #define ISP_8100_FC_FW_ADDR 0x280000 1517 #define ISP_8100_FC_FW_SIZE 0x80000 1518 1519 #define FLT_REGION_FC_VPD0 0x14 1520 #define ISP_8100_FC_VPD0_ADDR 0x340000 1521 #define ISP_8100_FC_VPD0_SIZE 0x200 1522 1523 #define FLT_REGION_FC_NVRAM0 0x15 1524 #define ISP_8100_FC_NVRAM0_ADDR 0x340200 1525 #define ISP_8100_FC_NVRAM0_SIZE 0x200 1526 1527 #define FLT_REGION_FC_VPD1 0x16 1528 #define ISP_8100_FC_VPD1_ADDR 0x340400 1529 #define ISP_8100_FC_VPD1_SIZE 0x200 1530 1531 #define FLT_REGION_FC_NVRAM1 0x17 1532 #define ISP_8100_FC_NVRAM1_ADDR 0x340600 1533 #define ISP_8100_FC_NVRAM1_SIZE 0x200 1534 1535 #define FLT_REGION_FC_BOOT_CODE 0x07 1536 #define ISP_8100_FC_BOOT_CODE_ADDR 0x200000 1537 #define ISP_8100_FC_BOOT_CODE_SIZE 0x80000 1538 1539 #define FLT_REGION_FC_FW 0x01 1540 #define ISP_8100_FC_FW_ADDR 0x280000 1541 #define ISP_8100_FC_FW_SIZE 0x80000 1542 1543 #define FLT_REGION_TIME_STAMP 0x60 1544 1545 /* flash region for testing */ 1546 #define FLT_REGION_WIN_FW_DUMP0 0x48 1547 #define ISP_8100_WIN_FW_DUMP0_ADDR 0x190000 1548 #define ISP_8100_WIN_FW_DUMP0_SIZE 0x30000 1549 1550 #define ISP_8100_FLASH_TEST_REGION_ADDR ISP_8100_WIN_FW_DUMP0_ADDR 1551 #define ISP_8100_FLASH_TEST_REGION_SIZE 0x10000 1552 1553 /* mailbox */ 1554 #define QL_8XXX_SFP_SIZE 256 1555 1556 #define MAILBOX_TOV 30 /* Default Timeout value. */ 1557 /* 1558 * ISP mailbox commands from Host 1559 */ 1560 #define MBC_NO_OPERATION 0 /* No Operation. */ 1561 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1562 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1563 #define MBC_MAILBOX_REGISTER_TEST 6 /* Mailbox echo test */ 1564 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1565 #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 1566 #define MBC_RISC_MEMORY_COPY 0xA /* Copy RISC memory. */ 1567 #define MBC_LOAD_RISC_RAM 0xB /* Load RISC RAM command. */ 1568 #define MBC_DUMP_RISC_RAM 0xC /* Dump RISC RAM command. */ 1569 #define MBC_INIT_RISC_RAM 0xE 1570 #define MBC_READ_RAM_WORD 0xF /* Read RAM */ 1571 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 1572 #define MBC_GENERATE_SYS_ERROR 0x2A /* Generate System Error */ 1573 #define MBC_WRITE_SFP 0x30 /* Write SFP. */ 1574 #define MBC_READ_SFP 0x31 /* Read SFP. */ 1575 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1576 #define MBC_GET_INIT_CTRL_BLOCK 0x61 /* Get Initialization CBLK */ 1577 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1578 #define MBC_IDC_REQUEST 0x100 /* IDC Request. */ 1579 #define IDC_REQ_ALL_DEST_FUNC_MASK BIT_4 /* Mailbox 1 */ 1580 1581 #define IDC_REQ_DEST_FUNC_0_MASK BIT_0 /* Mailbox 2 */ 1582 #define IDC_REQ_DEST_FUNC_1_MASK BIT_1 1583 #define IDC_REQ_DEST_FUNC_2_MASK BIT_2 1584 #define IDC_REQ_DEST_FUNC_3_MASK BIT_3 1585 1586 enum IDC_REQ_DEST_FUNC { 1587 IDC_REQ_DEST_FUNC_0, 1588 IDC_REQ_DEST_FUNC_1, 1589 IDC_REQ_DEST_FUNC_2, 1590 IDC_REQ_DEST_FUNC_3, 1591 IDC_REQ_DEST_FUNC_ALL = 0x0F 1592 }; 1593 1594 #define IDC_REQ_TIMEOUT_MASK 0x01 1595 1596 #define MBC_IDC_ACK 0x101 /* IDC Acknowledge. */ 1597 #define MBC_IDC_TIME_EXTENDED 0x102 /* IDC Time Extended. */ 1598 1599 #define MBC_SET_WAKE_ON_LANE_MODE 0x110 1600 #define MBC_SET_WAKE_ON_LANE_FILTER 0x111 1601 #define MBC_CLEAR_WAKE_ON_LANE_FILTER 0x112 1602 #define MBC_SET_WAKE_ON_LANE_MAGIC_PKT 0x113 1603 #define MBC_CLEAR_WAKE_ON_LANE_MAGIC_PKT 0x114 1604 1605 #define MBC_PORT_RESET 0x120 1606 #define MBC_SET_PORT_CONFIG 0x122 1607 #define MBC_GET_PORT_CONFIG 0x123 1608 #define ENABLE_JUMBO_FRAME_SIZE_MASK BIT_16 1609 #define MBC_GET_LINK_STATUS 0x124 1610 1611 #define MBC_SET_LED_CONFIG 0x125 1612 #define MBC_GET_LED_CONFIG 0x126 1613 1614 /* 1615 * ISP mailbox command complete status codes 1616 */ 1617 #define MBS_COMMAND_COMPLETE 0x4000 1618 #define MBS_INVALID_COMMAND 0x4001 1619 #define MBS_HOST_INTERFACE_ERROR 0x4002 1620 #define MBS_TEST_FAILED 0x4003 1621 #define MBS_POST_ERROR 0x4004 1622 #define MBS_COMMAND_ERROR 0x4005 1623 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1624 #define MBS_PORT_ID_USED 0x4007 1625 #define MBS_LOOP_ID_USED 0x4008 1626 #define MBS_ALL_IDS_IN_USE 0x4009 1627 #define MBS_NOT_LOGGED_IN 0x400A 1628 #define MBS_LOOP_DOWN 0x400B 1629 #define MBS_LOOP_BACK_ERROR 0x400C 1630 #define MBS_CHECKSUM_ERROR 0x4010 1631 1632 /* Async Event Status */ 1633 #define MBA_IDC_INTERMEDIATE_COMPLETE 0x1000 1634 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1635 #define MBA_SYSTEM_ERR 0x8002 1636 #define MBA_LINK_UP 0x8011 1637 enum { 1638 XFI_NETWORK_INTERFACE = 1, 1639 XAUI_NETWORK_INTERFACE, 1640 XFI_BACKPLANE_INTERFACE, 1641 XAUI_BACKPLANE_INTERFACE, 1642 EXT_10GBASE_T_PHY, 1643 EXT_EXT_EDC_PHY 1644 }; 1645 #define MBA_LINK_DOWN 0x8012 1646 #define MBA_IDC_COMPLETE 0x8100 1647 #define MBA_IDC_REQUEST_NOTIFICATION 0x8101 1648 #define MBA_IDC_TIME_EXTENDED 0x8102 1649 #define MBA_DCBX_CONFIG_CHANGE 0x8110 1650 #define MBA_NOTIFICATION_LOST 0x8120 1651 #define MBA_SFT_TRANSCEIVER_INSERTION 0x8130 1652 #define MBA_SFT_TRANSCEIVER_REMOVAL 0x8131 1653 #define MBA_FIRMWARE_INIT_COMPLETE 0x8400 1654 #define MBA_FIRMWARE_INIT_FAILED 0x8401 1655 1656 typedef struct firmware_version_info { 1657 uint8_t reserved; 1658 uint8_t major_version; 1659 uint8_t minor_version; 1660 uint8_t sub_minor_version; 1661 } firmware_version_info_t; 1662 1663 typedef struct phy_firmware_version_info { 1664 uint8_t reserved; 1665 uint8_t major_version; 1666 uint8_t minor_version; 1667 uint8_t sub_minor_version; 1668 } phy_firmware_version_info_t; 1669 1670 #define ENABLE_JUMBO BIT_16 1671 #define STD_PAUSE 0x20 1672 #define PP_PAUSE 0x40 1673 #define DCBX_ENABLE 0x10 1674 #define LOOP_INTERNAL_PARALLEL 0x02 1675 #define LOOP_INTERNAL_SERIAL 0x04 1676 #define LOOP_EXTERNAL_PHY 0x06 1677 1678 typedef struct port_cfg_info { 1679 uint32_t link_cfg; 1680 uint32_t max_frame_size; 1681 } port_cfg_info_t; 1682 1683 enum { 1684 PAUSE_MODE_DISABLED, 1685 PAUSE_MODE_STANDARD, /* Standard Ethernet Pause */ 1686 PAUSE_MODE_PER_PRIORITY /* Class Based Pause */ 1687 }; 1688 1689 /* Mailbox command parameter structure definition. */ 1690 typedef struct mbx_cmd { 1691 uint32_t from_mpi; /* number of Incomming from MPI to driver */ 1692 uint32_t mb[NUM_MAILBOX_REGS]; 1693 clock_t timeout; /* Timeout in seconds. */ 1694 } mbx_cmd_t; 1695 1696 /* Returned Mailbox registers. */ 1697 typedef struct mbx_data { 1698 uint32_t from_mpi; /* number of Incomming from MPI to driver */ 1699 uint32_t mb[NUM_MAILBOX_REGS]; 1700 } mbx_data_t; 1701 1702 /* Address/Length pairs for the coredump. */ 1703 1704 #define MPI_CORE_REGS_ADDR 0x00030000 1705 #define MPI_CORE_REGS_CNT 127 1706 #define MPI_CORE_SH_REGS_CNT 16 1707 #define TEST_REGS_ADDR 0x00001000 1708 #define TEST_REGS_CNT 23 1709 #define RMII_REGS_ADDR 0x00001040 1710 #define RMII_REGS_CNT 64 1711 #define FCMAC1_REGS_ADDR 0x00001080 1712 #define FCMAC2_REGS_ADDR 0x000010c0 1713 #define FCMAC_REGS_CNT 64 1714 #define FC1_MBX_REGS_ADDR 0x00001100 1715 #define FC2_MBX_REGS_ADDR 0x00001240 1716 #define FC_MBX_REGS_CNT 64 1717 #define IDE_REGS_ADDR 0x00001140 1718 #define IDE_REGS_CNT 64 1719 #define NIC1_MBX_REGS_ADDR 0x00001180 1720 #define NIC2_MBX_REGS_ADDR 0x00001280 1721 #define NIC_MBX_REGS_CNT 64 1722 #define SMBUS_REGS_ADDR 0x00001200 1723 #define SMBUS_REGS_CNT 64 1724 #define I2C_REGS_ADDR 0x00001fc0 1725 #define I2C_REGS_CNT 64 1726 #define MEMC_REGS_ADDR 0x00003000 1727 #define MEMC_REGS_CNT 256 1728 #define PBUS_REGS_ADDR 0x00007c00 1729 #define PBUS_REGS_CNT 256 1730 #define MDE_REGS_ADDR 0x00010000 1731 #define MDE_REGS_CNT 6 1732 #define CODE_RAM_ADDR 0x00020000 1733 #define CODE_RAM_CNT 0x2000 1734 #define MEMC_RAM_ADDR 0x00100000 1735 #define MEMC_RAM_CNT 0x2000 1736 1737 /* 64 probes, 8 bytes per probe + 4 bytes to list the probe ID */ 1738 #define PROBE_DATA_LENGTH_WORDS ((64 * 2) + 1) 1739 #define NUMBER_OF_PROBES 34 1740 #define NUMBER_ROUTING_REG_ENTRIES 48 1741 #define WORDS_PER_ROUTING_REG_ENTRY 4 1742 #define MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) + \ 1743 (4096 * 1) + (4 * 2) + (8 * 2) + \ 1744 (16 * 1) + (4 * 1) + (4 * 4) + \ 1745 (4 * 1)) 1746 /* Save both the address and data register */ 1747 #define WORDS_PER_MAC_PROT_ENTRY 2 1748 1749 #define MPI_COREDUMP_COOKIE 0x5555aaaa 1750 typedef struct mpi_coredump_global_header { 1751 uint32_t cookie; 1752 char id_string[16]; 1753 uint32_t time_lo; 1754 uint32_t time_hi; 1755 uint32_t total_image_size; 1756 uint32_t global_header_size; 1757 char driver_info[0xE0]; 1758 }mpi_coredump_global_header_t; 1759 1760 typedef struct mpi_coredump_segment_header { 1761 uint32_t cookie; 1762 uint32_t seg_number; 1763 uint32_t seg_size; 1764 uint32_t extra; 1765 char description[16]; 1766 }mpi_coredump_segment_header_t; 1767 1768 typedef struct ql_mpi_coredump { 1769 mpi_coredump_global_header_t mpi_global_header; 1770 1771 mpi_coredump_segment_header_t core_regs_seg_hdr; 1772 uint32_t mpi_core_regs[MPI_CORE_REGS_CNT]; 1773 uint32_t mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT]; 1774 1775 mpi_coredump_segment_header_t test_logic_regs_seg_hdr; 1776 uint32_t test_logic_regs[TEST_REGS_CNT]; 1777 1778 mpi_coredump_segment_header_t rmii_regs_seg_hdr; 1779 uint32_t rmii_regs[RMII_REGS_CNT]; 1780 1781 mpi_coredump_segment_header_t fcmac1_regs_seg_hdr; 1782 uint32_t fcmac1_regs[FCMAC_REGS_CNT]; 1783 1784 mpi_coredump_segment_header_t fcmac2_regs_seg_hdr; 1785 uint32_t fcmac2_regs[FCMAC_REGS_CNT]; 1786 1787 mpi_coredump_segment_header_t fc1_mbx_regs_seg_hdr; 1788 uint32_t fc1_mbx_regs[FC_MBX_REGS_CNT]; 1789 1790 mpi_coredump_segment_header_t ide_regs_seg_hdr; 1791 uint32_t ide_regs[IDE_REGS_CNT]; 1792 1793 mpi_coredump_segment_header_t nic1_mbx_regs_seg_hdr; 1794 uint32_t nic1_mbx_regs[NIC_MBX_REGS_CNT]; 1795 1796 mpi_coredump_segment_header_t smbus_regs_seg_hdr; 1797 uint32_t smbus_regs[SMBUS_REGS_CNT]; 1798 1799 mpi_coredump_segment_header_t fc2_mbx_regs_seg_hdr; 1800 uint32_t fc2_mbx_regs[FC_MBX_REGS_CNT]; 1801 1802 mpi_coredump_segment_header_t nic2_mbx_regs_seg_hdr; 1803 uint32_t nic2_mbx_regs[NIC_MBX_REGS_CNT]; 1804 1805 mpi_coredump_segment_header_t i2c_regs_seg_hdr; 1806 uint32_t i2c_regs[I2C_REGS_CNT]; 1807 1808 mpi_coredump_segment_header_t memc_regs_seg_hdr; 1809 uint32_t memc_regs[MEMC_REGS_CNT]; 1810 1811 mpi_coredump_segment_header_t pbus_regs_seg_hdr; 1812 uint32_t pbus_regs[PBUS_REGS_CNT]; 1813 1814 mpi_coredump_segment_header_t mde_regs_seg_hdr; 1815 uint32_t mde_regs[MDE_REGS_CNT]; 1816 1817 mpi_coredump_segment_header_t xaui_an_hdr; 1818 uint32_t serdes_xaui_an[14]; 1819 1820 mpi_coredump_segment_header_t xaui_hss_pcs_hdr; 1821 uint32_t serdes_xaui_hss_pcs[33]; 1822 1823 mpi_coredump_segment_header_t xfi_an_hdr; 1824 uint32_t serdes_xfi_an[14]; 1825 1826 mpi_coredump_segment_header_t xfi_train_hdr; 1827 uint32_t serdes_xfi_train[12]; 1828 1829 mpi_coredump_segment_header_t xfi_hss_pcs_hdr; 1830 uint32_t serdes_xfi_hss_pcs[15]; 1831 1832 mpi_coredump_segment_header_t xfi_hss_tx_hdr; 1833 uint32_t serdes_xfi_hss_tx[32]; 1834 1835 mpi_coredump_segment_header_t xfi_hss_rx_hdr; 1836 uint32_t serdes_xfi_hss_rx[32]; 1837 1838 mpi_coredump_segment_header_t xfi_hss_pll_hdr; 1839 uint32_t serdes_xfi_hss_pll[32]; 1840 1841 mpi_coredump_segment_header_t nic_regs_seg_hdr; 1842 uint32_t nic_regs[64]; 1843 1844 /* one interrupt state for each CQ */ 1845 mpi_coredump_segment_header_t intr_states_seg_hdr; 1846 uint32_t intr_states[MAX_RX_RINGS]; 1847 1848 mpi_coredump_segment_header_t xgmac_seg_hdr; 1849 #define XGMAC_REGISTER_END 0x740 1850 uint32_t xgmac[XGMAC_REGISTER_END]; 1851 1852 mpi_coredump_segment_header_t probe_dump_seg_hdr; 1853 uint32_t probe_dump[PROBE_DATA_LENGTH_WORDS * NUMBER_OF_PROBES]; 1854 1855 mpi_coredump_segment_header_t routing_reg_seg_hdr; 1856 uint32_t routing_regs[NUMBER_ROUTING_REG_ENTRIES * WORDS_PER_ROUTING_REG_ENTRY]; 1857 1858 mpi_coredump_segment_header_t mac_prot_reg_seg_hdr; 1859 uint32_t mac_prot_regs[MAC_PROTOCOL_REGISTER_WORDS * WORDS_PER_MAC_PROT_ENTRY]; 1860 1861 1862 mpi_coredump_segment_header_t ets_seg_hdr; 1863 uint32_t ets[8+2]; 1864 1865 mpi_coredump_segment_header_t code_ram_seg_hdr; 1866 uint32_t code_ram[CODE_RAM_CNT]; 1867 1868 mpi_coredump_segment_header_t memc_ram_seg_hdr; 1869 uint32_t memc_ram[MEMC_RAM_CNT]; 1870 1871 } ql_mpi_coredump_t; 1872 1873 #define WCS_MPI_CODE_RAM_LENGTH (0x2000*4) 1874 #define MEMC_MPI_RAM_LENGTH (0x2000*4) 1875 1876 #define XG_SERDES_ADDR_RDY BIT_31 1877 #define XG_SERDES_ADDR_R BIT_30 1878 1879 #define CORE_SEG_NUM 1 1880 #define TEST_LOGIC_SEG_NUM 2 1881 #define RMII_SEG_NUM 3 1882 #define FCMAC1_SEG_NUM 4 1883 #define FCMAC2_SEG_NUM 5 1884 #define FC1_MBOX_SEG_NUM 6 1885 #define IDE_SEG_NUM 7 1886 #define NIC1_MBOX_SEG_NUM 8 1887 #define SMBUS_SEG_NUM 9 1888 #define FC2_MBOX_SEG_NUM 10 1889 #define NIC2_MBOX_SEG_NUM 11 1890 #define I2C_SEG_NUM 12 1891 #define MEMC_SEG_NUM 13 1892 #define PBUS_SEG_NUM 14 1893 #define MDE_SEG_NUM 15 1894 #define NIC1_CONTROL_SEG_NUM 16 1895 #define NIC2_CONTROL_SEG_NUM 17 1896 #define NIC1_XGMAC_SEG_NUM 18 1897 #define NIC2_XGMAC_SEG_NUM 19 1898 #define WCS_RAM_SEG_NUM 20 1899 #define MEMC_RAM_SEG_NUM 21 1900 #define XAUI_AN_SEG_NUM 22 1901 #define XAUI_HSS_PCS_SEG_NUM 23 1902 #define XFI_AN_SEG_NUM 24 1903 #define XFI_TRAIN_SEG_NUM 25 1904 #define XFI_HSS_PCS_SEG_NUM 26 1905 #define XFI_HSS_TX_SEG_NUM 27 1906 #define XFI_HSS_RX_SEG_NUM 28 1907 #define XFI_HSS_PLL_SEG_NUM 29 1908 #define INTR_STATES_SEG_NUM 31 1909 #define ETS_SEG_NUM 34 1910 #define PROBE_DUMP_SEG_NUM 35 1911 #define ROUTING_INDEX_SEG_NUM 36 1912 #define MAC_PROTOCOL_SEG_NUM 37 1913 1914 /* Force byte packing for the following structures */ 1915 #pragma pack(1) 1916 1917 /* 1918 * Work Queue (Request Queue) Initialization Control Block (WQICB) 1919 */ 1920 1921 struct wqicb_t { 1922 uint16_t len; 1923 #define Q_LEN_V (1 << 4) 1924 #define Q_LEN_CPP_CONT 0x0000 1925 #define Q_LEN_CPP_16 0x0001 1926 #define Q_LEN_CPP_32 0x0002 1927 #define Q_LEN_CPP_64 0x0003 1928 #define Q_LEN_CPP_512 0x0006 1929 uint16_t flags; 1930 #define Q_PRI_SHIFT 1 1931 #define Q_FLAGS_LC 0x1000 1932 #define Q_FLAGS_LB 0x2000 1933 #define Q_FLAGS_LI 0x4000 1934 #define Q_FLAGS_LO 0x8000 1935 uint16_t cq_id_rss; 1936 #define Q_CQ_ID_RSS_RV 0x8000 1937 uint16_t rid; 1938 uint32_t wq_addr_lo; 1939 uint32_t wq_addr_hi; 1940 uint32_t cnsmr_idx_addr_lo; 1941 uint32_t cnsmr_idx_addr_hi; 1942 }; 1943 1944 /* 1945 * Completion Queue (Response Queue) Initialization Control Block (CQICB) 1946 */ 1947 1948 struct cqicb_t { 1949 uint8_t msix_vect; 1950 uint8_t reserved1; 1951 uint8_t reserved2; 1952 uint8_t flags; 1953 #define FLAGS_LV 0x08 1954 #define FLAGS_LS 0x10 1955 #define FLAGS_LL 0x20 1956 #define FLAGS_LI 0x40 1957 #define FLAGS_LC 0x80 1958 uint16_t len; 1959 #define LEN_V (1 << 4) 1960 #define LEN_CPP_CONT 0x0000 1961 #define LEN_CPP_32 0x0001 1962 #define LEN_CPP_64 0x0002 1963 #define LEN_CPP_128 0x0003 1964 uint16_t rid; 1965 uint32_t cq_base_addr_lo; /* completion queue base address */ 1966 uint32_t cq_base_addr_hi; 1967 uint32_t prod_idx_addr_lo; /* completion queue host copy */ 1968 /* producer index host shadow */ 1969 uint32_t prod_idx_addr_hi; 1970 uint16_t pkt_delay; 1971 uint16_t irq_delay; 1972 uint32_t lbq_addr_lo; 1973 uint32_t lbq_addr_hi; 1974 uint16_t lbq_buf_size; 1975 uint16_t lbq_len; /* entry count */ 1976 uint32_t sbq_addr_lo; 1977 uint32_t sbq_addr_hi; 1978 uint16_t sbq_buf_size; 1979 uint16_t sbq_len; /* entry count */ 1980 }; 1981 1982 struct ricb { 1983 uint8_t base_cq; 1984 #define RSS_L4K 0x80 1985 uint8_t flags; 1986 #define RSS_L6K 0x01 1987 #define RSS_LI 0x02 1988 #define RSS_LB 0x04 1989 #define RSS_LM 0x08 1990 #define RSS_RI4 0x10 1991 #define RSS_RT4 0x20 1992 #define RSS_RI6 0x40 1993 #define RSS_RT6 0x80 1994 uint16_t mask; 1995 #define RSS_HASH_CQ_ID_MAX 1024 1996 uint8_t hash_cq_id[RSS_HASH_CQ_ID_MAX]; 1997 uint32_t ipv6_hash_key[10]; 1998 uint32_t ipv4_hash_key[4]; 1999 }; 2000 2001 /* 2002 * Host Command IOCB Formats 2003 */ 2004 2005 #define OPCODE_OB_MAC_IOCB 0x01 2006 #define OPCODE_OB_MAC_OFFLOAD_IOCB 0x02 2007 2008 #define OPCODE_IB_MAC_IOCB 0x20 2009 #define OPCODE_IB_SYS_EVENT_IOCB 0x3f 2010 2011 /* 2012 * The following constants define control bits for buffer 2013 * length fields for all IOCB's. 2014 */ 2015 #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */ 2016 #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */ 2017 2018 struct oal_entry { 2019 uint32_t buf_addr_low; 2020 uint32_t buf_addr_high; 2021 uint32_t buf_len; 2022 }; 2023 2024 /* 32 words, 128 bytes */ 2025 #define TX_DESC_PER_IOCB 8 /* Number of descs in one TX IOCB */ 2026 2027 struct ob_mac_iocb_req { 2028 uint8_t opcode; 2029 uint8_t flag0; 2030 #define OB_MAC_IOCB_REQ_IPv6 0x80 2031 #define OB_MAC_IOCB_REQ_IPv4 0x40 2032 #define OB_MAC_IOCB_REQ_D 0x08 /* disable generation of comp. msg */ 2033 #define OB_MAC_IOCB_REQ_I 0x02 /* disable generation of intr at comp */ 2034 uint8_t flag1; 2035 #define OB_MAC_IOCB_REQ_TC 0x80 /* enable TCP checksum offload */ 2036 #define OB_MAC_IOCB_REQ_UC 0x40 /* enable UDP checksum offload */ 2037 #define OB_MAC_IOCB_REQ_LSO 0x20 /* enable LSO offload */ 2038 uint8_t flag2; 2039 #define OB_MAC_IOCB_REQ_VLAN_OFFSET_MASK 0xF8 /* VLAN TCI insert */ 2040 #define OB_MAC_IOCB_REQ_V 0x04 /* insert VLAN TCI */ 2041 #define OB_MAC_IOCB_REQ_DFP 0x02 /* Drop for Failover port */ 2042 #define OB_MAC_IOCB_REQ_IC 0x01 /* enable IP checksum offload */ 2043 uint32_t unused; 2044 uint32_t reserved_cq_tag; 2045 uint32_t frame_len; /* max 9000,for none LSO, 16M for LSO */ 2046 uint32_t tid; 2047 uint32_t txq_idx; 2048 uint16_t protocol_hdr_len; 2049 uint16_t hdr_off; /* tcp/udp hdr offset */ 2050 uint16_t vlan_tci; 2051 uint16_t mss; 2052 2053 struct oal_entry oal_entry[TX_DESC_PER_IOCB]; /* max FFFFF 1M bytes */ 2054 2055 }; 2056 /* 16 words, 64 bytes */ 2057 struct ob_mac_iocb_rsp { 2058 uint8_t opcode; 2059 uint8_t flags1; 2060 #define OB_MAC_IOCB_RSP_OI 0x01 /* */ 2061 #define OB_MAC_IOCB_RSP_I 0x02 /* */ 2062 #define OB_MAC_IOCB_RSP_E 0x08 /* */ 2063 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */ 2064 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */ 2065 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */ 2066 2067 uint8_t flags2; 2068 uint8_t flags3; 2069 2070 #define OB_MAC_IOCB_RSP_B 0x80 2071 2072 uint32_t tid; 2073 uint32_t txq_idx; 2074 2075 uint32_t reserved[13]; 2076 }; 2077 2078 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff 2079 2080 struct ib_mac_iocb_rsp { 2081 uint8_t opcode; /* 0x20 */ 2082 uint8_t flags1; 2083 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ 2084 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ 2085 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ 2086 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ 2087 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ 2088 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */ 2089 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */ 2090 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */ 2091 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */ 2092 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */ 2093 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */ 2094 uint8_t flags2; 2095 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */ 2096 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */ 2097 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */ 2098 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04 2099 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08 2100 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10 2101 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14 2102 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18 2103 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c 2104 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */ 2105 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */ 2106 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */ 2107 uint8_t flags3; 2108 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */ 2109 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */ 2110 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */ 2111 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */ 2112 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */ 2113 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */ 2114 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */ 2115 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */ 2116 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */ 2117 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ 2118 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ 2119 uint32_t data_len; 2120 uint64_t data_addr; 2121 uint32_t rss; 2122 uint16_t vlan_id; /* 12 bits */ 2123 #define IB_MAC_IOCB_RSP_VLAN_ID_MASK 0xFFF 2124 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ 2125 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */ 2126 2127 uint16_t reserved1; 2128 uint32_t reserved2[6]; 2129 uint8_t reserved3[3]; 2130 uint8_t flags4; 2131 #define IB_MAC_IOCB_RSP_HV 0x20 2132 #define IB_MAC_IOCB_RSP_HS 0x40 2133 #define IB_MAC_IOCB_RSP_HL 0x80 2134 uint32_t hdr_len; 2135 uint64_t hdr_addr; 2136 }; 2137 2138 /* 16 words, 64 bytes */ 2139 struct ib_sys_event_iocb_rsp { 2140 uint8_t opcode; 2141 uint8_t flag0; 2142 uint8_t event_type; 2143 uint8_t q_id; 2144 uint32_t reserved[15]; 2145 }; 2146 #define SYS_EVENT_PORT_LINK_UP 0x0 2147 #define SYS_EVENT_PORT_LINK_DOWN 0x1 2148 #define SYS_EVENT_MULTIPLE_CAM_HITS 0x6 2149 #define SYS_EVENT_SOFT_ECC_ERR 0x7 2150 #define SYS_EVENT_MGMT_FATAL_ERR 0x8 /* MPI_PROCESSOR */ 2151 #define SYS_EVENT_MAC_INTERRUPT 0x9 2152 #define SYS_EVENT_PCI_ERR_READING_SML_LRG_BUF 0x40 2153 2154 /* 2155 * Status Register (#define STATUS) bit definitions. 2156 */ 2157 #define STATUS_FE (1 << 0) 2158 #define STATUS_PI (1 << 1) 2159 #define STATUS_PL0 (1 << 2), 2160 #define STATUS_PL1 (1 << 3) 2161 #define STATUS_PI0 (1 << 4) 2162 #define STATUS_PI1 (1 << 5) 2163 #define STATUS_FUNC_ID_MASK 0x000000c0 2164 #define STATUS_FUNC_ID_SHIFT 6 2165 #define STATUS_F0E (1 << 8) 2166 #define STATUS_F1E (1 << 9) 2167 #define STATUS_F2E (1 << 10) 2168 #define STATUS_F3E (1 << 11) 2169 #define STATUS_NFE (1 << 12) 2170 2171 /* 2172 * Generic Response Queue IOCB Format which abstracts the difference between 2173 * IB_MAC, OB_MAC IOCBs 2174 */ 2175 struct net_rsp_iocb { 2176 uint8_t opcode; 2177 uint8_t flag0; 2178 uint8_t flag1; 2179 uint8_t flag2; 2180 uint32_t reserved[15]; 2181 }; 2182 2183 /* Restore original packing rules */ 2184 #pragma pack() 2185 2186 #define RESPONSE_ENTRY_SIZE (sizeof (struct net_rsp_iocb)) 2187 #define REQUEST_ENTRY_SIZE (sizeof (struct ob_mac_iocb_req)) 2188 2189 /* flash */ 2190 /* Little endian machine correction defines. */ 2191 #ifdef _LITTLE_ENDIAN 2192 #define LITTLE_ENDIAN_16(x) 2193 #define LITTLE_ENDIAN_24(x) 2194 #define LITTLE_ENDIAN_32(x) 2195 #define LITTLE_ENDIAN_64(x) 2196 #define LITTLE_ENDIAN(bp, bytes) 2197 #define BIG_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2) 2198 #define BIG_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3) 2199 #define BIG_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4) 2200 #define BIG_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8) 2201 #define BIG_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes) 2202 #endif /* _LITTLE_ENDIAN */ 2203 2204 /* Big endian machine correction defines. */ 2205 #ifdef _BIG_ENDIAN 2206 #define LITTLE_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2) 2207 #define LITTLE_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3) 2208 #define LITTLE_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4) 2209 #define LITTLE_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8) 2210 #define LITTLE_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes) 2211 #define BIG_ENDIAN_16(x) 2212 #define BIG_ENDIAN_24(x) 2213 #define BIG_ENDIAN_32(x) 2214 #define BIG_ENDIAN_64(x) 2215 #define BIG_ENDIAN(bp, bytes) 2216 #endif /* _BIG_ENDIAN */ 2217 2218 void ql_change_endian(uint8_t *, size_t); 2219 2220 /* Flash Address Register 0x88 */ 2221 #define FLASH_RDY_FLAG BIT_31 2222 #define FLASH_R_FLAG BIT_30 2223 #define FLASH_ERR_FLAG BIT_29 2224 #define FLASH_CONF_ADDR 0x7D0000u 2225 #define FLASH_ADDR_MASK 0x7F0000 2226 2227 #define FLASH_WRSR_CMD 0x01 2228 #define FLASH_PP_CMD 0x02 2229 #define FLASH_READ_CMD 0x03 2230 #define FLASH_WRDI_CMD 0x04 2231 #define FLASH_RDSR_CMD 0x05 2232 #define FLASH_WREN_CMD 0x06 2233 #define FLASH_RDID_CMD 0x9F 2234 #define FLASH_RES_CMD 0xAB 2235 2236 /* 2237 * Flash definitions. 2238 */ 2239 typedef struct ql_flash_info { 2240 uint32_t type; /* flash type */ 2241 uint32_t flash_size; /* length in bytes of flash */ 2242 uint32_t sec_mask; /* sector number mask */ 2243 uint8_t flash_manuf; /* flash chip manufacturer id */ 2244 uint8_t flash_id; /* flash chip id */ 2245 uint8_t flash_cap; /* flash chip capacity */ 2246 } ql_flash_info_t; 2247 2248 /* 2249 * Flash Description Table 2250 */ 2251 #define FLASH_DESC_VERSION 1 2252 #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */ 2253 typedef struct flash_desc { 2254 uint32_t flash_valid; 2255 uint16_t flash_version; 2256 uint16_t flash_len; /* flash description table length */ 2257 uint16_t flash_checksum; 2258 uint16_t flash_unused; 2259 uint8_t flash_model[16]; 2260 uint16_t flash_manuf; 2261 uint16_t flash_id; 2262 uint8_t flash_flag; 2263 uint8_t erase_cmd; 2264 uint8_t alt_erase_cmd; 2265 uint8_t write_enable_cmd; 2266 uint8_t write_enable_bits; 2267 uint8_t write_statusreg_cmd; 2268 uint8_t unprotect_sector_cmd; 2269 uint8_t read_manuf_cmd; 2270 uint32_t block_size; 2271 uint32_t alt_block_size; 2272 uint32_t flash_size; 2273 uint32_t write_enable_data; 2274 uint8_t readid_address_len; 2275 uint8_t write_disable_bits; 2276 uint8_t read_device_id_len; 2277 uint8_t chip_erase_cmd; 2278 uint16_t read_timeout; 2279 uint8_t protect_sector_cmd; 2280 uint8_t exp_reserved[65]; 2281 } flash_desc_t; 2282 2283 /* flash manufacturer id's */ 2284 #define AMD_FLASH 0x01 /* AMD / Spansion */ 2285 #define ST_FLASH 0x20 /* ST Electronics */ 2286 #define SST_FLASH 0xbf /* SST Electronics */ 2287 #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */ 2288 #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */ 2289 #define WINBOND_FLASH 0xef /* Winbond (W25X16,W25X32) */ 2290 #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */ 2291 2292 /* flash id defines */ 2293 #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */ 2294 #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */ 2295 #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */ 2296 #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */ 2297 #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */ 2298 #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */ 2299 #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */ 2300 #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */ 2301 #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */ 2302 #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */ 2303 #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */ 2304 #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */ 2305 #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */ 2306 #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */ 2307 #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */ 2308 #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */ 2309 #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */ 2310 #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */ 2311 #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */ 2312 #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */ 2313 2314 /* flash type defines */ 2315 #define FLASH128 BIT_0 2316 #define FLASH512 BIT_1 2317 #define FLASH512S BIT_2 2318 #define FLASH1024 BIT_3 2319 #define FLASH2048 BIT_4 2320 #define FLASH4096 BIT_5 2321 #define FLASH8192 BIT_6 2322 #define FLASH_PAGE BIT_31 2323 #define FLASH_LEGACY (FLASH128 | FLASH512S) 2324 2325 #define FLASH_FIRMWARE_IMAGE_ADDR 0x100000 /* 1M */ 2326 typedef struct { 2327 uint8_t signature[2]; 2328 uint8_t reserved[0x16]; 2329 uint8_t dataoffset[2]; 2330 uint8_t pad[6]; 2331 } pci_header_t; 2332 2333 typedef struct { 2334 uint8_t signature[4]; 2335 uint8_t vid[2]; 2336 uint8_t did[2]; 2337 uint8_t reserved0[2]; 2338 uint8_t pcidatalen[2]; 2339 uint8_t pcidatarev; 2340 uint8_t classcode[3]; 2341 uint8_t imagelength[2]; /* In sectors */ 2342 uint8_t revisionlevel[2]; 2343 uint8_t codetype; 2344 uint8_t indicator; 2345 uint8_t reserved1[2]; 2346 uint8_t pad[8]; 2347 } pci_data_t; 2348 2349 #define PCI_HEADER0 0x55 2350 #define PCI_HEADER1 0xAA 2351 #define PCI_DATASIG "PCIR" 2352 #define PCI_SECTOR_SIZE 0x200 2353 #define PCI_CODE_X86PC 0 2354 #define PCI_CODE_FCODE 1 2355 #define PCI_CODE_HPPA 2 2356 #define PCI_CODE_EFI 3 2357 #define PCI_CODE_FW 0xfe 2358 #define PCI_IND_LAST_IMAGE 0x80 2359 #define SBUS_CODE_FCODE 0xf1 2360 2361 #define FBUFSIZE 100 2362 /* Flash Layout Table Data Structure(FLTDS) */ 2363 #define FLASH_FLTDS_SIGNATURE 0x544C4651 /* "QFLT" */ 2364 2365 typedef struct ql_fltds { 2366 uint32_t signature; 2367 uint16_t flt_addr_lo; 2368 uint16_t flt_addr_hi; 2369 uint8_t version; 2370 uint8_t reserved; 2371 uint16_t checksum; 2372 } ql_fltds_t; 2373 /* Image Layout Table Data Structure(ILTDS) */ 2374 #define FLASH_ILTDS_SIGNATURE 0x4D494651 /* "QFIM" */ 2375 typedef struct ql_iltds_header { 2376 uint32_t signature; 2377 uint16_t table_version; /* version of this structure */ 2378 uint16_t length; /* length of the table */ 2379 uint16_t checksum; 2380 uint16_t number_entries; /* Number of type/len/size entries */ 2381 uint16_t reserved; 2382 uint16_t version; /* version of the image */ 2383 } ql_iltds_header_t; 2384 2385 #define IMAGE_TABLE_HEADER_LEN sizeof (ql_iltds_header_t) 2386 2387 #define ILTDS_REGION_VERSION_LEN_NA 0 /* version not applicable */ 2388 typedef struct ql_iltds_img_entry { 2389 uint16_t region_type; 2390 uint8_t region_version_len; 2391 uint8_t region_version[3]; 2392 uint16_t offset_lo; 2393 uint16_t offset_hi; 2394 uint16_t size_lo; 2395 uint16_t size_hi; 2396 uint8_t swap_mode; 2397 #define ILTDS_IMG_SWAP_NONE 0 /* no swap needed */ 2398 #define ILTDS_IMG_SWAP_WORD 1 2399 2400 uint8_t card_type; 2401 #define ILTDS_IMG_CARD_TYPE_ALL 0 /* apply to all types */ 2402 #define ILTDS_IMG_CARD_TYPE_SR 1 /* apply to SR/fc cards */ 2403 #define ILTDS_IMG_CARD_TYPE_COPPER 2 /* apply to Copper cards */ 2404 #define ILTDS_IMG_CARD_TYPE_MEZZ 4 /* apply to Mezz cards */ 2405 } ql_iltds_img_entry_t; 2406 2407 #define IMAGE_TABLE_ENTRY_LEN sizeof (ql_iltds_img_entry_t) 2408 2409 typedef struct ql_iltds_time_stamp { 2410 uint16_t region_type; 2411 uint8_t region_version_len; 2412 uint8_t region_version[3]; 2413 uint8_t year; 2414 uint8_t month; 2415 uint8_t day; 2416 uint8_t hour; 2417 uint8_t min; 2418 uint8_t sec; 2419 uint32_t reserved; 2420 } ql_iltds_time_stamp_t; 2421 2422 #define IMAGE_TABLE_TIME_STAMP_LEN sizeof (ql_iltds_time_stamp_t) 2423 2424 #define IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES 5 2425 2426 typedef struct ql_iltds_description_header { 2427 ql_iltds_header_t iltds_table_header; 2428 ql_iltds_img_entry_t img_entry[IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES]; 2429 ql_iltds_time_stamp_t time_stamp; 2430 }ql_iltds_description_header_t; 2431 2432 #define ILTDS_DESCRIPTION_HEADERS_LEN sizeof (ql_iltds_description_header_t) 2433 2434 /* flash layout table definition */ 2435 /* header */ 2436 typedef struct ql_flt_header { 2437 uint16_t version; 2438 uint16_t length; /* length of the flt table,no table header */ 2439 uint16_t checksum; 2440 uint16_t reserved; 2441 } ql_flt_header_t; 2442 2443 /* table entry */ 2444 typedef struct ql_flt_entry { 2445 uint8_t region; 2446 uint8_t reserved0; 2447 uint8_t attr; 2448 #define FLT_ATTR_READ_ONLY BIT_0 2449 #define FLT_ATTR_NEED_FW_RESTART BIT_1 2450 #define FLT_ATTR_NEED_DATA_REALOAD BIT_2 2451 uint8_t reserved1; 2452 uint32_t size; 2453 uint32_t begin_addr; 2454 uint32_t end_addr; 2455 } ql_flt_entry_t; 2456 2457 /* flt table */ 2458 typedef struct ql_flt { 2459 ql_flt_header_t header; 2460 uint16_t num_entries; 2461 ql_flt_entry_t *ql_flt_entry_ptr; 2462 } ql_flt_t; 2463 2464 /* Nic Configuration Table */ 2465 #define FLASH_NIC_CONFIG_SIGNATURE 0x30303038 /* "8000" */ 2466 2467 enum { 2468 DATA_TYPE_NONE, 2469 DATA_TYPE_FACTORY_MAC_ADDR, 2470 DATA_TYPE_CLP_MAC_ADDR, 2471 DATA_TYPE_CLP_VLAN_MAC_ADDR, 2472 DATA_TYPE_RESERVED, 2473 DATA_TYPE_LAST_ENTRY 2474 }; 2475 2476 typedef struct ql_nic_config { 2477 uint32_t signature; 2478 uint16_t version; 2479 uint16_t size; 2480 uint16_t checksum; 2481 uint16_t reserved0; 2482 uint16_t total_data_size; 2483 uint16_t num_of_entries; 2484 uint8_t factory_data_type; 2485 uint8_t factory_data_type_size; 2486 uint8_t factory_MAC[6]; 2487 uint8_t clp_data_type; 2488 uint8_t clp_data_type_size; 2489 uint8_t clp_MAC[6]; 2490 uint8_t clp_vlan_data_type; 2491 uint8_t clp_vlan_data_type_size; 2492 uint16_t vlan_id; 2493 uint8_t last_data_type; 2494 uint8_t last_data_type_size; 2495 uint16_t last_entry; 2496 uint8_t reserved1[464]; 2497 uint16_t subsys_vendor_id; 2498 uint16_t subsys_device_id; 2499 uint8_t reserved2[4]; 2500 } ql_nic_config_t; 2501 2502 #ifdef __cplusplus 2503 } 2504 #endif 2505 2506 #endif /* _QLGE_HW_H */ 2507