1 /* $OpenBSD: if_liireg.h,v 1.4 2008/09/01 14:38:31 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * PCI configuration space seems to be mapped in the first 0x100 bytes of 31 * the register area. 32 */ 33 34 /* SPI Flash Control register */ 35 #define LII_SFC 0x0200 36 #define SFC_STS_NON_RDY 0x00000001 37 #define SFC_STS_WEN 0x00000002 38 #define SFC_STS_WPEN 0x00000080 39 #define SFC_DEV_STS_MASK 0x000000ff 40 #define SFC_DEV_STS_SHIFT 0 41 #define SFC_INS_MASK 0x07 42 #define SFC_INS_SHIFT 8 43 #define SFC_START 0x00000800 44 #define SFC_EN_VPD 0x00002000 45 #define SFC_LDSTART 0x00008000 46 #define SFC_CS_HI_MASK 0x03 47 #define SFC_CS_HI_SHIFT 16 48 #define SFC_CS_HOLD_MASK 0x03 49 #define SFC_CS_HOLD_SHIFT 18 50 #define SFC_CLK_LO_MASK 0x03 51 #define SFC_CLK_LO_SHIFT 20 52 #define SFC_CLK_HI_MASK 0x03 53 #define SFC_CLK_HI_SHIFT 22 54 #define SFC_CS_SETUP_MASK 0x03 55 #define SFC_CS_SETUP_SHIFT 24 56 #define SFC_EROMPGSZ_MASK 0x03 57 #define SFC_EROMPGSZ_SHIFT 26 58 #define SFC_WAIT_READY 0x10000000 59 60 /* SPI Flash Address register */ 61 #define LII_SF_ADDR 0x0204 62 63 /* SPI Flash Data register */ 64 #define LII_SF_DATA 0x0208 65 66 /* SPI Flash Configuration register */ 67 #define LII_SFCF 0x020c 68 #define SFCF_LD_ADDR_MASK 0x00ffffff 69 #define SFCF_LD_ADDR_SHIFT 0 70 #define SFCF_VPD_ADDR_MASK 0x03 71 #define SFCF_VPD_ADDR_SHIFT 24 72 #define SFCF_LD_EXISTS 0x04000000 73 74 /* SPI Flash op codes programmation registers */ 75 #define LII_SFOP_PROGRAM 0x0210 76 #define LII_SFOP_SC_ERASE 0x0211 77 #define LII_SFOP_CHIP_ERASE 0x0212 78 #define LII_SFOP_RDID 0x0213 79 #define LII_SFOP_WREN 0x0214 80 #define LII_SFOP_RDSR 0x0215 81 #define LII_SFOP_WRSR 0x0216 82 #define LII_SFOP_READ 0x0217 83 84 /* TWSI Control register, whatever that is */ 85 #define LII_TWSIC 0x0218 86 #define TWSIC_LD_OFFSET_MASK 0x000000ff 87 #define TWSIC_LD_OFFSET_SHIFT 0 88 #define TWSIC_LD_SLV_ADDR_MASK 0x07 89 #define TWSIC_LD_SLV_ADDR_SHIFT 8 90 #define TWSIC_SW_LDSTART 0x00000800 91 #define TWSIC_HW_LDSTART 0x00001000 92 #define TWSIC_SMB_SLV_ADDR_MASK 0x7F 93 #define TWSIC_SMB_SLV_ADDR_SHIFT 15 94 #define TWSIC_LD_EXIST 0x00400000 95 #define TWSIC_READ_FREQ_SEL_MASK 0x03 96 #define TWSIC_READ_FREQ_SEL_SHIFT 23 97 #define TWSIC_FREQ_SEL_100K 0 98 #define TWSIC_FREQ_SEL_200K 1 99 #define TWSIC_FREQ_SEL_300K 2 100 #define TWSIC_FREQ_SEL_400K 3 101 #define TWSIC_WRITE_FREQ_SEL_MASK 0x03 102 #define TWSIC_WRITE_FREQ_SEL_SHIFT 24 103 104 /* PCI-Express Device Misc. Control register? (size unknown) */ 105 #define LII_PCEDMC 0x021c 106 #define PCEDMC_RETRY_BUFDIS 0x01 107 #define PCEDMC_EXT_PIPE 0x02 108 #define PCEDMC_SPIROM_EXISTS 0x04 109 #define PCEDMC_SERDES_ENDIAN 0x08 110 #define PCEDMC_SERDES_SEL_DIN 0x10 111 112 /* PCI-Express PHY Miscellaneous register (size unknown) */ 113 #define LII_PCEPM 0x1000 114 #define PCEPM_FORCE_RCV_DET 0x04 115 116 /* Selene Master Control register */ 117 #define LII_SMC 0x1400 118 #define SMC_SOFT_RST 0x00000001 119 #define SMC_MTIMER_EN 0x00000002 120 #define SMC_ITIMER_EN 0x00000004 121 #define SMC_MANUAL_INT 0x00000008 122 #define SMC_REV_NUM_MASK 0xff 123 #define SMC_REV_NUM_SHIFT 16 124 #define SMC_DEV_ID_MASK 0xff 125 #define SMC_DEV_ID_SHIFT 24 126 127 /* Timer Initial Value register */ 128 #define LII_TIV 0x1404 129 130 /* IRQ Moderator Timer Initial Value register */ 131 #define LII_IMTIV 0x1408 132 133 /* PHY Control register */ 134 #define LII_PHYC 0x140c 135 #define PHYC_ENABLE 0x0001 136 137 /* IRQ Anti-Lost Timer Initial Value register 138 --> Time allowed for software to clear the interrupt */ 139 #define LII_IALTIV 0x140e 140 141 /* Block Idle Status register 142 --> Bit set if matching state machine is not idle */ 143 #define LII_BIS 0x1410 144 #define BIS_RXMAC 0x00000001 145 #define BIS_TXMAC 0x00000002 146 #define BIS_DMAR 0x00000004 147 #define BIS_DMAW 0x00000008 148 149 /* MDIO Control register */ 150 #define LII_MDIOC 0x1414 151 #define MDIOC_DATA_MASK 0x0000ffff 152 #define MDIOC_DATA_SHIFT 0 153 #define MDIOC_REG_MASK 0x1f 154 #define MDIOC_REG_SHIFT 16 155 #define MDIOC_WRITE 0x00000000 156 #define MDIOC_READ 0x00200000 157 #define MDIOC_SUP_PREAMBLE 0x00400000 158 #define MDIOC_START 0x00800000 159 #define MDIOC_CLK_SEL_MASK 0x07 160 #define MDIOC_CLK_SEL_SHIFT 24 161 #define MDIOC_CLK_25_4 0 162 #define MDIOC_CLK_25_6 2 163 #define MDIOC_CLK_25_8 3 164 #define MDIOC_CLK_25_10 4 165 #define MDIOC_CLK_25_14 5 166 #define MDIOC_CLK_25_20 6 167 #define MDIOC_CLK_25_28 7 168 #define MDIOC_BUSY 0x08000000 169 /* Time to wait for MDIO, waiting for 2us in-between */ 170 #define MDIO_WAIT_TIMES 10 171 172 /* SerDes Lock Detect Control and Status register */ 173 #define LII_SERDES 0x1424 174 #define SERDES_LOCK_DETECT 0x01 175 #define SERDES_LOCK_DETECT_EN 0x02 176 177 /* MAC Control register */ 178 #define LII_MACC 0x1480 179 #define MACC_TX_EN 0x00000001 180 #define MACC_RX_EN 0x00000002 181 #define MACC_TX_FLOW_EN 0x00000004 182 #define MACC_RX_FLOW_EN 0x00000008 183 #define MACC_LOOPBACK 0x00000010 184 #define MACC_FDX 0x00000020 185 #define MACC_ADD_CRC 0x00000040 186 #define MACC_PAD 0x00000080 187 #define MACC_PREAMBLE_LEN_MASK 0x0f 188 #define MACC_PREAMBLE_LEN_SHIFT 10 189 #define MACC_STRIP_VLAN 0x00004000 190 #define MACC_PROMISC_EN 0x00008000 191 #define MACC_DBG_TX_BKPRESSURE 0x00100000 192 #define MACC_ALLMULTI_EN 0x02000000 193 #define MACC_BCAST_EN 0x04000000 194 #define MACC_MACLP_CLK_PHY 0x08000000 195 #define MACC_HDX_LEFT_BUF_MASK 0x0f 196 #define MACC_HDX_LEFT_BUF_SHIFT 28 197 198 /* MAC IPG/IFG Control register */ 199 #define LII_MIPFG 0x1484 200 #define MIPFG_IPGT_MASK 0x0000007f 201 #define MIPFG_IPGT_SHIFT 0 202 #define MIPFG_MIFG_MASK 0xff 203 #define MIPFG_MIFG_SHIFT 8 204 #define MIPFG_IPGR1_MASK 0x7f 205 #define MIPFG_IPGR1_SHIFT 16 206 #define MIPFG_IPGR2_MASK 0x7f 207 #define MIPFG_IPGR2_SHIFT 24 208 209 /* MAC Address registers */ 210 #define LII_MAC_ADDR_0 0x1488 211 #define LII_MAC_ADDR_1 0x148c 212 213 /* Multicast Hash Table register */ 214 #define LII_MHT 0x1490 215 216 /* MAC Half-Duplex Control register */ 217 #define LII_MHDC 0x1498 218 #define MHDC_LCOL_MASK 0x000003ff 219 #define MHDC_LCOL_SHIFT 0 220 #define MHDC_RETRY_MASK 0x0f 221 #define MHDC_RETRY_SHIFT 12 222 #define MHDC_EXC_DEF_EN 0x00010000 223 #define MHDC_NO_BACK_C 0x00020000 224 #define MHDC_NO_BACK_P 0x00040000 225 #define MHDC_ABEDE 0x00080000 226 #define MHDC_ABEBT_MASK 0x0f 227 #define MHDC_ABEBT_SHIFT 20 228 #define MHDC_JAMIPG_MASK 0x0f 229 #define MHDC_JAMIPG_SHIFT 24 230 231 /* MTU Control register */ 232 #define LII_MTU 0x149c 233 234 /* WOL Control register */ 235 #define LII_WOLC 236 #define WOLC_PATTERN_EN 0x00000001 237 #define WOLC_PATTERN_PME_EN 0x00000002 238 #define WOLC_MAGIC_EN 0x00000004 239 #define WOLC_MAGIC_PME_EN 0x00000008 240 #define WOLC_LINK_CHG_EN 0x00000010 241 #define WOLC_LINK_CHG_PME_EN 0x00000020 242 #define WOLC_PATTERN_ST 0x00000100 243 #define WOLC_MAGIC_ST 0x00000200 244 #define WOLC_LINK_CHG_ST 0x00000400 245 #define WOLC_PT0_EN 0x00010000 246 #define WOLC_PT1_EN 0x00020000 247 #define WOLC_PT2_EN 0x00040000 248 #define WOLC_PT3_EN 0x00080000 249 #define WOLC_PT4_EN 0x00100000 250 #define WOLC_PT0_MATCH 0x01000000 251 #define WOLC_PT1_MATCH 0x02000000 252 #define WOLC_PT2_MATCH 0x04000000 253 #define WOLC_PT3_MATCH 0x08000000 254 #define WOLC_PT4_MATCH 0x10000000 255 256 /* Internal SRAM Partition register */ 257 #define LII_SRAM_TXRAM_END 0x1500 258 #define LII_SRAM_RXRAM_END 0x1502 259 260 /* Descriptor Control registers */ 261 #define LII_DESC_BASE_ADDR_HI 0x1540 262 #define LII_TXD_BASE_ADDR_LO 0x1544 263 #define LII_TXD_BUFFER_SIZE 0x1548 264 #define LII_TXS_BASE_ADDR_LO 0x154c 265 #define LII_TXS_NUM_ENTRIES 0x1550 266 #define LII_RXD_BASE_ADDR_LO 0x1554 267 #define LII_RXD_NUM_ENTRIES 0x1558 268 269 /* DMAR Control register */ 270 #define LII_DMAR 0x1580 271 #define DMAR_EN 0x01 272 273 /* TX Cur-Through Control register */ 274 #define LII_TX_CUT_THRESH 0x1590 275 276 /* DMAW Control register */ 277 #define LII_DMAW 0x15a0 278 #define DMAW_EN 0x01 279 280 /* Flow Control registers */ 281 #define LII_PAUSE_ON_TH 0x15a8 282 #define LII_PAUSE_OFF_TH 0x15aa 283 284 /* Mailbox registers */ 285 #define LII_MB_TXD_WR_IDX 0x15f0 286 #define LII_MB_RXD_RD_IDX 0x15f4 287 288 /* Interrupt Status register */ 289 #define LII_ISR 0x1600 290 #define ISR_TIMER 0x00000001 291 #define ISR_MANUAL 0x00000002 292 #define ISR_RXF_OV 0x00000004 293 #define ISR_TXF_UR 0x00000008 294 #define ISR_TXS_OV 0x00000010 295 #define ISR_RXS_OV 0x00000020 296 #define ISR_LINK_CHG 0x00000040 297 #define ISR_HOST_TXD_UR 0x00000080 298 #define ISR_HOST_RXD_OV 0x00000100 299 #define ISR_DMAR_TO_RST 0x00000200 300 #define ISR_DMAW_TO_RST 0x00000400 301 #define ISR_PHY 0x00000800 302 #define ISR_TS_UPDATE 0x00010000 303 #define ISR_RS_UPDATE 0x00020000 304 #define ISR_TX_EARLY 0x00040000 305 #define ISR_UR_DETECTED 0x01000000 306 #define ISR_FERR_DETECTED 0x02000000 307 #define ISR_NFERR_DETECTED 0x04000000 308 #define ISR_CERR_DETECTED 0x08000000 309 #define ISR_PHY_LINKDOWN 0x10000000 310 #define ISR_DIS_INT 0x80000000 311 312 #define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \ 313 ISR_HOST_TXD_UR | ISR_TS_UPDATE | \ 314 ISR_TX_EARLY) 315 #define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \ 316 ISR_HOST_RXD_OV | ISR_RS_UPDATE) 317 318 /* Interrupt Mask register */ 319 #define LII_IMR 0x1604 320 #define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \ 321 ISR_PHY | ISR_PHY_LINKDOWN | \ 322 ISR_TS_UPDATE | ISR_RS_UPDATE) 323 324 /* MAC RX Statistics registers */ 325 #define LII_STS_RX_PAUSE 0x1700 326 #define LII_STS_RXD_OV 0x1704 327 #define LII_STS_RXS_OV 0x1708 328 #define LII_STS_RX_FILTER 0x170c 329 330 struct tx_pkt_header { 331 uint16_t txph_size; 332 #define LII_TXH_ADD_VLAN_TAG 0x8000 333 uint16_t txph_vlan; 334 } __packed; 335 336 struct tx_pkt_status { 337 uint16_t txps_size; 338 uint16_t txps_flags :15; 339 #define LII_TXF_SUCCESS 0x0001 340 #define LII_TXF_BCAST 0x0002 341 #define LII_TXF_MCAST 0x0004 342 #define LII_TXF_PAUSE 0x0008 343 #define LII_TXF_CTRL 0x0010 344 #define LII_TXF_DEFER 0x0020 345 #define LII_TXF_EXC_DEFER 0x0040 346 #define LII_TXF_SINGLE_COL 0x0080 347 #define LII_TXF_MULTI_COL 0x0100 348 #define LII_TXF_LATE_COL 0x0200 349 #define LII_TXF_ABORT_COL 0x0400 350 #define LII_TXF_UNDERRUN 0x0800 351 uint16_t txps_update:1; 352 } __packed; 353 354 struct rx_pkt { 355 uint16_t rxp_size; 356 uint16_t rxp_flags :15; 357 #define LII_RXF_SUCCESS 0x0001 358 #define LII_RXF_BCAST 0x0002 359 #define LII_RXF_MCAST 0x0004 360 #define LII_RXF_PAUSE 0x0008 361 #define LII_RXF_CTRL 0x0010 362 #define LII_RXF_CRC 0x0020 363 #define LII_RXF_CODE 0x0040 364 #define LII_RXF_RUNT 0x0080 365 #define LII_RXF_FRAG 0x0100 366 #define LII_RXF_TRUNC 0x0200 367 #define LII_RXF_ALIGN 0x0400 368 #define LII_RXF_VLAN 0x0800 369 uint16_t rxp_update:1; 370 uint16_t rxp_vlan; 371 uint16_t __pad; 372 uint8_t rxp_data[1528]; 373 } __packed; 374