1 /* $NetBSD: mfireg.h,v 1.24 2022/07/16 06:52:40 msaitoh Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 #ifndef _DEV_IC_MFIREG_H_ 47 #define _DEV_IC_MFIREG_H_ 48 49 /* management interface constants */ 50 #define MFI_MGMT_VD 0x01 51 #define MFI_MGMT_SD 0x02 52 53 /* generic constants */ 54 #define MFI_FRAME_SIZE 64 55 #define MFI_SENSE_SIZE 128 56 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 58 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59 #define MFI_INVALID_CTX 0xffffffff 60 #define MFI_ENABLE_INTR 0x01 61 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 62 #define MFI_SECTOR_LEN 512 63 64 /* register offsets */ 65 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 66 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 67 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 68 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 69 #define MFI_IDB 0x20 /* inbound doorbell */ 70 #define MFI_ISTS 0x24 /* inbound intr stat */ 71 #define MFI_IMSK 0x28 /* inbound intr mask */ 72 #define MFI_ODB 0x2c /* outbound doorbell */ 73 #define MFI_OSTS 0x30 /* outbound intr stat */ 74 #define MFI_OMSK 0x34 /* outbound inter mask */ 75 #define MFI_IQP 0x40 /* inbound queue port */ 76 #define MFI_OQP 0x44 /* outbound queue port */ 77 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 78 #define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80 /* ThunderBolt specific Register */ 81 #define MFI_RPI 0x6c /* reply_post_host_index */ 82 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85 /* Aero specific Register */ 86 #define MFI_ISQP 0xc8 /* inbound_single_queue_port */ 87 88 /* OCR registers */ 89 #define MFI_WSR 0x004 /* write sequence register */ 90 #define MFI_HDR 0x008 /* host diagnostic register */ 91 #define MFI_RSR 0x3c3 /* Reset Status Register */ 92 93 /* OCR specific flags */ 94 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 95 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 96 97 /* 98 * skinny specific changes 99 */ 100 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 101 #define MFI_IQPL 0x000000c0 102 #define MFI_IQPH 0x000000c4 103 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 104 105 /* * firmware states */ 106 #define MFI_STATE_MASK 0xf0000000 107 #define MFI_STATE_UNDEFINED 0x00000000 108 #define MFI_STATE_BB_INIT 0x10000000 109 #define MFI_STATE_FW_INIT 0x40000000 110 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 111 #define MFI_STATE_FW_INIT_2 0x70000000 112 #define MFI_STATE_DEVICE_SCAN 0x80000000 113 #define MFI_STATE_FLUSH_CACHE 0xa0000000 114 #define MFI_STATE_READY 0xb0000000 115 #define MFI_STATE_OPERATIONAL 0xc0000000 116 #define MFI_STATE_FAULT 0xf0000000 117 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 118 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 119 #define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 120 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 121 #define MFI_RESET_REQUIRED 0x00000001 122 123 /* ThunderBolt Support */ 124 #define MFI_STATE_TB_MASK 0xf0000000 125 #define MFI_STATE_TB_RESET 0x00000000 126 #define MFI_STATE_TB_READY 0x10000000 127 #define MFI_STATE_TB_OPERATIONAL 0x20000000 128 #define MFI_STATE_TB_FAULT 0x40000000 129 130 /* Aero Support */ 131 #define MFI_STATE_ATOMIC_DESCRIPTOR 0x01000000 132 133 /* command reset register */ 134 #define MFI_INIT_ABORT 0x00000001 135 #define MFI_INIT_READY 0x00000002 136 #define MFI_INIT_MFIMODE 0x00000004 137 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 138 #define MFI_RESET_FLAGS MFI_INIT_READY | MFI_INIT_MFIMODE | \ 139 MFI_INIT_ABORT 140 #define MFI_INIT_HOTPLUG 0x00000010 141 142 /* ADP reset flags */ 143 #define MFI_STOP_ADP 0x00000020 144 #define MFI_ADP_RESET 0x00000040 145 #define DIAG_WRITE_ENABLE 0x00000080 146 #define DIAG_RESET_ADAPTER 0x00000004 147 148 /* mfi Frame flags */ 149 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 150 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 151 #define MFI_FRAME_SGL32 0x0000 152 #define MFI_FRAME_SGL64 0x0002 153 #define MFI_FRAME_SENSE32 0x0000 154 #define MFI_FRAME_SENSE64 0x0004 155 #define MFI_FRAME_DIR_NONE 0x0000 156 #define MFI_FRAME_DIR_WRITE 0x0008 157 #define MFI_FRAME_DIR_READ 0x0010 158 #define MFI_FRAME_DIR_BOTH 0x0018 159 #define MFI_FRAME_IEEE_SGL 0x0020 160 161 /* ThunderBolt Specific */ 162 163 /* 164 * Pre-TB command size and TB command size. 165 * We will be checking it at the load time for the time being 166 */ 167 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 168 169 #define MEGASAS_THUNDERBOLT_MSG_ALIGNMENT 256 170 /* 171 * We are defining only 128 byte message to reduce memory move over head 172 * and also it will reduce the SRB extension size by 128byte compared with 173 * 256 message size 174 */ 175 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 176 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 177 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 178 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 179 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 180 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 181 182 /* 183 * Calculating how many SGEs allowed in an allocated main message 184 * (size of the Message - Raid SCSI IO message size(except SGE)) 185 * / size of SGE 186 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 187 */ 188 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 189 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 190 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 191 ) / sizeof(mpi2_sge_io_union)) 192 193 /* 194 * (Command frame size allocated in SRB ext - Raid SCSI IO message size) 195 * / size of SGL ; 196 * (1280 - 256) / 16 = 64 197 */ 198 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 199 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 200 sizeof(mpi2_sge_io_union)) 201 202 /* 203 * This is the offset in number of 4 * 32bit words to the next chain 204 * (0x100 - 0x10)/0x10 = 0xF(15) 205 */ 206 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 207 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 208 209 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 210 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 211 212 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 213 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 214 215 #define MR_INTERNAL_MFI_FRAMES_SMID 1 216 #define MR_CTRL_EVENT_WAIT_SMID 2 217 #define MR_INTERNAL_DRIVER_RESET_SMID 3 218 219 /* mfi command opcodes */ 220 #define MFI_CMD_INIT 0x00 221 #define MFI_CMD_LD_READ 0x01 222 #define MFI_CMD_LD_WRITE 0x02 223 #define MFI_CMD_LD_SCSI_IO 0x03 224 #define MFI_CMD_PD_SCSI_IO 0x04 225 #define MFI_CMD_DCMD 0x05 226 #define MFI_CMD_ABORT 0x06 227 #define MFI_CMD_SMP 0x07 228 #define MFI_CMD_STP 0x08 229 230 /* direct commands */ 231 #define MR_DCMD_CTRL_GET_INFO 0x01010000 232 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 233 #define MR_FLUSH_CTRL_CACHE 0x01 234 #define MR_FLUSH_DISK_CACHE 0x02 235 #define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 236 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 237 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 238 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 239 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 240 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 241 #define MR_DCMD_PD_GET_LIST 0x02010000 242 #define MR_DCMD_PD_LIST_QUERY 0x02010100 243 #define MR_DCMD_PD_GET_INFO 0x02020000 244 #define MR_DCMD_PD_SET_STATE 0x02030100 245 #define MR_DCMD_PD_REBUILD 0x02040100 246 #define MR_DCMD_PD_BLINK 0x02070100 247 #define MR_DCMD_PD_UNBLINK 0x02070200 248 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 249 #define MR_DCMD_LD_SYNC 0x0300e102 250 #define MR_DCMD_LD_GET_LIST 0x03010000 251 #define MR_DCMD_LD_GET_INFO 0x03020000 252 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 253 #define MR_DCMD_CONF_GET 0x04010000 254 #define MR_DCMD_CFG_ADD 0x04020000 255 #define MR_DCMD_CFG_CLEAR 0x04030000 256 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 257 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 258 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 259 #define MR_DCMD_BBU_GET_STATUS 0x05010000 260 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 261 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 262 #define MR_DCMD_CLUSTER 0x08000000 263 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 264 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 265 266 #define MR_DCMD_SPEAKER_GET 0x01030100 267 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 268 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 269 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 270 #define MR_DCMD_SPEAKER_TEST 0x01030500 271 272 /* mailbox bytes in direct command */ 273 #define MFI_MBOX_SIZE 12 274 275 union mfi_mbox { 276 uint8_t b[MFI_MBOX_SIZE]; 277 uint16_t s[6]; 278 uint32_t w[3]; 279 }; 280 281 /* mfi completion codes */ 282 typedef enum { 283 MFI_STAT_OK = 0x00, 284 MFI_STAT_INVALID_CMD = 0x01, 285 MFI_STAT_INVALID_DCMD = 0x02, 286 MFI_STAT_INVALID_PARAMETER = 0x03, 287 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 288 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 289 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 290 MFI_STAT_APP_IN_USE = 0x07, 291 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 292 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 293 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 294 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 295 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 296 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 297 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 298 MFI_STAT_FLASH_BUSY = 0x0f, 299 MFI_STAT_FLASH_ERROR = 0x10, 300 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 301 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 302 MFI_STAT_FLASH_NOT_OPEN = 0x13, 303 MFI_STAT_FLASH_NOT_STARTED = 0x14, 304 MFI_STAT_FLUSH_FAILED = 0x15, 305 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 306 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 307 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 308 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 309 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 310 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 311 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 312 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 313 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 314 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 315 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 316 MFI_STAT_MFC_HW_ERROR = 0x21, 317 MFI_STAT_NO_HW_PRESENT = 0x22, 318 MFI_STAT_NOT_FOUND = 0x23, 319 MFI_STAT_NOT_IN_ENCL = 0x24, 320 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 321 MFI_STAT_PD_TYPE_WRONG = 0x26, 322 MFI_STAT_PR_DISABLED = 0x27, 323 MFI_STAT_ROW_INDEX_INVALID = 0x28, 324 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 325 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 326 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 327 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 328 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 329 MFI_STAT_SCSI_IO_FAILED = 0x2e, 330 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 331 MFI_STAT_SHUTDOWN_FAILED = 0x30, 332 MFI_STAT_TIME_NOT_SET = 0x31, 333 MFI_STAT_WRONG_STATE = 0x32, 334 MFI_STAT_LD_OFFLINE = 0x33, 335 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 336 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 337 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 338 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 339 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 340 MFI_STAT_INVALID_STATUS = 0xff 341 } mfi_status_t; 342 343 typedef enum { 344 MFI_EVT_CLASS_DEBUG = -2, 345 MFI_EVT_CLASS_PROGRESS = -1, 346 MFI_EVT_CLASS_INFO = 0, 347 MFI_EVT_CLASS_WARNING = 1, 348 MFI_EVT_CLASS_CRITICAL = 2, 349 MFI_EVT_CLASS_FATAL = 3, 350 MFI_EVT_CLASS_DEAD = 4 351 } mfi_evt_class_t; 352 353 typedef enum { 354 MFI_EVT_LOCALE_LD = 0x0001, 355 MFI_EVT_LOCALE_PD = 0x0002, 356 MFI_EVT_LOCALE_ENCL = 0x0004, 357 MFI_EVT_LOCALE_BBU = 0x0008, 358 MFI_EVT_LOCALE_SAS = 0x0010, 359 MFI_EVT_LOCALE_CTRL = 0x0020, 360 MFI_EVT_LOCALE_CONFIG = 0x0040, 361 MFI_EVT_LOCALE_CLUSTER = 0x0080, 362 MFI_EVT_LOCALE_ALL = 0xffff 363 } mfi_evt_locale_t; 364 365 typedef enum { 366 MR_EVT_ARGS_NONE = 0x00, 367 MR_EVT_ARGS_CDB_SENSE, 368 MR_EVT_ARGS_LD, 369 MR_EVT_ARGS_LD_COUNT, 370 MR_EVT_ARGS_LD_LBA, 371 MR_EVT_ARGS_LD_OWNER, 372 MR_EVT_ARGS_LD_LBA_PD_LBA, 373 MR_EVT_ARGS_LD_PROG, 374 MR_EVT_ARGS_LD_STATE, 375 MR_EVT_ARGS_LD_STRIP, 376 MR_EVT_ARGS_PD, 377 MR_EVT_ARGS_PD_ERR, 378 MR_EVT_ARGS_PD_LBA, 379 MR_EVT_ARGS_PD_LBA_LD, 380 MR_EVT_ARGS_PD_PROG, 381 MR_EVT_ARGS_PD_STATE, 382 MR_EVT_ARGS_PCI, 383 MR_EVT_ARGS_RATE, 384 MR_EVT_ARGS_STR, 385 MR_EVT_ARGS_TIME, 386 MR_EVT_ARGS_ECC 387 } mfi_evt_args; 388 389 /* XXX should be in mfi_evt_args ? */ 390 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 391 #define MR_EVT_ARGS_PD_ADDRESS 0x1d 392 #define MR_EVT_PD_INSERTED 0x005b 393 #define MR_EVT_PD_REMOVED 0x0070 394 #define MR_EVT_PD_STATE_CHANGE 0x0072 395 #define MR_EVT_LD_CHANGE 0x0051 396 #define MR_EVT_LD_CREATED 0x008a 397 #define MR_EVT_LD_DELETED 0x008b 398 #define MR_EVT_PD_REMOVED_EXT 0x00f8 399 #define MR_EVT_PD_INSERTED_EXT 0x00f7 400 401 402 403 typedef enum { 404 MR_PD_QUERY_TYPE_ALL = 0, 405 MR_PD_QUERY_TYPE_STATE = 1, 406 MR_PD_QUERY_TYPE_POWER_STATE = 2, 407 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 408 MR_PD_QUERY_TYPE_SPEED = 4, 409 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 410 } mfi_pd_query_type; 411 412 /* driver definitions */ 413 #define MFI_MAX_PD_CHANNELS 2 414 #define MFI_MAX_PD_ARRAY 32 415 #define MFI_MAX_LD_CHANNELS 2 416 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 417 #define MFI_MAX_CHANNEL_DEVS 128 418 #define MFI_DEFAULT_ID -1 419 #define MFI_MAX_LUN 8 420 #define MFI_MAX_LD 64 421 #define MFI_MAX_SPAN 8 422 #define MFI_MAX_ARRAY_DEDICATED 16 423 #define MFI_MAX_PD 256 424 425 /* sense buffer */ 426 struct mfi_sense { 427 uint8_t mse_data[MFI_SENSE_SIZE]; 428 }; 429 430 /* scatter gather elements */ 431 struct mfi_sg32 { 432 uint32_t addr; 433 uint32_t len; 434 }; 435 436 struct mfi_sg64 { 437 uint64_t addr; 438 uint32_t len; 439 } __packed; 440 441 struct mfi_sg_ieee { 442 uint64_t addr; 443 uint32_t len; 444 uint32_t flags; 445 }; 446 447 448 union mfi_sgl { 449 struct mfi_sg32 sg32[1]; 450 struct mfi_sg64 sg64[1]; 451 struct mfi_sg_ieee sg_ieee[1]; 452 }; 453 454 /* message frame */ 455 struct mfi_frame_header { 456 uint8_t mfh_cmd; 457 uint8_t mfh_sense_len; 458 uint8_t mfh_cmd_status; 459 uint8_t mfh_scsi_status; 460 uint8_t mfh_target_id; 461 uint8_t mfh_lun_id; 462 uint8_t mfh_cdb_len; 463 uint8_t mfh_sg_count; 464 uint32_t mfh_context; 465 uint32_t mfh_pad0; 466 uint16_t mfh_flags; 467 uint16_t mfh_timeout; 468 uint32_t mfh_data_len; 469 }; 470 471 union mfi_sgl_frame { 472 struct mfi_sg32 sge32[8]; 473 struct mfi_sg64 sge64[5]; 474 475 } __packed; 476 477 struct mfi_init_frame { 478 struct mfi_frame_header mif_header; 479 uint32_t mif_qinfo_new_addr_lo; 480 uint32_t mif_qinfo_new_addr_hi; 481 uint32_t mif_qinfo_old_addr_lo; 482 uint32_t mif_qinfo_old_addr_hi; 483 uint32_t driver_ver_lo; /* 0x28 */ 484 uint32_t driver_ver_hi; /* 0x2c */ 485 uint32_t reserved[4]; 486 } __packed; 487 488 /* queue init structure */ 489 struct mfi_init_qinfo { 490 uint32_t miq_flags; 491 uint32_t miq_rq_entries; 492 uint32_t miq_rq_addr_lo; 493 uint32_t miq_rq_addr_hi; 494 uint32_t miq_pi_addr_lo; 495 uint32_t miq_pi_addr_hi; 496 uint32_t miq_ci_addr_lo; 497 uint32_t miq_ci_addr_hi; 498 } __packed; 499 500 #define MFI_IO_FRAME_SIZE 40 501 struct mfi_io_frame { 502 struct mfi_frame_header mif_header; 503 uint32_t mif_sense_addr_lo; 504 uint32_t mif_sense_addr_hi; 505 uint32_t mif_lba_lo; 506 uint32_t mif_lba_hi; 507 union mfi_sgl mif_sgl; 508 } __packed; 509 510 #define MFI_PASS_FRAME_SIZE 48 511 struct mfi_pass_frame { 512 struct mfi_frame_header mpf_header; 513 uint32_t mpf_sense_addr_lo; 514 uint32_t mpf_sense_addr_hi; 515 uint8_t mpf_cdb[16]; 516 union mfi_sgl mpf_sgl; 517 } __packed; 518 519 #define MFI_DCMD_FRAME_SIZE 40 520 struct mfi_dcmd_frame { 521 struct mfi_frame_header mdf_header; 522 uint32_t mdf_opcode; 523 union mfi_mbox mdf_mbox; 524 union mfi_sgl mdf_sgl; 525 }; 526 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 527 528 struct mfi_abort_frame { 529 struct mfi_frame_header maf_header; 530 uint32_t maf_abort_context; 531 uint32_t maf_pad; 532 uint32_t maf_abort_mfi_addr_lo; 533 uint32_t maf_abort_mfi_addr_hi; 534 uint32_t maf_reserved[6]; 535 }; 536 537 struct mfi_smp_frame { 538 struct mfi_frame_header msf_header; 539 uint64_t msf_sas_addr; 540 union { 541 struct mfi_sg32 sg32[2]; 542 struct mfi_sg64 sg64[2]; 543 } msf_sgl; 544 } __packed; 545 546 struct mfi_stp_frame { 547 struct mfi_frame_header msf_header; 548 uint16_t msf_fis[10]; 549 uint32_t msf_stp_flags; 550 union { 551 struct mfi_sg32 sg32[2]; 552 struct mfi_sg64 sg64[2]; 553 } msf_sgl; 554 } __packed; 555 556 union mfi_frame { 557 struct mfi_frame_header mfr_header; 558 struct mfi_init_frame mfr_init; 559 struct mfi_io_frame mfr_io; 560 struct mfi_pass_frame mfr_pass; 561 struct mfi_dcmd_frame mfr_dcmd; 562 struct mfi_abort_frame mfr_abort; 563 struct mfi_smp_frame mfr_smp; 564 struct mfi_stp_frame mfr_stp; 565 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 566 }; 567 568 union mfi_evt_class_locale { 569 struct { 570 uint16_t locale; 571 uint8_t reserved; 572 int8_t class; 573 } mec_members; 574 uint32_t mec_word; 575 }; 576 577 struct mfi_evt_log_info { 578 uint32_t mel_newest_seq_num; 579 uint32_t mel_oldest_seq_num; 580 uint32_t mel_clear_seq_num; 581 uint32_t mel_shutdown_seq_num; 582 uint32_t mel_boot_seq_num; 583 }; 584 585 struct mfi_progress { 586 uint16_t mp_progress; 587 uint16_t mp_elapsed_seconds; 588 }; 589 590 struct mfi_evtarg_ld { 591 uint16_t mel_target_id; 592 uint8_t mel_ld_index; 593 uint8_t mel_reserved; 594 }; 595 596 struct mfi_evtarg_pd { 597 uint16_t mep_device_id; 598 uint8_t mep_encl_index; 599 uint8_t mep_slot_number; 600 }; 601 602 struct mfi_evtarg_pd_state { 603 struct mfi_evtarg_pd pd; 604 uint32_t prev_state; 605 uint32_t new_state; 606 }; 607 608 struct mfi_evtarg_pd_address { 609 uint16_t device_id; 610 uint16_t encl_id; 611 612 union { 613 struct { 614 uint8_t encl_index; 615 uint8_t slot_number; 616 } pd_address; 617 struct { 618 uint8_t encl_position; 619 uint8_t encl_connector_index; 620 } encl_address; 621 } address; 622 623 uint8_t scsi_dev_type; 624 625 union { 626 uint8_t port_bitmap; 627 uint8_t port_numbers; 628 } connected; 629 630 uint64_t sas_addr[2]; 631 }; 632 633 struct mfi_evt_detail { 634 uint32_t med_seq_num; 635 uint32_t med_time_stamp; 636 uint32_t med_code; 637 union mfi_evt_class_locale med_cl; 638 uint8_t med_arg_type; 639 uint8_t med_reserved1[15]; 640 641 union { 642 struct { 643 struct mfi_evtarg_pd pd; 644 uint8_t cdb_length; 645 uint8_t sense_length; 646 uint8_t reserved[2]; 647 uint8_t cdb[16]; 648 uint8_t sense[64]; 649 } __packed cdb_sense; 650 651 struct mfi_evtarg_ld ld; 652 653 struct { 654 struct mfi_evtarg_ld ld; 655 uint64_t count; 656 } __packed ld_count; 657 658 struct { 659 uint64_t lba; 660 struct mfi_evtarg_ld ld; 661 } __packed ld_lba; 662 663 struct { 664 struct mfi_evtarg_ld ld; 665 uint32_t prev_owner; 666 uint32_t new_owner; 667 } __packed ld_owner; 668 669 struct { 670 uint64_t ld_lba; 671 uint64_t pd_lba; 672 struct mfi_evtarg_ld ld; 673 struct mfi_evtarg_pd pd; 674 } __packed ld_lba_pd_lba; 675 676 struct { 677 struct mfi_evtarg_ld ld; 678 struct mfi_progress prog; 679 } __packed ld_prog; 680 681 struct { 682 struct mfi_evtarg_ld ld; 683 uint32_t prev_state; 684 uint32_t new_state; 685 } __packed ld_state; 686 687 struct { 688 uint64_t strip; 689 struct mfi_evtarg_ld ld; 690 } __packed ld_strip; 691 692 struct mfi_evtarg_pd pd; 693 694 struct { 695 struct mfi_evtarg_pd pd; 696 uint32_t err; 697 } __packed pd_err; 698 699 struct { 700 uint64_t lba; 701 struct mfi_evtarg_pd pd; 702 } __packed pd_lba; 703 704 struct { 705 uint64_t lba; 706 struct mfi_evtarg_pd pd; 707 struct mfi_evtarg_ld ld; 708 } __packed pd_lba_ld; 709 710 struct { 711 struct mfi_evtarg_pd pd; 712 struct mfi_progress prog; 713 } __packed pd_prog; 714 715 struct mfi_evtarg_pd_state pd_state; 716 717 struct { 718 uint16_t vendor_id; 719 uint16_t device_id; 720 uint16_t subvendor_id; 721 uint16_t subdevice_id; 722 } __packed pci; 723 724 uint32_t rate; 725 char str[96]; 726 727 struct { 728 uint32_t rtc; 729 uint32_t elapsed_seconds; 730 } __packed time; 731 732 struct { 733 uint32_t ecar; 734 uint32_t elog; 735 char str[64]; 736 } __packed ecc; 737 738 struct mfi_evtarg_pd_address pd_address; 739 740 uint8_t b[96]; 741 uint16_t s[48]; 742 uint32_t w[24]; 743 uint64_t d[12]; 744 } args; 745 746 char med_description[128]; 747 } __packed; 748 749 /* controller properties from mfi_ctrl_info */ 750 struct mfi_ctrl_props { 751 uint16_t mcp_seq_num; 752 uint16_t mcp_pred_fail_poll_interval; 753 uint16_t mcp_intr_throttle_cnt; 754 uint16_t mcp_intr_throttle_timeout; 755 uint8_t mcp_rebuild_rate; 756 uint8_t mcp_patrol_read_rate; 757 uint8_t mcp_bgi_rate; 758 uint8_t mcp_cc_rate; 759 uint8_t mcp_recon_rate; 760 uint8_t mcp_cache_flush_interval; 761 uint8_t mcp_spinup_drv_cnt; 762 uint8_t mcp_spinup_delay; 763 uint8_t mcp_cluster_enable; 764 uint8_t mcp_coercion_mode; 765 uint8_t mcp_alarm_enable; 766 uint8_t mcp_disable_auto_rebuild; 767 uint8_t mcp_disable_battery_warn; 768 uint8_t mcp_ecc_bucket_size; 769 uint16_t mcp_ecc_bucket_leak_rate; 770 uint8_t mcp_restore_hotspare_on_insertion; 771 uint8_t mcp_expose_encl_devices; 772 uint8_t maintainPdFailHistory; 773 uint8_t disallowHostRequestReordering; 774 /* set TRUE to abort CC on detecting an inconsistency */ 775 uint8_t abortCCOnError; 776 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 777 uint8_t loadBalanceMode; 778 /* 779 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 780 * h/w mechanism like GPIO pins 781 * 1 - disable auto detect SGPIO, 782 * 2 - disable i2c SEP auto detect 783 * 3 - disable both auto detect 784 */ 785 uint8_t disableAutoDetectBackplane; 786 /* 787 * % of source LD to be reserved for a VDs snapshot in snapshot 788 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 789 */ 790 uint8_t snapVDSpace; 791 792 /* 793 * Add properties that can be controlled by a bit in the following 794 * structure. 795 */ 796 struct { 797 /* set TRUE to disable copyBack (0=copback enabled) */ 798 uint32_t copyBackDisabled :1; 799 uint32_t SMARTerEnabled :1; 800 uint32_t prCorrectUnconfiguredAreas :1; 801 uint32_t useFdeOnly :1; 802 uint32_t disableNCQ :1; 803 uint32_t SSDSMARTerEnabled :1; 804 uint32_t SSDPatrolReadEnabled :1; 805 uint32_t enableSpinDownUnconfigured :1; 806 uint32_t autoEnhancedImport :1; 807 uint32_t enableSecretKeyControl :1; 808 uint32_t disableOnlineCtrlReset :1; 809 uint32_t allowBootWithPinnedCache :1; 810 uint32_t disableSpinDownHS :1; 811 uint32_t enableJBOD :1; 812 uint32_t disableCacheBypass :1; 813 uint32_t useDiskActivityForLocate :1; 814 uint32_t enablePI :1; 815 uint32_t preventPIImport :1; 816 uint32_t useGlobalSparesForEmergency :1; 817 uint32_t useUnconfGoodForEmergency :1; 818 uint32_t useEmergencySparesforSMARTer :1; 819 uint32_t forceSGPIOForQuadOnly :1; 820 uint32_t enableConfigAutoBalance :1; 821 uint32_t enableVirtualCache :1; 822 uint32_t enableAutoLockRecovery :1; 823 uint32_t disableImmediateIO :1; 824 uint32_t disableT10RebuildAssist :1; 825 uint32_t ignore64ldRestriction :1; 826 uint32_t enableSwZone :1; 827 uint32_t limitMaxRateSATA3G :1; 828 uint32_t reserved :2; 829 } OnOffProperties; 830 /* 831 * % of source LD to be reserved for auto snapshot in snapshot 832 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so 833 * on. 834 */ 835 uint8_t autoSnapVDSpace; 836 /* 837 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 838 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 839 */ 840 uint8_t viewSpace; 841 /* # of idle minutes before device is spun down (0=use FW defaults) */ 842 uint16_t spinDownTime; 843 uint8_t reserved[24]; 844 } __packed; 845 846 /* pci info */ 847 struct mfi_info_pci { 848 uint16_t mip_vendor; 849 uint16_t mip_device; 850 uint16_t mip_subvendor; 851 uint16_t mip_subdevice; 852 uint8_t mip_reserved[24]; 853 } __packed; 854 855 /* host interface info */ 856 struct mfi_info_host { 857 uint8_t mih_type; 858 #define MFI_INFO_HOST_PCIX 0x01 859 #define MFI_INFO_HOST_PCIE 0x02 860 #define MFI_INFO_HOST_ISCSI 0x04 861 #define MFI_INFO_HOST_SAS3G 0x08 862 uint8_t mih_reserved[6]; 863 uint8_t mih_port_count; 864 uint64_t mih_port_addr[8]; 865 } __packed; 866 867 /* device interface info */ 868 struct mfi_info_device { 869 uint8_t mid_type; 870 #define MFI_INFO_DEV_SPI 0x01 871 #define MFI_INFO_DEV_SAS3G 0x02 872 #define MFI_INFO_DEV_SATA1 0x04 873 #define MFI_INFO_DEV_SATA3G 0x08 874 uint8_t mid_reserved[6]; 875 uint8_t mid_port_count; 876 uint64_t mid_port_addr[8]; 877 } __packed; 878 879 /* firmware component info */ 880 struct mfi_info_component { 881 char mic_name[8]; 882 char mic_version[32]; 883 char mic_build_date[16]; 884 char mic_build_time[16]; 885 } __packed; 886 887 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 888 struct mfi_ctrl_info { 889 struct mfi_info_pci mci_pci; 890 struct mfi_info_host mci_host; 891 struct mfi_info_device mci_device; 892 893 /* Firmware components that are present and active. */ 894 uint32_t mci_image_check_word; 895 uint32_t mci_image_component_count; 896 struct mfi_info_component mci_image_component[8]; 897 898 /* Firmware components that have been flashed but are inactive */ 899 uint32_t mci_pending_image_component_count; 900 struct mfi_info_component mci_pending_image_component[8]; 901 902 uint8_t mci_max_arms; 903 uint8_t mci_max_spans; 904 uint8_t mci_max_arrays; 905 uint8_t mci_max_lds; 906 char mci_product_name[80]; 907 char mci_serial_number[32]; 908 uint32_t mci_hw_present; 909 #define MFI_INFO_HW_BBU 0x01 910 #define MFI_INFO_HW_ALARM 0x02 911 #define MFI_INFO_HW_NVRAM 0x04 912 #define MFI_INFO_HW_UART 0x08 913 uint32_t mci_current_fw_time; 914 uint16_t mci_max_cmds; 915 uint16_t mci_max_sg_elements; 916 uint32_t mci_max_request_size; 917 uint16_t mci_lds_present; 918 uint16_t mci_lds_degraded; 919 uint16_t mci_lds_offline; 920 uint16_t mci_pd_present; 921 uint16_t mci_pd_disks_present; 922 uint16_t mci_pd_disks_pred_failure; 923 uint16_t mci_pd_disks_failed; 924 uint16_t mci_nvram_size; 925 uint16_t mci_memory_size; 926 uint16_t mci_flash_size; 927 uint16_t mci_ram_correctable_errors; 928 uint16_t mci_ram_uncorrectable_errors; 929 uint8_t mci_cluster_allowed; 930 uint8_t mci_cluster_active; 931 uint16_t mci_max_strips_per_io; 932 933 uint32_t mci_raid_levels; 934 #define MFI_INFO_RAID_0 0x01 935 #define MFI_INFO_RAID_1 0x02 936 #define MFI_INFO_RAID_5 0x04 937 #define MFI_INFO_RAID_1E 0x08 938 #define MFI_INFO_RAID_6 0x10 939 940 uint32_t mci_adapter_ops; 941 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 942 #define MFI_INFO_AOPS_CC_RATE 0x0002 943 #define MFI_INFO_AOPS_BGI_RATE 0x0004 944 #define MFI_INFO_AOPS_RECON_RATE 0x0008 945 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 946 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 947 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 948 #define MFI_INFO_AOPS_BBU 0x0080 949 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 950 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 951 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 952 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 953 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 954 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 955 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 956 957 uint32_t mci_ld_ops; 958 #define MFI_INFO_LDOPS_READ_POLICY 0x01 959 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 960 #define MFI_INFO_LDOPS_IO_POLICY 0x04 961 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 962 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 963 964 struct { 965 uint8_t min; 966 uint8_t max; 967 uint8_t reserved[2]; 968 } __packed mci_stripe_sz_ops; 969 970 uint32_t mci_pd_ops; 971 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 972 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 973 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 974 975 uint32_t mci_pd_mix_support; 976 #define MFI_INFO_PDMIX_SAS 0x01 977 #define MFI_INFO_PDMIX_SATA 0x02 978 #define MFI_INFO_PDMIX_ENCL 0x04 979 #define MFI_INFO_PDMIX_LD 0x08 980 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 981 982 uint8_t mci_ecc_bucket_count; 983 uint8_t mci_reserved2[11]; 984 struct mfi_ctrl_props mci_properties; 985 char mci_package_version[0x60]; 986 987 uint64_t mci_dev_iface_port_addr2[8]; 988 uint8_t mci_reserved3[128]; 989 990 struct { 991 uint16_t raid_level_0; 992 uint16_t raid_level_1; 993 uint16_t raid_level_5; 994 uint16_t raid_level_1e; 995 uint16_t raid_level_6; 996 uint16_t raid_level_10; 997 uint16_t raid_level_50; 998 uint16_t raid_level_60; 999 uint16_t raid_level_1e_rlq0; 1000 uint16_t raid_level_1e0_rlq0; 1001 uint16_t reserved[6]; 1002 } __packed mci_pds_for_raid_levels; 1003 1004 uint16_t mci_max_pds; 1005 uint16_t mci_max_ded_hsps; 1006 uint16_t mci_max_global_hsps; 1007 uint16_t mci_ddf_size; 1008 uint8_t mci_max_lds_per_array; 1009 uint8_t mci_partitions_in_ddf; 1010 uint8_t mci_lock_key_binding; 1011 uint8_t mci_max_pits_per_ld; 1012 uint8_t mci_max_views_per_ld; 1013 uint8_t mci_max_target_id; 1014 uint16_t mci_max_bvl_vd_size; 1015 1016 uint16_t mci_max_configurable_ssc_size; 1017 uint16_t mci_current_ssc_size; 1018 1019 char mci_expander_fw_version[12]; 1020 1021 uint16_t mci_pfk_trial_time_remaining; 1022 uint16_t mci_cache_memory_size; 1023 1024 uint32_t mci_adapter_ops2; 1025 #define MFI_INFO_AOPS2_SUPP_PI_CTRL 0x00000001 1026 #define MFI_INFO_AOPS2_SUPP_LD_PIT1 0x00000002 1027 #define MFI_INFO_AOPS2_SUPP_LD_PIT2 0x00000004 1028 #define MFI_INFO_AOPS2_SUPP_LD_PIT3 0x00000008 1029 #define MFI_INFO_AOPS2_SUPP_LD_BBMI 0x00000010 1030 #define MFI_INFO_AOPS2_SUPP_SHIELD_STAT 0x00000020 1031 #define MFI_INFO_AOPS2_BLK_SSD_WC_CNG 0x00000040 1032 #define MFI_INFO_AOPS2_SUPP_SUSPRES_BGO 0x00000080 1033 #define MFI_INFO_AOPS2_SUPP_EMERG_SPARE 0x00000100 1034 #define MFI_INFO_AOPS2_SUPP_SET_LNKSPD 0x00000200 1035 #define MFI_INFO_AOPS2_SUPP_BT_PFK_CNG 0x00000400 1036 #define MFI_INFO_AOPS2_SUPP_JBOD 0x00000800 1037 #define MFI_INFO_AOPS2_DIS_ONLN_PFK_CNG 0x00001000 1038 #define MFI_INFO_AOPS2_SUPP_PERF_TUNE 0x00002000 1039 #define MFI_INFO_AOPS2_SUPP_SSD_PREAD 0x00004000 1040 #define MFI_INFO_AOPS2_RT_SCHED 0x00008000 1041 #define MFI_INFO_AOPS2_SUPP_RESET_NOW 0x00010000 1042 #define MFI_INFO_AOPS2_SUPP_EMU_DRIVE 0x00020000 1043 #define MFI_INFO_AOPS2_HEADLESS_MODE 0x00040000 1044 #define MFI_INFO_AOPS2_DEDIC_HSPARE_LIM 0x00080000 1045 #define MFI_INFO_AOPS2_SUPP_UNEVEN_SPAN 0x00100000 1046 1047 uint8_t mci_drv_version[32]; 1048 uint8_t mci_max_da_pd_count_spinup_60; 1049 uint8_t mci_temperature_roc; 1050 uint8_t mci_temperature_ctrl; 1051 uint8_t mci_reserved4; 1052 uint16_t mci_max_configurable_pds; 1053 uint8_t mci_reserved5[2]; 1054 1055 uint32_t cluster; 1056 1057 char cluster_id[16]; 1058 char reserved6[4]; 1059 1060 uint32_t mci_adapter_ops3; 1061 #define MFI_INFO_AOPS3_SUPP_PERSONALTY_CHANGE 0x00000003 1062 #define MFI_INFO_AOPS3_SUPP_THERMAL_POLL_INTVL 0x00000004 1063 #define MFI_INFO_AOPS3_SUPP_DIS_IMMEDIATE_IO 0x00000008 1064 #define MFI_INFO_AOPS3_SUPP_T10_REBUILD_ASSIST 0x00000010 1065 #define MFI_INFO_AOPS3_SUPP_MAX_EXT_LDS 0x00000020 1066 #define MFI_INFO_AOPS3_SUPP_CRASH_DUMP 0x00000040 1067 #define MFI_INFO_AOPS3_SUPP_SW_SONE 0x00000080 1068 #define MFI_INFO_AOPS3_SUPP_DEBUG_QUEUE 0x00000100 1069 #define MFI_INFO_AOPS3_SUPP_NVCACHE_ERASE 0x00000200 1070 #define MFI_INFO_AOPS3_SUPP_FORCE_TO_512E 0x00000400 1071 #define MFI_INFO_AOPS3_SUPP_HOQ_REBUILD 0x00000800 1072 #define MFI_INFO_AOPS3_SUPP_ALLOWED_OPS_DRVRMVL 0x00001000 1073 #define MFI_INFO_AOPS3_SUPP_DRV_ACTIVITY_LEDSET 0x00002000 1074 #define MFI_INFO_AOPS3_SUPP_NVDRAM 0x00004000 1075 #define MFI_INFO_AOPS3_SUPP_FORCE_FLASH 0x00008000 1076 #define MFI_INFO_AOPS3_SUPP_DIS_SES_MONITOR 0x00010000 1077 #define MFI_INFO_AOPS3_SUPP_CACHE_BYPASS_MODE 0x00020000 1078 #define MFI_INFO_AOPS3_SUPP_SECURITY_ON_JBOD 0x00040000 1079 #define MFI_INFO_AOPS3_DISCARD_CACHE_DUR_LD_DEL 0x00080000 1080 #define MFI_INFO_AOPS3_SUPP_TTY_LOG_COMPRESS 0x00100000 1081 #define MFI_INFO_AOPS3_SUPP_CPLD_UPDATE 0x00200000 1082 #define MFI_INFO_AOPS3_SUPP_DISK_CACHE_SYS_PD 0x00400000 1083 #define MFI_INFO_AOPS3_SUPP_EXTENDED_SSC_SIZE 0x00800000 1084 #define MFI_INFO_AOPS3_USE_SEQNUM_JBOD_FP 0x01000000 1085 1086 uint8_t mci_pad_cpld[16]; 1087 1088 uint16_t mci_adapter_ops4; 1089 1090 uint8_t mci_pad[0x800 - 0x7fe]; 1091 } __packed; 1092 1093 /* logical disk info from MR_DCMD_LD_GET_LIST */ 1094 struct mfi_ld { 1095 uint8_t mld_target; 1096 uint8_t mld_res; 1097 uint16_t mld_seq; 1098 } __packed; 1099 1100 struct mfi_ld_list { 1101 uint32_t mll_no_ld; 1102 uint32_t mll_res; 1103 struct { 1104 struct mfi_ld mll_ld; 1105 uint8_t mll_state; 1106 #define MFI_LD_OFFLINE 0x00 1107 #define MFI_LD_PART_DEGRADED 0x01 1108 #define MFI_LD_DEGRADED 0x02 1109 #define MFI_LD_ONLINE 0x03 1110 uint8_t mll_res2; 1111 uint8_t mll_res3; 1112 uint8_t mll_res4; 1113 uint64_t mll_size; 1114 } mll_list[MFI_MAX_LD]; 1115 } __packed; 1116 1117 /* logical disk details from MR_DCMD_LD_GET_INFO */ 1118 struct mfi_ld_prop { 1119 struct mfi_ld mlp_ld; 1120 char mlp_name[16]; 1121 uint8_t mlp_cache_policy; 1122 uint8_t mlp_acces_policy; 1123 uint8_t mlp_diskcache_policy; 1124 uint8_t mlp_cur_cache_policy; 1125 uint8_t mlp_disable_bgi; 1126 uint8_t mlp_res[7]; 1127 } __packed; 1128 1129 struct mfi_ld_parm { 1130 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 1131 #define MFI_DDF_PRL_RAID0 0x00 1132 #define MFI_DDF_PRL_RAID1 0x01 1133 #define MFI_DDF_PRL_RAID3 0x03 1134 #define MFI_DDF_PRL_RAID4 0x04 1135 #define MFI_DDF_PRL_RAID5 0x05 1136 #define MFI_DDF_PRL_RAID1E 0x11 1137 #define MFI_DDF_PRL_JBOD 0x0f 1138 #define MFI_DDF_PRL_CONCAT 0x1f 1139 #define MFI_DDF_PRL_RAID5E 0x15 1140 #define MFI_DDF_PRL_RAID5EE 0x25 1141 #define MFI_DDF_PRL_RAID6 0x16 1142 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 1143 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 1144 #define MFI_DDF_SRL_STRIPED 0x00 1145 #define MFI_DDF_SRL_MIRRORED 0x01 1146 #define MFI_DDF_SRL_CONCAT 0x02 1147 #define MFI_DDF_SRL_SPANNED 0x03 1148 uint8_t mpa_stripe_size; 1149 uint8_t mpa_no_drv_per_span; 1150 uint8_t mpa_span_depth; 1151 uint8_t mpa_state; 1152 uint8_t mpa_init_state; 1153 uint8_t mpa_is_consistent; 1154 uint8_t mpa_res1[6]; 1155 uint8_t mpa_isSSCD; 1156 uint8_t mpa_res[16]; 1157 } __packed; 1158 1159 struct mfi_ld_span { 1160 uint64_t mls_start_block; 1161 uint64_t mls_no_blocks; 1162 uint16_t mls_index; 1163 uint8_t mls_res[6]; 1164 } __packed; 1165 1166 struct mfi_ld_cfg { 1167 struct mfi_ld_prop mlc_prop; 1168 struct mfi_ld_parm mlc_parm; 1169 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 1170 } __packed; 1171 1172 struct mfi_ld_progress { 1173 uint32_t mlp_in_prog; 1174 #define MFI_LD_PROG_CC 0x01 1175 #define MFI_LD_PROG_BGI 0x02 1176 #define MFI_LD_PROG_FGI 0x04 1177 #define MFI_LD_PROG_RECONSTRUCT 0x08 1178 struct mfi_progress mlp_cc; 1179 struct mfi_progress mlp_bgi; 1180 struct mfi_progress mlp_fgi; 1181 struct mfi_progress mlp_reconstruct; 1182 struct mfi_progress mlp_res[4]; 1183 } __packed; 1184 1185 struct mfi_ld_details { 1186 struct mfi_ld_cfg mld_cfg; 1187 uint64_t mld_size; 1188 struct mfi_ld_progress mld_progress; 1189 uint16_t mld_clust_own_id; 1190 uint8_t mld_res1; 1191 uint8_t mld_res2; 1192 uint8_t mld_inq_page83[64]; 1193 uint8_t mld_res[16]; 1194 } __packed; 1195 1196 /* physical disk info from MR_DCMD_PD_GET_LIST */ 1197 struct mfi_pd_address { 1198 uint16_t mpa_pd_id; 1199 uint16_t mpa_enc_id; 1200 uint8_t mpa_enc_index; 1201 uint8_t mpa_enc_slot; 1202 uint8_t mpa_scsi_type; 1203 uint8_t mpa_port; 1204 uint64_t mpa_sas_address[2]; 1205 } __packed; 1206 1207 struct mfi_pd_list { 1208 uint32_t mpl_size; 1209 uint32_t mpl_no_pd; 1210 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 1211 } __packed; 1212 1213 struct mfi_pd { 1214 uint16_t mfp_id; 1215 uint16_t mfp_seq; 1216 } __packed; 1217 1218 struct mfi_pd_progress { 1219 uint32_t mfp_in_prog; 1220 #define MFI_PD_PROG_RBLD 0x01 1221 #define MFI_PD_PROG_PR 0x02 1222 #define MFI_PD_PROG_CLEAR 0x04 1223 struct mfi_progress mfp_rebuild; 1224 struct mfi_progress mfp_patrol_read; 1225 struct mfi_progress mfp_clear; 1226 struct mfi_progress mfp_res[4]; 1227 } __packed; 1228 1229 struct mfi_pd_details { 1230 struct mfi_pd mpd_pd; 1231 uint8_t mpd_inq_data[96]; 1232 uint8_t mpd_inq_page83[64]; 1233 uint8_t mpd_no_support; 1234 uint8_t mpd_scsi_type; 1235 uint8_t mpd_port; 1236 uint8_t mpd_speed; 1237 uint32_t mpd_mediaerr_cnt; 1238 uint32_t mpd_othererr_cnt; 1239 uint32_t mpd_predfail_cnt; 1240 uint32_t mpd_last_pred_event; 1241 uint16_t mpd_fw_state; 1242 uint8_t mpd_rdy_for_remove; 1243 uint8_t mpd_link_speed; 1244 uint32_t mpd_ddf_state; 1245 #define MFI_DDF_GUID_FORCED 0x01 1246 #define MFI_DDF_PART_OF_VD 0x02 1247 #define MFI_DDF_GLOB_HOTSPARE 0x04 1248 #define MFI_DDF_HOTSPARE 0x08 1249 #define MFI_DDF_FOREIGN 0x10 1250 #define MFI_DDF_TYPE_MASK 0xf000 1251 #define MFI_DDF_TYPE_UNKNOWN 0x0000 1252 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 1253 #define MFI_DDF_TYPE_SAS 0x2000 1254 #define MFI_DDF_TYPE_SATA 0x3000 1255 #define MFI_DDF_TYPE_FC 0x4000 1256 struct { 1257 uint8_t mpp_cnt; 1258 uint8_t mpp_severed; 1259 uint8_t mpp_res[6]; 1260 uint64_t mpp_sas_addr[4]; 1261 } __packed mpd_path; 1262 uint64_t mpd_size; 1263 uint64_t mpd_no_coerce_size; 1264 uint64_t mpd_coerce_size; 1265 uint16_t mpd_enc_id; 1266 uint8_t mpd_enc_idx; 1267 uint8_t mpd_enc_slot; 1268 struct mfi_pd_progress mpd_progress; 1269 uint8_t mpd_bblock_full; 1270 uint8_t mpd_unusable; 1271 uint8_t mpd_res[218]; /* size is 512 */ 1272 } __packed; 1273 1274 /* array configuration from MR_DCMD_CONF_GET */ 1275 struct mfi_array { 1276 uint64_t mar_smallest_pd; 1277 uint8_t mar_no_disk; 1278 uint8_t mar_res1; 1279 uint16_t mar_array_ref; 1280 uint8_t mar_res2[20]; 1281 struct { 1282 struct mfi_pd mar_pd; 1283 uint16_t mar_pd_state; 1284 #define MFI_PD_UNCONFIG_GOOD 0x00 1285 #define MFI_PD_UNCONFIG_BAD 0x01 1286 #define MFI_PD_HOTSPARE 0x02 1287 #define MFI_PD_OFFLINE 0x10 1288 #define MFI_PD_FAILED 0x11 1289 #define MFI_PD_REBUILD 0x14 1290 #define MFI_PD_ONLINE 0x18 1291 #define MFI_PD_COPYBACK 0x20 1292 #define MFI_PD_SYSTEM 0x40 1293 #define MFI_PD_JBOD MFI_PD_SYSTEM 1294 uint8_t mar_enc_pd; 1295 uint8_t mar_enc_slot; 1296 } pd[MFI_MAX_PD_ARRAY]; 1297 } __packed; 1298 1299 struct mfi_hotspare { 1300 struct mfi_pd mhs_pd; 1301 uint8_t mhs_type; 1302 #define MFI_PD_HS_DEDICATED 0x01 1303 #define MFI_PD_HS_REVERTIBLE 0x02 1304 #define MFI_PD_HS_ENC_AFFINITY 0x04 1305 uint8_t mhs_res[2]; 1306 uint8_t mhs_array_max; 1307 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1308 } __packed; 1309 1310 struct mfi_conf { 1311 uint32_t mfc_size; 1312 uint16_t mfc_no_array; 1313 uint16_t mfc_array_size; 1314 uint16_t mfc_no_ld; 1315 uint16_t mfc_ld_size; 1316 uint16_t mfc_no_hs; 1317 uint16_t mfc_hs_size; 1318 uint8_t mfc_res[16]; 1319 /* 1320 * XXX this is a ridiculous hack and does not reflect reality 1321 * Structures are actually indexed and therefore need pointer 1322 * math to reach. We need the size of this structure first so 1323 * call it with the size of this structure and then use the returned 1324 * values to allocate memory and do the transfer of the whole structure 1325 * then calculate pointers to each of these structures. 1326 */ 1327 struct mfi_array mfc_array[1]; 1328 struct mfi_ld_cfg mfc_ld[1]; 1329 struct mfi_hotspare mfc_hs[1]; 1330 } __packed; 1331 1332 /* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1333 struct mfi_bbu_capacity_info { 1334 uint16_t relative_charge; 1335 uint16_t absolute_charge; 1336 uint16_t remaining_capacity; 1337 uint16_t full_charge_capacity; 1338 uint16_t run_time_to_empty; 1339 uint16_t average_time_to_empty; 1340 uint16_t average_time_to_full; 1341 uint16_t cycle_count; 1342 uint16_t max_error; 1343 uint16_t remaining_capacity_alarm; 1344 uint16_t remaining_time_alarm; 1345 uint8_t reserved[26]; 1346 } __packed; 1347 1348 /* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1349 struct mfi_bbu_design_info { 1350 uint32_t mfg_date; 1351 uint16_t design_capacity; 1352 uint16_t design_voltage; 1353 uint16_t spec_info; 1354 uint16_t serial_number; 1355 uint16_t pack_stat_config; 1356 uint8_t mfg_name[12]; 1357 uint8_t device_name[8]; 1358 uint8_t device_chemistry[8]; 1359 uint8_t mfg_data[8]; 1360 uint8_t reserved[17]; 1361 } __packed; 1362 1363 struct mfi_ibbu_state { 1364 uint16_t gas_guage_status; 1365 uint16_t relative_charge; 1366 uint16_t charger_system_state; 1367 uint16_t charger_system_ctrl; 1368 uint16_t charging_current; 1369 uint16_t absolute_charge; 1370 uint16_t max_error; 1371 uint8_t reserved[18]; 1372 } __packed; 1373 1374 struct mfi_bbu_state { 1375 uint16_t gas_guage_status; 1376 uint16_t relative_charge; 1377 uint16_t charger_status; 1378 uint16_t remaining_capacity; 1379 uint16_t full_charge_capacity; 1380 uint8_t is_SOH_good; 1381 uint8_t reserved[21]; 1382 } __packed; 1383 1384 union mfi_bbu_status_detail { 1385 struct mfi_ibbu_state ibbu; 1386 struct mfi_bbu_state bbu; 1387 }; 1388 1389 /* informations from MR_DCMD_BBU_GET_STATUS */ 1390 struct mfi_bbu_status { 1391 uint8_t battery_type; 1392 #define MFI_BBU_TYPE_NONE 0 1393 #define MFI_BBU_TYPE_IBBU 1 1394 #define MFI_BBU_TYPE_BBU 2 1395 #define MFI_BBU_TYPE_IBBU09 5 1396 #define MFI_BBU_TYPE_CVPM02 6 1397 uint8_t reserved; 1398 uint16_t voltage; /* mV */ 1399 int16_t current; /* mA */ 1400 uint16_t temperature; /* degC */ 1401 uint32_t fw_status; 1402 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1403 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1404 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1405 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1406 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1407 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1408 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1409 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1410 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1411 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1412 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1413 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1414 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1415 #define MFI_BBU_STATE_BAD_IBBU ( \ 1416 MFI_BBU_STATE_PACK_MISSING | \ 1417 MFI_BBU_STATE_VOLTAGE_LOW | \ 1418 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1419 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1420 MFI_BBU_STATE_REPLACE_PACK | \ 1421 MFI_BBU_STATE_CAPACITY_LOW) 1422 #define MFI_BBU_STATE_BAD_BBU ( \ 1423 MFI_BBU_STATE_PACK_MISSING | \ 1424 MFI_BBU_STATE_REPLACE_PACK | \ 1425 MFI_BBU_STATE_CAPACITY_LOW) 1426 uint8_t pad[20]; 1427 union mfi_bbu_status_detail detail; 1428 } __packed; 1429 1430 /* ThunderBolt support */ 1431 1432 /* 1433 * Raid Context structure which describes MegaRAID specific IO Parameters 1434 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1435 */ 1436 typedef struct _mpi2_scsi_io_vendor_unique { 1437 uint16_t resvd0; /* 0x00 - 0x01 */ 1438 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1439 uint8_t regLockFlags; 1440 uint8_t armId; 1441 uint16_t TargetID; /* 0x06 - 0x07 */ 1442 1443 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1444 1445 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1446 1447 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1448 uint8_t exStatus; /* 0x16 */ 1449 uint8_t Status; /* 0x17 status */ 1450 1451 uint8_t RAIDFlags; /* 0x18 */ 1452 uint8_t numSGE; /* 0x19 numSge */ 1453 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1454 uint8_t spanArm; /* 0x1C */ 1455 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1456 } mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1457 1458 /***************************************************************************** 1459 * 1460 * Message Functions 1461 * 1462 *****************************************************************************/ 1463 1464 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1465 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1466 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1467 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1468 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1469 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1470 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1471 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1472 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1473 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1474 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1475 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1476 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1477 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1478 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1479 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1480 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1481 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1482 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1483 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1484 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1485 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1486 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1487 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1488 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1489 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1490 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1491 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1492 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1493 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1494 1495 /* Doorbell functions */ 1496 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1497 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1498 1499 /***************************************************************************** 1500 * 1501 * MPI Version Definitions 1502 * 1503 *****************************************************************************/ 1504 1505 #define MPI2_VERSION_MAJOR (0x02) 1506 #define MPI2_VERSION_MINOR (0x00) 1507 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1508 #define MPI2_VERSION_MAJOR_SHIFT (8) 1509 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1510 #define MPI2_VERSION_MINOR_SHIFT (0) 1511 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1512 MPI2_VERSION_MINOR) 1513 1514 #define MPI2_VERSION_02_00 (0x0200) 1515 1516 /* versioning for this MPI header set */ 1517 #define MPI2_HEADER_VERSION_UNIT (0x10) 1518 #define MPI2_HEADER_VERSION_DEV (0x00) 1519 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1520 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1521 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1522 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1523 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1524 MPI2_HEADER_VERSION_DEV) 1525 1526 1527 /* IOCInit Request message */ 1528 struct mpi2_ioc_init_request { 1529 uint8_t WhoInit; /* 0x00 */ 1530 uint8_t Reserved1; /* 0x01 */ 1531 uint8_t ChainOffset; /* 0x02 */ 1532 uint8_t Function; /* 0x03 */ 1533 uint16_t Reserved2; /* 0x04 */ 1534 uint8_t Reserved3; /* 0x06 */ 1535 uint8_t MsgFlags; /* 0x07 */ 1536 uint8_t VP_ID; /* 0x08 */ 1537 uint8_t VF_ID; /* 0x09 */ 1538 uint16_t Reserved4; /* 0x0A */ 1539 uint16_t MsgVersion; /* 0x0C */ 1540 uint16_t HeaderVersion; /* 0x0E */ 1541 uint32_t Reserved5; /* 0x10 */ 1542 uint16_t Reserved6; /* 0x14 */ 1543 uint8_t Reserved7; /* 0x16 */ 1544 uint8_t HostMSIxVectors; /* 0x17 */ 1545 uint16_t Reserved8; /* 0x18 */ 1546 uint16_t SystemRequestFrameSize; /* 0x1A */ 1547 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1548 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1549 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1550 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1551 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1552 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1553 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1554 uint64_t TimeStamp; /* 0x40 */ 1555 }; 1556 1557 /* WhoInit values */ 1558 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1559 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1560 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1561 #define MPI2_WHOINIT_PCI_PEER (0x03) 1562 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1563 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1564 1565 struct mpi2_sge_chain_union { 1566 uint16_t Length; 1567 uint8_t NextChainOffset; 1568 uint8_t Flags; 1569 union { 1570 uint32_t Address32; 1571 uint64_t Address64; 1572 } u; 1573 }; 1574 1575 struct mpi2_ieee_sge_simple32 { 1576 uint32_t Address; 1577 uint32_t FlagsLength; 1578 }; 1579 1580 struct mpi2_ieee_sge_simple64 { 1581 uint64_t Address; 1582 uint32_t Length; 1583 uint16_t Reserved1; 1584 uint8_t Reserved2; 1585 uint8_t Flags; 1586 }; 1587 1588 typedef union _mpi2_ieee_simple_union { 1589 struct mpi2_ieee_sge_simple32 Simple32; 1590 struct mpi2_ieee_sge_simple64 Simple64; 1591 } mpi2_ieee_simple_union; 1592 1593 typedef struct _mpi2_sge_simple_union { 1594 uint32_t FlagsLength; 1595 union { 1596 uint32_t Address32; 1597 uint64_t Address64; 1598 } u; 1599 } mpi2_sge_simple_union; 1600 1601 /* MPI 2.5 SGLs */ 1602 1603 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1604 1605 struct mpi25_ieee_sge_chain64 { 1606 uint64_t Address; 1607 uint32_t Length; 1608 uint16_t Reserved1; 1609 uint8_t NextChainOffset; 1610 uint8_t Flags; 1611 }; 1612 1613 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1614 1615 /**************************************************************************** 1616 * IEEE SGE field definitions and masks 1617 ****************************************************************************/ 1618 1619 /* Flags field bit definitions */ 1620 1621 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1622 1623 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1624 1625 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1626 1627 /* Element Type */ 1628 1629 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1630 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1631 1632 /* Data Location Address Space */ 1633 1634 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1635 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1636 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1637 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1638 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1639 1640 /* Address Size */ 1641 1642 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1643 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1644 1645 /*******************/ 1646 /* SCSI IO Control bits */ 1647 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1648 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1649 1650 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1651 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1652 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1653 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1654 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1655 1656 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1657 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1658 1659 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1660 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1661 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1662 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1663 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1664 1665 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1666 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1667 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1668 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1669 1670 /*******************/ 1671 1672 typedef struct { 1673 uint8_t CDB[20]; /* 0x00 */ 1674 uint32_t PrimaryReferenceTag; /* 0x14 */ 1675 uint16_t PrimaryApplicationTag; /* 0x18 */ 1676 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1677 uint32_t TransferLength; /* 0x1C */ 1678 } mpi2_scsi_io_cdb_eedp32; 1679 1680 1681 typedef union _mpi2_ieee_sge_chain_union { 1682 struct mpi2_ieee_sge_simple32 Chain32; 1683 struct mpi25_ieee_sge_chain64 Chain64; 1684 } mpi2_ieee_sge_chain_union; 1685 1686 typedef union _mpi2_simple_sge_union { 1687 mpi2_sge_simple_union MpiSimple; 1688 mpi2_ieee_simple_union IeeeSimple; 1689 } mpi2_simple_sge_union; 1690 1691 typedef union _mpi2_sge_io_union { 1692 mpi2_sge_simple_union MpiSimple; 1693 struct mpi2_sge_chain_union MpiChain; 1694 mpi2_ieee_simple_union IeeeSimple; 1695 mpi2_ieee_sge_chain_union IeeeChain; 1696 } mpi2_sge_io_union; 1697 1698 typedef union { 1699 uint8_t CDB32[32]; 1700 mpi2_scsi_io_cdb_eedp32 EEDP32; 1701 mpi2_sge_simple_union SGE; 1702 } mpi2_scsi_io_cdb_union; 1703 1704 1705 1706 /********/ 1707 1708 /* 1709 * RAID SCSI IO Request Message 1710 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1711 */ 1712 struct mfi_mpi2_request_raid_scsi_io { 1713 uint16_t DevHandle; /* 0x00 */ 1714 uint8_t ChainOffset; /* 0x02 */ 1715 uint8_t Function; /* 0x03 */ 1716 uint16_t Reserved1; /* 0x04 */ 1717 uint8_t Reserved2; /* 0x06 */ 1718 uint8_t MsgFlags; /* 0x07 */ 1719 uint8_t VP_ID; /* 0x08 */ 1720 uint8_t VF_ID; /* 0x09 */ 1721 uint16_t Reserved3; /* 0x0A */ 1722 uint32_t SenseBufferLowAddress; /* 0x0C */ 1723 uint16_t SGLFlags; /* 0x10 */ 1724 uint8_t SenseBufferLength; /* 0x12 */ 1725 uint8_t Reserved4; /* 0x13 */ 1726 uint8_t SGLOffset0; /* 0x14 */ 1727 uint8_t SGLOffset1; /* 0x15 */ 1728 uint8_t SGLOffset2; /* 0x16 */ 1729 uint8_t SGLOffset3; /* 0x17 */ 1730 uint32_t SkipCount; /* 0x18 */ 1731 uint32_t DataLength; /* 0x1C */ 1732 uint32_t BidirectionalDataLength; /* 0x20 */ 1733 uint16_t IoFlags; /* 0x24 */ 1734 uint16_t EEDPFlags; /* 0x26 */ 1735 uint32_t EEDPBlockSize; /* 0x28 */ 1736 uint32_t SecondaryReferenceTag; /* 0x2C */ 1737 uint16_t SecondaryApplicationTag; /* 0x30 */ 1738 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1739 uint8_t LUN[8]; /* 0x34 */ 1740 uint32_t Control; /* 0x3C */ 1741 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1742 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1743 mpi2_sge_io_union SGL; /* 0x80 */ 1744 } __packed; 1745 1746 /* 1747 * MPT RAID MFA IO Descriptor. 1748 */ 1749 typedef struct _mfi_raid_mfa_io_descriptor { 1750 uint32_t RequestFlags : 8; 1751 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1752 uint32_t MessageAddress2; /* bits 61:32 */ 1753 } mfi_raid_mfa_io_request_descriptor; 1754 1755 struct mfi_mpi2_request_header { 1756 uint8_t RequestFlags; /* 0x00 */ 1757 uint8_t MSIxIndex; /* 0x01 */ 1758 uint16_t SMID; /* 0x02 */ 1759 uint16_t LMID; /* 0x04 */ 1760 }; 1761 1762 /* defines for the RequestFlags field */ 1763 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1764 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1765 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1766 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1767 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1768 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1769 1770 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1771 1772 struct mfi_mpi2_request_high_priority { 1773 struct mfi_mpi2_request_header header; 1774 uint16_t reserved; 1775 }; 1776 1777 struct mfi_mpi2_request_scsi_io { 1778 struct mfi_mpi2_request_header header; 1779 uint16_t scsi_io_dev_handle; 1780 }; 1781 1782 struct mfi_mpi2_request_scsi_target { 1783 struct mfi_mpi2_request_header header; 1784 uint16_t scsi_target_io_index; 1785 }; 1786 1787 /* Request Descriptors */ 1788 union mfi_mpi2_request_descriptor { 1789 struct mfi_mpi2_request_header header; 1790 struct mfi_mpi2_request_high_priority high_priority; 1791 struct mfi_mpi2_request_scsi_io scsi_io; 1792 struct mfi_mpi2_request_scsi_target scsi_target; 1793 uint64_t words; 1794 }; 1795 1796 /* 1797 * Request descriptor types 1798 */ 1799 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1800 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1801 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1802 1803 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1804 1805 struct mfi_mpi2_reply_header { 1806 uint8_t ReplyFlags; /* 0x00 */ 1807 uint8_t MSIxIndex; /* 0x01 */ 1808 uint16_t SMID; /* 0x02 */ 1809 }; 1810 1811 /* defines for the ReplyFlags field */ 1812 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1813 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1814 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1815 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1816 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1817 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1818 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1819 1820 /* values for marking a reply descriptor as unused */ 1821 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1822 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1823 1824 struct mfi_mpi2_reply_default { 1825 struct mfi_mpi2_reply_header header; 1826 uint32_t DescriptorTypeDependent2; 1827 }; 1828 1829 struct mfi_mpi2_reply_address { 1830 struct mfi_mpi2_reply_header header; 1831 uint32_t ReplyFrameAddress; 1832 }; 1833 1834 struct mfi_mpi2_reply_scsi_io { 1835 struct mfi_mpi2_reply_header header; 1836 uint16_t TaskTag; /* 0x04 */ 1837 uint16_t Reserved1; /* 0x06 */ 1838 }; 1839 1840 struct mfi_mpi2_reply_target_assist { 1841 struct mfi_mpi2_reply_header header; 1842 uint8_t SequenceNumber; /* 0x04 */ 1843 uint8_t Reserved1; /* 0x04 */ 1844 uint16_t IoIndex; /* 0x06 */ 1845 }; 1846 1847 struct mfi_mpi2_reply_target_cmd_buffer { 1848 struct mfi_mpi2_reply_header header; 1849 uint8_t SequenceNumber; /* 0x04 */ 1850 uint8_t Flags; /* 0x04 */ 1851 uint16_t InitiatorDevHandle; /* 0x06 */ 1852 uint16_t IoIndex; /* 0x06 */ 1853 }; 1854 1855 struct mfi_mpi2_reply_raid_accel { 1856 struct mfi_mpi2_reply_header header; 1857 uint8_t SequenceNumber; /* 0x04 */ 1858 uint32_t Reserved; /* 0x04 */ 1859 }; 1860 1861 /* union of Reply Descriptors */ 1862 union mfi_mpi2_reply_descriptor { 1863 struct mfi_mpi2_reply_header header; 1864 struct mfi_mpi2_reply_scsi_io scsi_io; 1865 struct mfi_mpi2_reply_target_assist target_assist; 1866 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1867 struct mfi_mpi2_reply_raid_accel raid_accel; 1868 struct mfi_mpi2_reply_default reply_default; 1869 uint64_t words; 1870 }; 1871 1872 struct io_request_info { 1873 uint64_t ldStartBlock; 1874 uint32_t numBlocks; 1875 uint16_t ldTgtId; 1876 uint8_t isRead; 1877 uint16_t devHandle; 1878 uint64_t pdBlock; 1879 uint8_t fpOkForIo; 1880 }; 1881 1882 /* 1883 * Define MFI Address Context union. 1884 */ 1885 #ifdef MFI_ADDRESS_IS_uint64_t 1886 typedef uint64_t mfi_address; 1887 #else 1888 typedef union _mfi_address { 1889 struct { 1890 uint32_t addressLow; 1891 uint32_t addressHigh; 1892 } u; 1893 uint64_t address; 1894 } mfi_address; 1895 #endif 1896 1897 #define MEGASAS_MAX_NAME 32 1898 #define MEGASAS_VERSION "4.23" 1899 1900 #endif /* _DEV_IC_MFIREG_H_ */ 1901