Home
last modified time | relevance | path

Searched defs:MI_BATCH_BUFFER (Results 1 – 22 of 22) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h159 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h159 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h159 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) macro
/dports/graphics/cairo/cairo-1.17.4/src/drm/
H A Dcairo-drm-intel-command-private.h41 #define MI_BATCH_BUFFER (CMD_MI | (0x30 << 23) | 1) macro
/dports/www/firefox-esr/firefox-91.8.0/gfx/cairo/cairo/src/drm/
H A Dcairo-drm-intel-command-private.h41 #define MI_BATCH_BUFFER (CMD_MI | (0x30 << 23) | 1) macro
/dports/www/firefox/firefox-99.0/gfx/cairo/cairo/src/drm/
H A Dcairo-drm-intel-command-private.h41 #define MI_BATCH_BUFFER (CMD_MI | (0x30 << 23) | 1) macro
/dports/mail/thunderbird/thunderbird-91.8.0/gfx/cairo/cairo/src/drm/
H A Dcairo-drm-intel-command-private.h41 #define MI_BATCH_BUFFER (CMD_MI | (0x30 << 23) | 1) macro
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/i915/
H A Di915_reg.h889 #define MI_BATCH_BUFFER (0x30 << 23) macro
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/i915/
H A Di915_reg.h921 #define MI_BATCH_BUFFER (0x30<<23) macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/
H A Di915_reg.h130 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) macro
/dports/x11-drivers/xf86-video-intel/xf86-video-intel-31486f40f8e8f8923ca0799aea84b58799754564/src/legacy/i810/
H A Di810_reg.h2558 #define MI_BATCH_BUFFER ((0x30 << 23) | 1) macro
/dports/graphics/intel-backlight/intel_backlight_fbsd-a6c0e39/
H A Dintel_reg.h2791 #define MI_BATCH_BUFFER ((0x30 << 23) | 1) macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h275 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) macro