1 /* $OpenBSD: mpiireg.h,v 1.15 2019/12/29 09:34:43 jmatthew Exp $ */ 2 /* 3 * Copyright (c) 2010 Mike Belopuhov 4 * Copyright (c) 2009 James Giannoules 5 * Copyright (c) 2005 - 2010 David Gwynne <dlg@openbsd.org> 6 * Copyright (c) 2005 - 2010 Marco Peereboom <marco@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define MPII_DOORBELL (0x00) 22 /* doorbell read bits */ 23 #define MPII_DOORBELL_STATE (0xf<<28) /* ioc state */ 24 #define MPII_DOORBELL_STATE_RESET (0x0<<28) 25 #define MPII_DOORBELL_STATE_READY (0x1<<28) 26 #define MPII_DOORBELL_STATE_OPER (0x2<<28) 27 #define MPII_DOORBELL_STATE_FAULT (0x4<<28) 28 #define MPII_DOORBELL_INUSE (0x1<<27) /* doorbell used */ 29 #define MPII_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */ 30 #define MPII_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */ 31 #define MPII_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */ 32 #define MPII_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */ 33 #define MPII_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */ 34 #define MPII_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */ 35 #define MPII_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */ 36 #define MPII_DOORBELL_FAULT (0xffff<<0) /* fault code */ 37 /* doorbell write bits */ 38 #define MPII_DOORBELL_FUNCTION_SHIFT (24) 39 #define MPII_DOORBELL_FUNCTION_MASK (0xff << MPII_DOORBELL_FUNCTION_SHIFT) 40 #define MPII_DOORBELL_FUNCTION(x) \ 41 (((x) << MPII_DOORBELL_FUNCTION_SHIFT) & MPII_DOORBELL_FUNCTION_MASK) 42 #define MPII_DOORBELL_DWORDS_SHIFT 16 43 #define MPII_DOORBELL_DWORDS_MASK (0xff << MPII_DOORBELL_DWORDS_SHIFT) 44 #define MPII_DOORBELL_DWORDS(x) \ 45 (((x) << MPII_DOORBELL_DWORDS_SHIFT) & MPII_DOORBELL_DWORDS_MASK) 46 #define MPII_DOORBELL_DATA_MASK (0xffff) 47 48 #define MPII_WRITESEQ (0x04) 49 #define MPII_WRITESEQ_KEY_VALUE_MASK (0x0000000f) /* key value */ 50 #define MPII_WRITESEQ_FLUSH (0x00) 51 #define MPII_WRITESEQ_1 (0x0f) 52 #define MPII_WRITESEQ_2 (0x04) 53 #define MPII_WRITESEQ_3 (0x0b) 54 #define MPII_WRITESEQ_4 (0x02) 55 #define MPII_WRITESEQ_5 (0x07) 56 #define MPII_WRITESEQ_6 (0x0d) 57 58 #define MPII_HOSTDIAG (0x08) 59 #define MPII_HOSTDIAG_BDS_MASK (0x00001800) /* boot device select */ 60 #define MPII_HOSTDIAG_BDS_DEFAULT (0<<11) /* default address map, flash */ 61 #define MPII_HOSTDIAG_BDS_HCDW (1<<11) /* host code and data window */ 62 #define MPII_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */ 63 #define MPII_HOSTDIAG_FORCE_HCB_ONBOOT (1<<9) /* force host controlled boot */ 64 #define MPII_HOSTDIAG_HCB_MODE (1<<8) /* host controlled boot mode */ 65 #define MPII_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */ 66 #define MPII_HOSTDIAG_FBS (1<<6) /* flash bad sig */ 67 #define MPII_HOSTDIAG_RESET_HIST (1<<5) /* reset history */ 68 #define MPII_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */ 69 #define MPII_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */ 70 #define MPII_HOSTDIAG_HOLD_IOC_RESET (1<<1) /* hold ioc in reset */ 71 #define MPII_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */ 72 73 #define MPII_DIAGRWDATA (0x10) 74 75 #define MPII_DIAGRWADDRLOW (0x14) 76 77 #define MPII_DIAGRWADDRHIGH (0x18) 78 79 #define MPII_INTR_STATUS (0x30) 80 #define MPII_INTR_STATUS_SYS2IOCDB (1<<31) /* ioc written to by host */ 81 #define MPII_INTR_STATUS_RESET (1<<30) /* physical ioc reset */ 82 #define MPII_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */ 83 #define MPII_INTR_STATUS_IOC2SYSDB (1<<0) /* ioc write to doorbell */ 84 85 #define MPII_INTR_MASK (0x34) 86 #define MPII_INTR_MASK_RESET (1<<30) /* ioc reset intr mask */ 87 #define MPII_INTR_MASK_REPLY (1<<3) /* reply message intr mask */ 88 #define MPII_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */ 89 90 #define MPII_DCR_DATA (0x38) 91 92 #define MPII_DCR_ADDRESS (0x3c) 93 94 #define MPII_REPLY_FREE_HOST_INDEX (0x48) 95 96 #define MPII_REPLY_POST_HOST_INDEX (0x6c) 97 98 #define MPII_HCB_SIZE (0x74) 99 100 #define MPII_HCB_ADDRESS_LOW (0x78) 101 #define MPII_HCB_ADDRESS_HIGH (0x7c) 102 103 #define MPII_REQ_DESCR_POST_LOW (0xc0) 104 #define MPII_REQ_DESCR_POST_HIGH (0xc4) 105 106 /* 107 * Scatter Gather Lists 108 */ 109 110 #define MPII_SGE_FL_LAST (0x1<<31) /* last element in segment */ 111 #define MPII_SGE_FL_EOB (0x1<<30) /* last element of buffer */ 112 #define MPII_SGE_FL_TYPE (0x3<<28) /* element type */ 113 #define MPII_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */ 114 #define MPII_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */ 115 #define MPII_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */ 116 #define MPII_SGE_FL_LOCAL (0x1<<27) /* local address */ 117 #define MPII_SGE_FL_DIR (0x1<<26) /* direction */ 118 #define MPII_SGE_FL_DIR_OUT (0x1<<26) 119 #define MPII_SGE_FL_DIR_IN (0x0<<26) 120 #define MPII_SGE_FL_SIZE (0x1<<25) /* address size */ 121 #define MPII_SGE_FL_SIZE_32 (0x0<<25) 122 #define MPII_SGE_FL_SIZE_64 (0x1<<25) 123 #define MPII_SGE_FL_EOL (0x1<<24) /* end of list */ 124 125 struct mpii_sge { 126 u_int32_t sg_hdr; 127 u_int32_t sg_addr_lo; 128 u_int32_t sg_addr_hi; 129 } __packed __aligned(4); 130 131 /* 132 * SAS3 (IEEE) Scatter Gather Lists 133 */ 134 135 #define MPII_IEEE_SGE_ADDR_MASK (0x03) 136 #define MPII_IEEE_SGE_ADDR_SYSTEM (0x00) 137 #define MPII_IEEE_SGE_ADDR_IOCDDR (0x01) 138 #define MPII_IEEE_SGE_ADDR_IOCPLB (0x02) 139 #define MPII_IEEE_SGE_ADDR_IOCPLBNTA (0x03) 140 #define MPII_IEEE_SGE_END_OF_LIST (0x40) 141 #define MPII_IEEE_SGE_CHAIN_ELEMENT (0x80) 142 143 struct mpii_ieee_sge { 144 u_int64_t sg_addr; 145 u_int32_t sg_len; 146 u_int16_t _reserved; 147 u_int8_t sg_next_chain_offset; 148 u_int8_t sg_flags; 149 } __packed __aligned(8); 150 151 struct mpii_fw_tce { 152 u_int8_t reserved1; 153 u_int8_t context_size; 154 u_int8_t details_length; 155 u_int8_t flags; 156 157 u_int32_t reserved2; 158 159 u_int32_t image_offset; 160 161 u_int32_t image_size; 162 } __packed __aligned(4); 163 164 /* 165 * Messages 166 */ 167 168 /* functions */ 169 #define MPII_FUNCTION_SCSI_IO_REQUEST (0x00) 170 #define MPII_FUNCTION_SCSI_TASK_MGMT (0x01) 171 #define MPII_FUNCTION_IOC_INIT (0x02) 172 #define MPII_FUNCTION_IOC_FACTS (0x03) 173 #define MPII_FUNCTION_CONFIG (0x04) 174 #define MPII_FUNCTION_PORT_FACTS (0x05) 175 #define MPII_FUNCTION_PORT_ENABLE (0x06) 176 #define MPII_FUNCTION_EVENT_NOTIFICATION (0x07) 177 #define MPII_FUNCTION_EVENT_ACK (0x08) 178 #define MPII_FUNCTION_FW_DOWNLOAD (0x09) 179 #define MPII_FUNCTION_TARGET_CMD_BUFFER_POST (0x0a) 180 #define MPII_FUNCTION_TARGET_ASSIST (0x0b) 181 #define MPII_FUNCTION_TARGET_STATUS_SEND (0x0c) 182 #define MPII_FUNCTION_TARGET_MODE_ABORT (0x0d) 183 #define MPII_FUNCTION_FW_UPLOAD (0x12) 184 185 #define MPII_FUNCTION_RAID_ACTION (0x15) 186 #define MPII_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 187 188 #define MPII_FUNCTION_TOOLBOX (0x17) 189 190 #define MPII_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 191 192 #define MPII_FUNCTION_SMP_PASSTHROUGH (0x1a) 193 #define MPII_FUNCTION_SAS_IO_UNIT_CONTROL (0x1b) 194 #define MPII_FUNCTION_SATA_PASSTHROUGH (0x1c) 195 196 #define MPII_FUNCTION_DIAG_BUFFER_POST (0x1d) 197 #define MPII_FUNCTION_DIAG_RELEASE (0x1e) 198 199 #define MPII_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 200 #define MPII_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 201 202 #define MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 203 #define MPII_FUNCTION_IO_UNIT_RESET (0x41) 204 #define MPII_FUNCTION_HANDSHAKE (0x42) 205 206 /* Common IOCStatus values for all replies */ 207 #define MPII_IOCSTATUS_MASK (0x7fff) 208 #define MPII_IOCSTATUS_SUCCESS (0x0000) 209 #define MPII_IOCSTATUS_INVALID_FUNCTION (0x0001) 210 #define MPII_IOCSTATUS_BUSY (0x0002) 211 #define MPII_IOCSTATUS_INVALID_SGL (0x0003) 212 #define MPII_IOCSTATUS_INTERNAL_ERROR (0x0004) 213 #define MPII_IOCSTATUS_INVALID_VPID (0x0005) 214 #define MPII_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 215 #define MPII_IOCSTATUS_INVALID_FIELD (0x0007) 216 #define MPII_IOCSTATUS_INVALID_STATE (0x0008) 217 #define MPII_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 218 /* Config IOCStatus values */ 219 #define MPII_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 220 #define MPII_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 221 #define MPII_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 222 #define MPII_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 223 #define MPII_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 224 #define MPII_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 225 /* SCSIIO Reply initiator values */ 226 #define MPII_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 227 #define MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 228 #define MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 229 #define MPII_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 230 #define MPII_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 231 #define MPII_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 232 #define MPII_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 233 #define MPII_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 234 #define MPII_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 235 #define MPII_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 236 #define MPII_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 237 #define MPII_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 238 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */ 239 #define MPII_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 240 #define MPII_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 241 #define MPII_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 242 /* SCSI (SPI & FCP) target values */ 243 #define MPII_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 244 #define MPII_IOCSTATUS_TARGET_ABORTED (0x0063) 245 #define MPII_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 246 #define MPII_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 247 #define MPII_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 248 #define MPII_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 249 #define MPII_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 250 #define MPII_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 251 #define MPII_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 252 #define MPII_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 253 /* Serial Attached SCSI values */ 254 #define MPII_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 255 #define MPII_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 256 /* Diagnostic Tools values */ 257 #define MPII_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 258 259 #define MPII_REP_IOCLOGINFO_TYPE (0xf<<28) 260 #define MPII_REP_IOCLOGINFO_TYPE_NONE (0x0<<28) 261 #define MPII_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28) 262 #define MPII_REP_IOCLOGINFO_TYPE_FC (0x2<<28) 263 #define MPII_REP_IOCLOGINFO_TYPE_SAS (0x3<<28) 264 #define MPII_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28) 265 #define MPII_REP_IOCLOGINFO_DATA (0x0fffffff) 266 267 /* event notification types */ 268 #define MPII_EVENT_NONE (0x00) 269 #define MPII_EVENT_LOG_DATA (0x01) 270 #define MPII_EVENT_STATE_CHANGE (0x02) 271 #define MPII_EVENT_HARD_RESET_RECEIVED (0x05) 272 #define MPII_EVENT_EVENT_CHANGE (0x0a) 273 #define MPII_EVENT_TASK_SET_FULL (0x0e) 274 #define MPII_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0f) 275 #define MPII_EVENT_IR_OPERATION_STATUS (0x14) 276 #define MPII_EVENT_SAS_DISCOVERY (0x16) 277 #define MPII_EVENT_SAS_BROADCAST_PRIMITIVE (0x17) 278 #define MPII_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x18) 279 #define MPII_EVENT_SAS_INIT_TABLE_OVERFLOW (0x19) 280 #define MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x1c) 281 #define MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x1d) 282 #define MPII_EVENT_IR_VOLUME (0x1e) 283 #define MPII_EVENT_IR_PHYSICAL_DISK (0x1f) 284 #define MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x20) 285 #define MPII_EVENT_LOG_ENTRY_ADDED (0x21) 286 287 /* messages */ 288 289 #define MPII_WHOINIT_NOONE (0x00) 290 #define MPII_WHOINIT_SYSTEM_BIOS (0x01) 291 #define MPII_WHOINIT_ROM_BIOS (0x02) 292 #define MPII_WHOINIT_PCI_PEER (0x03) 293 #define MPII_WHOINIT_HOST_DRIVER (0x04) 294 #define MPII_WHOINIT_MANUFACTURER (0x05) 295 296 /* default messages */ 297 298 struct mpii_msg_request { 299 u_int8_t reserved1; 300 u_int8_t reserved2; 301 u_int8_t chain_offset; 302 u_int8_t function; 303 304 u_int8_t reserved3; 305 u_int8_t reserved4; 306 u_int8_t reserved5; 307 u_int8_t msg_flags; 308 309 u_int8_t vp_id; 310 u_int8_t vf_id; 311 u_int16_t reserved6; 312 } __packed __aligned(4); 313 314 struct mpii_msg_reply { 315 u_int16_t reserved1; 316 u_int8_t msg_length; 317 u_int8_t function; 318 319 u_int16_t reserved2; 320 u_int8_t reserved3; 321 u_int8_t msg_flags; 322 323 u_int8_t vp_id; 324 u_int8_t vf_if; 325 u_int16_t reserved4; 326 327 u_int16_t reserved5; 328 u_int16_t ioc_status; 329 330 u_int32_t ioc_loginfo; 331 } __packed __aligned(4); 332 333 /* ioc init */ 334 335 struct mpii_msg_iocinit_request { 336 u_int8_t whoinit; 337 u_int8_t reserved1; 338 u_int8_t chain_offset; 339 u_int8_t function; 340 341 u_int16_t reserved2; 342 u_int8_t reserved3; 343 u_int8_t msg_flags; 344 345 u_int8_t vp_id; 346 u_int8_t vf_id; 347 u_int16_t reserved4; 348 349 u_int8_t msg_version_min; 350 u_int8_t msg_version_maj; 351 u_int8_t hdr_version_unit; 352 u_int8_t hdr_version_dev; 353 354 u_int32_t reserved5; 355 356 u_int32_t reserved6; 357 358 u_int16_t reserved7; 359 u_int16_t system_request_frame_size; 360 361 u_int16_t reply_descriptor_post_queue_depth; 362 u_int16_t reply_free_queue_depth; 363 364 u_int32_t sense_buffer_address_high; 365 366 u_int32_t system_reply_address_high; 367 368 u_int32_t system_request_frame_base_address_lo; 369 u_int32_t system_request_frame_base_address_hi; 370 371 u_int32_t reply_descriptor_post_queue_address_lo; 372 u_int32_t reply_descriptor_post_queue_address_hi; 373 374 u_int32_t reply_free_queue_address_lo; 375 u_int32_t reply_free_queue_address_hi; 376 377 u_int64_t timestamp; 378 } __packed __aligned(4); 379 380 struct mpii_msg_iocinit_reply { 381 u_int8_t whoinit; 382 u_int8_t reserved1; 383 u_int8_t msg_length; 384 u_int8_t function; 385 386 u_int16_t reserved2; 387 u_int8_t reserved3; 388 u_int8_t msg_flags; 389 390 u_int8_t vp_id; 391 u_int8_t vf_id; 392 u_int16_t reserved4; 393 394 u_int16_t reserved5; 395 u_int16_t ioc_status; 396 397 u_int32_t ioc_loginfo; 398 } __packed __aligned(4); 399 400 struct mpii_msg_iocfacts_request { 401 u_int16_t reserved1; 402 u_int8_t chain_offset; 403 u_int8_t function; 404 405 u_int16_t reserved2; 406 u_int8_t reserved3; 407 u_int8_t msg_flags; 408 409 u_int8_t vp_id; 410 u_int8_t vf_id; 411 u_int16_t reserved4; 412 } __packed __aligned(4); 413 414 struct mpii_msg_iocfacts_reply { 415 u_int8_t msg_version_min; 416 u_int8_t msg_version_maj; 417 u_int8_t msg_length; 418 u_int8_t function; 419 420 u_int8_t header_version_dev; 421 u_int8_t header_version_unit; 422 u_int8_t ioc_number; 423 u_int8_t msg_flags; 424 425 u_int8_t vp_id; 426 u_int8_t vf_id; 427 u_int16_t reserved1; 428 429 u_int16_t ioc_exceptions; 430 #define MPII_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0) 431 #define MPII_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1) 432 #define MPII_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2) 433 #define MPII_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (1<<3) 434 #define MPII_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (1<<4) 435 #define MPII_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAC (1<<8) 436 /* XXX JPG BOOT_STATUS in bits[7:5] */ 437 /* XXX JPG all these #defines need to be fixed up */ 438 u_int16_t ioc_status; 439 440 u_int32_t ioc_loginfo; 441 442 u_int8_t max_chain_depth; 443 u_int8_t whoinit; 444 u_int8_t number_of_ports; 445 u_int8_t reserved2; 446 447 u_int16_t request_credit; 448 u_int16_t product_id; 449 450 u_int32_t ioc_capabilities; 451 #define MPII_IOCFACTS_CAPABILITY_EVENT_REPLAY (1<<13) 452 #define MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID (1<<12) 453 #define MPII_IOCFACTS_CAPABILITY_TLR (1<<11) 454 #define MPII_IOCFACTS_CAPABILITY_MULTICAST (1<<8) 455 #define MPII_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (1<<7) 456 #define MPII_IOCFACTS_CAPABILITY_EEDP (1<<6) 457 #define MPII_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4) 458 #define MPII_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3) 459 #define MPII_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (1<<2) 460 461 u_int8_t fw_version_dev; 462 u_int8_t fw_version_unit; 463 u_int8_t fw_version_min; 464 u_int8_t fw_version_maj; 465 466 u_int16_t ioc_request_frame_size; 467 u_int16_t ioc_max_chain_seg_size; 468 469 u_int16_t max_initiators; 470 u_int16_t max_targets; 471 472 u_int16_t max_sas_expanders; 473 u_int16_t max_enclosures; 474 475 u_int16_t protocol_flags; 476 u_int16_t high_priority_credit; 477 478 u_int16_t max_reply_descriptor_post_queue_depth; 479 u_int8_t reply_frame_size; 480 u_int8_t max_volumes; 481 482 u_int16_t max_dev_handle; 483 u_int16_t max_persistent_entries; 484 485 u_int32_t reserved4; 486 } __packed __aligned(4); 487 488 struct mpii_msg_portfacts_request { 489 u_int16_t reserved1; 490 u_int8_t chain_offset; 491 u_int8_t function; 492 493 u_int16_t reserved2; 494 u_int8_t port_number; 495 u_int8_t msg_flags; 496 497 u_int8_t vp_id; 498 u_int8_t vf_id; 499 u_int16_t reserved3; 500 } __packed __aligned(4); 501 502 struct mpii_msg_portfacts_reply { 503 u_int16_t reserved1; 504 u_int8_t msg_length; 505 u_int8_t function; 506 507 u_int16_t reserved2; 508 u_int8_t port_number; 509 u_int8_t msg_flags; 510 511 u_int8_t vp_id; 512 u_int8_t vf_id; 513 u_int16_t reserved3; 514 515 u_int16_t reserved4; 516 u_int16_t ioc_status; 517 518 u_int32_t ioc_loginfo; 519 520 u_int8_t reserved5; 521 u_int8_t port_type; 522 #define MPII_PORTFACTS_PORTTYPE_INACTIVE (0x00) 523 #define MPII_PORTFACTS_PORTTYPE_FC (0x10) 524 #define MPII_PORTFACTS_PORTTYPE_ISCSI (0x20) 525 #define MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 526 #define MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 527 #define MPII_PORTFACTS_PORTTYPE_TRI_MODE (0x40) 528 u_int16_t reserved6; 529 530 u_int16_t max_posted_cmd_buffers; 531 u_int16_t reserved7; 532 } __packed __aligned(4); 533 534 struct mpii_msg_portenable_request { 535 u_int16_t reserved1; 536 u_int8_t chain_offset; 537 u_int8_t function; 538 539 u_int8_t reserved2; 540 u_int8_t port_flags; 541 u_int8_t reserved3; 542 u_int8_t msg_flags; 543 544 u_int8_t vp_id; 545 u_int8_t vf_id; 546 u_int16_t reserved4; 547 } __packed __aligned(4); 548 549 struct mpii_msg_portenable_reply { 550 u_int16_t reserved1; 551 u_int8_t msg_length; 552 u_int8_t function; 553 554 u_int8_t reserved2; 555 u_int8_t port_flags; 556 u_int8_t reserved3; 557 u_int8_t msg_flags; 558 559 u_int8_t vp_id; 560 u_int8_t vf_id; 561 u_int16_t reserved4; 562 563 u_int16_t reserved5; 564 u_int16_t ioc_status; 565 566 u_int32_t ioc_loginfo; 567 } __packed __aligned(4); 568 569 struct mpii_msg_event_request { 570 u_int16_t reserved1; 571 u_int8_t chain_offset; 572 u_int8_t function; 573 574 u_int16_t reserved2; 575 u_int8_t reserved3; 576 u_int8_t msg_flags; 577 578 u_int8_t vp_id; 579 u_int8_t vf_id; 580 u_int16_t reserved4; 581 582 u_int32_t reserved5; 583 584 u_int32_t reserved6; 585 586 u_int32_t event_masks[4]; 587 588 u_int16_t sas_broadcase_primitive_masks; 589 u_int16_t reserved7; 590 591 u_int32_t reserved8; 592 } __packed __aligned(4); 593 594 struct mpii_msg_event_reply { 595 u_int16_t event_data_length; 596 u_int8_t msg_length; 597 u_int8_t function; 598 599 u_int16_t reserved1; 600 u_int8_t ack_required; 601 #define MPII_EVENT_ACK_REQUIRED (0x01) 602 u_int8_t msg_flags; 603 #define MPII_EVENT_FLAGS_REPLY_KEPT (1<<7) 604 605 u_int8_t vp_id; 606 u_int8_t vf_id; 607 u_int16_t reserved2; 608 609 u_int16_t reserved3; 610 u_int16_t ioc_status; 611 612 u_int32_t ioc_loginfo; 613 614 u_int16_t event; 615 u_int16_t reserved4; 616 617 u_int32_t event_context; 618 619 /* event data follows */ 620 } __packed __aligned(4); 621 622 struct mpii_msg_eventack_request { 623 u_int16_t reserved1; 624 u_int8_t chain_offset; 625 u_int8_t function; 626 627 u_int8_t reserved2[3]; 628 u_int8_t msg_flags; 629 630 u_int8_t vp_id; 631 u_int8_t vf_id; 632 u_int16_t reserved3; 633 634 u_int16_t event; 635 u_int16_t reserved4; 636 637 u_int32_t event_context; 638 } __packed __aligned(4); 639 640 struct mpii_msg_eventack_reply { 641 u_int16_t reserved1; 642 u_int8_t msg_length; 643 u_int8_t function; 644 645 u_int8_t reserved2[3]; 646 u_int8_t msg_flags; 647 648 u_int8_t vp_id; 649 u_int8_t vf_id; 650 u_int16_t reserved3; 651 652 u_int16_t reserved4; 653 u_int16_t ioc_status; 654 655 u_int32_t ioc_loginfo; 656 } __packed __aligned(4); 657 658 struct mpii_msg_fwupload_request { 659 u_int8_t image_type; 660 #define MPII_FWUPLOAD_IMAGETYPE_IOC_FW (0x00) 661 #define MPII_FWUPLOAD_IMAGETYPE_NV_FW (0x01) 662 #define MPII_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05) 663 #define MPII_FWUPLOAD_IMAGETYPE_NV_MANUFACTURING (0x06) 664 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_1 (0x07) 665 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_2 (0x08) 666 #define MPII_FWUPLOAD_IMAGETYPE_NV_MEGARAID (0x09) 667 #define MPII_FWUPLOAD_IMAGETYPE_NV_COMPLETE (0x0a) 668 #define MPII_FWUPLOAD_IMAGETYPE_COMMON_BOOT_BLOCK (0x0b) 669 u_int8_t reserved1; 670 u_int8_t chain_offset; 671 u_int8_t function; 672 673 u_int8_t reserved2[3]; 674 u_int8_t msg_flags; 675 676 u_int8_t vp_id; 677 u_int8_t vf_id; 678 u_int16_t reserved3; 679 680 u_int32_t reserved4; 681 682 u_int32_t reserved5; 683 684 struct mpii_fw_tce tce; 685 686 /* followed by an sgl */ 687 } __packed __aligned(4); 688 689 struct mpii_msg_fwupload_reply { 690 u_int8_t image_type; 691 u_int8_t reserved1; 692 u_int8_t msg_length; 693 u_int8_t function; 694 695 u_int8_t reserved2[3]; 696 u_int8_t msg_flags; 697 698 u_int8_t vp_id; 699 u_int8_t vf_id; 700 u_int16_t reserved3; 701 702 u_int16_t reserved4; 703 u_int16_t ioc_status; 704 705 u_int32_t ioc_loginfo; 706 707 u_int32_t actual_image_size; 708 } __packed __aligned(4); 709 710 struct mpii_msg_scsi_io { 711 u_int16_t dev_handle; 712 u_int8_t chain_offset; 713 u_int8_t function; 714 715 u_int16_t reserved1; 716 u_int8_t reserved2; 717 u_int8_t msg_flags; 718 719 u_int8_t vp_id; 720 u_int8_t vf_id; 721 u_int16_t reserved3; 722 723 u_int32_t sense_buffer_low_address; 724 725 u_int16_t sgl_flags; 726 u_int8_t sense_buffer_length; 727 u_int8_t reserved4; 728 729 u_int8_t sgl_offset0; 730 u_int8_t sgl_offset1; 731 u_int8_t sgl_offset2; 732 u_int8_t sgl_offset3; 733 734 u_int32_t skip_count; 735 736 u_int32_t data_length; 737 738 u_int32_t bidirectional_data_length; 739 740 u_int16_t io_flags; 741 u_int16_t eedp_flags; 742 743 u_int32_t eedp_block_size; 744 745 u_int32_t secondary_reference_tag; 746 747 u_int16_t secondary_application_tag; 748 u_int16_t application_tag_translation_mask; 749 750 u_int16_t lun[4]; 751 752 /* the following 16 bits are defined in MPI2 as the control field */ 753 u_int8_t reserved5; 754 u_int8_t tagging; 755 #define MPII_SCSIIO_ATTR_SIMPLE_Q (0x0) 756 #define MPII_SCSIIO_ATTR_HEAD_OF_Q (0x1) 757 #define MPII_SCSIIO_ATTR_ORDERED_Q (0x2) 758 #define MPII_SCSIIO_ATTR_ACA_Q (0x4) 759 #define MPII_SCSIIO_ATTR_UNTAGGED (0x5) 760 #define MPII_SCSIIO_ATTR_NO_DISCONNECT (0x7) 761 u_int8_t reserved6; 762 u_int8_t direction; 763 #define MPII_SCSIIO_DIR_NONE (0x0) 764 #define MPII_SCSIIO_DIR_WRITE (0x1) 765 #define MPII_SCSIIO_DIR_READ (0x2) 766 767 #define MPII_CDB_LEN (32) 768 u_int8_t cdb[MPII_CDB_LEN]; 769 770 /* followed by an sgl */ 771 } __packed __aligned(4); 772 773 struct mpii_msg_scsi_io_error { 774 u_int16_t dev_handle; 775 u_int8_t msg_length; 776 u_int8_t function; 777 778 u_int16_t reserved1; 779 u_int8_t reserved2; 780 u_int8_t msg_flags; 781 782 u_int8_t vp_id; 783 u_int8_t vf_id; 784 u_int16_t reserved3; 785 786 u_int8_t scsi_status; 787 #define MPII_SCSIIO_STATUS_GOOD (0x00) 788 #define MPII_SCSIIO_STATUS_CHECK_COND (0x02) 789 #define MPII_SCSIIO_STATUS_COND_MET (0x04) 790 #define MPII_SCSIIO_STATUS_BUSY (0x08) 791 #define MPII_SCSIIO_STATUS_INTERMEDIATE (0x10) 792 #define MPII_SCSIIO_STATUS_INTERMEDIATE_CONDMET (0x14) 793 #define MPII_SCSIIO_STATUS_RESERVATION_CONFLICT (0x18) 794 #define MPII_SCSIIO_STATUS_CMD_TERM (0x22) 795 #define MPII_SCSIIO_STATUS_TASK_SET_FULL (0x28) 796 #define MPII_SCSIIO_STATUS_ACA_ACTIVE (0x30) 797 #define MPII_SCSIIO_STATUS_TASK_ABORTED (0x40) 798 u_int8_t scsi_state; 799 #define MPII_SCSIIO_STATE_AUTOSENSE_VALID (1<<0) 800 #define MPII_SCSIIO_STATE_AUTOSENSE_FAILED (1<<1) 801 #define MPII_SCSIIO_STATE_NO_SCSI_STATUS (1<<2) 802 #define MPII_SCSIIO_STATE_TERMINATED (1<<3) 803 #define MPII_SCSIIO_STATE_RESPONSE_INFO_VALID (1<<4) 804 u_int16_t ioc_status; 805 806 u_int32_t ioc_loginfo; 807 808 u_int32_t transfer_count; 809 810 u_int32_t sense_count; 811 812 u_int32_t response_info; 813 814 u_int16_t task_tag; 815 u_int16_t reserved4; 816 817 u_int32_t bidirectional_transfer_count; 818 819 u_int32_t reserved5; 820 821 u_int32_t reserved6; 822 } __packed __aligned(4); 823 824 struct mpii_request_descr { 825 u_int8_t request_flags; 826 #define MPII_REQ_DESCR_TYPE_MASK (0x0e) 827 #define MPII_REQ_DESCR_SCSI_IO (0x00) 828 #define MPII_REQ_DESCR_SCSI_TARGET (0x02) 829 #define MPII_REQ_DESCR_HIGH_PRIORITY (0x06) 830 #define MPII_REQ_DESCR_DEFAULT (0x08) 831 u_int8_t vf_id; 832 u_int16_t smid; 833 834 u_int16_t lmid; 835 u_int16_t dev_handle; 836 } __packed __aligned(8); 837 838 struct mpii_reply_descr { 839 u_int8_t reply_flags; 840 #define MPII_REPLY_DESCR_TYPE_MASK (0x0f) 841 #define MPII_REPLY_DESCR_SCSI_IO_SUCCESS (0x00) 842 #define MPII_REPLY_DESCR_ADDRESS_REPLY (0x01) 843 #define MPII_REPLY_DESCR_TARGET_ASSIST_SUCCESS (0x02) 844 #define MPII_REPLY_DESCR_TARGET_COMMAND_BUFFER (0x03) 845 #define MPII_REPLY_DESCR_UNUSED (0x0f) 846 u_int8_t vf_id; 847 u_int16_t smid; 848 849 union { 850 u_int32_t data; 851 u_int32_t frame_addr; /* Address Reply */ 852 }; 853 } __packed __aligned(8); 854 855 struct mpii_request_header { 856 u_int16_t function_dependent1; 857 u_int8_t chain_offset; 858 u_int8_t function; 859 860 u_int16_t function_dependent2; 861 u_int8_t function_dependent3; 862 u_int8_t message_flags; 863 864 u_int8_t vp_id; 865 u_int8_t vf_id; 866 u_int16_t reserved; 867 } __packed __aligned(4); 868 869 struct mpii_msg_scsi_task_request { 870 u_int16_t dev_handle; 871 u_int8_t chain_offset; 872 u_int8_t function; 873 874 u_int8_t reserved1; 875 u_int8_t task_type; 876 #define MPII_SCSI_TASK_ABORT_TASK (0x01) 877 #define MPII_SCSI_TASK_ABRT_TASK_SET (0x02) 878 #define MPII_SCSI_TASK_TARGET_RESET (0x03) 879 #define MPII_SCSI_TASK_RESET_BUS (0x04) 880 #define MPII_SCSI_TASK_LOGICAL_UNIT_RESET (0x05) 881 u_int8_t reserved2; 882 u_int8_t msg_flags; 883 884 u_int8_t vp_id; 885 u_int8_t vf_id; 886 u_int16_t reserved3; 887 888 u_int16_t lun[4]; 889 890 u_int32_t reserved4[7]; 891 892 u_int16_t task_mid; 893 u_int16_t reserved5; 894 } __packed __aligned(4); 895 896 struct mpii_msg_scsi_task_reply { 897 u_int16_t dev_handle; 898 u_int8_t msg_length; 899 u_int8_t function; 900 901 u_int8_t response_code; 902 u_int8_t task_type; 903 u_int8_t reserved1; 904 u_int8_t msg_flags; 905 906 u_int8_t vp_id; 907 u_int8_t vf_id; 908 u_int16_t reserved2; 909 910 u_int16_t reserved3; 911 u_int16_t ioc_status; 912 913 u_int32_t ioc_loginfo; 914 915 u_int32_t termination_count; 916 } __packed __aligned(4); 917 918 struct mpii_msg_sas_oper_request { 919 u_int8_t operation; 920 #define MPII_SAS_OP_CLEAR_PERSISTENT (0x02) 921 #define MPII_SAS_OP_PHY_LINK_RESET (0x06) 922 #define MPII_SAS_OP_PHY_HARD_RESET (0x07) 923 #define MPII_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) 924 #define MPII_SAS_OP_SEND_PRIMITIVE (0x0a) 925 #define MPII_SAS_OP_FORCE_FULL_DISCOVERY (0x0b) 926 #define MPII_SAS_OP_TRANSMIT_PORT_SELECT (0x0c) 927 #define MPII_SAS_OP_REMOVE_DEVICE (0x0d) 928 #define MPII_SAS_OP_LOOKUP_MAPPING (0x0e) 929 #define MPII_SAS_OP_SET_IOC_PARAM (0x0f) 930 u_int8_t reserved1; 931 u_int8_t chain_offset; 932 u_int8_t function; 933 934 u_int16_t dev_handle; 935 u_int8_t ioc_param; 936 u_int8_t msg_flags; 937 938 u_int8_t vp_id; 939 u_int8_t vf_id; 940 u_int16_t reserved2; 941 942 u_int16_t reserved3; 943 u_int8_t phy_num; 944 u_int8_t prim_flags; 945 946 u_int32_t primitive; 947 948 u_int8_t lookup_method; 949 #define MPII_SAS_LOOKUP_METHOD_SAS_ADDR (0x01) 950 #define MPII_SAS_LOOKUP_METHOD_SAS_ENCL (0x02) 951 #define MPII_SAS_LOOKUP_METHOD_SAS_DEVNAME (0x03) 952 u_int8_t reserved4; 953 u_int16_t slot_num; 954 955 u_int64_t lookup_addr; 956 957 u_int32_t ioc_param_value; 958 959 u_int64_t reserved5; 960 } __packed __aligned(4); 961 962 struct mpii_msg_sas_oper_reply { 963 u_int8_t operation; 964 u_int8_t reserved1; 965 u_int8_t chain_offset; 966 u_int8_t function; 967 968 u_int16_t dev_handle; 969 u_int8_t ioc_param; 970 u_int8_t msg_flags; 971 972 u_int8_t vp_id; 973 u_int8_t vf_id; 974 u_int16_t reserved2; 975 976 u_int16_t reserved3; 977 u_int16_t ioc_status; 978 979 u_int32_t ioc_loginfo; 980 } __packed __aligned(4); 981 982 struct mpii_msg_raid_action_request { 983 u_int8_t action; 984 #define MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) 985 u_int8_t reserved1; 986 u_int8_t chain_offset; 987 u_int8_t function; 988 989 u_int16_t vol_dev_handle; 990 u_int8_t phys_disk_num; 991 u_int8_t msg_flags; 992 993 u_int8_t vp_id; 994 u_int8_t vf_if; 995 u_int16_t reserved2; 996 997 u_int32_t reserved3; 998 999 u_int32_t action_data; 1000 #define MPII_RAID_VOL_WRITE_CACHE_MASK (0x03) 1001 #define MPII_RAID_VOL_WRITE_CACHE_DISABLE (0x01) 1002 #define MPII_RAID_VOL_WRITE_CACHE_ENABLE (0x02) 1003 1004 struct mpii_sge action_sge; 1005 } __packed __aligned(4); 1006 1007 struct mpii_msg_raid_action_reply { 1008 u_int8_t action; 1009 u_int8_t reserved1; 1010 u_int8_t chain_offset; 1011 u_int8_t function; 1012 1013 u_int16_t vol_dev_handle; 1014 u_int8_t phys_disk_num; 1015 u_int8_t msg_flags; 1016 1017 u_int8_t vp_id; 1018 u_int8_t vf_if; 1019 u_int16_t reserved2; 1020 1021 u_int16_t reserved3; 1022 u_int16_t ioc_status; 1023 1024 u_int32_t action_data[5]; 1025 } __packed __aligned(4); 1026 1027 struct mpii_cfg_hdr { 1028 u_int8_t page_version; 1029 u_int8_t page_length; 1030 u_int8_t page_number; 1031 u_int8_t page_type; 1032 #define MPII_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0) 1033 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 1034 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 1035 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 1036 1037 #define MPII_CONFIG_REQ_PAGE_TYPE_MASK (0x0f) 1038 #define MPII_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00) 1039 #define MPII_CONFIG_REQ_PAGE_TYPE_IOC (0x01) 1040 #define MPII_CONFIG_REQ_PAGE_TYPE_BIOS (0x02) 1041 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08) 1042 #define MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09) 1043 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0a) 1044 #define MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0f) 1045 } __packed __aligned(4); 1046 1047 struct mpii_ecfg_hdr { 1048 u_int8_t page_version; 1049 u_int8_t reserved1; 1050 u_int8_t page_number; 1051 u_int8_t page_type; 1052 1053 u_int16_t ext_page_length; 1054 u_int8_t ext_page_type; 1055 #define MPII_CONFIG_REQ_PAGE_TYPE_SAS_DEVICE (0x12) 1056 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG (0x16) 1057 #define MPII_CONFIG_REQ_PAGE_TYPE_DRIVER_MAPPING (0x17) 1058 u_int8_t reserved2; 1059 } __packed __aligned(4); 1060 1061 /* config page address formats */ 1062 #define MPII_PGAD_SAS_DEVICE_FORM_MASK (0xf0000000) 1063 #define MPII_PGAD_SAS_DEVICE_FORM_GET_NEXT_HANDLE (0x00000000) 1064 #define MPII_PGAD_SAS_DEVICE_FORM_HANDLE (0x20000000) 1065 1066 #define MPII_PGAD_SAS_DEVICE_HANDLE_MASK (0x0000ffff) 1067 1068 struct mpii_msg_config_request { 1069 u_int8_t action; 1070 #define MPII_CONFIG_REQ_ACTION_PAGE_HEADER (0x00) 1071 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01) 1072 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02) 1073 #define MPII_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03) 1074 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04) 1075 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05) 1076 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06) 1077 u_int8_t sgl_flags; 1078 u_int8_t chain_offset; 1079 u_int8_t function; 1080 1081 u_int16_t ext_page_len; 1082 u_int8_t ext_page_type; 1083 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10) 1084 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11) 1085 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12) 1086 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13) 1087 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14) 1088 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 1089 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 1090 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 1091 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 1092 u_int8_t msg_flags; 1093 1094 u_int8_t vp_id; 1095 u_int8_t vf_id; 1096 u_int16_t reserved1; 1097 1098 u_int32_t reserved2[2]; 1099 1100 struct mpii_cfg_hdr config_header; 1101 1102 u_int32_t page_address; 1103 /* XXX lots of defns here */ 1104 1105 struct mpii_sge page_buffer; 1106 } __packed __aligned(4); 1107 1108 struct mpii_msg_config_reply { 1109 u_int8_t action; 1110 u_int8_t sgl_flags; 1111 u_int8_t msg_length; 1112 u_int8_t function; 1113 1114 u_int16_t ext_page_length; 1115 u_int8_t ext_page_type; 1116 u_int8_t msg_flags; 1117 1118 u_int8_t vp_id; 1119 u_int8_t vf_id; 1120 u_int16_t reserved1; 1121 1122 u_int16_t reserved2; 1123 u_int16_t ioc_status; 1124 1125 u_int32_t ioc_loginfo; 1126 1127 struct mpii_cfg_hdr config_header; 1128 } __packed __aligned(4); 1129 1130 struct mpii_cfg_manufacturing_pg0 { 1131 struct mpii_cfg_hdr config_header; 1132 1133 char chip_name[16]; 1134 char chip_revision[8]; 1135 char board_name[16]; 1136 char board_assembly[16]; 1137 char board_tracer_number[16]; 1138 } __packed __aligned(4); 1139 1140 struct mpii_cfg_ioc_pg1 { 1141 struct mpii_cfg_hdr config_header; 1142 1143 u_int32_t flags; 1144 1145 u_int32_t coalescing_timeout; 1146 #define MPII_CFG_IOC_1_REPLY_COALESCING (1<<0) 1147 1148 u_int8_t coalescing_depth; 1149 u_int8_t pci_slot_num; 1150 u_int8_t pci_bus_num; 1151 u_int8_t pci_domain_segment; 1152 1153 u_int32_t reserved1; 1154 1155 u_int32_t reserved2; 1156 } __packed __aligned(4); 1157 1158 struct mpii_cfg_ioc_pg3 { 1159 struct mpii_cfg_hdr config_header; 1160 1161 u_int8_t no_phys_disks; 1162 u_int8_t reserved[3]; 1163 1164 /* followed by a list of mpii_cfg_raid_physdisk structs */ 1165 } __packed __aligned(4); 1166 1167 struct mpii_cfg_ioc_pg8 { 1168 struct mpii_cfg_hdr config_header; 1169 1170 u_int8_t num_devs_per_enclosure; 1171 u_int8_t reserved1; 1172 u_int16_t reserved2; 1173 1174 u_int16_t max_persistent_entries; 1175 u_int16_t max_num_physical_mapped_ids; 1176 1177 u_int16_t flags; 1178 #define MPII_IOC_PG8_FLAGS_DA_START_SLOT_1 (1<<5) 1179 #define MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0 (1<<4) 1180 #define MPII_IOC_PG8_FLAGS_MAPPING_MODE_MASK (0x0000000e) 1181 #define MPII_IOC_PG8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0<<1) 1182 #define MPII_IOC_PG8_FLAGS_ENCLOSURE_SLOT_MAPPING (1<<1) 1183 #define MPII_IOC_PG8_FLAGS_DISABLE_PERSISTENT_MAPPING (1<<0) 1184 #define MPII_IOC_PG8_FLAGS_ENABLE_PERSISTENT_MAPPING (0<<0) 1185 u_int16_t reserved3; 1186 1187 u_int16_t ir_volume_mapping_flags; 1188 #define MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK (0x00000003) 1189 #define MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING (0<<0) 1190 #define MPII_IOC_PG8_IRFLAGS_HIGH_VOLUME_MAPPING (1<<0) 1191 u_int16_t reserved4; 1192 1193 u_int32_t reserved5; 1194 } __packed __aligned(4); 1195 1196 struct mpii_cfg_raid_physdisk { 1197 u_int8_t phys_disk_id; 1198 u_int8_t phys_disk_bus; 1199 u_int8_t phys_disk_ioc; 1200 u_int8_t phys_disk_num; 1201 } __packed __aligned(4); 1202 1203 struct mpii_cfg_fc_port_pg0 { 1204 struct mpii_cfg_hdr config_header; 1205 1206 u_int32_t flags; 1207 1208 u_int8_t mpii_port_nr; 1209 u_int8_t link_type; 1210 u_int8_t port_state; 1211 u_int8_t reserved1; 1212 1213 u_int32_t port_id; 1214 1215 u_int64_t wwnn; 1216 1217 u_int64_t wwpn; 1218 1219 u_int32_t supported_service_class; 1220 1221 u_int32_t supported_speeds; 1222 1223 u_int32_t current_speed; 1224 1225 u_int32_t max_frame_size; 1226 1227 u_int64_t fabric_wwnn; 1228 1229 u_int64_t fabric_wwpn; 1230 1231 u_int32_t discovered_port_count; 1232 1233 u_int32_t max_initiators; 1234 1235 u_int8_t max_aliases_supported; 1236 u_int8_t max_hard_aliases_supported; 1237 u_int8_t num_current_aliases; 1238 u_int8_t reserved2; 1239 } __packed __aligned(4); 1240 1241 struct mpii_cfg_fc_port_pg1 { 1242 struct mpii_cfg_hdr config_header; 1243 1244 u_int32_t flags; 1245 1246 u_int64_t noseepromwwnn; 1247 1248 u_int64_t noseepromwwpn; 1249 1250 u_int8_t hard_alpa; 1251 u_int8_t link_config; 1252 u_int8_t topology_config; 1253 u_int8_t alt_connector; 1254 1255 u_int8_t num_req_aliases; 1256 u_int8_t rr_tov; 1257 u_int8_t initiator_dev_to; 1258 u_int8_t initiator_lo_pend_to; 1259 } __packed __aligned(4); 1260 1261 struct mpii_cfg_fc_device_pg0 { 1262 struct mpii_cfg_hdr config_header; 1263 1264 u_int64_t wwnn; 1265 1266 u_int64_t wwpn; 1267 1268 u_int32_t port_id; 1269 1270 u_int8_t protocol; 1271 u_int8_t flags; 1272 u_int16_t bb_credit; 1273 1274 u_int16_t max_rx_frame_size; 1275 u_int8_t adisc_hard_alpa; 1276 u_int8_t port_nr; 1277 1278 u_int8_t fc_ph_low_version; 1279 u_int8_t fc_ph_high_version; 1280 u_int8_t current_target_id; 1281 u_int8_t current_bus; 1282 } __packed __aligned(4); 1283 1284 #define MPII_CFG_RAID_VOL_ADDR_HANDLE (1<<28) 1285 1286 struct mpii_cfg_raid_vol_pg0 { 1287 struct mpii_cfg_hdr config_header; 1288 1289 u_int16_t volume_handle; 1290 u_int8_t volume_state; 1291 #define MPII_CFG_RAID_VOL_0_STATE_MISSING (0x00) 1292 #define MPII_CFG_RAID_VOL_0_STATE_FAILED (0x01) 1293 #define MPII_CFG_RAID_VOL_0_STATE_INITIALIZING (0x02) 1294 #define MPII_CFG_RAID_VOL_0_STATE_ONLINE (0x03) 1295 #define MPII_CFG_RAID_VOL_0_STATE_DEGRADED (0x04) 1296 #define MPII_CFG_RAID_VOL_0_STATE_OPTIMAL (0x05) 1297 u_int8_t volume_type; 1298 #define MPII_CFG_RAID_VOL_0_TYPE_RAID0 (0x00) 1299 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1E (0x01) 1300 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1 (0x02) 1301 #define MPII_CFG_RAID_VOL_0_TYPE_RAID10 (0x05) 1302 #define MPII_CFG_RAID_VOL_0_TYPE_UNKNOWN (0xff) 1303 1304 u_int32_t volume_status; 1305 #define MPII_CFG_RAID_VOL_0_STATUS_SCRUB (1<<20) 1306 #define MPII_CFG_RAID_VOL_0_STATUS_RESYNC (1<<16) 1307 1308 u_int16_t volume_settings; 1309 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK (0x3<<0) 1310 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_UNCHANGED (0x0<<0) 1311 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_DISABLED (0x1<<0) 1312 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED (0x2<<0) 1313 1314 u_int8_t hot_spare_pool; 1315 u_int8_t reserved1; 1316 1317 u_int64_t max_lba; 1318 1319 u_int32_t stripe_size; 1320 1321 u_int16_t block_size; 1322 u_int16_t reserved2; 1323 1324 u_int8_t phys_disk_types; 1325 u_int8_t resync_rate; 1326 u_int16_t data_scrub_rate; 1327 1328 u_int8_t num_phys_disks; 1329 u_int16_t reserved3; 1330 u_int8_t inactive_status; 1331 #define MPII_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00) 1332 #define MPII_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01) 1333 #define MPII_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02) 1334 #define MPII_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03) 1335 #define MPII_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04) 1336 #define MPII_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05) 1337 1338 /* followed by a list of mpii_cfg_raid_vol_pg0_physdisk structs */ 1339 } __packed __aligned(4); 1340 1341 struct mpii_cfg_raid_vol_pg0_physdisk { 1342 u_int8_t raid_set_num; 1343 u_int8_t phys_disk_map; 1344 u_int8_t phys_disk_num; 1345 u_int8_t reserved; 1346 } __packed __aligned(4); 1347 1348 struct mpii_cfg_raid_vol_pg1 { 1349 struct mpii_cfg_hdr config_header; 1350 1351 u_int8_t volume_id; 1352 u_int8_t volume_bus; 1353 u_int8_t volume_ioc; 1354 u_int8_t reserved1; 1355 1356 u_int8_t guid[24]; 1357 1358 u_int8_t name[16]; 1359 1360 u_int64_t wwid; 1361 1362 u_int32_t reserved2; 1363 1364 u_int32_t reserved3; 1365 } __packed __aligned(4); 1366 1367 #define MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER (1<<28) 1368 1369 struct mpii_cfg_raid_physdisk_pg0 { 1370 struct mpii_cfg_hdr config_header; 1371 1372 u_int16_t dev_handle; 1373 u_int8_t reserved1; 1374 u_int8_t phys_disk_num; 1375 1376 u_int8_t enc_id; 1377 u_int8_t enc_bus; 1378 u_int8_t hot_spare_pool; 1379 u_int8_t enc_type; 1380 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0) 1381 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1) 1382 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2) 1383 1384 u_int32_t reserved2; 1385 1386 u_int8_t vendor_id[8]; 1387 1388 u_int8_t product_id[16]; 1389 1390 u_int8_t product_rev[4]; 1391 1392 u_int8_t serial[32]; 1393 1394 u_int32_t reserved3; 1395 1396 u_int8_t phys_disk_state; 1397 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED (0x00) 1398 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE (0x01) 1399 #define MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x02) 1400 #define MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x03) 1401 #define MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE (0x04) 1402 #define MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED (0x05) 1403 #define MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING (0x06) 1404 #define MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL (0x07) 1405 u_int8_t offline_reason; 1406 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_MISSING (0x01) 1407 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED (0x03) 1408 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_INITIALIZING (0x04) 1409 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_REQUESTED (0x05) 1410 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ (0x06) 1411 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_OTHER (0xff) 1412 1413 u_int8_t incompat_reason; 1414 u_int8_t phys_disk_attrs; 1415 1416 u_int32_t phys_disk_status; 1417 #define MPII_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0) 1418 #define MPII_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1) 1419 1420 u_int64_t dev_max_lba; 1421 1422 u_int64_t host_max_lba; 1423 1424 u_int64_t coerced_max_lba; 1425 1426 u_int16_t block_size; 1427 u_int16_t reserved4; 1428 1429 u_int32_t reserved5; 1430 } __packed __aligned(4); 1431 1432 struct mpii_cfg_raid_physdisk_pg1 { 1433 struct mpii_cfg_hdr config_header; 1434 1435 u_int8_t num_phys_disk_paths; 1436 u_int8_t phys_disk_num; 1437 u_int16_t reserved1; 1438 1439 u_int32_t reserved2; 1440 1441 /* followed by mpii_cfg_raid_physdisk_path structs */ 1442 } __packed __aligned(4); 1443 1444 struct mpii_cfg_raid_physdisk_path { 1445 u_int8_t phys_disk_id; 1446 u_int8_t phys_disk_bus; 1447 u_int16_t reserved1; 1448 1449 u_int64_t wwwid; 1450 1451 u_int64_t owner_wwid; 1452 1453 u_int8_t ownder_id; 1454 u_int8_t reserved2; 1455 u_int16_t flags; 1456 #define MPII_CFG_RAID_PHYDISK_PATH_INVALID (1<<0) 1457 #define MPII_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1) 1458 } __packed __aligned(4); 1459 1460 #define MPII_CFG_SAS_DEV_ADDR_NEXT (0<<28) 1461 #define MPII_CFG_SAS_DEV_ADDR_BUS (1<<28) 1462 #define MPII_CFG_SAS_DEV_ADDR_HANDLE (2<<28) 1463 1464 struct mpii_cfg_sas_dev_pg0 { 1465 struct mpii_ecfg_hdr config_header; 1466 1467 u_int16_t slot; 1468 u_int16_t enc_handle; 1469 1470 u_int64_t sas_addr; 1471 1472 u_int16_t parent_dev_handle; 1473 u_int8_t phy_num; 1474 u_int8_t access_status; 1475 1476 u_int16_t dev_handle; 1477 u_int8_t target; 1478 u_int8_t bus; 1479 1480 u_int32_t device_info; 1481 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE (0x7) 1482 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE (0x0) 1483 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_END (0x1) 1484 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER (0x2) 1485 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER (0x3) 1486 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_HOST (1<<3) 1487 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR (1<<4) 1488 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR (1<<5) 1489 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR (1<<6) 1490 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE (1<<7) 1491 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET (1<<8) 1492 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_TARGET (1<<9) 1493 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET (1<<10) 1494 #define MPII_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED (1<<11) 1495 #define MPII_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE (1<<12) 1496 #define MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE (1<<13) 1497 #define MPII_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE (1<<14) 1498 1499 u_int16_t flags; 1500 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT (1<<0) 1501 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED (1<<1) 1502 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT (1<<2) 1503 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR (1<<3) 1504 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_FUA (1<<4) 1505 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_NCQ (1<<5) 1506 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SMART (1<<6) 1507 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_LBA48 (1<<7) 1508 #define MPII_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED (1<<8) 1509 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS (1<<9) 1510 u_int8_t physical_port; 1511 u_int8_t max_port_conn; 1512 1513 u_int64_t device_name; 1514 1515 u_int8_t port_groups; 1516 u_int8_t dma_group; 1517 u_int8_t ctrl_group; 1518 u_int8_t reserved1; 1519 1520 u_int64_t reserved2; 1521 } __packed __aligned(4); 1522 1523 #define MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG (2<<28) 1524 1525 struct mpii_cfg_raid_config_pg0 { 1526 struct mpii_ecfg_hdr config_header; 1527 1528 u_int8_t num_hot_spares; 1529 u_int8_t num_phys_disks; 1530 u_int8_t num_volumes; 1531 u_int8_t config_num; 1532 1533 u_int32_t flags; 1534 #define MPII_CFG_RAID_CONFIG_0_FLAGS_NATIVE (0<<0) 1535 #define MPII_CFG_RAID_CONFIG_0_FLAGS_FOREIGN (1<<0) 1536 1537 u_int32_t config_guid[6]; 1538 1539 u_int32_t reserved1; 1540 1541 u_int8_t num_elements; 1542 u_int8_t reserved2[3]; 1543 1544 /* followed by struct mpii_raid_config_element structs */ 1545 } __packed __aligned(4); 1546 1547 struct mpii_raid_config_element { 1548 u_int16_t element_flags; 1549 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME (0x0) 1550 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME_PHYS_DISK (0x1) 1551 #define MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK (0x2) 1552 #define MPII_RAID_CONFIG_ELEMENT_ONLINE_CE_PHYS_DISK (0x3) 1553 u_int16_t vol_dev_handle; 1554 1555 u_int8_t hot_spare_pool; 1556 u_int8_t phys_disk_num; 1557 u_int16_t phys_disk_dev_handle; 1558 } __packed __aligned(4); 1559 1560 struct mpii_cfg_dpm_pg0 { 1561 struct mpii_ecfg_hdr config_header; 1562 #define MPII_DPM_ADDRESS_FORM_MASK (0xf0000000) 1563 #define MPII_DPM_ADDRESS_FORM_ENTRY_RANGE (0x00000000) 1564 #define MPII_DPM_ADDRESS_ENTRY_COUNT_MASK (0x0fff0000) 1565 #define MPII_DPM_ADDRESS_ENTRY_COUNT_SHIFT (16) 1566 #define MPII_DPM_ADDRESS_START_ENTRY_MASK (0x0000ffff) 1567 1568 /* followed by struct mpii_dpm_entry structs */ 1569 } __packed __aligned(4); 1570 1571 struct mpii_dpm_entry { 1572 u_int64_t physical_identifier; 1573 1574 u_int16_t mapping_information; 1575 u_int16_t device_index; 1576 1577 u_int32_t physical_bits_mapping; 1578 1579 u_int32_t reserved1; 1580 } __packed __aligned(4); 1581 1582 struct mpii_evt_sas_discovery { 1583 u_int8_t flags; 1584 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_MASK (1<<1) 1585 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_NO_CHANGE (0<<1) 1586 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_CHANGE (1<<1) 1587 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROG_MASK (1<<0) 1588 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_NOT_IN_PROGRESS (1<<0) 1589 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROGRESS (0<<0) 1590 u_int8_t reason_code; 1591 #define MPII_EVENT_SAS_DISC_REASON_CODE_STARTED (0x01) 1592 #define MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED (0x02) 1593 u_int8_t physical_port; 1594 u_int8_t reserved1; 1595 1596 u_int32_t discovery_status; 1597 } __packed __aligned(4); 1598 1599 struct mpii_evt_ir_status { 1600 u_int16_t vol_dev_handle; 1601 u_int16_t reserved1; 1602 1603 u_int8_t operation; 1604 #define MPII_EVENT_IR_RAIDOP_RESYNC (0x00) 1605 #define MPII_EVENT_IR_RAIDOP_OCE (0x01) 1606 #define MPII_EVENT_IR_RAIDOP_CONS_CHECK (0x02) 1607 #define MPII_EVENT_IR_RAIDOP_BG_INIT (0x03) 1608 #define MPII_EVENT_IR_RAIDOP_MAKE_CONS (0x04) 1609 u_int8_t percent; 1610 u_int16_t reserved2; 1611 1612 u_int32_t reserved3; 1613 }; 1614 1615 struct mpii_evt_ir_volume { 1616 u_int16_t vol_dev_handle; 1617 u_int8_t reason_code; 1618 #define MPII_EVENT_IR_VOL_RC_SETTINGS_CHANGED (0x01) 1619 #define MPII_EVENT_IR_VOL_RC_STATUS_CHANGED (0x02) 1620 #define MPII_EVENT_IR_VOL_RC_STATE_CHANGED (0x03) 1621 u_int8_t reserved1; 1622 1623 u_int32_t new_value; 1624 u_int32_t prev_value; 1625 } __packed __aligned(4); 1626 1627 struct mpii_evt_ir_physical_disk { 1628 u_int16_t reserved1; 1629 u_int8_t reason_code; 1630 #define MPII_EVENT_IR_PD_RC_SETTINGS_CHANGED (0x01) 1631 #define MPII_EVENT_IR_PD_RC_STATUS_FLAGS_CHANGED (0x02) 1632 #define MPII_EVENT_IR_PD_RC_STATUS_CHANGED (0x03) 1633 u_int8_t phys_disk_num; 1634 1635 u_int16_t phys_disk_dev_handle; 1636 u_int16_t reserved2; 1637 1638 u_int16_t slot; 1639 u_int16_t enclosure_handle; 1640 1641 u_int32_t new_value; 1642 u_int32_t previous_value; 1643 } __packed __aligned(4); 1644 1645 struct mpii_evt_sas_tcl { 1646 u_int16_t enclosure_handle; 1647 u_int16_t expander_handle; 1648 1649 u_int8_t num_phys; 1650 u_int8_t reserved1[3]; 1651 1652 u_int8_t num_entries; 1653 u_int8_t start_phy_num; 1654 u_int8_t expn_status; 1655 #define MPII_EVENT_SAS_TOPO_ES_ADDED (0x01) 1656 #define MPII_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1657 #define MPII_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1658 #define MPII_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1659 u_int8_t physical_port; 1660 1661 /* followed by num_entries number of struct mpii_evt_phy_entry */ 1662 } __packed __aligned(4); 1663 1664 struct mpii_evt_phy_entry { 1665 u_int16_t dev_handle; 1666 u_int8_t link_rate; 1667 u_int8_t phy_status; 1668 #define MPII_EVENT_SAS_TOPO_PS_RC_MASK (0x0f) 1669 #define MPII_EVENT_SAS_TOPO_PS_RC_ADDED (0x01) 1670 #define MPII_EVENT_SAS_TOPO_PS_RC_MISSING (0x02) 1671 } __packed __aligned(4); 1672 1673 struct mpii_evt_ir_cfg_change_list { 1674 u_int8_t num_elements; 1675 u_int16_t reserved; 1676 u_int8_t config_num; 1677 1678 u_int32_t flags; 1679 #define MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN (0x1) 1680 1681 /* followed by num_elements struct mpii_evt_ir_cfg_elements */ 1682 } __packed __aligned(4); 1683 1684 struct mpii_evt_ir_cfg_element { 1685 u_int16_t element_flags; 1686 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK (0xf) 1687 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME (0x0) 1688 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK (0x1) 1689 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE (0x2) 1690 u_int16_t vol_dev_handle; 1691 1692 u_int8_t reason_code; 1693 #define MPII_EVT_IR_CFG_ELEMENT_RC_ADDED (0x01) 1694 #define MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED (0x02) 1695 #define MPII_EVT_IR_CFG_ELEMENT_RC_NO_CHANGE (0x03) 1696 #define MPII_EVT_IR_CFG_ELEMENT_RC_HIDE (0x04) 1697 #define MPII_EVT_IR_CFG_ELEMENT_RC_UNHIDE (0x05) 1698 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED (0x06) 1699 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED (0x07) 1700 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED (0x08) 1701 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_DELETED (0x09) 1702 u_int8_t phys_disk_num; 1703 u_int16_t phys_disk_dev_handle; 1704 } __packed __aligned(4); 1705