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Searched defs:MSR_IA32_MISC_ENABLE (Results 1 – 25 of 92) sorted by relevance

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/dports/sysutils/x86info/x86info-1b41e8b/include/
H A Dintel.h33 #define MSR_IA32_MISC_ENABLE 0x1a0 macro
/dports/net-mgmt/collectd5/collectd-5.12.0/src/
H A Dmsr-index.h82 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/lang/gnatdroid-sysroot-x86/android-19-x86/usr/include/asm/
H A Dmsr-index.h186 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/devel/py-pyperf/pyperf-2.3.0/pyperf/
H A D_system.py17 MSR_IA32_MISC_ENABLE = 0x1a0 variable
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/x86/include/asm/
H A Dmsr-index.h369 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/x86/include/asm/
H A Dmsr-index.h407 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/
H A Dmsr-index.h407 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/x86/include/asm/
H A Dmsr-index.h407 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/
H A Dmsr-index.h407 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/x86/include/asm/
H A Dmsr-index.h100 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/x86/include/asm/
H A Dmsr-index.h407 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/x86/include/asm/
H A Dmsr-index.h115 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro

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