xref: /qemu/target/i386/cpu.h (revision 62d39b28)
1 /*
2  * i386 virtual CPU header
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22 
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "exec/memop.h"
28 #include "hw/i386/topology.h"
29 #include "qapi/qapi-types-common.h"
30 #include "qemu/cpu-float.h"
31 #include "qemu/timer.h"
32 
33 #define XEN_NR_VIRQS 24
34 
35 #define KVM_HAVE_MCE_INJECTION 1
36 
37 /* support for self modifying code even if the modified instruction is
38    close to the modifying instruction */
39 #define TARGET_HAS_PRECISE_SMC
40 
41 #ifdef TARGET_X86_64
42 #define I386_ELF_MACHINE  EM_X86_64
43 #define ELF_MACHINE_UNAME "x86_64"
44 #else
45 #define I386_ELF_MACHINE  EM_386
46 #define ELF_MACHINE_UNAME "i686"
47 #endif
48 
49 enum {
50     R_EAX = 0,
51     R_ECX = 1,
52     R_EDX = 2,
53     R_EBX = 3,
54     R_ESP = 4,
55     R_EBP = 5,
56     R_ESI = 6,
57     R_EDI = 7,
58     R_R8 = 8,
59     R_R9 = 9,
60     R_R10 = 10,
61     R_R11 = 11,
62     R_R12 = 12,
63     R_R13 = 13,
64     R_R14 = 14,
65     R_R15 = 15,
66 
67     R_AL = 0,
68     R_CL = 1,
69     R_DL = 2,
70     R_BL = 3,
71     R_AH = 4,
72     R_CH = 5,
73     R_DH = 6,
74     R_BH = 7,
75 };
76 
77 typedef enum X86Seg {
78     R_ES = 0,
79     R_CS = 1,
80     R_SS = 2,
81     R_DS = 3,
82     R_FS = 4,
83     R_GS = 5,
84     R_LDTR = 6,
85     R_TR = 7,
86 } X86Seg;
87 
88 /* segment descriptor fields */
89 #define DESC_G_SHIFT    23
90 #define DESC_G_MASK     (1 << DESC_G_SHIFT)
91 #define DESC_B_SHIFT    22
92 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
93 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
94 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
95 #define DESC_AVL_SHIFT  20
96 #define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
97 #define DESC_P_SHIFT    15
98 #define DESC_P_MASK     (1 << DESC_P_SHIFT)
99 #define DESC_DPL_SHIFT  13
100 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
101 #define DESC_S_SHIFT    12
102 #define DESC_S_MASK     (1 << DESC_S_SHIFT)
103 #define DESC_TYPE_SHIFT 8
104 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
105 #define DESC_A_MASK     (1 << 8)
106 
107 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
108 #define DESC_C_MASK     (1 << 10) /* code: conforming */
109 #define DESC_R_MASK     (1 << 9)  /* code: readable */
110 
111 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
112 #define DESC_W_MASK     (1 << 9)  /* data: writable */
113 
114 #define DESC_TSS_BUSY_MASK (1 << 9)
115 
116 /* eflags masks */
117 #define CC_C    0x0001
118 #define CC_P    0x0004
119 #define CC_A    0x0010
120 #define CC_Z    0x0040
121 #define CC_S    0x0080
122 #define CC_O    0x0800
123 
124 #define TF_SHIFT   8
125 #define IOPL_SHIFT 12
126 #define VM_SHIFT   17
127 
128 #define TF_MASK                 0x00000100
129 #define IF_MASK                 0x00000200
130 #define DF_MASK                 0x00000400
131 #define IOPL_MASK               0x00003000
132 #define NT_MASK                 0x00004000
133 #define RF_MASK                 0x00010000
134 #define VM_MASK                 0x00020000
135 #define AC_MASK                 0x00040000
136 #define VIF_MASK                0x00080000
137 #define VIP_MASK                0x00100000
138 #define ID_MASK                 0x00200000
139 
140 /* hidden flags - used internally by qemu to represent additional cpu
141    states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
142    avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
143    positions to ease oring with eflags. */
144 /* current cpl */
145 #define HF_CPL_SHIFT         0
146 /* true if hardware interrupts must be disabled for next instruction */
147 #define HF_INHIBIT_IRQ_SHIFT 3
148 /* 16 or 32 segments */
149 #define HF_CS32_SHIFT        4
150 #define HF_SS32_SHIFT        5
151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
152 #define HF_ADDSEG_SHIFT      6
153 /* copy of CR0.PE (protected mode) */
154 #define HF_PE_SHIFT          7
155 #define HF_TF_SHIFT          8 /* must be same as eflags */
156 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
157 #define HF_EM_SHIFT         10
158 #define HF_TS_SHIFT         11
159 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
160 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
161 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
162 #define HF_RF_SHIFT         16 /* must be same as eflags */
163 #define HF_VM_SHIFT         17 /* must be same as eflags */
164 #define HF_AC_SHIFT         18 /* must be same as eflags */
165 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
166 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
167 #define HF_GUEST_SHIFT      21 /* SVM intercepts are active */
168 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
169 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
170 #define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
171 #define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
172 #define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
173 #define HF_UMIP_SHIFT       27 /* CR4.UMIP */
174 #define HF_AVX_EN_SHIFT     28 /* AVX Enabled (CR4+XCR0) */
175 
176 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
177 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
178 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
179 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
180 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
181 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
182 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
183 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
184 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
185 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
186 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
187 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
188 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
189 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
190 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
191 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
192 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
193 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
194 #define HF_GUEST_MASK        (1 << HF_GUEST_SHIFT)
195 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
196 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
197 #define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
198 #define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
199 #define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
200 #define HF_UMIP_MASK         (1 << HF_UMIP_SHIFT)
201 #define HF_AVX_EN_MASK       (1 << HF_AVX_EN_SHIFT)
202 
203 /* hflags2 */
204 
205 #define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
206 #define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
207 #define HF2_NMI_SHIFT            2 /* CPU serving NMI */
208 #define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
209 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
210 #define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
211 #define HF2_NPT_SHIFT            6 /* Nested Paging enabled */
212 #define HF2_IGNNE_SHIFT          7 /* Ignore CR0.NE=0 */
213 #define HF2_VGIF_SHIFT           8 /* Can take VIRQ*/
214 
215 #define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
216 #define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
217 #define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
218 #define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
219 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
220 #define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
221 #define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)
222 #define HF2_IGNNE_MASK          (1 << HF2_IGNNE_SHIFT)
223 #define HF2_VGIF_MASK           (1 << HF2_VGIF_SHIFT)
224 
225 #define CR0_PE_SHIFT 0
226 #define CR0_MP_SHIFT 1
227 
228 #define CR0_PE_MASK  (1U << 0)
229 #define CR0_MP_MASK  (1U << 1)
230 #define CR0_EM_MASK  (1U << 2)
231 #define CR0_TS_MASK  (1U << 3)
232 #define CR0_ET_MASK  (1U << 4)
233 #define CR0_NE_MASK  (1U << 5)
234 #define CR0_WP_MASK  (1U << 16)
235 #define CR0_AM_MASK  (1U << 18)
236 #define CR0_NW_MASK  (1U << 29)
237 #define CR0_CD_MASK  (1U << 30)
238 #define CR0_PG_MASK  (1U << 31)
239 
240 #define CR4_VME_MASK  (1U << 0)
241 #define CR4_PVI_MASK  (1U << 1)
242 #define CR4_TSD_MASK  (1U << 2)
243 #define CR4_DE_MASK   (1U << 3)
244 #define CR4_PSE_MASK  (1U << 4)
245 #define CR4_PAE_MASK  (1U << 5)
246 #define CR4_MCE_MASK  (1U << 6)
247 #define CR4_PGE_MASK  (1U << 7)
248 #define CR4_PCE_MASK  (1U << 8)
249 #define CR4_OSFXSR_SHIFT 9
250 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
251 #define CR4_OSXMMEXCPT_MASK  (1U << 10)
252 #define CR4_UMIP_MASK   (1U << 11)
253 #define CR4_LA57_MASK   (1U << 12)
254 #define CR4_VMXE_MASK   (1U << 13)
255 #define CR4_SMXE_MASK   (1U << 14)
256 #define CR4_FSGSBASE_MASK (1U << 16)
257 #define CR4_PCIDE_MASK  (1U << 17)
258 #define CR4_OSXSAVE_MASK (1U << 18)
259 #define CR4_SMEP_MASK   (1U << 20)
260 #define CR4_SMAP_MASK   (1U << 21)
261 #define CR4_PKE_MASK   (1U << 22)
262 #define CR4_PKS_MASK   (1U << 24)
263 #define CR4_LAM_SUP_MASK (1U << 28)
264 
265 #ifdef TARGET_X86_64
266 #define CR4_FRED_MASK   (1ULL << 32)
267 #else
268 #define CR4_FRED_MASK   0
269 #endif
270 
271 #define CR4_RESERVED_MASK \
272 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
273                 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
274                 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
275                 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
276                 | CR4_LA57_MASK \
277                 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
278                 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
279                 | CR4_LAM_SUP_MASK | CR4_FRED_MASK))
280 
281 #define DR6_BD          (1 << 13)
282 #define DR6_BS          (1 << 14)
283 #define DR6_BT          (1 << 15)
284 #define DR6_FIXED_1     0xffff0ff0
285 
286 #define DR7_GD          (1 << 13)
287 #define DR7_TYPE_SHIFT  16
288 #define DR7_LEN_SHIFT   18
289 #define DR7_FIXED_1     0x00000400
290 #define DR7_GLOBAL_BP_MASK   0xaa
291 #define DR7_LOCAL_BP_MASK    0x55
292 #define DR7_MAX_BP           4
293 #define DR7_TYPE_BP_INST     0x0
294 #define DR7_TYPE_DATA_WR     0x1
295 #define DR7_TYPE_IO_RW       0x2
296 #define DR7_TYPE_DATA_RW     0x3
297 
298 #define DR_RESERVED_MASK 0xffffffff00000000ULL
299 
300 #define PG_PRESENT_BIT  0
301 #define PG_RW_BIT       1
302 #define PG_USER_BIT     2
303 #define PG_PWT_BIT      3
304 #define PG_PCD_BIT      4
305 #define PG_ACCESSED_BIT 5
306 #define PG_DIRTY_BIT    6
307 #define PG_PSE_BIT      7
308 #define PG_GLOBAL_BIT   8
309 #define PG_PSE_PAT_BIT  12
310 #define PG_PKRU_BIT     59
311 #define PG_NX_BIT       63
312 
313 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
314 #define PG_RW_MASK       (1 << PG_RW_BIT)
315 #define PG_USER_MASK     (1 << PG_USER_BIT)
316 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
317 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
318 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
319 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
320 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
321 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
322 #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
323 #define PG_ADDRESS_MASK  0x000ffffffffff000LL
324 #define PG_HI_USER_MASK  0x7ff0000000000000LL
325 #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
326 #define PG_NX_MASK       (1ULL << PG_NX_BIT)
327 
328 #define PG_ERROR_W_BIT     1
329 
330 #define PG_ERROR_P_MASK    0x01
331 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
332 #define PG_ERROR_U_MASK    0x04
333 #define PG_ERROR_RSVD_MASK 0x08
334 #define PG_ERROR_I_D_MASK  0x10
335 #define PG_ERROR_PK_MASK   0x20
336 
337 #define PG_MODE_PAE      (1 << 0)
338 #define PG_MODE_LMA      (1 << 1)
339 #define PG_MODE_NXE      (1 << 2)
340 #define PG_MODE_PSE      (1 << 3)
341 #define PG_MODE_LA57     (1 << 4)
342 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
343 
344 /* Bits of CR4 that do not affect the NPT page format.  */
345 #define PG_MODE_WP       (1 << 16)
346 #define PG_MODE_PKE      (1 << 17)
347 #define PG_MODE_PKS      (1 << 18)
348 #define PG_MODE_SMEP     (1 << 19)
349 
350 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
351 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
352 #define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
353 
354 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
355 #define MCE_BANKS_DEF   10
356 
357 #define MCG_CAP_BANKS_MASK 0xff
358 
359 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
360 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
361 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
362 #define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */
363 
364 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
365 
366 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
367 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
368 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
369 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
370 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
371 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
372 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
373 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
374 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
375 #define MCI_STATUS_DEFERRED    (1ULL<<44)  /* Deferred error */
376 #define MCI_STATUS_POISON      (1ULL<<43)  /* Poisoned data consumed */
377 
378 /* MISC register defines */
379 #define MCM_ADDR_SEGOFF  0      /* segment offset */
380 #define MCM_ADDR_LINEAR  1      /* linear address */
381 #define MCM_ADDR_PHYS    2      /* physical address */
382 #define MCM_ADDR_MEM     3      /* memory address */
383 #define MCM_ADDR_GENERIC 7      /* generic */
384 
385 #define MSR_IA32_TSC                    0x10
386 #define MSR_IA32_APICBASE               0x1b
387 #define MSR_IA32_APICBASE_BSP           (1<<8)
388 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
389 #define MSR_IA32_APICBASE_EXTD          (1 << 10)
390 #define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
391 #define MSR_IA32_APICBASE_RESERVED \
392         (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
393                      | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
394 
395 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
396 #define MSR_TSC_ADJUST                  0x0000003b
397 #define MSR_IA32_SPEC_CTRL              0x48
398 #define MSR_VIRT_SSBD                   0xc001011f
399 #define MSR_IA32_PRED_CMD               0x49
400 #define MSR_IA32_UCODE_REV              0x8b
401 #define MSR_IA32_CORE_CAPABILITY        0xcf
402 
403 #define MSR_IA32_ARCH_CAPABILITIES      0x10a
404 #define ARCH_CAP_TSX_CTRL_MSR		(1<<7)
405 
406 #define MSR_IA32_PERF_CAPABILITIES      0x345
407 #define PERF_CAP_LBR_FMT                0x3f
408 
409 #define MSR_IA32_TSX_CTRL		0x122
410 #define MSR_IA32_TSCDEADLINE            0x6e0
411 #define MSR_IA32_PKRS                   0x6e1
412 #define MSR_RAPL_POWER_UNIT             0x00000606
413 #define MSR_PKG_POWER_LIMIT             0x00000610
414 #define MSR_PKG_ENERGY_STATUS           0x00000611
415 #define MSR_PKG_POWER_INFO              0x00000614
416 #define MSR_ARCH_LBR_CTL                0x000014ce
417 #define MSR_ARCH_LBR_DEPTH              0x000014cf
418 #define MSR_ARCH_LBR_FROM_0             0x00001500
419 #define MSR_ARCH_LBR_TO_0               0x00001600
420 #define MSR_ARCH_LBR_INFO_0             0x00001200
421 
422 #define FEATURE_CONTROL_LOCKED                    (1<<0)
423 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX  (1ULL << 1)
424 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
425 #define FEATURE_CONTROL_SGX_LC                    (1ULL << 17)
426 #define FEATURE_CONTROL_SGX                       (1ULL << 18)
427 #define FEATURE_CONTROL_LMCE                      (1<<20)
428 
429 #define MSR_IA32_SGXLEPUBKEYHASH0       0x8c
430 #define MSR_IA32_SGXLEPUBKEYHASH1       0x8d
431 #define MSR_IA32_SGXLEPUBKEYHASH2       0x8e
432 #define MSR_IA32_SGXLEPUBKEYHASH3       0x8f
433 
434 #define MSR_P6_PERFCTR0                 0xc1
435 
436 #define MSR_IA32_SMBASE                 0x9e
437 #define MSR_SMI_COUNT                   0x34
438 #define MSR_CORE_THREAD_COUNT           0x35
439 #define MSR_MTRRcap                     0xfe
440 #define MSR_MTRRcap_VCNT                8
441 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
442 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
443 
444 #define MSR_IA32_SYSENTER_CS            0x174
445 #define MSR_IA32_SYSENTER_ESP           0x175
446 #define MSR_IA32_SYSENTER_EIP           0x176
447 
448 #define MSR_MCG_CAP                     0x179
449 #define MSR_MCG_STATUS                  0x17a
450 #define MSR_MCG_CTL                     0x17b
451 #define MSR_MCG_EXT_CTL                 0x4d0
452 
453 #define MSR_P6_EVNTSEL0                 0x186
454 
455 #define MSR_IA32_PERF_STATUS            0x198
456 
457 #define MSR_IA32_MISC_ENABLE            0x1a0
458 /* Indicates good rep/movs microcode on some processors: */
459 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
460 #define MSR_IA32_MISC_ENABLE_MWAIT      (1ULL << 18)
461 
462 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
463 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
464 
465 #define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)
466 
467 #define MSR_MTRRfix64K_00000            0x250
468 #define MSR_MTRRfix16K_80000            0x258
469 #define MSR_MTRRfix16K_A0000            0x259
470 #define MSR_MTRRfix4K_C0000             0x268
471 #define MSR_MTRRfix4K_C8000             0x269
472 #define MSR_MTRRfix4K_D0000             0x26a
473 #define MSR_MTRRfix4K_D8000             0x26b
474 #define MSR_MTRRfix4K_E0000             0x26c
475 #define MSR_MTRRfix4K_E8000             0x26d
476 #define MSR_MTRRfix4K_F0000             0x26e
477 #define MSR_MTRRfix4K_F8000             0x26f
478 
479 #define MSR_PAT                         0x277
480 
481 #define MSR_MTRRdefType                 0x2ff
482 
483 #define MSR_CORE_PERF_FIXED_CTR0        0x309
484 #define MSR_CORE_PERF_FIXED_CTR1        0x30a
485 #define MSR_CORE_PERF_FIXED_CTR2        0x30b
486 #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
487 #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
488 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
489 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
490 
491 #define MSR_MC0_CTL                     0x400
492 #define MSR_MC0_STATUS                  0x401
493 #define MSR_MC0_ADDR                    0x402
494 #define MSR_MC0_MISC                    0x403
495 
496 #define MSR_IA32_RTIT_OUTPUT_BASE       0x560
497 #define MSR_IA32_RTIT_OUTPUT_MASK       0x561
498 #define MSR_IA32_RTIT_CTL               0x570
499 #define MSR_IA32_RTIT_STATUS            0x571
500 #define MSR_IA32_RTIT_CR3_MATCH         0x572
501 #define MSR_IA32_RTIT_ADDR0_A           0x580
502 #define MSR_IA32_RTIT_ADDR0_B           0x581
503 #define MSR_IA32_RTIT_ADDR1_A           0x582
504 #define MSR_IA32_RTIT_ADDR1_B           0x583
505 #define MSR_IA32_RTIT_ADDR2_A           0x584
506 #define MSR_IA32_RTIT_ADDR2_B           0x585
507 #define MSR_IA32_RTIT_ADDR3_A           0x586
508 #define MSR_IA32_RTIT_ADDR3_B           0x587
509 #define MAX_RTIT_ADDRS                  8
510 
511 #define MSR_EFER                        0xc0000080
512 
513 #define MSR_EFER_SCE   (1 << 0)
514 #define MSR_EFER_LME   (1 << 8)
515 #define MSR_EFER_LMA   (1 << 10)
516 #define MSR_EFER_NXE   (1 << 11)
517 #define MSR_EFER_SVME  (1 << 12)
518 #define MSR_EFER_FFXSR (1 << 14)
519 
520 #define MSR_EFER_RESERVED\
521         (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
522             | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
523             | MSR_EFER_FFXSR))
524 
525 #define MSR_STAR                        0xc0000081
526 #define MSR_LSTAR                       0xc0000082
527 #define MSR_CSTAR                       0xc0000083
528 #define MSR_FMASK                       0xc0000084
529 #define MSR_FSBASE                      0xc0000100
530 #define MSR_GSBASE                      0xc0000101
531 #define MSR_KERNELGSBASE                0xc0000102
532 #define MSR_TSC_AUX                     0xc0000103
533 #define MSR_AMD64_TSC_RATIO             0xc0000104
534 
535 #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
536 
537 #define MSR_K7_HWCR                     0xc0010015
538 
539 #define MSR_VM_HSAVE_PA                 0xc0010117
540 
541 #define MSR_IA32_XFD                    0x000001c4
542 #define MSR_IA32_XFD_ERR                0x000001c5
543 
544 /* FRED MSRs */
545 #define MSR_IA32_FRED_RSP0              0x000001cc       /* Stack level 0 regular stack pointer */
546 #define MSR_IA32_FRED_RSP1              0x000001cd       /* Stack level 1 regular stack pointer */
547 #define MSR_IA32_FRED_RSP2              0x000001ce       /* Stack level 2 regular stack pointer */
548 #define MSR_IA32_FRED_RSP3              0x000001cf       /* Stack level 3 regular stack pointer */
549 #define MSR_IA32_FRED_STKLVLS           0x000001d0       /* FRED exception stack levels */
550 #define MSR_IA32_FRED_SSP1              0x000001d1       /* Stack level 1 shadow stack pointer in ring 0 */
551 #define MSR_IA32_FRED_SSP2              0x000001d2       /* Stack level 2 shadow stack pointer in ring 0 */
552 #define MSR_IA32_FRED_SSP3              0x000001d3       /* Stack level 3 shadow stack pointer in ring 0 */
553 #define MSR_IA32_FRED_CONFIG            0x000001d4       /* FRED Entrypoint and interrupt stack level */
554 
555 #define MSR_IA32_BNDCFGS                0x00000d90
556 #define MSR_IA32_XSS                    0x00000da0
557 #define MSR_IA32_UMWAIT_CONTROL         0xe1
558 
559 #define MSR_IA32_VMX_BASIC              0x00000480
560 #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
561 #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
562 #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
563 #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
564 #define MSR_IA32_VMX_MISC               0x00000485
565 #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
566 #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
567 #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
568 #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
569 #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
570 #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
571 #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
572 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
573 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
574 #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
575 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
576 #define MSR_IA32_VMX_VMFUNC             0x00000491
577 
578 #define MSR_APIC_START                  0x00000800
579 #define MSR_APIC_END                    0x000008ff
580 
581 #define XSTATE_FP_BIT                   0
582 #define XSTATE_SSE_BIT                  1
583 #define XSTATE_YMM_BIT                  2
584 #define XSTATE_BNDREGS_BIT              3
585 #define XSTATE_BNDCSR_BIT               4
586 #define XSTATE_OPMASK_BIT               5
587 #define XSTATE_ZMM_Hi256_BIT            6
588 #define XSTATE_Hi16_ZMM_BIT             7
589 #define XSTATE_PKRU_BIT                 9
590 #define XSTATE_ARCH_LBR_BIT             15
591 #define XSTATE_XTILE_CFG_BIT            17
592 #define XSTATE_XTILE_DATA_BIT           18
593 
594 #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
595 #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
596 #define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
597 #define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
598 #define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
599 #define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
600 #define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
601 #define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
602 #define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
603 #define XSTATE_ARCH_LBR_MASK            (1ULL << XSTATE_ARCH_LBR_BIT)
604 #define XSTATE_XTILE_CFG_MASK           (1ULL << XSTATE_XTILE_CFG_BIT)
605 #define XSTATE_XTILE_DATA_MASK          (1ULL << XSTATE_XTILE_DATA_BIT)
606 
607 #define XSTATE_DYNAMIC_MASK             (XSTATE_XTILE_DATA_MASK)
608 
609 #define ESA_FEATURE_ALIGN64_BIT         1
610 #define ESA_FEATURE_XFD_BIT             2
611 
612 #define ESA_FEATURE_ALIGN64_MASK        (1U << ESA_FEATURE_ALIGN64_BIT)
613 #define ESA_FEATURE_XFD_MASK            (1U << ESA_FEATURE_XFD_BIT)
614 
615 
616 /* CPUID feature bits available in XCR0 */
617 #define CPUID_XSTATE_XCR0_MASK  (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
618                                  XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
619                                  XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
620                                  XSTATE_ZMM_Hi256_MASK | \
621                                  XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
622                                  XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
623 
624 /* CPUID feature words */
625 typedef enum FeatureWord {
626     FEAT_1_EDX,         /* CPUID[1].EDX */
627     FEAT_1_ECX,         /* CPUID[1].ECX */
628     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
629     FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
630     FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
631     FEAT_7_1_EAX,       /* CPUID[EAX=7,ECX=1].EAX */
632     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
633     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
634     FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */
635     FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
636     FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
637     FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
638     FEAT_8000_0021_EBX, /* CPUID[8000_0021].EBX */
639     FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */
640     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
641     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
642     FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
643     FEAT_SVM,           /* CPUID[8000_000A].EDX */
644     FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
645     FEAT_6_EAX,         /* CPUID[6].EAX */
646     FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
647     FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
648     FEAT_ARCH_CAPABILITIES,
649     FEAT_CORE_CAPABILITY,
650     FEAT_PERF_CAPABILITIES,
651     FEAT_VMX_PROCBASED_CTLS,
652     FEAT_VMX_SECONDARY_CTLS,
653     FEAT_VMX_PINBASED_CTLS,
654     FEAT_VMX_EXIT_CTLS,
655     FEAT_VMX_ENTRY_CTLS,
656     FEAT_VMX_MISC,
657     FEAT_VMX_EPT_VPID_CAPS,
658     FEAT_VMX_BASIC,
659     FEAT_VMX_VMFUNC,
660     FEAT_14_0_ECX,
661     FEAT_SGX_12_0_EAX,  /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
662     FEAT_SGX_12_0_EBX,  /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
663     FEAT_SGX_12_1_EAX,  /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
664     FEAT_XSAVE_XSS_LO,     /* CPUID[EAX=0xd,ECX=1].ECX */
665     FEAT_XSAVE_XSS_HI,     /* CPUID[EAX=0xd,ECX=1].EDX */
666     FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
667     FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
668     FEAT_24_0_EBX,      /* CPUID[EAX=0x24,ECX=0].EBX */
669     FEATURE_WORDS,
670 } FeatureWord;
671 
672 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
673 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
674 
675 /* cpuid_features bits */
676 #define CPUID_FP87 (1U << 0)
677 #define CPUID_VME  (1U << 1)
678 #define CPUID_DE   (1U << 2)
679 #define CPUID_PSE  (1U << 3)
680 #define CPUID_TSC  (1U << 4)
681 #define CPUID_MSR  (1U << 5)
682 #define CPUID_PAE  (1U << 6)
683 #define CPUID_MCE  (1U << 7)
684 #define CPUID_CX8  (1U << 8)
685 #define CPUID_APIC (1U << 9)
686 #define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
687 #define CPUID_MTRR (1U << 12)
688 #define CPUID_PGE  (1U << 13)
689 #define CPUID_MCA  (1U << 14)
690 #define CPUID_CMOV (1U << 15)
691 #define CPUID_PAT  (1U << 16)
692 #define CPUID_PSE36   (1U << 17)
693 #define CPUID_PN   (1U << 18)
694 #define CPUID_CLFLUSH (1U << 19)
695 #define CPUID_DTS (1U << 21)
696 #define CPUID_ACPI (1U << 22)
697 #define CPUID_MMX  (1U << 23)
698 #define CPUID_FXSR (1U << 24)
699 #define CPUID_SSE  (1U << 25)
700 #define CPUID_SSE2 (1U << 26)
701 #define CPUID_SS (1U << 27)
702 #define CPUID_HT (1U << 28)
703 #define CPUID_TM (1U << 29)
704 #define CPUID_IA64 (1U << 30)
705 #define CPUID_PBE (1U << 31)
706 
707 #define CPUID_EXT_SSE3     (1U << 0)
708 #define CPUID_EXT_PCLMULQDQ (1U << 1)
709 #define CPUID_EXT_DTES64   (1U << 2)
710 #define CPUID_EXT_MONITOR  (1U << 3)
711 #define CPUID_EXT_DSCPL    (1U << 4)
712 #define CPUID_EXT_VMX      (1U << 5)
713 #define CPUID_EXT_SMX      (1U << 6)
714 #define CPUID_EXT_EST      (1U << 7)
715 #define CPUID_EXT_TM2      (1U << 8)
716 #define CPUID_EXT_SSSE3    (1U << 9)
717 #define CPUID_EXT_CID      (1U << 10)
718 #define CPUID_EXT_FMA      (1U << 12)
719 #define CPUID_EXT_CX16     (1U << 13)
720 #define CPUID_EXT_XTPR     (1U << 14)
721 #define CPUID_EXT_PDCM     (1U << 15)
722 #define CPUID_EXT_PCID     (1U << 17)
723 #define CPUID_EXT_DCA      (1U << 18)
724 #define CPUID_EXT_SSE41    (1U << 19)
725 #define CPUID_EXT_SSE42    (1U << 20)
726 #define CPUID_EXT_X2APIC   (1U << 21)
727 #define CPUID_EXT_MOVBE    (1U << 22)
728 #define CPUID_EXT_POPCNT   (1U << 23)
729 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
730 #define CPUID_EXT_AES      (1U << 25)
731 #define CPUID_EXT_XSAVE    (1U << 26)
732 #define CPUID_EXT_OSXSAVE  (1U << 27)
733 #define CPUID_EXT_AVX      (1U << 28)
734 #define CPUID_EXT_F16C     (1U << 29)
735 #define CPUID_EXT_RDRAND   (1U << 30)
736 #define CPUID_EXT_HYPERVISOR  (1U << 31)
737 
738 #define CPUID_EXT2_FPU     (1U << 0)
739 #define CPUID_EXT2_VME     (1U << 1)
740 #define CPUID_EXT2_DE      (1U << 2)
741 #define CPUID_EXT2_PSE     (1U << 3)
742 #define CPUID_EXT2_TSC     (1U << 4)
743 #define CPUID_EXT2_MSR     (1U << 5)
744 #define CPUID_EXT2_PAE     (1U << 6)
745 #define CPUID_EXT2_MCE     (1U << 7)
746 #define CPUID_EXT2_CX8     (1U << 8)
747 #define CPUID_EXT2_APIC    (1U << 9)
748 #define CPUID_EXT2_SYSCALL (1U << 11)
749 #define CPUID_EXT2_MTRR    (1U << 12)
750 #define CPUID_EXT2_PGE     (1U << 13)
751 #define CPUID_EXT2_MCA     (1U << 14)
752 #define CPUID_EXT2_CMOV    (1U << 15)
753 #define CPUID_EXT2_PAT     (1U << 16)
754 #define CPUID_EXT2_PSE36   (1U << 17)
755 #define CPUID_EXT2_MP      (1U << 19)
756 #define CPUID_EXT2_NX      (1U << 20)
757 #define CPUID_EXT2_MMXEXT  (1U << 22)
758 #define CPUID_EXT2_MMX     (1U << 23)
759 #define CPUID_EXT2_FXSR    (1U << 24)
760 #define CPUID_EXT2_FFXSR   (1U << 25)
761 #define CPUID_EXT2_PDPE1GB (1U << 26)
762 #define CPUID_EXT2_RDTSCP  (1U << 27)
763 #define CPUID_EXT2_LM      (1U << 29)
764 #define CPUID_EXT2_3DNOWEXT (1U << 30)
765 #define CPUID_EXT2_3DNOW   (1U << 31)
766 
767 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
768 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
769                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
770                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
771                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
772                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
773                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
774                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
775                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
776                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
777 
778 #define CPUID_EXT3_LAHF_LM (1U << 0)
779 #define CPUID_EXT3_CMP_LEG (1U << 1)
780 #define CPUID_EXT3_SVM     (1U << 2)
781 #define CPUID_EXT3_EXTAPIC (1U << 3)
782 #define CPUID_EXT3_CR8LEG  (1U << 4)
783 #define CPUID_EXT3_ABM     (1U << 5)
784 #define CPUID_EXT3_SSE4A   (1U << 6)
785 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
786 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
787 #define CPUID_EXT3_OSVW    (1U << 9)
788 #define CPUID_EXT3_IBS     (1U << 10)
789 #define CPUID_EXT3_XOP     (1U << 11)
790 #define CPUID_EXT3_SKINIT  (1U << 12)
791 #define CPUID_EXT3_WDT     (1U << 13)
792 #define CPUID_EXT3_LWP     (1U << 15)
793 #define CPUID_EXT3_FMA4    (1U << 16)
794 #define CPUID_EXT3_TCE     (1U << 17)
795 #define CPUID_EXT3_NODEID  (1U << 19)
796 #define CPUID_EXT3_TBM     (1U << 21)
797 #define CPUID_EXT3_TOPOEXT (1U << 22)
798 #define CPUID_EXT3_PERFCORE (1U << 23)
799 #define CPUID_EXT3_PERFNB  (1U << 24)
800 
801 #define CPUID_SVM_NPT             (1U << 0)
802 #define CPUID_SVM_LBRV            (1U << 1)
803 #define CPUID_SVM_SVMLOCK         (1U << 2)
804 #define CPUID_SVM_NRIPSAVE        (1U << 3)
805 #define CPUID_SVM_TSCSCALE        (1U << 4)
806 #define CPUID_SVM_VMCBCLEAN       (1U << 5)
807 #define CPUID_SVM_FLUSHASID       (1U << 6)
808 #define CPUID_SVM_DECODEASSIST    (1U << 7)
809 #define CPUID_SVM_PAUSEFILTER     (1U << 10)
810 #define CPUID_SVM_PFTHRESHOLD     (1U << 12)
811 #define CPUID_SVM_AVIC            (1U << 13)
812 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
813 #define CPUID_SVM_VGIF            (1U << 16)
814 #define CPUID_SVM_VNMI            (1U << 25)
815 #define CPUID_SVM_SVME_ADDR_CHK   (1U << 28)
816 
817 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
818 #define CPUID_7_0_EBX_FSGSBASE          (1U << 0)
819 /* Support TSC adjust MSR */
820 #define CPUID_7_0_EBX_TSC_ADJUST        (1U << 1)
821 /* Support SGX */
822 #define CPUID_7_0_EBX_SGX               (1U << 2)
823 /* 1st Group of Advanced Bit Manipulation Extensions */
824 #define CPUID_7_0_EBX_BMI1              (1U << 3)
825 /* Hardware Lock Elision */
826 #define CPUID_7_0_EBX_HLE               (1U << 4)
827 /* Intel Advanced Vector Extensions 2 */
828 #define CPUID_7_0_EBX_AVX2              (1U << 5)
829 /* FPU data pointer updated only on x87 exceptions */
830 #define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
831 /* Supervisor-mode Execution Prevention */
832 #define CPUID_7_0_EBX_SMEP              (1U << 7)
833 /* 2nd Group of Advanced Bit Manipulation Extensions */
834 #define CPUID_7_0_EBX_BMI2              (1U << 8)
835 /* Enhanced REP MOVSB/STOSB */
836 #define CPUID_7_0_EBX_ERMS              (1U << 9)
837 /* Invalidate Process-Context Identifier */
838 #define CPUID_7_0_EBX_INVPCID           (1U << 10)
839 /* Restricted Transactional Memory */
840 #define CPUID_7_0_EBX_RTM               (1U << 11)
841 /* Zero out FPU CS and FPU DS */
842 #define CPUID_7_0_EBX_ZERO_FCS_FDS      (1U << 13)
843 /* Memory Protection Extension */
844 #define CPUID_7_0_EBX_MPX               (1U << 14)
845 /* AVX-512 Foundation */
846 #define CPUID_7_0_EBX_AVX512F           (1U << 16)
847 /* AVX-512 Doubleword & Quadword Instruction */
848 #define CPUID_7_0_EBX_AVX512DQ          (1U << 17)
849 /* Read Random SEED */
850 #define CPUID_7_0_EBX_RDSEED            (1U << 18)
851 /* ADCX and ADOX instructions */
852 #define CPUID_7_0_EBX_ADX               (1U << 19)
853 /* Supervisor Mode Access Prevention */
854 #define CPUID_7_0_EBX_SMAP              (1U << 20)
855 /* AVX-512 Integer Fused Multiply Add */
856 #define CPUID_7_0_EBX_AVX512IFMA        (1U << 21)
857 /* Flush a Cache Line Optimized */
858 #define CPUID_7_0_EBX_CLFLUSHOPT        (1U << 23)
859 /* Cache Line Write Back */
860 #define CPUID_7_0_EBX_CLWB              (1U << 24)
861 /* Intel Processor Trace */
862 #define CPUID_7_0_EBX_INTEL_PT          (1U << 25)
863 /* AVX-512 Prefetch */
864 #define CPUID_7_0_EBX_AVX512PF          (1U << 26)
865 /* AVX-512 Exponential and Reciprocal */
866 #define CPUID_7_0_EBX_AVX512ER          (1U << 27)
867 /* AVX-512 Conflict Detection */
868 #define CPUID_7_0_EBX_AVX512CD          (1U << 28)
869 /* SHA1/SHA256 Instruction Extensions */
870 #define CPUID_7_0_EBX_SHA_NI            (1U << 29)
871 /* AVX-512 Byte and Word Instructions */
872 #define CPUID_7_0_EBX_AVX512BW          (1U << 30)
873 /* AVX-512 Vector Length Extensions */
874 #define CPUID_7_0_EBX_AVX512VL          (1U << 31)
875 
876 /* AVX-512 Vector Byte Manipulation Instruction */
877 #define CPUID_7_0_ECX_AVX512_VBMI       (1U << 1)
878 /* User-Mode Instruction Prevention */
879 #define CPUID_7_0_ECX_UMIP              (1U << 2)
880 /* Protection Keys for User-mode Pages */
881 #define CPUID_7_0_ECX_PKU               (1U << 3)
882 /* OS Enable Protection Keys */
883 #define CPUID_7_0_ECX_OSPKE             (1U << 4)
884 /* UMONITOR/UMWAIT/TPAUSE Instructions */
885 #define CPUID_7_0_ECX_WAITPKG           (1U << 5)
886 /* Additional AVX-512 Vector Byte Manipulation Instruction */
887 #define CPUID_7_0_ECX_AVX512_VBMI2      (1U << 6)
888 /* Galois Field New Instructions */
889 #define CPUID_7_0_ECX_GFNI              (1U << 8)
890 /* Vector AES Instructions */
891 #define CPUID_7_0_ECX_VAES              (1U << 9)
892 /* Carry-Less Multiplication Quadword */
893 #define CPUID_7_0_ECX_VPCLMULQDQ        (1U << 10)
894 /* Vector Neural Network Instructions */
895 #define CPUID_7_0_ECX_AVX512VNNI        (1U << 11)
896 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
897 #define CPUID_7_0_ECX_AVX512BITALG      (1U << 12)
898 /* POPCNT for vectors of DW/QW */
899 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ  (1U << 14)
900 /* 5-level Page Tables */
901 #define CPUID_7_0_ECX_LA57              (1U << 16)
902 /* Read Processor ID */
903 #define CPUID_7_0_ECX_RDPID             (1U << 22)
904 /* Bus Lock Debug Exception */
905 #define CPUID_7_0_ECX_BUS_LOCK_DETECT   (1U << 24)
906 /* Cache Line Demote Instruction */
907 #define CPUID_7_0_ECX_CLDEMOTE          (1U << 25)
908 /* Move Doubleword as Direct Store Instruction */
909 #define CPUID_7_0_ECX_MOVDIRI           (1U << 27)
910 /* Move 64 Bytes as Direct Store Instruction */
911 #define CPUID_7_0_ECX_MOVDIR64B         (1U << 28)
912 /* Support SGX Launch Control */
913 #define CPUID_7_0_ECX_SGX_LC            (1U << 30)
914 /* Protection Keys for Supervisor-mode Pages */
915 #define CPUID_7_0_ECX_PKS               (1U << 31)
916 
917 /* AVX512 Neural Network Instructions */
918 #define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)
919 /* AVX512 Multiply Accumulation Single Precision */
920 #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
921 /* Fast Short Rep Mov */
922 #define CPUID_7_0_EDX_FSRM              (1U << 4)
923 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
924 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
925 /* SERIALIZE instruction */
926 #define CPUID_7_0_EDX_SERIALIZE         (1U << 14)
927 /* TSX Suspend Load Address Tracking instruction */
928 #define CPUID_7_0_EDX_TSX_LDTRK         (1U << 16)
929 /* Architectural LBRs */
930 #define CPUID_7_0_EDX_ARCH_LBR          (1U << 19)
931 /* AMX_BF16 instruction */
932 #define CPUID_7_0_EDX_AMX_BF16          (1U << 22)
933 /* AVX512_FP16 instruction */
934 #define CPUID_7_0_EDX_AVX512_FP16       (1U << 23)
935 /* AMX tile (two-dimensional register) */
936 #define CPUID_7_0_EDX_AMX_TILE          (1U << 24)
937 /* AMX_INT8 instruction */
938 #define CPUID_7_0_EDX_AMX_INT8          (1U << 25)
939 /* Speculation Control */
940 #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
941 /* Single Thread Indirect Branch Predictors */
942 #define CPUID_7_0_EDX_STIBP             (1U << 27)
943 /* Flush L1D cache */
944 #define CPUID_7_0_EDX_FLUSH_L1D         (1U << 28)
945 /* Arch Capabilities */
946 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
947 /* Core Capability */
948 #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)
949 /* Speculative Store Bypass Disable */
950 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD    (1U << 31)
951 
952 /* AVX VNNI Instruction */
953 #define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
954 /* AVX512 BFloat16 Instruction */
955 #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
956 /* CMPCCXADD Instructions */
957 #define CPUID_7_1_EAX_CMPCCXADD         (1U << 7)
958 /* Fast Zero REP MOVS */
959 #define CPUID_7_1_EAX_FZRM              (1U << 10)
960 /* Fast Short REP STOS */
961 #define CPUID_7_1_EAX_FSRS              (1U << 11)
962 /* Fast Short REP CMPS/SCAS */
963 #define CPUID_7_1_EAX_FSRC              (1U << 12)
964 /* Support Tile Computational Operations on FP16 Numbers */
965 #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
966 /* Support for VPMADD52[H,L]UQ */
967 #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
968 /* Linear Address Masking */
969 #define CPUID_7_1_EAX_LAM               (1U << 26)
970 
971 /* Support for VPDPB[SU,UU,SS]D[,S] */
972 #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
973 /* AVX NE CONVERT Instructions */
974 #define CPUID_7_1_EDX_AVX_NE_CONVERT    (1U << 5)
975 /* AMX COMPLEX Instructions */
976 #define CPUID_7_1_EDX_AMX_COMPLEX       (1U << 8)
977 /* PREFETCHIT0/1 Instructions */
978 #define CPUID_7_1_EDX_PREFETCHITI       (1U << 14)
979 /* Support for Advanced Vector Extensions 10 */
980 #define CPUID_7_1_EDX_AVX10             (1U << 19)
981 /* Flexible return and event delivery (FRED) */
982 #define CPUID_7_1_EAX_FRED              (1U << 17)
983 /* Load into IA32_KERNEL_GS_BASE (LKGS) */
984 #define CPUID_7_1_EAX_LKGS              (1U << 18)
985 /* Non-Serializing Write to Model Specific Register (WRMSRNS) */
986 #define CPUID_7_1_EAX_WRMSRNS           (1U << 19)
987 
988 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
989 #define CPUID_7_2_EDX_MCDT_NO           (1U << 5)
990 
991 /* XFD Extend Feature Disabled */
992 #define CPUID_D_1_EAX_XFD               (1U << 4)
993 
994 /* Packets which contain IP payload have LIP values */
995 #define CPUID_14_0_ECX_LIP              (1U << 31)
996 
997 /* AVX10 128-bit vector support is present */
998 #define CPUID_24_0_EBX_AVX10_128        (1U << 16)
999 /* AVX10 256-bit vector support is present */
1000 #define CPUID_24_0_EBX_AVX10_256        (1U << 17)
1001 /* AVX10 512-bit vector support is present */
1002 #define CPUID_24_0_EBX_AVX10_512        (1U << 18)
1003 /* AVX10 vector length support mask */
1004 #define CPUID_24_0_EBX_AVX10_VL_MASK    (CPUID_24_0_EBX_AVX10_128 | \
1005                                          CPUID_24_0_EBX_AVX10_256 | \
1006                                          CPUID_24_0_EBX_AVX10_512)
1007 
1008 /* RAS Features */
1009 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV    (1U << 0)
1010 #define CPUID_8000_0007_EBX_SUCCOR      (1U << 1)
1011 
1012 /* CLZERO instruction */
1013 #define CPUID_8000_0008_EBX_CLZERO      (1U << 0)
1014 /* Always save/restore FP error pointers */
1015 #define CPUID_8000_0008_EBX_XSAVEERPTR  (1U << 2)
1016 /* Write back and do not invalidate cache */
1017 #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
1018 /* Indirect Branch Prediction Barrier */
1019 #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
1020 /* Indirect Branch Restricted Speculation */
1021 #define CPUID_8000_0008_EBX_IBRS        (1U << 14)
1022 /* Single Thread Indirect Branch Predictors */
1023 #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
1024 /* STIBP mode has enhanced performance and may be left always on */
1025 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON    (1U << 17)
1026 /* Speculative Store Bypass Disable */
1027 #define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
1028 /* Paravirtualized Speculative Store Bypass Disable MSR */
1029 #define CPUID_8000_0008_EBX_VIRT_SSBD   (1U << 25)
1030 /* Predictive Store Forwarding Disable */
1031 #define CPUID_8000_0008_EBX_AMD_PSFD    (1U << 28)
1032 
1033 /* Processor ignores nested data breakpoints */
1034 #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP            (1U << 0)
1035 /* LFENCE is always serializing */
1036 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
1037 /* Null Selector Clears Base */
1038 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE            (1U << 6)
1039 /* Automatic IBRS */
1040 #define CPUID_8000_0021_EAX_AUTO_IBRS                    (1U << 8)
1041 /* Enhanced Return Address Predictor Scurity */
1042 #define CPUID_8000_0021_EAX_ERAPS                        (1U << 24)
1043 /* Selective Branch Predictor Barrier */
1044 #define CPUID_8000_0021_EAX_SBPB                         (1U << 27)
1045 /* IBPB includes branch type prediction flushing */
1046 #define CPUID_8000_0021_EAX_IBPB_BRTYPE                  (1U << 28)
1047 /* Not vulnerable to Speculative Return Stack Overflow */
1048 #define CPUID_8000_0021_EAX_SRSO_NO                      (1U << 29)
1049 /* Not vulnerable to SRSO at the user-kernel boundary */
1050 #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO          (1U << 30)
1051 
1052 /*
1053  * Return Address Predictor size. RapSize x 8 is the minimum number of
1054  * CALL instructions software needs to execute to flush the RAP.
1055  */
1056 #define CPUID_8000_0021_EBX_RAPSIZE    (8U << 16)
1057 
1058 /* Performance Monitoring Version 2 */
1059 #define CPUID_8000_0022_EAX_PERFMON_V2  (1U << 0)
1060 
1061 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
1062 #define CPUID_XSAVE_XSAVEC     (1U << 1)
1063 #define CPUID_XSAVE_XGETBV1    (1U << 2)
1064 #define CPUID_XSAVE_XSAVES     (1U << 3)
1065 
1066 #define CPUID_6_EAX_ARAT       (1U << 2)
1067 
1068 /* CPUID[0x80000007].EDX flags: */
1069 #define CPUID_APM_INVTSC       (1U << 8)
1070 
1071 #define CPUID_VENDOR_SZ      12
1072 
1073 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1074 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1075 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1076 #define CPUID_VENDOR_INTEL "GenuineIntel"
1077 
1078 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
1079 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
1080 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
1081 #define CPUID_VENDOR_AMD   "AuthenticAMD"
1082 
1083 #define CPUID_VENDOR_VIA   "CentaurHauls"
1084 
1085 #define CPUID_VENDOR_HYGON    "HygonGenuine"
1086 
1087 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1088                            (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1089                            (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1090 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1091                          (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1092                          (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1093 
1094 #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
1095 #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
1096 
1097 /* CPUID[0xB].ECX level types */
1098 #define CPUID_B_ECX_TOPO_LEVEL_INVALID  0
1099 #define CPUID_B_ECX_TOPO_LEVEL_SMT      1
1100 #define CPUID_B_ECX_TOPO_LEVEL_CORE     2
1101 
1102 /* COUID[0x1F].ECX level types */
1103 #define CPUID_1F_ECX_TOPO_LEVEL_INVALID  CPUID_B_ECX_TOPO_LEVEL_INVALID
1104 #define CPUID_1F_ECX_TOPO_LEVEL_SMT      CPUID_B_ECX_TOPO_LEVEL_SMT
1105 #define CPUID_1F_ECX_TOPO_LEVEL_CORE     CPUID_B_ECX_TOPO_LEVEL_CORE
1106 #define CPUID_1F_ECX_TOPO_LEVEL_MODULE   3
1107 #define CPUID_1F_ECX_TOPO_LEVEL_DIE      5
1108 
1109 /* MSR Feature Bits */
1110 #define MSR_ARCH_CAP_RDCL_NO            (1U << 0)
1111 #define MSR_ARCH_CAP_IBRS_ALL           (1U << 1)
1112 #define MSR_ARCH_CAP_RSBA               (1U << 2)
1113 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1114 #define MSR_ARCH_CAP_SSB_NO             (1U << 4)
1115 #define MSR_ARCH_CAP_MDS_NO             (1U << 5)
1116 #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
1117 #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
1118 #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
1119 #define MSR_ARCH_CAP_SBDR_SSDP_NO       (1U << 13)
1120 #define MSR_ARCH_CAP_FBSDP_NO           (1U << 14)
1121 #define MSR_ARCH_CAP_PSDP_NO            (1U << 15)
1122 #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
1123 #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
1124 
1125 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
1126 
1127 /* VMX MSR features */
1128 #define MSR_VMX_BASIC_VMCS_REVISION_MASK             0x7FFFFFFFull
1129 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK         (0x00001FFFull << 32)
1130 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK             (0x003C0000ull << 32)
1131 #define MSR_VMX_BASIC_DUAL_MONITOR                   (1ULL << 49)
1132 #define MSR_VMX_BASIC_INS_OUTS                       (1ULL << 54)
1133 #define MSR_VMX_BASIC_TRUE_CTLS                      (1ULL << 55)
1134 #define MSR_VMX_BASIC_ANY_ERRCODE                    (1ULL << 56)
1135 #define MSR_VMX_BASIC_NESTED_EXCEPTION               (1ULL << 58)
1136 
1137 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK     0x1Full
1138 #define MSR_VMX_MISC_STORE_LMA                       (1ULL << 5)
1139 #define MSR_VMX_MISC_ACTIVITY_HLT                    (1ULL << 6)
1140 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN               (1ULL << 7)
1141 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI              (1ULL << 8)
1142 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK          0x0E000000ull
1143 #define MSR_VMX_MISC_VMWRITE_VMEXIT                  (1ULL << 29)
1144 #define MSR_VMX_MISC_ZERO_LEN_INJECT                 (1ULL << 30)
1145 
1146 #define MSR_VMX_EPT_EXECONLY                         (1ULL << 0)
1147 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4               (1ULL << 6)
1148 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5               (1ULL << 7)
1149 #define MSR_VMX_EPT_UC                               (1ULL << 8)
1150 #define MSR_VMX_EPT_WB                               (1ULL << 14)
1151 #define MSR_VMX_EPT_2MB                              (1ULL << 16)
1152 #define MSR_VMX_EPT_1GB                              (1ULL << 17)
1153 #define MSR_VMX_EPT_INVEPT                           (1ULL << 20)
1154 #define MSR_VMX_EPT_AD_BITS                          (1ULL << 21)
1155 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO             (1ULL << 22)
1156 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT            (1ULL << 25)
1157 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT               (1ULL << 26)
1158 #define MSR_VMX_EPT_INVVPID                          (1ULL << 32)
1159 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR              (1ULL << 40)
1160 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT           (1ULL << 41)
1161 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT              (1ULL << 42)
1162 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1163 
1164 #define MSR_VMX_VMFUNC_EPT_SWITCHING                 (1ULL << 0)
1165 
1166 
1167 /* VMX controls */
1168 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
1169 #define VMX_CPU_BASED_USE_TSC_OFFSETING             0x00000008
1170 #define VMX_CPU_BASED_HLT_EXITING                   0x00000080
1171 #define VMX_CPU_BASED_INVLPG_EXITING                0x00000200
1172 #define VMX_CPU_BASED_MWAIT_EXITING                 0x00000400
1173 #define VMX_CPU_BASED_RDPMC_EXITING                 0x00000800
1174 #define VMX_CPU_BASED_RDTSC_EXITING                 0x00001000
1175 #define VMX_CPU_BASED_CR3_LOAD_EXITING              0x00008000
1176 #define VMX_CPU_BASED_CR3_STORE_EXITING             0x00010000
1177 #define VMX_CPU_BASED_CR8_LOAD_EXITING              0x00080000
1178 #define VMX_CPU_BASED_CR8_STORE_EXITING             0x00100000
1179 #define VMX_CPU_BASED_TPR_SHADOW                    0x00200000
1180 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
1181 #define VMX_CPU_BASED_MOV_DR_EXITING                0x00800000
1182 #define VMX_CPU_BASED_UNCOND_IO_EXITING             0x01000000
1183 #define VMX_CPU_BASED_USE_IO_BITMAPS                0x02000000
1184 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
1185 #define VMX_CPU_BASED_USE_MSR_BITMAPS               0x10000000
1186 #define VMX_CPU_BASED_MONITOR_EXITING               0x20000000
1187 #define VMX_CPU_BASED_PAUSE_EXITING                 0x40000000
1188 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
1189 
1190 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1191 #define VMX_SECONDARY_EXEC_ENABLE_EPT               0x00000002
1192 #define VMX_SECONDARY_EXEC_DESC                     0x00000004
1193 #define VMX_SECONDARY_EXEC_RDTSCP                   0x00000008
1194 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
1195 #define VMX_SECONDARY_EXEC_ENABLE_VPID              0x00000020
1196 #define VMX_SECONDARY_EXEC_WBINVD_EXITING           0x00000040
1197 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
1198 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
1199 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
1200 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
1201 #define VMX_SECONDARY_EXEC_RDRAND_EXITING           0x00000800
1202 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
1203 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
1204 #define VMX_SECONDARY_EXEC_SHADOW_VMCS              0x00004000
1205 #define VMX_SECONDARY_EXEC_ENCLS_EXITING            0x00008000
1206 #define VMX_SECONDARY_EXEC_RDSEED_EXITING           0x00010000
1207 #define VMX_SECONDARY_EXEC_ENABLE_PML               0x00020000
1208 #define VMX_SECONDARY_EXEC_XSAVES                   0x00100000
1209 #define VMX_SECONDARY_EXEC_TSC_SCALING              0x02000000
1210 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE   0x04000000
1211 
1212 #define VMX_PIN_BASED_EXT_INTR_MASK                 0x00000001
1213 #define VMX_PIN_BASED_NMI_EXITING                   0x00000008
1214 #define VMX_PIN_BASED_VIRTUAL_NMIS                  0x00000020
1215 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
1216 #define VMX_PIN_BASED_POSTED_INTR                   0x00000080
1217 
1218 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
1219 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
1220 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
1221 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
1222 #define VMX_VM_EXIT_SAVE_IA32_PAT                   0x00040000
1223 #define VMX_VM_EXIT_LOAD_IA32_PAT                   0x00080000
1224 #define VMX_VM_EXIT_SAVE_IA32_EFER                  0x00100000
1225 #define VMX_VM_EXIT_LOAD_IA32_EFER                  0x00200000
1226 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
1227 #define VMX_VM_EXIT_CLEAR_BNDCFGS                   0x00800000
1228 #define VMX_VM_EXIT_PT_CONCEAL_PIP                  0x01000000
1229 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL             0x02000000
1230 #define VMX_VM_EXIT_LOAD_IA32_PKRS                  0x20000000
1231 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS     0x80000000
1232 
1233 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
1234 #define VMX_VM_ENTRY_IA32E_MODE                     0x00000200
1235 #define VMX_VM_ENTRY_SMM                            0x00000400
1236 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
1237 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
1238 #define VMX_VM_ENTRY_LOAD_IA32_PAT                  0x00004000
1239 #define VMX_VM_ENTRY_LOAD_IA32_EFER                 0x00008000
1240 #define VMX_VM_ENTRY_LOAD_BNDCFGS                   0x00010000
1241 #define VMX_VM_ENTRY_PT_CONCEAL_PIP                 0x00020000
1242 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
1243 #define VMX_VM_ENTRY_LOAD_IA32_PKRS                 0x00400000
1244 
1245 /* Supported Hyper-V Enlightenments */
1246 #define HYPERV_FEAT_RELAXED             0
1247 #define HYPERV_FEAT_VAPIC               1
1248 #define HYPERV_FEAT_TIME                2
1249 #define HYPERV_FEAT_CRASH               3
1250 #define HYPERV_FEAT_RESET               4
1251 #define HYPERV_FEAT_VPINDEX             5
1252 #define HYPERV_FEAT_RUNTIME             6
1253 #define HYPERV_FEAT_SYNIC               7
1254 #define HYPERV_FEAT_STIMER              8
1255 #define HYPERV_FEAT_FREQUENCIES         9
1256 #define HYPERV_FEAT_REENLIGHTENMENT     10
1257 #define HYPERV_FEAT_TLBFLUSH            11
1258 #define HYPERV_FEAT_EVMCS               12
1259 #define HYPERV_FEAT_IPI                 13
1260 #define HYPERV_FEAT_STIMER_DIRECT       14
1261 #define HYPERV_FEAT_AVIC                15
1262 #define HYPERV_FEAT_SYNDBG              16
1263 #define HYPERV_FEAT_MSR_BITMAP          17
1264 #define HYPERV_FEAT_XMM_INPUT           18
1265 #define HYPERV_FEAT_TLBFLUSH_EXT        19
1266 #define HYPERV_FEAT_TLBFLUSH_DIRECT     20
1267 
1268 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1269 #define HYPERV_SPINLOCK_NEVER_NOTIFY             0xFFFFFFFF
1270 #endif
1271 
1272 #define EXCP00_DIVZ	0
1273 #define EXCP01_DB	1
1274 #define EXCP02_NMI	2
1275 #define EXCP03_INT3	3
1276 #define EXCP04_INTO	4
1277 #define EXCP05_BOUND	5
1278 #define EXCP06_ILLOP	6
1279 #define EXCP07_PREX	7
1280 #define EXCP08_DBLE	8
1281 #define EXCP09_XERR	9
1282 #define EXCP0A_TSS	10
1283 #define EXCP0B_NOSEG	11
1284 #define EXCP0C_STACK	12
1285 #define EXCP0D_GPF	13
1286 #define EXCP0E_PAGE	14
1287 #define EXCP10_COPR	16
1288 #define EXCP11_ALGN	17
1289 #define EXCP12_MCHK	18
1290 
1291 #define EXCP_VMEXIT     0x100 /* only for system emulation */
1292 #define EXCP_SYSCALL    0x101 /* only for user emulation */
1293 #define EXCP_VSYSCALL   0x102 /* only for user emulation */
1294 
1295 /* i386-specific interrupt pending bits.  */
1296 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
1297 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
1298 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
1299 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
1300 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
1301 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
1302 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
1303 
1304 /* Use a clearer name for this.  */
1305 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
1306 
1307 #define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX)
1308 
1309 /* Instead of computing the condition codes after each x86 instruction,
1310  * QEMU just stores one operand (called CC_SRC), the result
1311  * (called CC_DST) and the type of operation (called CC_OP). When the
1312  * condition codes are needed, the condition codes can be calculated
1313  * using this information. Condition codes are not generated if they
1314  * are only needed for conditional branches.
1315  */
1316 typedef enum {
1317     CC_OP_EFLAGS = 0,  /* all cc are explicitly computed, CC_SRC = flags */
1318     CC_OP_ADCX = 1,    /* CC_DST = C, CC_SRC = rest.  */
1319     CC_OP_ADOX = 2,    /* CC_SRC2 = O, CC_SRC = rest.  */
1320     CC_OP_ADCOX = 3,   /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
1321 
1322     /* Low 2 bits = MemOp constant for the size */
1323 #define CC_OP_FIRST_BWLQ CC_OP_MULB
1324     CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */
1325     CC_OP_MULW,
1326     CC_OP_MULL,
1327     CC_OP_MULQ,
1328 
1329     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1330     CC_OP_ADDW,
1331     CC_OP_ADDL,
1332     CC_OP_ADDQ,
1333 
1334     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1335     CC_OP_ADCW,
1336     CC_OP_ADCL,
1337     CC_OP_ADCQ,
1338 
1339     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1340     CC_OP_SUBW,
1341     CC_OP_SUBL,
1342     CC_OP_SUBQ,
1343 
1344     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1345     CC_OP_SBBW,
1346     CC_OP_SBBL,
1347     CC_OP_SBBQ,
1348 
1349     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1350     CC_OP_LOGICW,
1351     CC_OP_LOGICL,
1352     CC_OP_LOGICQ,
1353 
1354     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1355     CC_OP_INCW,
1356     CC_OP_INCL,
1357     CC_OP_INCQ,
1358 
1359     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
1360     CC_OP_DECW,
1361     CC_OP_DECL,
1362     CC_OP_DECQ,
1363 
1364     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1365     CC_OP_SHLW,
1366     CC_OP_SHLL,
1367     CC_OP_SHLQ,
1368 
1369     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1370     CC_OP_SARW,
1371     CC_OP_SARL,
1372     CC_OP_SARQ,
1373 
1374     CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1375     CC_OP_BMILGW,
1376     CC_OP_BMILGL,
1377     CC_OP_BMILGQ,
1378 
1379     CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
1380     CC_OP_BLSIW,
1381     CC_OP_BLSIL,
1382     CC_OP_BLSIQ,
1383 
1384     /*
1385      * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
1386      * is used or implemented, because the translation needs
1387      * to zero-extend CC_DST anyway.
1388      */
1389     CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear.  */
1390     CC_OP_POPCNTW__,
1391     CC_OP_POPCNTL__,
1392     CC_OP_POPCNTQ__,
1393     CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__,
1394 #define CC_OP_LAST_BWLQ CC_OP_POPCNTQ__
1395 
1396     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1397 } CCOp;
1398 
1399 /* See X86DecodedInsn.cc_op, using int8_t. */
1400 QEMU_BUILD_BUG_ON(CC_OP_DYNAMIC > INT8_MAX);
1401 
cc_op_size(CCOp op)1402 static inline MemOp cc_op_size(CCOp op)
1403 {
1404     MemOp size = op & 3;
1405 
1406     QEMU_BUILD_BUG_ON(CC_OP_FIRST_BWLQ & 3);
1407     assert(op >= CC_OP_FIRST_BWLQ && op <= CC_OP_LAST_BWLQ);
1408     assert(size <= MO_TL);
1409 
1410     return size;
1411 }
1412 
1413 typedef struct SegmentCache {
1414     uint32_t selector;
1415     target_ulong base;
1416     uint32_t limit;
1417     uint32_t flags;
1418 } SegmentCache;
1419 
1420 typedef union MMXReg {
1421     uint8_t  _b_MMXReg[64 / 8];
1422     uint16_t _w_MMXReg[64 / 16];
1423     uint32_t _l_MMXReg[64 / 32];
1424     uint64_t _q_MMXReg[64 / 64];
1425     float32  _s_MMXReg[64 / 32];
1426     float64  _d_MMXReg[64 / 64];
1427 } MMXReg;
1428 
1429 typedef union XMMReg {
1430     uint64_t _q_XMMReg[128 / 64];
1431 } XMMReg;
1432 
1433 typedef union YMMReg {
1434     uint64_t _q_YMMReg[256 / 64];
1435     XMMReg   _x_YMMReg[256 / 128];
1436 } YMMReg;
1437 
1438 typedef union ZMMReg {
1439     uint8_t  _b_ZMMReg[512 / 8];
1440     uint16_t _w_ZMMReg[512 / 16];
1441     uint32_t _l_ZMMReg[512 / 32];
1442     uint64_t _q_ZMMReg[512 / 64];
1443     float16  _h_ZMMReg[512 / 16];
1444     float32  _s_ZMMReg[512 / 32];
1445     float64  _d_ZMMReg[512 / 64];
1446     XMMReg   _x_ZMMReg[512 / 128];
1447     YMMReg   _y_ZMMReg[512 / 256];
1448 } ZMMReg;
1449 
1450 typedef struct BNDReg {
1451     uint64_t lb;
1452     uint64_t ub;
1453 } BNDReg;
1454 
1455 typedef struct BNDCSReg {
1456     uint64_t cfgu;
1457     uint64_t sts;
1458 } BNDCSReg;
1459 
1460 #define BNDCFG_ENABLE       1ULL
1461 #define BNDCFG_BNDPRESERVE  2ULL
1462 #define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK
1463 
1464 #if HOST_BIG_ENDIAN
1465 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1466 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1467 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1468 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1469 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1470 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1471 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1472 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1473 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1474 
1475 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1476 
1477 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1478 #define YMM_X(n) _x_YMMReg[1 - (n)]
1479 
1480 #define MMX_B(n) _b_MMXReg[7 - (n)]
1481 #define MMX_W(n) _w_MMXReg[3 - (n)]
1482 #define MMX_L(n) _l_MMXReg[1 - (n)]
1483 #define MMX_S(n) _s_MMXReg[1 - (n)]
1484 #else
1485 #define ZMM_B(n) _b_ZMMReg[n]
1486 #define ZMM_W(n) _w_ZMMReg[n]
1487 #define ZMM_L(n) _l_ZMMReg[n]
1488 #define ZMM_H(n) _h_ZMMReg[n]
1489 #define ZMM_S(n) _s_ZMMReg[n]
1490 #define ZMM_Q(n) _q_ZMMReg[n]
1491 #define ZMM_D(n) _d_ZMMReg[n]
1492 #define ZMM_X(n) _x_ZMMReg[n]
1493 #define ZMM_Y(n) _y_ZMMReg[n]
1494 
1495 #define XMM_Q(n) _q_XMMReg[n]
1496 
1497 #define YMM_Q(n) _q_YMMReg[n]
1498 #define YMM_X(n) _x_YMMReg[n]
1499 
1500 #define MMX_B(n) _b_MMXReg[n]
1501 #define MMX_W(n) _w_MMXReg[n]
1502 #define MMX_L(n) _l_MMXReg[n]
1503 #define MMX_S(n) _s_MMXReg[n]
1504 #endif
1505 #define MMX_Q(n) _q_MMXReg[n]
1506 
1507 typedef union {
1508     floatx80 d __attribute__((aligned(16)));
1509     MMXReg mmx;
1510 } FPReg;
1511 
1512 typedef struct {
1513     uint64_t base;
1514     uint64_t mask;
1515 } MTRRVar;
1516 
1517 #define CPU_NB_REGS64 16
1518 #define CPU_NB_REGS32 8
1519 
1520 #ifdef TARGET_X86_64
1521 #define CPU_NB_REGS CPU_NB_REGS64
1522 #else
1523 #define CPU_NB_REGS CPU_NB_REGS32
1524 #endif
1525 
1526 #define MAX_FIXED_COUNTERS 3
1527 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1528 
1529 #define TARGET_INSN_START_EXTRA_WORDS 1
1530 
1531 #define NB_OPMASK_REGS 8
1532 
1533 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1534  * that APIC ID hasn't been set yet
1535  */
1536 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1537 
1538 typedef struct X86LegacyXSaveArea {
1539     uint16_t fcw;
1540     uint16_t fsw;
1541     uint8_t ftw;
1542     uint8_t reserved;
1543     uint16_t fpop;
1544     union {
1545         struct {
1546             uint64_t fpip;
1547             uint64_t fpdp;
1548         };
1549         struct {
1550             uint32_t fip;
1551             uint32_t fcs;
1552             uint32_t foo;
1553             uint32_t fos;
1554         };
1555     };
1556     uint32_t mxcsr;
1557     uint32_t mxcsr_mask;
1558     FPReg fpregs[8];
1559     uint8_t xmm_regs[16][16];
1560     uint32_t hw_reserved[12];
1561     uint32_t sw_reserved[12];
1562 } X86LegacyXSaveArea;
1563 
1564 QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512);
1565 
1566 typedef struct X86XSaveHeader {
1567     uint64_t xstate_bv;
1568     uint64_t xcomp_bv;
1569     uint64_t reserve0;
1570     uint8_t reserved[40];
1571 } X86XSaveHeader;
1572 
1573 /* Ext. save area 2: AVX State */
1574 typedef struct XSaveAVX {
1575     uint8_t ymmh[16][16];
1576 } XSaveAVX;
1577 
1578 /* Ext. save area 3: BNDREG */
1579 typedef struct XSaveBNDREG {
1580     BNDReg bnd_regs[4];
1581 } XSaveBNDREG;
1582 
1583 /* Ext. save area 4: BNDCSR */
1584 typedef union XSaveBNDCSR {
1585     BNDCSReg bndcsr;
1586     uint8_t data[64];
1587 } XSaveBNDCSR;
1588 
1589 /* Ext. save area 5: Opmask */
1590 typedef struct XSaveOpmask {
1591     uint64_t opmask_regs[NB_OPMASK_REGS];
1592 } XSaveOpmask;
1593 
1594 /* Ext. save area 6: ZMM_Hi256 */
1595 typedef struct XSaveZMM_Hi256 {
1596     uint8_t zmm_hi256[16][32];
1597 } XSaveZMM_Hi256;
1598 
1599 /* Ext. save area 7: Hi16_ZMM */
1600 typedef struct XSaveHi16_ZMM {
1601     uint8_t hi16_zmm[16][64];
1602 } XSaveHi16_ZMM;
1603 
1604 /* Ext. save area 9: PKRU state */
1605 typedef struct XSavePKRU {
1606     uint32_t pkru;
1607     uint32_t padding;
1608 } XSavePKRU;
1609 
1610 /* Ext. save area 17: AMX XTILECFG state */
1611 typedef struct XSaveXTILECFG {
1612     uint8_t xtilecfg[64];
1613 } XSaveXTILECFG;
1614 
1615 /* Ext. save area 18: AMX XTILEDATA state */
1616 typedef struct XSaveXTILEDATA {
1617     uint8_t xtiledata[8][1024];
1618 } XSaveXTILEDATA;
1619 
1620 typedef struct {
1621        uint64_t from;
1622        uint64_t to;
1623        uint64_t info;
1624 } LBREntry;
1625 
1626 #define ARCH_LBR_NR_ENTRIES            32
1627 
1628 /* Ext. save area 19: Supervisor mode Arch LBR state */
1629 typedef struct XSavesArchLBR {
1630     uint64_t lbr_ctl;
1631     uint64_t lbr_depth;
1632     uint64_t ler_from;
1633     uint64_t ler_to;
1634     uint64_t ler_info;
1635     LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1636 } XSavesArchLBR;
1637 
1638 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1639 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1640 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1641 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1642 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1643 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1644 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1645 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1646 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1647 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1648 
1649 typedef struct ExtSaveArea {
1650     uint32_t feature, bits;
1651     uint32_t offset, size;
1652     uint32_t ecx;
1653 } ExtSaveArea;
1654 
1655 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1656 
1657 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1658 
1659 typedef enum TPRAccess {
1660     TPR_ACCESS_READ,
1661     TPR_ACCESS_WRITE,
1662 } TPRAccess;
1663 
1664 /* Cache information data structures: */
1665 
1666 enum CacheType {
1667     DATA_CACHE,
1668     INSTRUCTION_CACHE,
1669     UNIFIED_CACHE
1670 };
1671 
1672 typedef struct CPUCacheInfo {
1673     enum CacheType type;
1674     uint8_t level;
1675     /* Size in bytes */
1676     uint32_t size;
1677     /* Line size, in bytes */
1678     uint16_t line_size;
1679     /*
1680      * Associativity.
1681      * Note: representation of fully-associative caches is not implemented
1682      */
1683     uint8_t associativity;
1684     /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1685     uint8_t partitions;
1686     /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1687     uint32_t sets;
1688     /*
1689      * Lines per tag.
1690      * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1691      * (Is this synonym to @partitions?)
1692      */
1693     uint8_t lines_per_tag;
1694 
1695     /* Self-initializing cache */
1696     bool self_init;
1697     /*
1698      * WBINVD/INVD is not guaranteed to act upon lower level caches of
1699      * non-originating threads sharing this cache.
1700      * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1701      */
1702     bool no_invd_sharing;
1703     /*
1704      * Cache is inclusive of lower cache levels.
1705      * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1706      */
1707     bool inclusive;
1708     /*
1709      * A complex function is used to index the cache, potentially using all
1710      * address bits.  CPUID[4].EDX[bit 2].
1711      */
1712     bool complex_indexing;
1713 
1714     /*
1715      * Cache Topology. The level that cache is shared in.
1716      * Used to encode CPUID[4].EAX[bits 25:14] or
1717      * CPUID[0x8000001D].EAX[bits 25:14].
1718      */
1719     enum CPUTopoLevel share_level;
1720 } CPUCacheInfo;
1721 
1722 
1723 typedef struct CPUCaches {
1724         CPUCacheInfo *l1d_cache;
1725         CPUCacheInfo *l1i_cache;
1726         CPUCacheInfo *l2_cache;
1727         CPUCacheInfo *l3_cache;
1728 } CPUCaches;
1729 
1730 typedef struct HVFX86LazyFlags {
1731     target_ulong result;
1732     target_ulong auxbits;
1733 } HVFX86LazyFlags;
1734 
1735 typedef struct CPUArchState {
1736     /* standard registers */
1737     target_ulong regs[CPU_NB_REGS];
1738     target_ulong eip;
1739     target_ulong eflags; /* eflags register. During CPU emulation, CC
1740                         flags and DF are set to zero because they are
1741                         stored elsewhere */
1742 
1743     /* emulator internal eflags handling */
1744     target_ulong cc_dst;
1745     target_ulong cc_src;
1746     target_ulong cc_src2;
1747     uint32_t cc_op;
1748     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1749     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1750                         are known at translation time. */
1751     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1752 
1753     /* segments */
1754     SegmentCache segs[6]; /* selector values */
1755     SegmentCache ldt;
1756     SegmentCache tr;
1757     SegmentCache gdt; /* only base and limit are used */
1758     SegmentCache idt; /* only base and limit are used */
1759 
1760     target_ulong cr[5]; /* NOTE: cr1 is unused */
1761 
1762     bool pdptrs_valid;
1763     uint64_t pdptrs[4];
1764     int32_t a20_mask;
1765 
1766     BNDReg bnd_regs[4];
1767     BNDCSReg bndcs_regs;
1768     uint64_t msr_bndcfgs;
1769     uint64_t efer;
1770 
1771     /* Beginning of state preserved by INIT (dummy marker).  */
1772     struct {} start_init_save;
1773 
1774     /* FPU state */
1775     unsigned int fpstt; /* top of stack index */
1776     uint16_t fpus;
1777     uint16_t fpuc;
1778     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
1779     FPReg fpregs[8];
1780     /* KVM-only so far */
1781     uint16_t fpop;
1782     uint16_t fpcs;
1783     uint16_t fpds;
1784     uint64_t fpip;
1785     uint64_t fpdp;
1786 
1787     /* emulator internal variables */
1788     float_status fp_status;
1789     floatx80 ft0;
1790 
1791     float_status mmx_status; /* for 3DNow! float ops */
1792     float_status sse_status;
1793     uint32_t mxcsr;
1794     ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1795     ZMMReg xmm_t0 QEMU_ALIGNED(16);
1796     MMXReg mmx_t0;
1797 
1798     uint64_t opmask_regs[NB_OPMASK_REGS];
1799 #ifdef TARGET_X86_64
1800     uint8_t xtilecfg[64];
1801     uint8_t xtiledata[8192];
1802 #endif
1803 
1804     /* sysenter registers */
1805     uint32_t sysenter_cs;
1806     target_ulong sysenter_esp;
1807     target_ulong sysenter_eip;
1808     uint64_t star;
1809 
1810     uint64_t vm_hsave;
1811 
1812 #ifdef TARGET_X86_64
1813     target_ulong lstar;
1814     target_ulong cstar;
1815     target_ulong fmask;
1816     target_ulong kernelgsbase;
1817 
1818     /* FRED MSRs */
1819     uint64_t fred_rsp0;
1820     uint64_t fred_rsp1;
1821     uint64_t fred_rsp2;
1822     uint64_t fred_rsp3;
1823     uint64_t fred_stklvls;
1824     uint64_t fred_ssp1;
1825     uint64_t fred_ssp2;
1826     uint64_t fred_ssp3;
1827     uint64_t fred_config;
1828 #endif
1829 
1830     uint64_t tsc_adjust;
1831     uint64_t tsc_deadline;
1832     uint64_t tsc_aux;
1833 
1834     uint64_t xcr0;
1835 
1836     uint64_t mcg_status;
1837     uint64_t msr_ia32_misc_enable;
1838     uint64_t msr_ia32_feature_control;
1839     uint64_t msr_ia32_sgxlepubkeyhash[4];
1840 
1841     uint64_t msr_fixed_ctr_ctrl;
1842     uint64_t msr_global_ctrl;
1843     uint64_t msr_global_status;
1844     uint64_t msr_global_ovf_ctrl;
1845     uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1846     uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1847     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1848 
1849     uint64_t pat;
1850     uint32_t smbase;
1851     uint64_t msr_smi_count;
1852 
1853     uint32_t pkru;
1854     uint32_t pkrs;
1855     uint32_t tsx_ctrl;
1856 
1857     uint64_t spec_ctrl;
1858     uint64_t amd_tsc_scale_msr;
1859     uint64_t virt_ssbd;
1860 
1861     /* End of state preserved by INIT (dummy marker).  */
1862     struct {} end_init_save;
1863 
1864     uint64_t system_time_msr;
1865     uint64_t wall_clock_msr;
1866     uint64_t steal_time_msr;
1867     uint64_t async_pf_en_msr;
1868     uint64_t async_pf_int_msr;
1869     uint64_t pv_eoi_en_msr;
1870     uint64_t poll_control_msr;
1871 
1872     /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1873     uint64_t msr_hv_hypercall;
1874     uint64_t msr_hv_guest_os_id;
1875     uint64_t msr_hv_tsc;
1876     uint64_t msr_hv_syndbg_control;
1877     uint64_t msr_hv_syndbg_status;
1878     uint64_t msr_hv_syndbg_send_page;
1879     uint64_t msr_hv_syndbg_recv_page;
1880     uint64_t msr_hv_syndbg_pending_page;
1881     uint64_t msr_hv_syndbg_options;
1882 
1883     /* Per-VCPU HV MSRs */
1884     uint64_t msr_hv_vapic;
1885     uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1886     uint64_t msr_hv_runtime;
1887     uint64_t msr_hv_synic_control;
1888     uint64_t msr_hv_synic_evt_page;
1889     uint64_t msr_hv_synic_msg_page;
1890     uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1891     uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1892     uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1893     uint64_t msr_hv_reenlightenment_control;
1894     uint64_t msr_hv_tsc_emulation_control;
1895     uint64_t msr_hv_tsc_emulation_status;
1896 
1897     uint64_t msr_rtit_ctrl;
1898     uint64_t msr_rtit_status;
1899     uint64_t msr_rtit_output_base;
1900     uint64_t msr_rtit_output_mask;
1901     uint64_t msr_rtit_cr3_match;
1902     uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1903 
1904     /* Per-VCPU XFD MSRs */
1905     uint64_t msr_xfd;
1906     uint64_t msr_xfd_err;
1907 
1908     /* Per-VCPU Arch LBR MSRs */
1909     uint64_t msr_lbr_ctl;
1910     uint64_t msr_lbr_depth;
1911     LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1912 
1913     /* AMD MSRC001_0015 Hardware Configuration */
1914     uint64_t msr_hwcr;
1915 
1916     /* exception/interrupt handling */
1917     int error_code;
1918     int exception_is_int;
1919     target_ulong exception_next_eip;
1920     target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1921     union {
1922         struct CPUBreakpoint *cpu_breakpoint[4];
1923         struct CPUWatchpoint *cpu_watchpoint[4];
1924     }; /* break/watchpoints for dr[0..3] */
1925     int old_exception;  /* exception in flight */
1926 
1927     uint64_t vm_vmcb;
1928     uint64_t tsc_offset;
1929     uint64_t intercept;
1930     uint16_t intercept_cr_read;
1931     uint16_t intercept_cr_write;
1932     uint16_t intercept_dr_read;
1933     uint16_t intercept_dr_write;
1934     uint32_t intercept_exceptions;
1935     uint64_t nested_cr3;
1936     uint32_t nested_pg_mode;
1937     uint8_t v_tpr;
1938     uint32_t int_ctl;
1939 
1940     /* KVM states, automatically cleared on reset */
1941     uint8_t nmi_injected;
1942     uint8_t nmi_pending;
1943 
1944     uintptr_t retaddr;
1945 
1946     /* RAPL MSR */
1947     uint64_t msr_rapl_power_unit;
1948     uint64_t msr_pkg_energy_status;
1949 
1950     /* Fields up to this point are cleared by a CPU reset */
1951     struct {} end_reset_fields;
1952 
1953     /* Fields after this point are preserved across CPU reset. */
1954 
1955     /* processor features (e.g. for CPUID insn) */
1956     /* Minimum cpuid leaf 7 value */
1957     uint32_t cpuid_level_func7;
1958     /* Actual cpuid leaf 7 value */
1959     uint32_t cpuid_min_level_func7;
1960     /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1961     uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1962     /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1963     uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1964     /* Actual level/xlevel/xlevel2 value: */
1965     uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1966     uint32_t cpuid_vendor1;
1967     uint32_t cpuid_vendor2;
1968     uint32_t cpuid_vendor3;
1969     uint32_t cpuid_version;
1970     FeatureWordArray features;
1971     /* AVX10 version */
1972     uint8_t avx10_version;
1973     /* Features that were explicitly enabled/disabled */
1974     FeatureWordArray user_features;
1975     uint32_t cpuid_model[12];
1976     /* Cache information for CPUID.  When legacy-cache=on, the cache data
1977      * on each CPUID leaf will be different, because we keep compatibility
1978      * with old QEMU versions.
1979      */
1980     CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1981 
1982     /* MTRRs */
1983     uint64_t mtrr_fixed[11];
1984     uint64_t mtrr_deftype;
1985     MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1986 
1987     /* For KVM */
1988     uint32_t mp_state;
1989     int32_t exception_nr;
1990     int32_t interrupt_injected;
1991     uint8_t soft_interrupt;
1992     uint8_t exception_pending;
1993     uint8_t exception_injected;
1994     uint8_t has_error_code;
1995     uint8_t exception_has_payload;
1996     uint64_t exception_payload;
1997     uint8_t triple_fault_pending;
1998     uint32_t ins_len;
1999     uint32_t sipi_vector;
2000     bool tsc_valid;
2001     int64_t tsc_khz;
2002     int64_t user_tsc_khz; /* for sanity check only */
2003     uint64_t apic_bus_freq;
2004     uint64_t tsc;
2005 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2006     void *xsave_buf;
2007     uint32_t xsave_buf_len;
2008 #endif
2009 #if defined(CONFIG_KVM)
2010     struct kvm_nested_state *nested_state;
2011     MemoryRegion *xen_vcpu_info_mr;
2012     void *xen_vcpu_info_hva;
2013     uint64_t xen_vcpu_info_gpa;
2014     uint64_t xen_vcpu_info_default_gpa;
2015     uint64_t xen_vcpu_time_info_gpa;
2016     uint64_t xen_vcpu_runstate_gpa;
2017     uint8_t xen_vcpu_callback_vector;
2018     bool xen_callback_asserted;
2019     uint16_t xen_virq[XEN_NR_VIRQS];
2020     uint64_t xen_singleshot_timer_ns;
2021     QEMUTimer *xen_singleshot_timer;
2022     uint64_t xen_periodic_timer_period;
2023     QEMUTimer *xen_periodic_timer;
2024     QemuMutex xen_timers_lock;
2025 #endif
2026 #if defined(CONFIG_HVF)
2027     HVFX86LazyFlags hvf_lflags;
2028     void *hvf_mmio_buf;
2029 #endif
2030 
2031     uint64_t mcg_cap;
2032     uint64_t mcg_ctl;
2033     uint64_t mcg_ext_ctl;
2034     uint64_t mce_banks[MCE_BANKS_DEF*4];
2035     uint64_t xstate_bv;
2036 
2037     /* vmstate */
2038     uint16_t fpus_vmstate;
2039     uint16_t fptag_vmstate;
2040     uint16_t fpregs_format_vmstate;
2041 
2042     uint64_t xss;
2043     uint32_t umwait;
2044 
2045     TPRAccess tpr_access_type;
2046 
2047     /* Number of dies within this CPU package. */
2048     unsigned nr_dies;
2049 
2050     /* Number of modules within one die. */
2051     unsigned nr_modules;
2052 
2053     /* Bitmap of available CPU topology levels for this CPU. */
2054     DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
2055 } CPUX86State;
2056 
2057 struct kvm_msrs;
2058 
2059 /**
2060  * X86CPU:
2061  * @env: #CPUX86State
2062  * @migratable: If set, only migratable flags will be accepted when "enforce"
2063  * mode is used, and only migratable flags will be included in the "host"
2064  * CPU model.
2065  *
2066  * An x86 CPU.
2067  */
2068 struct ArchCPU {
2069     CPUState parent_obj;
2070 
2071     CPUX86State env;
2072     VMChangeStateEntry *vmsentry;
2073 
2074     uint64_t ucode_rev;
2075 
2076     uint32_t hyperv_spinlock_attempts;
2077     char *hyperv_vendor;
2078     bool hyperv_synic_kvm_only;
2079     uint64_t hyperv_features;
2080     bool hyperv_passthrough;
2081     OnOffAuto hyperv_no_nonarch_cs;
2082     uint32_t hyperv_vendor_id[3];
2083     uint32_t hyperv_interface_id[4];
2084     uint32_t hyperv_limits[3];
2085     bool hyperv_enforce_cpuid;
2086     uint32_t hyperv_ver_id_build;
2087     uint16_t hyperv_ver_id_major;
2088     uint16_t hyperv_ver_id_minor;
2089     uint32_t hyperv_ver_id_sp;
2090     uint8_t hyperv_ver_id_sb;
2091     uint32_t hyperv_ver_id_sn;
2092 
2093     bool check_cpuid;
2094     bool enforce_cpuid;
2095     /*
2096      * Force features to be enabled even if the host doesn't support them.
2097      * This is dangerous and should be done only for testing CPUID
2098      * compatibility.
2099      */
2100     bool force_features;
2101     bool expose_kvm;
2102     bool expose_tcg;
2103     bool migratable;
2104     bool migrate_smi_count;
2105     bool max_features; /* Enable all supported features automatically */
2106     uint32_t apic_id;
2107 
2108     /* Enables publishing of TSC increment and Local APIC bus frequencies to
2109      * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2110     bool vmware_cpuid_freq;
2111 
2112     /* if true the CPUID code directly forward host cache leaves to the guest */
2113     bool cache_info_passthrough;
2114 
2115     /* if true the CPUID code directly forwards
2116      * host monitor/mwait leaves to the guest */
2117     struct {
2118         uint32_t eax;
2119         uint32_t ebx;
2120         uint32_t ecx;
2121         uint32_t edx;
2122     } mwait;
2123 
2124     /* Features that were filtered out because of missing host capabilities */
2125     FeatureWordArray filtered_features;
2126 
2127     /* Enable PMU CPUID bits. This can't be enabled by default yet because
2128      * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
2129      * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
2130      * capabilities) directly to the guest.
2131      */
2132     bool enable_pmu;
2133 
2134     /*
2135      * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
2136      * This can't be initialized with a default because it doesn't have
2137      * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
2138      * returned by kvm_arch_get_supported_msr_feature()(which depends on both
2139      * host CPU and kernel capabilities) to the guest.
2140      */
2141     uint64_t lbr_fmt;
2142 
2143     /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
2144      * disabled by default to avoid breaking migration between QEMU with
2145      * different LMCE configurations.
2146      */
2147     bool enable_lmce;
2148 
2149     /* Compatibility bits for old machine types.
2150      * If true present virtual l3 cache for VM, the vcpus in the same virtual
2151      * socket share an virtual l3 cache.
2152      */
2153     bool enable_l3_cache;
2154 
2155     /* Compatibility bits for old machine types.
2156      * If true present L1 cache as per-thread, not per-core.
2157      */
2158     bool l1_cache_per_core;
2159 
2160     /* Compatibility bits for old machine types.
2161      * If true present the old cache topology information
2162      */
2163     bool legacy_cache;
2164 
2165     /* Compatibility bits for old machine types.
2166      * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2167      * nodes per processor
2168      */
2169     bool legacy_multi_node;
2170 
2171     /* Compatibility bits for old machine types: */
2172     bool enable_cpuid_0xb;
2173 
2174     /* Enable auto level-increase for all CPUID leaves */
2175     bool full_cpuid_auto_level;
2176 
2177     /* Only advertise CPUID leaves defined by the vendor */
2178     bool vendor_cpuid_only;
2179 
2180     /* Only advertise TOPOEXT features that AMD defines */
2181     bool amd_topoext_features_only;
2182 
2183     /* Enable auto level-increase for Intel Processor Trace leave */
2184     bool intel_pt_auto_level;
2185 
2186     /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2187     bool fill_mtrr_mask;
2188 
2189     /* if true override the phys_bits value with a value read from the host */
2190     bool host_phys_bits;
2191 
2192     /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2193     uint8_t host_phys_bits_limit;
2194 
2195     /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2196     bool kvm_pv_enforce_cpuid;
2197 
2198     /* Number of physical address bits supported */
2199     uint32_t phys_bits;
2200 
2201     /*
2202      * Number of guest physical address bits available. Usually this is
2203      * identical to host physical address bits. With NPT or EPT 4-level
2204      * paging, guest physical address space might be restricted to 48 bits
2205      * even if the host cpu supports more physical address bits.
2206      */
2207     uint32_t guest_phys_bits;
2208 
2209     /* in order to simplify APIC support, we leave this pointer to the
2210        user */
2211     struct DeviceState *apic_state;
2212     struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2213     Notifier machine_done;
2214 
2215     struct kvm_msrs *kvm_msr_buf;
2216 
2217     int32_t node_id; /* NUMA node this CPU belongs to */
2218     int32_t socket_id;
2219     int32_t die_id;
2220     int32_t module_id;
2221     int32_t core_id;
2222     int32_t thread_id;
2223 
2224     int32_t hv_max_vps;
2225 
2226     bool xen_vapic;
2227 };
2228 
2229 typedef struct X86CPUModel X86CPUModel;
2230 
2231 /**
2232  * X86CPUClass:
2233  * @cpu_def: CPU model definition
2234  * @host_cpuid_required: Whether CPU model requires cpuid from host.
2235  * @ordering: Ordering on the "-cpu help" CPU model list.
2236  * @migration_safe: See CpuDefinitionInfo::migration_safe
2237  * @static_model: See CpuDefinitionInfo::static
2238  * @parent_realize: The parent class' realize handler.
2239  * @parent_phases: The parent class' reset phase handlers.
2240  *
2241  * An x86 CPU model or family.
2242  */
2243 struct X86CPUClass {
2244     CPUClass parent_class;
2245 
2246     /*
2247      * CPU definition, automatically loaded by instance_init if not NULL.
2248      * Should be eventually replaced by subclass-specific property defaults.
2249      */
2250     X86CPUModel *model;
2251 
2252     bool host_cpuid_required;
2253     int ordering;
2254     bool migration_safe;
2255     bool static_model;
2256 
2257     /*
2258      * Optional description of CPU model.
2259      * If unavailable, cpu_def->model_id is used.
2260      */
2261     const char *model_description;
2262 
2263     DeviceRealize parent_realize;
2264     DeviceUnrealize parent_unrealize;
2265     ResettablePhases parent_phases;
2266 };
2267 
2268 #ifndef CONFIG_USER_ONLY
2269 extern const VMStateDescription vmstate_x86_cpu;
2270 #endif
2271 
2272 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2273 
2274 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2275                              int cpuid, DumpState *s);
2276 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2277                              int cpuid, DumpState *s);
2278 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2279                                  DumpState *s);
2280 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2281                                  DumpState *s);
2282 
2283 bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2284                                 Error **errp);
2285 
2286 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2287 
2288 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2289 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2290 void x86_cpu_gdb_init(CPUState *cs);
2291 
2292 void x86_cpu_list(void);
2293 int cpu_x86_support_mca_broadcast(CPUX86State *env);
2294 
2295 #ifndef CONFIG_USER_ONLY
2296 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2297                                          MemTxAttrs *attrs);
2298 int cpu_get_pic_interrupt(CPUX86State *s);
2299 
2300 /* MS-DOS compatibility mode FPU exception support */
2301 void x86_register_ferr_irq(qemu_irq irq);
2302 void fpu_check_raise_ferr_irq(CPUX86State *s);
2303 void cpu_set_ignne(void);
2304 void cpu_clear_ignne(void);
2305 #endif
2306 
2307 /* mpx_helper.c */
2308 void cpu_sync_bndcs_hflags(CPUX86State *env);
2309 
2310 /* this function must always be used to load data in the segment
2311    cache: it synchronizes the hflags with the segment cache values */
cpu_x86_load_seg_cache(CPUX86State * env,X86Seg seg_reg,unsigned int selector,target_ulong base,unsigned int limit,unsigned int flags)2312 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2313                                           X86Seg seg_reg, unsigned int selector,
2314                                           target_ulong base,
2315                                           unsigned int limit,
2316                                           unsigned int flags)
2317 {
2318     SegmentCache *sc;
2319     unsigned int new_hflags;
2320 
2321     sc = &env->segs[seg_reg];
2322     sc->selector = selector;
2323     sc->base = base;
2324     sc->limit = limit;
2325     sc->flags = flags;
2326 
2327     /* update the hidden flags */
2328     {
2329         if (seg_reg == R_CS) {
2330 #ifdef TARGET_X86_64
2331             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2332                 /* long mode */
2333                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2334                 env->hflags &= ~(HF_ADDSEG_MASK);
2335             } else
2336 #endif
2337             {
2338                 /* legacy / compatibility case */
2339                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2340                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2341                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2342                     new_hflags;
2343             }
2344         }
2345         if (seg_reg == R_SS) {
2346             int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2347 #if HF_CPL_MASK != 3
2348 #error HF_CPL_MASK is hardcoded
2349 #endif
2350             env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2351             /* Possibly switch between BNDCFGS and BNDCFGU */
2352             cpu_sync_bndcs_hflags(env);
2353         }
2354         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2355             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2356         if (env->hflags & HF_CS64_MASK) {
2357             /* zero base assumed for DS, ES and SS in long mode */
2358         } else if (!(env->cr[0] & CR0_PE_MASK) ||
2359                    (env->eflags & VM_MASK) ||
2360                    !(env->hflags & HF_CS32_MASK)) {
2361             /* XXX: try to avoid this test. The problem comes from the
2362                fact that is real mode or vm86 mode we only modify the
2363                'base' and 'selector' fields of the segment cache to go
2364                faster. A solution may be to force addseg to one in
2365                translate-i386.c. */
2366             new_hflags |= HF_ADDSEG_MASK;
2367         } else {
2368             new_hflags |= ((env->segs[R_DS].base |
2369                             env->segs[R_ES].base |
2370                             env->segs[R_SS].base) != 0) <<
2371                 HF_ADDSEG_SHIFT;
2372         }
2373         env->hflags = (env->hflags &
2374                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2375     }
2376 }
2377 
cpu_x86_load_seg_cache_sipi(X86CPU * cpu,uint8_t sipi_vector)2378 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2379                                                uint8_t sipi_vector)
2380 {
2381     CPUState *cs = CPU(cpu);
2382     CPUX86State *env = &cpu->env;
2383 
2384     env->eip = 0;
2385     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2386                            sipi_vector << 12,
2387                            env->segs[R_CS].limit,
2388                            env->segs[R_CS].flags);
2389     cs->halted = 0;
2390 }
2391 
2392 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2393                             target_ulong *base, unsigned int *limit,
2394                             unsigned int *flags);
2395 
2396 /* op_helper.c */
2397 /* used for debug or cpu save/restore */
2398 
2399 /* cpu-exec.c */
2400 /*
2401  * The following helpers are only usable in user mode simulation.
2402  * The host pointers should come from lock_user().
2403  */
2404 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2405 void cpu_x86_fsave(CPUX86State *s, void *host, size_t len);
2406 void cpu_x86_frstor(CPUX86State *s, void *host, size_t len);
2407 void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len);
2408 void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len);
2409 void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2410 bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2411 
2412 /* cpu.c */
2413 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2414                               uint32_t vendor2, uint32_t vendor3);
2415 typedef struct PropValue {
2416     const char *prop, *value;
2417 } PropValue;
2418 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2419 
2420 void x86_cpu_after_reset(X86CPU *cpu);
2421 
2422 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2423 
2424 /* cpu.c other functions (cpuid) */
2425 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2426                    uint32_t *eax, uint32_t *ebx,
2427                    uint32_t *ecx, uint32_t *edx);
2428 void cpu_clear_apic_feature(CPUX86State *env);
2429 void cpu_set_apic_feature(CPUX86State *env);
2430 void host_cpuid(uint32_t function, uint32_t count,
2431                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2432 bool cpu_has_x2apic_feature(CPUX86State *env);
2433 
2434 /* helper.c */
2435 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2436 void cpu_sync_avx_hflag(CPUX86State *env);
2437 
2438 #ifndef CONFIG_USER_ONLY
x86_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)2439 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2440 {
2441     return !!attrs.secure;
2442 }
2443 
cpu_addressspace(CPUState * cs,MemTxAttrs attrs)2444 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2445 {
2446     return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2447 }
2448 
2449 /*
2450  * load efer and update the corresponding hflags. XXX: do consistency
2451  * checks with cpuid bits?
2452  */
2453 void cpu_load_efer(CPUX86State *env, uint64_t val);
2454 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2455 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2456 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2457 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2458 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2459 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2460 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2461 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2462 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2463 #endif
2464 
2465 /* will be suppressed */
2466 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2467 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2468 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2469 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2470 
2471 /* hw/pc.c */
2472 uint64_t cpu_get_tsc(CPUX86State *env);
2473 
2474 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2475 
2476 #ifdef TARGET_X86_64
2477 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2478 #else
2479 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2480 #endif
2481 
2482 #define cpu_list x86_cpu_list
2483 
2484 /* MMU modes definitions */
2485 #define MMU_KSMAP64_IDX    0
2486 #define MMU_KSMAP32_IDX    1
2487 #define MMU_USER64_IDX     2
2488 #define MMU_USER32_IDX     3
2489 #define MMU_KNOSMAP64_IDX  4
2490 #define MMU_KNOSMAP32_IDX  5
2491 #define MMU_PHYS_IDX       6
2492 #define MMU_NESTED_IDX     7
2493 
2494 #ifdef CONFIG_USER_ONLY
2495 #ifdef TARGET_X86_64
2496 #define MMU_USER_IDX MMU_USER64_IDX
2497 #else
2498 #define MMU_USER_IDX MMU_USER32_IDX
2499 #endif
2500 #endif
2501 
is_mmu_index_smap(int mmu_index)2502 static inline bool is_mmu_index_smap(int mmu_index)
2503 {
2504     return (mmu_index & ~1) == MMU_KSMAP64_IDX;
2505 }
2506 
is_mmu_index_user(int mmu_index)2507 static inline bool is_mmu_index_user(int mmu_index)
2508 {
2509     return (mmu_index & ~1) == MMU_USER64_IDX;
2510 }
2511 
is_mmu_index_32(int mmu_index)2512 static inline bool is_mmu_index_32(int mmu_index)
2513 {
2514     assert(mmu_index < MMU_PHYS_IDX);
2515     return mmu_index & 1;
2516 }
2517 
2518 int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
2519 int cpu_mmu_index_kernel(CPUX86State *env);
2520 
2521 #define CC_DST  (env->cc_dst)
2522 #define CC_SRC  (env->cc_src)
2523 #define CC_SRC2 (env->cc_src2)
2524 #define CC_OP   (env->cc_op)
2525 
2526 #include "exec/cpu-all.h"
2527 #include "svm.h"
2528 
2529 #if !defined(CONFIG_USER_ONLY)
2530 #include "hw/i386/apic.h"
2531 #endif
2532 
cpu_get_tb_cpu_state(CPUX86State * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2533 static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2534                                         uint64_t *cs_base, uint32_t *flags)
2535 {
2536     *flags = env->hflags |
2537         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2538     if (env->hflags & HF_CS64_MASK) {
2539         *cs_base = 0;
2540         *pc = env->eip;
2541     } else {
2542         *cs_base = env->segs[R_CS].base;
2543         *pc = (uint32_t)(*cs_base + env->eip);
2544     }
2545 }
2546 
2547 void do_cpu_init(X86CPU *cpu);
2548 
2549 #define MCE_INJECT_BROADCAST    1
2550 #define MCE_INJECT_UNCOND_AO    2
2551 
2552 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2553                         uint64_t status, uint64_t mcg_status, uint64_t addr,
2554                         uint64_t misc, int flags);
2555 
2556 uint32_t cpu_cc_compute_all(CPUX86State *env1);
2557 
cpu_compute_eflags(CPUX86State * env)2558 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2559 {
2560     uint32_t eflags = env->eflags;
2561     if (tcg_enabled()) {
2562         eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2563     }
2564     return eflags;
2565 }
2566 
cpu_get_mem_attrs(CPUX86State * env)2567 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2568 {
2569     return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2570 }
2571 
x86_get_a20_mask(CPUX86State * env)2572 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2573 {
2574     if (env->hflags & HF_SMM_MASK) {
2575         return -1;
2576     } else {
2577         return env->a20_mask;
2578     }
2579 }
2580 
cpu_has_vmx(CPUX86State * env)2581 static inline bool cpu_has_vmx(CPUX86State *env)
2582 {
2583     return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2584 }
2585 
cpu_has_svm(CPUX86State * env)2586 static inline bool cpu_has_svm(CPUX86State *env)
2587 {
2588     return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2589 }
2590 
2591 /*
2592  * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2593  * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2594  * VMX operation. This is because CR4.VMXE is one of the bits set
2595  * in MSR_IA32_VMX_CR4_FIXED1.
2596  *
2597  * There is one exception to above statement when vCPU enters SMM mode.
2598  * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2599  * may also reset CR4.VMXE during execution in SMM mode.
2600  * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2601  * and CR4.VMXE is restored to it's original value of being set.
2602  *
2603  * Therefore, when vCPU is not in SMM mode, we can infer whether
2604  * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2605  * know for certain.
2606  */
cpu_vmx_maybe_enabled(CPUX86State * env)2607 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2608 {
2609     return cpu_has_vmx(env) &&
2610            ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2611 }
2612 
2613 /* excp_helper.c */
2614 int get_pg_mode(CPUX86State *env);
2615 
2616 /* fpu_helper.c */
2617 
2618 /* Set all non-runtime-variable float_status fields to x86 handling */
2619 void cpu_init_fp_statuses(CPUX86State *env);
2620 void update_fp_status(CPUX86State *env);
2621 void update_mxcsr_status(CPUX86State *env);
2622 void update_mxcsr_from_sse_status(CPUX86State *env);
2623 
cpu_set_mxcsr(CPUX86State * env,uint32_t mxcsr)2624 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2625 {
2626     env->mxcsr = mxcsr;
2627     if (tcg_enabled()) {
2628         update_mxcsr_status(env);
2629     }
2630 }
2631 
cpu_set_fpuc(CPUX86State * env,uint16_t fpuc)2632 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2633 {
2634      env->fpuc = fpuc;
2635      if (tcg_enabled()) {
2636         update_fp_status(env);
2637      }
2638 }
2639 
2640 /* svm_helper.c */
2641 #ifdef CONFIG_USER_ONLY
2642 static inline void
cpu_svm_check_intercept_param(CPUX86State * env1,uint32_t type,uint64_t param,uintptr_t retaddr)2643 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2644                               uint64_t param, uintptr_t retaddr)
2645 { /* no-op */ }
2646 static inline bool
cpu_svm_has_intercept(CPUX86State * env,uint32_t type)2647 cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2648 { return false; }
2649 #else
2650 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2651                                    uint64_t param, uintptr_t retaddr);
2652 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2653 #endif
2654 
2655 /* apic.c */
2656 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2657 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2658                                    TPRAccess access);
2659 
2660 /* Special values for X86CPUVersion: */
2661 
2662 /* Resolve to latest CPU version */
2663 #define CPU_VERSION_LATEST -1
2664 
2665 /*
2666  * Resolve to version defined by current machine type.
2667  * See x86_cpu_set_default_version()
2668  */
2669 #define CPU_VERSION_AUTO   -2
2670 
2671 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2672 #define CPU_VERSION_LEGACY  0
2673 
2674 typedef int X86CPUVersion;
2675 
2676 /*
2677  * Set default CPU model version for CPU models having
2678  * version == CPU_VERSION_AUTO.
2679  */
2680 void x86_cpu_set_default_version(X86CPUVersion version);
2681 
2682 #ifndef CONFIG_USER_ONLY
2683 
2684 void do_cpu_sipi(X86CPU *cpu);
2685 
2686 #define APIC_DEFAULT_ADDRESS 0xfee00000
2687 #define APIC_SPACE_SIZE      0x100000
2688 
2689 /* cpu-dump.c */
2690 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2691 
2692 #endif
2693 
2694 /* cpu.c */
2695 bool cpu_is_bsp(X86CPU *cpu);
2696 
2697 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2698 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2699 uint32_t xsave_area_size(uint64_t mask, bool compacted);
2700 void x86_update_hflags(CPUX86State* env);
2701 
hyperv_feat_enabled(X86CPU * cpu,int feat)2702 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2703 {
2704     return !!(cpu->hyperv_features & BIT(feat));
2705 }
2706 
cr4_reserved_bits(CPUX86State * env)2707 static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2708 {
2709     uint64_t reserved_bits = CR4_RESERVED_MASK;
2710     if (!env->features[FEAT_XSAVE]) {
2711         reserved_bits |= CR4_OSXSAVE_MASK;
2712     }
2713     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2714         reserved_bits |= CR4_SMEP_MASK;
2715     }
2716     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2717         reserved_bits |= CR4_SMAP_MASK;
2718     }
2719     if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2720         reserved_bits |= CR4_FSGSBASE_MASK;
2721     }
2722     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2723         reserved_bits |= CR4_PKE_MASK;
2724     }
2725     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2726         reserved_bits |= CR4_LA57_MASK;
2727     }
2728     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2729         reserved_bits |= CR4_UMIP_MASK;
2730     }
2731     if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2732         reserved_bits |= CR4_PKS_MASK;
2733     }
2734     if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
2735         reserved_bits |= CR4_LAM_SUP_MASK;
2736     }
2737     if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) {
2738         reserved_bits |= CR4_FRED_MASK;
2739     }
2740     return reserved_bits;
2741 }
2742 
ctl_has_irq(CPUX86State * env)2743 static inline bool ctl_has_irq(CPUX86State *env)
2744 {
2745     uint32_t int_prio;
2746     uint32_t tpr;
2747 
2748     int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2749     tpr = env->int_ctl & V_TPR_MASK;
2750 
2751     if (env->int_ctl & V_IGN_TPR_MASK) {
2752         return (env->int_ctl & V_IRQ_MASK);
2753     }
2754 
2755     return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2756 }
2757 
2758 #if defined(TARGET_X86_64) && \
2759     defined(CONFIG_USER_ONLY) && \
2760     defined(CONFIG_LINUX)
2761 # define TARGET_VSYSCALL_PAGE  (UINT64_C(-10) << 20)
2762 #endif
2763 
2764 #endif /* I386_CPU_H */
2765