| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|
| /dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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| /dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/x86/include/asm/ |
| H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
|