1 /* $OpenBSD: if_ngbereg.h,v 1.2 2024/09/01 03:08:59 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2015-2017 Beijing WangXun Technology Co., Ltd. 5 * Copyright (c) 2023 Kevin Lo <kevlo@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define NGBE_PCIREG PCI_MAPREG_START /* BAR 0 */ 21 #define NGBE_MAX_VECTORS 8 22 #define NGBE_SP_MAX_TX_QUEUES 8 23 #define NGBE_SP_MAX_RX_QUEUES 8 24 #define NGBE_SP_RAR_ENTRIES 32 25 #define NGBE_SP_MC_TBL_SIZE 128 26 #define NGBE_SP_VFT_TBL_SIZE 128 27 #define NGBE_SP_RX_PB_SIZE 42 28 29 #define NGBE_PSR_VLAN_SWC_ENTRIES 32 30 #define NGBE_MAX_MTA 128 31 #define NGBE_MAX_VFTA_ENTRIES 128 32 #define NGBE_MAX_INTS_PER_SEC 8000 33 #define NGBE_MAX_JUMBO_FRAME_SIZE 9432 34 35 #define NGBE_TX_TIMEOUT 5 36 #define NGBE_LINK_UP_TIME 90 37 #define NGBE_MAX_FLASH_LOAD_POLL_TIME 10 38 39 /* Additional bittime to account for NGBE framing */ 40 #define NGBE_ETH_FRAMING 20 41 42 /* Tx/Rx descriptor defines */ 43 #define NGBE_DEFAULT_TXD 512 44 #define NGBE_DEFAULT_RXD 512 45 46 /* Flow control */ 47 #define NGBE_DEFAULT_FCPAUSE 0xffff 48 49 /* Flow control defines */ 50 #define NGBE_TAF_SYM_PAUSE 0x1 51 #define NGBE_TAF_ASM_PAUSE 0x2 52 53 /* Interrupt Registers */ 54 #define NGBE_PX_MISC_IC 0x00100 55 #define NGBE_PX_MISC_IEN 0x00108 56 #define NGBE_PX_GPIE 0x00118 57 #define NGBE_PX_IC 0x00120 58 #define NGBE_PX_IMS 0x00140 59 #define NGBE_PX_IMC 0x00150 60 #define NGBE_PX_ISB_ADDR_L 0x00160 61 #define NGBE_PX_ISB_ADDR_H 0x00164 62 #define NGBE_PX_TRANSACTION_PENDING 0x00168 63 #define NGBE_PX_ITRSEL 0x00180 64 #define NGBE_PX_ITR(_i) (0x00200 + (_i) * 4) 65 #define NGBE_PX_MISC_IVAR 0x004fc 66 #define NGBE_PX_IVAR(_i) (0x00500 + (_i) * 4) 67 68 /* Receive DMA Registers */ 69 #define NGBE_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40)) 70 #define NGBE_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40)) 71 #define NGBE_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40)) 72 #define NGBE_PX_RR_RP(_i) (0x0100c + ((_i) * 0x40)) 73 #define NGBE_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40)) 74 75 /* Statistic */ 76 #define NGBE_PX_MPRC(_i) (0x01020 + ((_i) * 64)) 77 78 /* Transmit DMA Registers */ 79 #define NGBE_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40)) 80 #define NGBE_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40)) 81 #define NGBE_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40)) 82 #define NGBE_PX_TR_RP(_i) (0x0300c + ((_i) * 0x40)) 83 #define NGBE_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) 84 85 /* Chip Control Registers */ 86 #define NGBE_MIS_PWR 0x10000 87 #define NGBE_MIS_RST 0x1000c 88 #define NGBE_MIS_PRB_CTL 0x10010 89 #define NGBE_MIS_ST 0x10028 90 #define NGBE_MIS_SWSM 0x1002c 91 #define NGBE_MIS_RST_ST 0x10030 92 93 /* FMGR Registers */ 94 #define NGBE_SPI_CMD 0x10104 95 #define NGBE_SPI_DATA 0x10108 96 #define NGBE_SPI_STATUS 0x1010c 97 #define NGBE_SPI_ILDR_STATUS 0x10120 98 99 /* Checksum and EEPROM Registers */ 100 #define NGBE_CALSUM_CAP_STATUS 0x10224 101 #define NGBE_EEPROM_VERSION_STORE_REG 0x1022c 102 103 /* Sensors for PVT(Process Voltage Temperature) */ 104 #define NGBE_TS_EN 0x10304 105 #define NGBE_TS_ALARM_THRE 0x1030c 106 #define NGBE_TS_DALARM_THRE 0x10310 107 #define NGBE_TS_INT_EN 0x10314 108 #define NGBE_TS_ALARM_ST 0x10318 109 110 /* MAC Registers */ 111 #define NGBE_MAC_TX_CFG 0x11000 112 #define NGBE_MAC_RX_CFG 0x11004 113 #define NGBE_MAC_PKT_FLT 0x11008 114 #define NGBE_MAC_WDG_TIMEOUT 0x1100c 115 #define NGBE_MAC_RX_FLOW_CTRL 0x11090 116 117 /* Media-dependent registers. */ 118 #define NGBE_MDIO_CLAUSE_SELECT 0x11220 119 120 /* Statistic */ 121 #define NGBE_MMC_CONTROL 0x11800 122 #define NGBE_TX_FRAME_CNT_GOOD_BAD_LOW 0x1181c 123 #define NGBE_TX_BC_FRAMES_GOOD_LOW 0x11824 124 #define NGBE_TX_MC_FRAMES_GOOD_LOW 0x1182c 125 #define NGBE_RX_FRAME_CNT_GOOD_BAD_LOW 0x11900 126 #define NGBE_RX_BC_FRAMES_GOOD_LOW 0x11918 127 #define NGBE_RX_CRC_ERROR_FRAMES_LOW 0x11928 128 #define NGBE_RX_UNDERSIZE_FRAMES_GOOD 0x11938 129 #define NGBE_RX_OVERSIZE_FRAMES_GOOD 0x1193c 130 #define NGBE_RX_LEN_ERROR_FRAMES_LOW 0x11978 131 #define NGBE_MAC_LXOFFRXC 0x11988 132 #define NGBE_MAC_PXOFFRXC 0x119dc 133 134 /* Interrupt Registers */ 135 #define NGBE_BME_CTL 0x12020 136 137 /* Statistic */ 138 #define NGBE_RDM_DRP_PKT 0x12500 139 #define NGBE_PX_GPRC 0x12504 140 #define NGBE_PX_GORC_MSB 0x1250c 141 142 /* Internal phy reg_offset [0,31] */ 143 #define NGBE_PHY_CONFIG(offset) (0x14000 + ((offset) * 4)) 144 145 /* Port cfg Registers */ 146 #define NGBE_CFG_PORT_CTL 0x14400 147 #define NGBE_CFG_PORT_ST 0x14404 148 #define NGBE_CFG_LAN_SPEED 0x14440 149 150 /* GPIO Registers */ 151 #define NGBE_GPIO_DDR 0x14804 152 #define NGBE_GPIO_INTEN 0x14830 153 #define NGBE_GPIO_INTTYPE_LEVEL 0x14838 154 #define NGBE_GPIO_POLARITY 0x1483c 155 #define NGBE_GPIO_INTSTATUS 0x14840 156 #define NGBE_GPIO_EOI 0x1484c 157 158 /* PSR Control Registers */ 159 #define NGBE_PSR_CTL 0x15000 160 #define NGBE_PSR_MAX_SZ 0x15020 161 #define NGBE_PSR_VLAN_CTL 0x15088 162 163 /* mcast/ucast overflow tbl */ 164 #define NGBE_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4)) 165 #define NGBE_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4)) 166 167 /* Management Registers */ 168 #define NGBE_PSR_MNG_FLEX_SEL 0x1582c 169 #define NGBE_PSR_MNG_FLEX_DW_L(_i) (0x15a00 + ((_i) * 16)) 170 #define NGBE_PSR_MNG_FLEX_DW_H(_i) (0x15a04 + ((_i) * 16)) 171 #define NGBE_PSR_MNG_FLEX_MSK(_i) (0x15a08 + ((_i) * 16)) 172 173 /* Wake Up Registers */ 174 #define NGBE_PSR_LAN_FLEX_SEL 0x15b8c 175 #define NGBE_PSR_LAN_FLEX_DW_L(_i) (0x15c00 + ((_i) * 16)) 176 #define NGBE_PSR_LAN_FLEX_DW_H(_i) (0x15c04 + ((_i) * 16)) 177 #define NGBE_PSR_LAN_FLEX_MSK(_i) (0x15c08 + ((_i) * 16)) 178 179 /* VLAN tbl */ 180 #define NGBE_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4)) 181 182 /* MAC switcher */ 183 #define NGBE_PSR_MAC_SWC_AD_L 0x16200 184 #define NGBE_PSR_MAC_SWC_AD_H 0x16204 185 #define NGBE_PSR_MAC_SWC_VM 0x16208 186 #define NGBE_PSR_MAC_SWC_IDX 0x16210 187 188 /* VLAN switch */ 189 #define NGBE_PSR_VLAN_SWC 0x16220 190 #define NGBE_PSR_VLAN_SWC_VM_L 0x16224 191 #define NGBE_PSR_VLAN_SWC_IDX 0x16230 192 193 /* RSEC Registers */ 194 #define NGBE_RSEC_CTL 0x17000 195 #define NGBE_RSEC_ST 0x17004 196 197 /* Transmit Global Control Registers */ 198 #define NGBE_TDM_CTL 0x18000 199 #define NGBE_TDM_PB_THRE 0x18020 200 201 /* Statistic */ 202 #define NGBE_PX_GPTC 0x18308 203 #define NGBE_PX_GOTC_MSB 0x18310 204 205 /* Receive packet buffer */ 206 #define NGBE_RDB_PB_CTL 0x19000 207 #define NGBE_RDB_PB_SZ 0x19020 208 #define NGBE_RDB_RFCV 0x19200 209 210 /* Statistic */ 211 #define NGBE_RDB_PFCMACDAL 0x19210 212 #define NGBE_RDB_PFCMACDAH 0x19214 213 #define NGBE_RDB_LXONTXC 0x1921c 214 #define NGBE_RDB_LXOFFTXC 0x19218 215 216 /* Flow Control Registers */ 217 #define NGBE_RDB_RFCL 0x19220 218 #define NGBE_RDB_RFCH 0x19260 219 #define NGBE_RDB_RFCRT 0x192a0 220 #define NGBE_RDB_RFCC 0x192a4 221 222 /* Ring Assignment */ 223 #define NGBE_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4)) 224 #define NGBE_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4)) 225 #define NGBE_RDB_RSSRK(_i) (0x19480 + ((_i) * 4)) 226 #define NGBE_RDB_RA_CTL 0x194f4 227 228 /* TDB */ 229 #define NGBE_TDB_PB_SZ 0x1cc00 230 231 /* Security Control Registers */ 232 #define NGBE_TSEC_CTL 0x1d000 233 #define NGBE_TSEC_BUF_AE 0x1d00c 234 235 /* MNG */ 236 #define NGBE_MNG_SWFW_SYNC 0x1e008 237 #define NGBE_MNG_MBOX 0x1e100 238 #define NGBE_MNG_MBOX_CTL 0x1e044 239 240 /* Bits in NGBE_PX_MISC_IC register */ 241 #define NGBE_PX_MISC_IC_PHY 0x00040000 242 #define NGBE_PX_MISC_IC_GPIO 0x04000000 243 244 /* Bits in NGBE_PX_MISC_IEN register */ 245 #define NGBE_PX_MISC_IEN_ETH_LKDN 0x00000100 246 #define NGBE_PX_MISC_IEN_DEV_RST 0x00000400 247 #define NGBE_PX_MISC_IEN_STALL 0x00001000 248 #define NGBE_PX_MISC_IEN_ETH_EVENT 0x00020000 249 #define NGBE_PX_MISC_IEN_ETH_LK 0x00040000 250 #define NGBE_PX_MISC_IEN_ETH_AN 0x00080000 251 #define NGBE_PX_MISC_IEN_INT_ERR 0x00100000 252 #define NGBE_PX_MISC_IEN_VF_MBOX 0x00800000 253 #define NGBE_PX_MISC_IEN_GPIO 0x04000000 254 #define NGBE_PX_MISC_IEN_PCIE_REQ_ERR 0x08000000 255 #define NGBE_PX_MISC_IEN_OVER_HEAT 0x10000000 256 #define NGBE_PX_MISC_IEN_MNG_HOST_MBOX 0x40000000 257 #define NGBE_PX_MISC_IEN_TIMER 0x80000000 258 259 #define NGBE_PX_MISC_IEN_MASK \ 260 (NGBE_PX_MISC_IEN_ETH_LKDN | NGBE_PX_MISC_IEN_DEV_RST | \ 261 NGBE_PX_MISC_IEN_STALL | NGBE_PX_MISC_IEN_ETH_EVENT | \ 262 NGBE_PX_MISC_IEN_ETH_LK | NGBE_PX_MISC_IEN_ETH_AN | \ 263 NGBE_PX_MISC_IEN_INT_ERR | NGBE_PX_MISC_IEN_VF_MBOX | \ 264 NGBE_PX_MISC_IEN_GPIO | NGBE_PX_MISC_IEN_PCIE_REQ_ERR | \ 265 NGBE_PX_MISC_IEN_MNG_HOST_MBOX | NGBE_PX_MISC_IEN_TIMER) 266 267 /* Bits in NGBE_PX_GPIE register */ 268 #define NGBE_PX_GPIE_MODEL 0x00000001 269 270 /* Bits in NGBE_PX_ITR register */ 271 #define NGBE_MAX_EITR 0x00007ffc 272 #define NGBE_PX_ITR_CNT_WDIS 0x80000000 273 274 /* Bits in NGBE_PX_IVAR register */ 275 #define NGBE_PX_IVAR_ALLOC_VAL 0x80 276 277 /* Bits in NGBE_PX_RR_CFG register */ 278 #define NGBE_PX_RR_CFG_RR_EN 0x00000001 279 #define NGBE_PX_RR_CFG_SPLIT_MODE 0x04000000 280 #define NGBE_PX_RR_CFG_DROP_EN 0x40000000 281 #define NGBE_PX_RR_CFG_VLAN 0x80000000 282 283 #define NGBE_PX_RR_CFG_RR_BUF_SZ 0x00000f00 284 #define NGBE_PX_RR_CFG_RR_HDR_SZ 0x0000f000 285 #define NGBE_PX_RR_CFG_RR_SIZE_SHIFT 1 286 #define NGBE_PX_RR_CFG_BSIZEPKT_SHIFT 2 287 #define NGBE_PX_RR_CFG_RR_THER_SHIFT 16 288 289 /* Bits in NGBE_PX_TR_CFG register */ 290 #define NGBE_PX_TR_CFG_ENABLE (1) 291 #define NGBE_PX_TR_CFG_SWFLSH 0x04000000 292 293 #define NGBE_PX_TR_CFG_TR_SIZE_SHIFT 1 294 #define NGBE_PX_TR_CFG_WTHRESH_SHIFT 16 295 296 /* Bits in NGBE_MIS_RST register */ 297 #define NGBE_MIS_RST_SW_RST 0x00000001 298 #define NGBE_MIS_RST_LAN0_RST 0x00000002 299 #define NGBE_MIS_RST_LAN1_RST 0x00000004 300 #define NGBE_MIS_RST_LAN2_RST 0x00000008 301 #define NGBE_MIS_RST_LAN3_RST 0x00000010 302 303 /* Bits in NGBE_MIS_PRB_CTL register */ 304 #define NGBE_MIS_PRB_CTL_LAN3_UP 0x1 305 #define NGBE_MIS_PRB_CTL_LAN2_UP 0x2 306 #define NGBE_MIS_PRB_CTL_LAN1_UP 0x4 307 #define NGBE_MIS_PRB_CTL_LAN0_UP 0x8 308 309 /* Bits in NGBE_MIS_ST register */ 310 #define NGBE_MIS_ST_MNG_INIT_DN 0x00000001 311 #define NGBE_MIS_ST_MNG_VETO 0x00000100 312 #define NGBE_MIS_ST_LAN0_ECC 0x00010000 313 #define NGBE_MIS_ST_LAN1_ECC 0x00020000 314 #define NGBE_MIS_ST_GPHY_IN_RST(_r) (0x00000200 << (_r)) 315 316 /* Bits in NGBE_MIS_SWSM register */ 317 #define NGBE_MIS_SWSM_SMBI 1 318 319 /* Bits in NGBE_MIS_RST_ST register */ 320 #define NGBE_MIS_RST_ST_RST_INIT 0x0000ff00 321 322 #define NGBE_MIS_RST_ST_RST_INI_SHIFT 8 323 #define NGBE_MIS_RST_ST_DEV_RST_ST_MASK 0x00180000 324 325 /* Bits in NGBE_SPI_STATUS register */ 326 #define NGBE_SPI_STATUS_FLASH_BYPASS 0x80000000 327 328 /* Bits in NGBE_SPI_ILDR_STATUS register */ 329 #define NGBE_SPI_ILDR_STATUS_PERST 0x00000001 330 #define NGBE_SPI_ILDR_STATUS_PWRRST 0x00000002 331 #define NGBE_SPI_ILDR_STATUS_SW_RESET 0x00000800 332 333 /* Bits in NGBE_TS_EN register */ 334 #define NGBE_TS_EN_ENA 0x00000001 335 336 /* Bits in NGBE_TS_INT_EN register */ 337 #define NGBE_TS_INT_EN_ALARM_INT_EN 0x00000001 338 #define NGBE_TS_INT_EN_DALARM_INT_EN 0x00000002 339 340 /* Bits in NGBE_TS_ALARM_ST register */ 341 #define NGBE_TS_ALARM_ST_DALARM 0x00000002 342 #define NGBE_TS_ALARM_ST_ALARM 0x00000001 343 344 /* Bits in NGBE_MAC_TX_CFG register */ 345 #define NGBE_MAC_TX_CFG_TE 0x00000001 346 #define NGBE_MAC_TX_CFG_SPEED_MASK 0x60000000 347 #define NGBE_MAC_TX_CFG_SPEED_1G 0x60000000 348 349 /* Bits in NGBE_MAC_RX_CFG register */ 350 #define NGBE_MAC_RX_CFG_RE 0x00000001 351 #define NGBE_MAC_RX_CFG_JE 0x00000100 352 353 /* Bits in NGBE_MAC_PKT_FLT register */ 354 #define NGBE_MAC_PKT_FLT_PR 0x00000001 355 #define NGBE_MAC_PKT_FLT_RA 0x80000000 356 357 /* Bits in NGBE_MAC_RX_FLOW_CTRL register */ 358 #define NGBE_MAC_RX_FLOW_CTRL_RFE 0x00000001 359 360 /* Bits in NGBE_MMC_CONTROL register */ 361 #define NGBE_MMC_CONTROL_RSTONRD 0x4 362 #define NGBE_MMC_CONTROL_UP 0x700 363 364 /* Bits in NGBE_CFG_PORT_CTL register */ 365 #define NGBE_CFG_PORT_CTL_DRV_LOAD 0x00000008 366 #define NGBE_CFG_PORT_CTL_PFRSTD 0x00004000 367 368 /* Bits in NGBE_CFG_PORT_ST register */ 369 #define NGBE_CFG_PORT_ST_LAN_ID(_r) ((0x00000300 & (_r)) >> 8) 370 371 /* Bits in NGBE_PSR_CTL register */ 372 #define NGBE_PSR_CTL_MO 0x00000060 373 #define NGBE_PSR_CTL_MFE 0x00000080 374 #define NGBE_PSR_CTL_MPE 0x00000100 375 #define NGBE_PSR_CTL_UPE 0x00000200 376 #define NGBE_PSR_CTL_BAM 0x00000400 377 #define NGBE_PSR_CTL_PCSD 0x00002000 378 #define NGBE_PSR_CTL_SW_EN 0x00040000 379 380 #define NGBE_PSR_CTL_MO_SHIFT 5 381 382 /* Bits in NGBE_PSR_VLAN_CTL register */ 383 #define NGBE_PSR_VLAN_CTL_CFIEN 0x20000000 384 #define NGBE_PSR_VLAN_CTL_VFE 0x40000000 385 386 /* Bits in NGBE_PSR_MAC_SWC_AD_H register */ 387 #define NGBE_PSR_MAC_SWC_AD_H_AV 0x80000000 388 389 #define NGBE_PSR_MAC_SWC_AD_H_AD(v) (((v) & 0xffff)) 390 #define NGBE_PSR_MAC_SWC_AD_H_ADTYPE(v) (((v) & 0x1) << 30) 391 392 /* Bits in NGBE_RSEC_CTL register */ 393 #define NGBE_RSEC_CTL_RX_DIS 0x00000002 394 #define NGBE_RSEC_CTL_CRC_STRIP 0x00000004 395 396 /* Bits in NGBE_RSEC_ST register */ 397 #define NGBE_RSEC_ST_RSEC_RDY 0x00000001 398 399 /* Bits in NGBE_TDM_CTL register */ 400 #define NGBE_TDM_CTL_TE 0x1 401 402 /* Bits in NGBE_TDM_PB_THRE register */ 403 #define NGBE_TXPKT_SIZE_MAX 0xa 404 405 /* Bits in NGBE_RDB_PB_CTL register */ 406 #define NGBE_RDB_PB_CTL_PBEN 0x80000000 407 408 #define NGBE_RDB_PB_SZ_SHIFT 10 409 410 /* Bits in NGBE_RDB_RFCC register */ 411 #define NGBE_RDB_RFCC_RFCE_802_3X 0x00000008 412 413 /* Bits in RFCL register */ 414 #define NGBE_RDB_RFCL_XONE 0x80000000 415 416 /* Bits in RFCH register */ 417 #define NGBE_RDB_RFCH_XOFFE 0x80000000 418 419 /* Bits in NGBE_RDB_PL_CFG register */ 420 #define NGBE_RDB_PL_CFG_L4HDR 0x2 421 #define NGBE_RDB_PL_CFG_L3HDR 0x4 422 #define NGBE_RDB_PL_CFG_L2HDR 0x8 423 #define NGBE_RDB_PL_CFG_TUN_TUNHDR 0x10 424 #define NGBE_RDB_PL_CFG_TUN_OUTER_L2HDR 0x20 425 426 /* Bits in NGBE_RDB_RA_CTL register */ 427 #define NGBE_RDB_RA_CTL_RSS_EN 0x00000004 428 #define NGBE_RDB_RA_CTL_RSS_IPV4_TCP 0x00010000 429 #define NGBE_RDB_RA_CTL_RSS_IPV4 0x00020000 430 #define NGBE_RDB_RA_CTL_RSS_IPV6 0x00100000 431 #define NGBE_RDB_RA_CTL_RSS_IPV6_TCP 0x00200000 432 433 /* Bits in NGBE_TDB_PB register */ 434 #define NGBE_TDB_PB_SZ_MAX 0x00005000 435 436 /* NGBE_MNG_SWFW_SYNC definitions */ 437 #define NGBE_MNG_SWFW_SYNC_SW_PHY 0x0001 438 #define NGBE_MNG_SWFW_SYNC_SW_MB 0x0004 439 440 /* Bits in NGBE_MNG_MBOX_CTL register */ 441 #define NGBE_MNG_MBOX_CTL_SWRDY 0x1 442 #define NGBE_MNG_MBOX_CTL_FWRDY 0x4 443 444 #define NGBE_CHECKSUM_CAP_ST_PASS 0x80658383 445 #define NGBE_CHECKSUM_CAP_ST_FAIL 0x70657376 446 447 #define NGBE_CALSUM_COMMAND 0xe9 448 449 #define RGMII_FPGA 0x0080 450 #define OEM_MASK 0x00ff 451 452 /* PHY register definitions */ 453 #define NGBE_MDIO_AUTO_NEG_STATUS 0x1a 454 #define NGBE_MDIO_AUTO_NEG_LSC 0x1d 455 456 /* Internal PHY control */ 457 #define NGBE_INTERNAL_PHY_PAGE_OFFSET 0xa43 458 #define NGBE_INTERNAL_PHY_PAGE_SELECT_OFFSET 31 459 #define NGBE_INTERNAL_PHY_ID 0x000732 460 461 #define NGBE_INTPHY_INT_ANC 0x0008 462 #define NGBE_INTPHY_INT_LSC 0x0010 463 464 /* PHY mdi standard config */ 465 #define NGBE_MDI_PHY_ID1_OFFSET 2 466 #define NGBE_MDI_PHY_ID2_OFFSET 3 467 #define NGBE_MDI_PHY_ID_MASK 0xfffffc00 468 #define NGBE_MDI_PHY_SPEED_SELECT1 0x0040 469 #define NGBE_MDI_PHY_DUPLEX 0x0100 470 #define NGBE_MDI_PHY_RESTART_AN 0x0200 471 #define NGBE_MDI_PHY_ANE 0x1000 472 #define NGBE_MDI_PHY_SPEED_SELECT0 0x2000 473 #define NGBE_MDI_PHY_RESET 0x8000 474 475 #define NGBE_PHY_RST_WAIT_PERIOD 50 476 477 #define NGBE_SR_AN_MMD_ADV_REG1_PAUSE_SYM 0x400 478 #define NGBE_SR_AN_MMD_ADV_REG1_PAUSE_ASM 0x800 479 480 #define SPI_CMD_READ_DWORD 1 481 #define SPI_CLK_DIV 3 482 #define SPI_CLK_DIV_OFFSET 25 483 #define SPI_CLK_CMD_OFFSET 28 484 #define SPI_TIME_OUT_VALUE 10000 485 486 /* PCI bus info */ 487 #define NGBE_PCI_LINK_STATUS 0xb2 488 489 #define NGBE_PCI_LINK_WIDTH 0x3f0 490 #define NGBE_PCI_LINK_WIDTH_1 0x10 491 #define NGBE_PCI_LINK_WIDTH_2 0x20 492 #define NGBE_PCI_LINK_WIDTH_4 0x40 493 #define NGBE_PCI_LINK_WIDTH_8 0x80 494 495 #define NGBE_PCI_LINK_SPEED 0xf 496 #define NGBE_PCI_LINK_SPEED_2500 0x1 497 #define NGBE_PCI_LINK_SPEED_5000 0x2 498 #define NGBE_PCI_LINK_SPEED_8000 0x3 499 500 /* Number of 100 microseconds we wait for PCI Express master disable */ 501 #define NGBE_PCI_MASTER_DISABLE_TIMEOUT 800 502 503 /* Check whether address is multicast. This is little-endian specific check. */ 504 #define NGBE_IS_MULTICAST(Address) \ 505 (int)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) 506 507 /* Check whether an address is broadcast. */ 508 #define NGBE_IS_BROADCAST(Address) \ 509 ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && \ 510 (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) 511 512 /* Link speed */ 513 #define NGBE_LINK_SPEED_UNKNOWN 0 514 #define NGBE_LINK_SPEED_100_FULL 1 515 #define NGBE_LINK_SPEED_1GB_FULL 2 516 #define NGBE_LINK_SPEED_10_FULL 8 517 #define NGBE_LINK_SPEED_AUTONEG \ 518 (NGBE_LINK_SPEED_100_FULL | NGBE_LINK_SPEED_1GB_FULL | \ 519 NGBE_LINK_SPEED_10_FULL) 520 521 522 #define NGBE_HI_MAX_BLOCK_BYTE_LENGTH 256 523 #define NGBE_HI_COMMAND_TIMEOUT 5000 524 525 /* CEM support */ 526 #define FW_CEM_CMD_RESERVED 0x0 527 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 528 #define FW_CEM_HDR_LEN 0x4 529 530 #define FW_CEM_CMD_DRIVER_INFO 0xdd 531 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 532 533 #define FW_EEPROM_CHECK_STATUS 0xe9 534 #define FW_PHY_LED_CONF 0xf1 535 #define FW_DEFAULT_CHECKSUM 0xff 536 537 #define FW_CEM_MAX_RETRIES 3 538 539 #define NGBE_MAX_SCATTER 32 540 #define NGBE_TSO_SIZE 32767 541 #define NGBE_MAX_RX_DESC_POLL 10 542 543 /* Packet buffer allocation strategies */ 544 #define PBA_STRATEGY_EQUAL 0 545 #define PBA_STRATEGY_WEIGHTED 1 546 547 /* BitTimes (BT) conversion */ 548 #define NGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 549 #define NGBE_B2BT(BT) (BT * 8) 550 551 /* Calculate Delay to respond to PFC */ 552 #define NGBE_PFC_D 672 553 554 /* Calculate Cable Delay */ 555 #define NGBE_CABLE_DC 5556 556 557 /* Calculate Interface Delay */ 558 #define NGBE_PHY_D 12800 559 #define NGBE_MAC_D 4096 560 #define NGBE_XAUI_D (2 * 1024) 561 562 #define NGBE_ID (NGBE_MAC_D + NGBE_XAUI_D + NGBE_PHY_D) 563 564 /* Calculate Delay incurred from higher layer */ 565 #define NGBE_HD 6144 566 567 /* Calculate PCI Bus delay for low thresholds */ 568 #define NGBE_PCI_DELAY 10000 569 570 /* Calculate delay value in bit times */ 571 #define NGBE_DV(_max_frame_link, _max_frame_tc) \ 572 ((36 * (NGBE_B2BT(_max_frame_link) + NGBE_PFC_D + \ 573 (2 * NGBE_CABLE_DC) + (2 * NGBE_ID) + NGBE_HD) / 25 + 1) + \ 574 2 * NGBE_B2BT(_max_frame_tc)) 575 576 /* Calculate low threshold delay values */ 577 #define NGBE_LOW_DV_X540(_max_frame_tc) \ 578 (2 * NGBE_B2BT(_max_frame_tc) + (36 * NGBE_PCI_DELAY / 25) + 1) 579 580 #define NGBE_LOW_DV(_max_frame_tc) \ 581 (2 * NGBE_LOW_DV_X540(_max_frame_tc)) 582 583 /* Compatibility glue. */ 584 #define msec_delay(x) DELAY(1000 * (x)) 585 #define roundup2(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 586 #define le32_to_cpup(x) (le32toh(*(const uint32_t *)(x))) 587 #define le32_to_cpus(x) \ 588 do { *((uint32_t *)(x)) = le32_to_cpup((x)); } while (0) 589 590 enum ngbe_media_type { 591 ngbe_media_type_unknown = 0, 592 ngbe_media_type_fiber, 593 ngbe_media_type_copper, 594 ngbe_media_type_backplane, 595 ngbe_media_type_virtual 596 }; 597 598 /* Flow Control Settings */ 599 enum ngbe_fc_mode { 600 ngbe_fc_none = 0, 601 ngbe_fc_rx_pause, 602 ngbe_fc_tx_pause, 603 ngbe_fc_full, 604 ngbe_fc_default 605 }; 606 607 enum ngbe_eeprom_type { 608 ngbe_eeprom_uninitialized = 0, 609 ngbe_eeprom_spi, 610 ngbe_flash, 611 ngbe_eeprom_none /* No NVM support */ 612 }; 613 614 enum ngbe_phy_type { 615 ngbe_phy_unknown = 0, 616 ngbe_phy_none, 617 ngbe_phy_internal, 618 }; 619 620 enum ngbe_reset_type { 621 NGBE_LAN_RESET = 0, 622 NGBE_SW_RESET, 623 NGBE_GLOBAL_RESET 624 }; 625 626 enum ngbe_isb_idx { 627 NGBE_ISB_HEADER, 628 NGBE_ISB_MISC, 629 NGBE_ISB_VEC0, 630 NGBE_ISB_VEC1, 631 NGBE_ISB_MAX 632 }; 633 634 /* PCI bus types */ 635 enum ngbe_bus_type { 636 ngbe_bus_type_unknown = 0, 637 ngbe_bus_type_pci, 638 ngbe_bus_type_pcix, 639 ngbe_bus_type_pci_express, 640 ngbe_bus_type_internal, 641 ngbe_bus_type_reserved 642 }; 643 644 /* PCI bus speeds */ 645 enum ngbe_bus_speed { 646 ngbe_bus_speed_unknown = 0, 647 ngbe_bus_speed_33 = 33, 648 ngbe_bus_speed_66 = 66, 649 ngbe_bus_speed_100 = 100, 650 ngbe_bus_speed_120 = 120, 651 ngbe_bus_speed_133 = 133, 652 ngbe_bus_speed_2500 = 2500, 653 ngbe_bus_speed_5000 = 5000, 654 ngbe_bus_speed_8000 = 8000, 655 ngbe_bus_speed_reserved 656 }; 657 658 /* PCI bus widths */ 659 enum ngbe_bus_width { 660 ngbe_bus_width_unknown = 0, 661 ngbe_bus_width_pcie_x1 = 1, 662 ngbe_bus_width_pcie_x2 = 2, 663 ngbe_bus_width_pcie_x4 = 4, 664 ngbe_bus_width_pcie_x8 = 8, 665 ngbe_bus_width_32 = 32, 666 ngbe_bus_width_64 = 64, 667 ngbe_bus_width_reserved 668 }; 669 670 /* Host interface command structures */ 671 struct ngbe_hic_hdr { 672 uint8_t cmd; 673 uint8_t buf_len; 674 union { 675 uint8_t cmd_resv; 676 uint8_t ret_status; 677 } cmd_or_resp; 678 uint8_t checksum; 679 }; 680 681 struct ngbe_hic_hdr2_req { 682 uint8_t cmd; 683 uint8_t buf_lenh; 684 uint8_t buf_lenl; 685 uint8_t checksum; 686 }; 687 688 struct ngbe_hic_hdr2_rsp { 689 uint8_t cmd; 690 uint8_t buf_lenl; 691 uint8_t buf_lenh_status; 692 uint8_t checksum; 693 }; 694 695 union ngbe_hic_hdr2 { 696 struct ngbe_hic_hdr2_req req; 697 struct ngbe_hic_hdr2_rsp rsp; 698 }; 699 700 struct ngbe_hic_drv_info { 701 struct ngbe_hic_hdr hdr; 702 uint8_t port_num; 703 uint8_t ver_sub; 704 uint8_t ver_build; 705 uint8_t ver_min; 706 uint8_t ver_maj; 707 uint8_t pad; 708 uint16_t pad2; 709 }; 710 711 struct ngbe_hic_read_shadow_ram { 712 union ngbe_hic_hdr2 hdr; 713 uint32_t address; 714 uint16_t length; 715 uint16_t pad2; 716 uint16_t data; 717 uint16_t pad3; 718 }; 719 720 struct ngbe_osdep { 721 bus_dma_tag_t os_dmat; 722 bus_space_tag_t os_memt; 723 bus_space_handle_t os_memh; 724 725 bus_size_t os_memsize; 726 bus_addr_t os_membase; 727 728 void *os_sc; 729 struct pci_attach_args os_pa; 730 }; 731 732 /* Forward declaration. */ 733 struct ngbe_hw; 734 struct ngbe_softc; 735 736 /* Iterator type for walking multicast address lists */ 737 typedef uint8_t * (*ngbe_mc_addr_itr) (struct ngbe_hw *, uint8_t **, \ 738 uint32_t *); 739 740 struct ngbe_eeprom_operations { 741 void (*init_params)(struct ngbe_hw *); 742 int (*eeprom_chksum_cap_st)(struct ngbe_softc *, uint16_t, 743 uint32_t *); 744 int (*phy_led_oem_chk)(struct ngbe_softc *, uint32_t *); 745 }; 746 747 struct ngbe_mac_operations { 748 int (*init_hw)(struct ngbe_softc *); 749 int (*reset_hw)(struct ngbe_softc *); 750 int (*start_hw)(struct ngbe_softc *); 751 void (*clear_hw_cntrs)(struct ngbe_hw *); 752 enum ngbe_media_type (*get_media_type)(struct ngbe_hw *); 753 void (*get_mac_addr)(struct ngbe_hw *, uint8_t *); 754 int (*stop_adapter)(struct ngbe_softc *); 755 void (*get_bus_info)(struct ngbe_softc *); 756 void (*set_lan_id)(struct ngbe_hw *); 757 void (*enable_rx_dma)(struct ngbe_hw *, uint32_t); 758 void (*disable_sec_rx_path)(struct ngbe_hw *); 759 void (*enable_sec_rx_path)(struct ngbe_hw *); 760 int (*acquire_swfw_sync)(struct ngbe_softc *, 761 uint32_t); 762 void (*release_swfw_sync)(struct ngbe_softc *, 763 uint32_t); 764 765 /* Link */ 766 int (*setup_link)(struct ngbe_softc *, uint32_t, 767 int); 768 int (*check_link)(struct ngbe_hw *, uint32_t *, 769 int *, int); 770 void (*get_link_capabilities)(struct ngbe_hw *, 771 uint32_t *, int *); 772 773 /* Packet Buffer manipulation */ 774 void (*setup_rxpba)(struct ngbe_hw *, int, uint32_t, 775 int); 776 777 /* RAR, Multicast, VLAN */ 778 int (*set_rar)(struct ngbe_softc *, uint32_t, 779 uint8_t *, uint64_t, uint32_t); 780 void (*init_rx_addrs)(struct ngbe_softc *); 781 void (*update_mc_addr_list)(struct ngbe_hw *, 782 uint8_t *, uint32_t, ngbe_mc_addr_itr, int); 783 784 void (*clear_vfta)(struct ngbe_hw *); 785 void (*init_uta_tables)(struct ngbe_hw *); 786 787 /* Flow Control */ 788 int (*fc_enable)(struct ngbe_softc *); 789 int (*setup_fc)(struct ngbe_softc *); 790 791 /* Manageability interface */ 792 int (*set_fw_drv_ver)(struct ngbe_softc *, uint8_t, 793 uint8_t, uint8_t, uint8_t); 794 void (*init_thermal_sensor_thresh)(struct ngbe_hw *); 795 void (*disable_rx)(struct ngbe_hw *); 796 void (*enable_rx)(struct ngbe_hw *); 797 }; 798 799 struct ngbe_phy_operations { 800 int (*identify)(struct ngbe_softc *); 801 int (*init)(struct ngbe_softc *); 802 int (*reset)(struct ngbe_softc *); 803 int (*read_reg)(struct ngbe_hw *, uint32_t, uint32_t, 804 uint16_t *); 805 int (*write_reg)(struct ngbe_hw *, uint32_t, uint32_t, 806 uint16_t); 807 int (*setup_link)(struct ngbe_softc *, uint32_t, int); 808 void (*phy_led_ctrl)(struct ngbe_softc *); 809 int (*check_overtemp)(struct ngbe_hw *); 810 void (*check_event)(struct ngbe_softc *); 811 void (*get_adv_pause)(struct ngbe_hw *, uint8_t *); 812 void (*get_lp_adv_pause)(struct ngbe_hw *, uint8_t *); 813 int (*set_adv_pause)(struct ngbe_hw *, uint16_t); 814 int (*setup_once)(struct ngbe_softc *); 815 }; 816 817 struct ngbe_addr_filter_info { 818 uint32_t num_mc_addrs; 819 uint32_t rar_used_count; 820 uint32_t mta_in_use; 821 uint32_t overflow_promisc; 822 int user_set_promisc; 823 }; 824 825 /* Bus parameters */ 826 struct ngbe_bus_info { 827 enum ngbe_bus_speed speed; 828 enum ngbe_bus_width width; 829 enum ngbe_bus_type type; 830 uint16_t lan_id; 831 }; 832 833 struct ngbe_eeprom_info { 834 struct ngbe_eeprom_operations ops; 835 enum ngbe_eeprom_type type; 836 uint16_t sw_region_offset; 837 }; 838 839 struct ngbe_mac_info { 840 struct ngbe_mac_operations ops; 841 uint8_t addr[ETHER_ADDR_LEN]; 842 uint8_t perm_addr[ETHER_ADDR_LEN]; 843 uint32_t mta_shadow[NGBE_MAX_MTA]; 844 int mc_filter_type; 845 uint32_t mcft_size; 846 uint32_t vft_shadow[NGBE_MAX_VFTA_ENTRIES]; 847 uint32_t vft_size; 848 uint32_t num_rar_entries; 849 uint32_t rx_pb_size; 850 uint32_t max_tx_queues; 851 uint32_t max_rx_queues; 852 int autotry_restart; 853 int set_lben; 854 int autoneg; 855 }; 856 857 /* Flow control parameters */ 858 struct ngbe_fc_info { 859 uint32_t high_water; 860 uint32_t low_water; 861 uint16_t pause_time; 862 int strict_ieee; 863 int disable_fc_autoneg; 864 int fc_was_autonegged; 865 enum ngbe_fc_mode current_mode; 866 enum ngbe_fc_mode requested_mode; 867 }; 868 869 struct ngbe_phy_info { 870 struct ngbe_phy_operations ops; 871 enum ngbe_phy_type type; 872 uint32_t addr; 873 uint32_t id; 874 uint32_t phy_semaphore_mask; 875 enum ngbe_media_type media_type; 876 uint32_t autoneg_advertised; 877 int reset_if_overtemp; 878 uint32_t force_speed; 879 }; 880 881 struct ngbe_hw { 882 void *back; 883 struct ngbe_mac_info mac; 884 struct ngbe_addr_filter_info addr_ctrl; 885 struct ngbe_fc_info fc; 886 struct ngbe_phy_info phy; 887 struct ngbe_eeprom_info eeprom; 888 struct ngbe_bus_info bus; 889 uint32_t subsystem_device_id; 890 int adapter_stopped; 891 enum ngbe_reset_type reset_type; 892 int force_full_reset; 893 }; 894 895 /* Transmit Descriptor */ 896 union ngbe_tx_desc { 897 struct { 898 uint64_t buffer_addr; 899 uint32_t cmd_type_len; 900 uint32_t olinfo_status; 901 } read; 902 struct { 903 uint64_t rsvd; 904 uint32_t nxtseq_seed; 905 uint32_t status; 906 } wb; 907 }; 908 #define NGBE_TXD_DTYP_DATA 0x00000000 909 #define NGBE_TXD_DTYP_CTXT 0x00100000 910 #define NGBE_TXD_STAT_DD 0x00000001 911 #define NGBE_TXD_L4CS 0x00000200 912 #define NGBE_TXD_IIPCS 0x00000400 913 #define NGBE_TXD_EOP 0x01000000 914 #define NGBE_TXD_IFCS 0x02000000 915 #define NGBE_TXD_RS 0x08000000 916 #define NGBE_TXD_VLE 0x40000000 917 #define NGBE_TXD_MACLEN_SHIFT 9 918 #define NGBE_TXD_PAYLEN_SHIFT 13 919 #define NGBE_TXD_VLAN_SHIFT 16 920 921 #define NGBE_PTYPE_PKT_IPV6 0x08 922 #define NGBE_PTYPE_PKT_IP 0x20 923 #define NGBE_PTYPE_TYP_IP 0x02 924 #define NGBE_PTYPE_TYP_UDP 0x03 925 #define NGBE_PTYPE_TYP_TCP 0x04 926 927 /* Receive Descriptor */ 928 union ngbe_rx_desc { 929 struct { 930 uint64_t pkt_addr; 931 uint64_t hdr_addr; 932 } read; 933 struct { 934 struct { 935 union { 936 uint32_t data; 937 struct { 938 uint16_t pkt_info; 939 uint16_t hdr_info; 940 } hs_rss; 941 } lo_dword; 942 union { 943 uint32_t rss; 944 struct { 945 uint16_t ip_id; 946 uint16_t csum; 947 } csum_ip; 948 } hi_dword; 949 } lower; 950 struct { 951 uint32_t status_error; 952 uint16_t length; 953 uint16_t vlan; 954 } upper; 955 } wb; 956 }; 957 #define NGBE_RXD_STAT_DD 0x00000001 958 #define NGBE_RXD_STAT_EOP 0x00000002 959 #define NGBE_RXD_STAT_VP 0x00000020 960 #define NGBE_RXD_STAT_L4CS 0x00000080 961 #define NGBE_RXD_STAT_IPCS 0x00000100 962 #define NGBE_RXD_ERR_RXE 0x20000000 963 #define NGBE_RXD_ERR_TCPE 0x40000000 964 #define NGBE_RXD_ERR_IPE 0x80000000 965 #define NGBE_RXD_RSSTYPE_MASK 0x0000000f 966 967 /* RSS hash results */ 968 #define NGBE_RXD_RSSTYPE_NONE 0x00000000 969 970 /* Context descriptor */ 971 struct ngbe_tx_context_desc { 972 uint32_t vlan_macip_lens; 973 uint32_t seqnum_seed; 974 uint32_t type_tucmd_mlhl; 975 uint32_t mss_l4len_idx; 976 }; 977 978 struct ngbe_tx_buf { 979 uint32_t eop_index; 980 struct mbuf *m_head; 981 bus_dmamap_t map; 982 }; 983 984 struct ngbe_rx_buf { 985 struct mbuf *buf; 986 struct mbuf *fmp; 987 bus_dmamap_t map; 988 }; 989 990 struct ngbe_dma_alloc { 991 caddr_t dma_vaddr; 992 bus_dma_tag_t dma_tag; 993 bus_dmamap_t dma_map; 994 bus_dma_segment_t dma_seg; 995 bus_size_t dma_size; 996 int dma_nseg; 997 }; 998 999 struct tx_ring { 1000 struct ngbe_softc *sc; 1001 struct ifqueue *ifq; 1002 uint32_t me; 1003 uint32_t watchdog_timer; 1004 union ngbe_tx_desc *tx_base; 1005 struct ngbe_tx_buf *tx_buffers; 1006 struct ngbe_dma_alloc txdma; 1007 uint32_t next_avail_desc; 1008 uint32_t next_to_clean; 1009 bus_dma_tag_t txtag; 1010 }; 1011 1012 struct rx_ring { 1013 struct ngbe_softc *sc; 1014 struct ifiqueue *ifiq; 1015 uint32_t me; 1016 union ngbe_rx_desc *rx_base; 1017 struct ngbe_rx_buf *rx_buffers; 1018 struct ngbe_dma_alloc rxdma; 1019 uint32_t last_desc_filled; 1020 uint32_t next_to_check; 1021 struct timeout rx_refill; 1022 struct if_rxring rx_ring; 1023 }; 1024 1025 struct ngbe_queue { 1026 struct ngbe_softc *sc; 1027 uint32_t msix; 1028 uint32_t eims; 1029 char name[16]; 1030 pci_intr_handle_t ih; 1031 void *tag; 1032 struct tx_ring *txr; 1033 struct rx_ring *rxr; 1034 }; 1035 1036 struct ngbe_softc { 1037 struct device sc_dev; 1038 struct arpcom sc_ac; 1039 struct ifmedia sc_media; 1040 struct intrmap *sc_intrmap; 1041 1042 struct ngbe_osdep osdep; 1043 struct ngbe_hw hw; 1044 1045 void *tag; 1046 1047 uint32_t led_conf; 1048 uint32_t gphy_efuse[2]; 1049 uint32_t link_speed; 1050 uint32_t linkvec; 1051 int link_up; 1052 1053 int num_tx_desc; 1054 int num_rx_desc; 1055 1056 struct ngbe_dma_alloc isbdma; 1057 uint32_t *isb_base; 1058 1059 unsigned int sc_nqueues; 1060 struct ngbe_queue *queues; 1061 1062 struct tx_ring *tx_rings; 1063 struct rx_ring *rx_rings; 1064 1065 /* Multicast array memory */ 1066 uint8_t *mta; 1067 }; 1068 1069 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 1070 1071 #define NGBE_FAILED_READ_REG 0xffffffff 1072 1073 /* Register READ/WRITE macros */ 1074 #define NGBE_WRITE_FLUSH(a) \ 1075 NGBE_READ_REG(a, NGBE_MIS_PWR) 1076 #define NGBE_READ_REG(a, reg) \ 1077 bus_space_read_4(((struct ngbe_osdep *)(a)->back)->os_memt, \ 1078 ((struct ngbe_osdep *)(a)->back)->os_memh, reg) 1079 #define NGBE_WRITE_REG(a, reg, value) \ 1080 bus_space_write_4(((struct ngbe_osdep *)(a)->back)->os_memt, \ 1081 ((struct ngbe_osdep *)(a)->back)->os_memh, reg, value) 1082 #define NGBE_READ_REG_ARRAY(a, reg, offset) \ 1083 bus_space_read_4(((struct ngbe_osdep *)(a)->back)->os_memt, \ 1084 ((struct ngbe_osdep *)(a)->back)->os_memh, (reg + ((offset) << 2))) 1085 #define NGBE_WRITE_REG_ARRAY(a, reg, offset, value) \ 1086 bus_space_write_4(((struct ngbe_osdep *)(a)->back)->os_memt, \ 1087 ((struct ngbe_osdep *)(a)->back)->os_memh, \ 1088 (reg + ((offset) << 2)), value) 1089