xref: /linux/drivers/comedi/drivers/ni_tio.h (revision df0e68c1)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Header file for NI general purpose counter support code (ni_tio.c)
4  *
5  * COMEDI - Linux Control and Measurement Device Interface
6  */
7 
8 #ifndef _COMEDI_NI_TIO_H
9 #define _COMEDI_NI_TIO_H
10 
11 #include <linux/comedi/comedidev.h>
12 
13 enum ni_gpct_register {
14 	NITIO_G0_AUTO_INC,
15 	NITIO_G1_AUTO_INC,
16 	NITIO_G2_AUTO_INC,
17 	NITIO_G3_AUTO_INC,
18 	NITIO_G0_CMD,
19 	NITIO_G1_CMD,
20 	NITIO_G2_CMD,
21 	NITIO_G3_CMD,
22 	NITIO_G0_HW_SAVE,
23 	NITIO_G1_HW_SAVE,
24 	NITIO_G2_HW_SAVE,
25 	NITIO_G3_HW_SAVE,
26 	NITIO_G0_SW_SAVE,
27 	NITIO_G1_SW_SAVE,
28 	NITIO_G2_SW_SAVE,
29 	NITIO_G3_SW_SAVE,
30 	NITIO_G0_MODE,
31 	NITIO_G1_MODE,
32 	NITIO_G2_MODE,
33 	NITIO_G3_MODE,
34 	NITIO_G0_LOADA,
35 	NITIO_G1_LOADA,
36 	NITIO_G2_LOADA,
37 	NITIO_G3_LOADA,
38 	NITIO_G0_LOADB,
39 	NITIO_G1_LOADB,
40 	NITIO_G2_LOADB,
41 	NITIO_G3_LOADB,
42 	NITIO_G0_INPUT_SEL,
43 	NITIO_G1_INPUT_SEL,
44 	NITIO_G2_INPUT_SEL,
45 	NITIO_G3_INPUT_SEL,
46 	NITIO_G0_CNT_MODE,
47 	NITIO_G1_CNT_MODE,
48 	NITIO_G2_CNT_MODE,
49 	NITIO_G3_CNT_MODE,
50 	NITIO_G0_GATE2,
51 	NITIO_G1_GATE2,
52 	NITIO_G2_GATE2,
53 	NITIO_G3_GATE2,
54 	NITIO_G01_STATUS,
55 	NITIO_G23_STATUS,
56 	NITIO_G01_RESET,
57 	NITIO_G23_RESET,
58 	NITIO_G01_STATUS1,
59 	NITIO_G23_STATUS1,
60 	NITIO_G01_STATUS2,
61 	NITIO_G23_STATUS2,
62 	NITIO_G0_DMA_CFG,
63 	NITIO_G1_DMA_CFG,
64 	NITIO_G2_DMA_CFG,
65 	NITIO_G3_DMA_CFG,
66 	NITIO_G0_DMA_STATUS,
67 	NITIO_G1_DMA_STATUS,
68 	NITIO_G2_DMA_STATUS,
69 	NITIO_G3_DMA_STATUS,
70 	NITIO_G0_ABZ,
71 	NITIO_G1_ABZ,
72 	NITIO_G0_INT_ACK,
73 	NITIO_G1_INT_ACK,
74 	NITIO_G2_INT_ACK,
75 	NITIO_G3_INT_ACK,
76 	NITIO_G0_STATUS,
77 	NITIO_G1_STATUS,
78 	NITIO_G2_STATUS,
79 	NITIO_G3_STATUS,
80 	NITIO_G0_INT_ENA,
81 	NITIO_G1_INT_ENA,
82 	NITIO_G2_INT_ENA,
83 	NITIO_G3_INT_ENA,
84 	NITIO_NUM_REGS,
85 };
86 
87 enum ni_gpct_variant {
88 	ni_gpct_variant_e_series,
89 	ni_gpct_variant_m_series,
90 	ni_gpct_variant_660x
91 };
92 
93 struct ni_gpct {
94 	struct ni_gpct_device *counter_dev;
95 	unsigned int counter_index;
96 	unsigned int chip_index;
97 	u64 clock_period_ps;	/* clock period in picoseconds */
98 	struct mite_channel *mite_chan;
99 	spinlock_t lock;	/* protects 'mite_chan' */
100 };
101 
102 struct ni_gpct_device {
103 	struct comedi_device *dev;
104 	void (*write)(struct ni_gpct *counter, unsigned int value,
105 		      enum ni_gpct_register);
106 	unsigned int (*read)(struct ni_gpct *counter, enum ni_gpct_register);
107 	enum ni_gpct_variant variant;
108 	struct ni_gpct *counters;
109 	unsigned int num_counters;
110 	unsigned int num_chips;
111 	unsigned int (*regs)[NITIO_NUM_REGS]; /* [num_chips][NITIO_NUM_REGS] */
112 	spinlock_t regs_lock;		/* protects 'regs' */
113 	const struct ni_route_tables *routing_tables; /* link to routes */
114 };
115 
116 struct ni_gpct_device *
117 ni_gpct_device_construct(struct comedi_device *dev,
118 			 void (*write)(struct ni_gpct *counter,
119 				       unsigned int value,
120 				       enum ni_gpct_register),
121 			 unsigned int (*read)(struct ni_gpct *counter,
122 					      enum ni_gpct_register),
123 			 enum ni_gpct_variant,
124 			 unsigned int num_counters,
125 			 unsigned int counters_per_chip,
126 			 const struct ni_route_tables *routing_tables);
127 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev);
128 void ni_tio_init_counter(struct ni_gpct *counter);
129 int ni_tio_insn_read(struct comedi_device *dev, struct comedi_subdevice *s,
130 		     struct comedi_insn *insn, unsigned int *data);
131 int ni_tio_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
132 		       struct comedi_insn *insn, unsigned int *data);
133 int ni_tio_insn_write(struct comedi_device *dev, struct comedi_subdevice *s,
134 		      struct comedi_insn *insn, unsigned int *data);
135 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
136 int ni_tio_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
137 		   struct comedi_cmd *cmd);
138 int ni_tio_cancel(struct ni_gpct *counter);
139 void ni_tio_handle_interrupt(struct ni_gpct *counter,
140 			     struct comedi_subdevice *s);
141 void ni_tio_set_mite_channel(struct ni_gpct *counter,
142 			     struct mite_channel *mite_chan);
143 void ni_tio_acknowledge(struct ni_gpct *counter);
144 
145 /*
146  * Retrieves the register value of the current source of the output selector for
147  * the given destination.
148  *
149  * If the terminal for the destination is not already configured as an output,
150  * this function returns -EINVAL as error.
151  *
152  * Return: the register value of the destination output selector;
153  *         -EINVAL if terminal is not configured for output.
154  */
155 int ni_tio_get_routing(struct ni_gpct_device *counter_dev,
156 		       unsigned int destination);
157 
158 /*
159  * Sets the register value of the selector MUX for the given destination.
160  * @counter_dev:Pointer to general counter device.
161  * @destination:Device-global identifier of route destination.
162  * @register_value:
163  *		The first several bits of this value should store the desired
164  *		value to write to the register.  All other bits are for
165  *		transmitting information that modify the mode of the particular
166  *		destination/gate.  These mode bits might include a bitwise or of
167  *		CR_INVERT and CR_EDGE.  Note that the calling function should
168  *		have already validated the correctness of this value.
169  */
170 int ni_tio_set_routing(struct ni_gpct_device *counter_dev,
171 		       unsigned int destination, unsigned int register_value);
172 
173 /*
174  * Sets the given destination MUX to its default value or disable it.
175  *
176  * Return: 0 if successful; -EINVAL if terminal is unknown.
177  */
178 int ni_tio_unset_routing(struct ni_gpct_device *counter_dev,
179 			 unsigned int destination);
180 
181 #endif /* _COMEDI_NI_TIO_H */
182