1 /*
2 * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_GPIO_H__
33 #define NRF_GPIO_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_gpio_hal GPIO HAL
43 * @{
44 * @ingroup nrf_gpio
45 * @brief Hardware access layer for managing the GPIO peripheral.
46 */
47
48 #if (GPIO_COUNT == 1)
49 #define NUMBER_OF_PINS (P0_PIN_NUM)
50 #define GPIO_REG_LIST {NRF_GPIO}
51 #elif (GPIO_COUNT == 2)
52 #define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
53 #define GPIO_REG_LIST {NRF_P0, NRF_P1}
54 #else
55 #error "Not supported."
56 #endif
57
58
59 /**
60 * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions.
61 */
62 #define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
63
64 /**
65 * @brief Pin direction definitions.
66 */
67 typedef enum
68 {
69 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
70 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
71 } nrf_gpio_pin_dir_t;
72
73 /**
74 * @brief Connection of input buffer.
75 */
76 typedef enum
77 {
78 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
79 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
80 } nrf_gpio_pin_input_t;
81
82 /**
83 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration.
84 */
85 typedef enum
86 {
87 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
88 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
89 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
90 } nrf_gpio_pin_pull_t;
91
92 /**
93 * @brief Enumerator used for selecting output drive mode.
94 */
95 typedef enum
96 {
97 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
98 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'.
99 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'.
100 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'.
101 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'.
102 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'.
103 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'.
104 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
105 } nrf_gpio_pin_drive_t;
106
107 /**
108 * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
109 */
110 typedef enum
111 {
112 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
113 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
114 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
115 } nrf_gpio_pin_sense_t;
116
117 /**
118 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
119 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
120 *
121 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
122 *
123 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
124 *
125 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
126 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
127 */
128 __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
129
130 /**
131 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
132 * This function can be used to configure pin range as simple input.
133 *
134 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
135 *
136 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
137 *
138 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
139 *
140 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
141 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
142 */
143 __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
144 uint32_t pin_range_end,
145 nrf_gpio_pin_pull_t pull_config);
146
147 /**
148 * @brief Pin configuration function.
149 *
150 * The main pin configuration function.
151 * This function allows to set any aspect in PIN_CNF register.
152 * @param pin_number Specifies the pin number.
153 * @param dir Pin direction.
154 * @param input Connect or disconnect the input buffer.
155 * @param pull Pull configuration.
156 * @param drive Drive configuration.
157 * @param sense Pin sensing mechanism.
158 */
159 __STATIC_INLINE void nrf_gpio_cfg(
160 uint32_t pin_number,
161 nrf_gpio_pin_dir_t dir,
162 nrf_gpio_pin_input_t input,
163 nrf_gpio_pin_pull_t pull,
164 nrf_gpio_pin_drive_t drive,
165 nrf_gpio_pin_sense_t sense);
166
167 /**
168 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
169 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
170 *
171 * @param pin_number Specifies the pin number.
172 *
173 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
174 */
175 __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
176
177 /**
178 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
179 * This function can be used to configure a pin as simple input.
180 *
181 * @param pin_number Specifies the pin number.
182 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
183 *
184 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
185 */
186 __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
187
188 /**
189 * @brief Function for resetting pin configuration to its default state.
190 *
191 * @param pin_number Specifies the pin number.
192 */
193 __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
194
195 /**
196 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
197 *
198 * @param pin_number Specifies the pin number.
199 *
200 */
201 __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
202
203 /**
204 * @brief Function for disconnecting input for the given GPIO.
205 *
206 * @param pin_number Specifies the pin number.
207 *
208 */
209 __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
210
211 /**
212 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
213 * This function can be used to configure pin range as simple input.
214 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
215 *
216 * @param pin_number Specifies the pin number.
217 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
218 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
219 */
220 __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
221 nrf_gpio_pin_pull_t pull_config,
222 nrf_gpio_pin_sense_t sense_config);
223
224 /**
225 * @brief Function for configuring sense level for the given GPIO.
226 *
227 * @param pin_number Specifies the pin number.
228 * @param sense_config Sense configuration.
229 *
230 */
231 __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
232
233 /**
234 * @brief Function for setting the direction for a GPIO pin.
235 *
236 * @param pin_number Specifies the pin number for which to set the direction.
237 *
238 * @param direction Specifies the direction.
239 */
240 __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
241
242 /**
243 * @brief Function for setting a GPIO pin.
244 *
245 * Note that the pin must be configured as an output for this function to have any effect.
246 *
247 * @param pin_number Specifies the pin number to set.
248 */
249 __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
250
251 /**
252 * @brief Function for clearing a GPIO pin.
253 *
254 * Note that the pin must be configured as an output for this
255 * function to have any effect.
256 *
257 * @param pin_number Specifies the pin number to clear.
258 */
259 __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
260
261 /**
262 * @brief Function for toggling a GPIO pin.
263 *
264 * Note that the pin must be configured as an output for this
265 * function to have any effect.
266 *
267 * @param pin_number Specifies the pin number to toggle.
268 */
269 __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
270
271 /**
272 * @brief Function for writing a value to a GPIO pin.
273 *
274 * Note that the pin must be configured as an output for this
275 * function to have any effect.
276 *
277 * @param pin_number Specifies the pin number to write.
278 *
279 * @param value Specifies the value to be written to the pin.
280 * @arg 0 Clears the pin.
281 * @arg >=1 Sets the pin.
282 */
283 __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
284
285 /**
286 * @brief Function for reading the input level of a GPIO pin.
287 *
288 * Note that the pin must have input connected for the value
289 * returned from this function to be valid.
290 *
291 * @param pin_number Specifies the pin number to read.
292 *
293 * @return 0 if the pin input level is low. Positive value if the pin is high.
294 */
295 __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
296
297 /**
298 * @brief Function for reading the output level of a GPIO pin.
299 *
300 * @param pin_number Specifies the pin number to read.
301 *
302 * @return 0 if the pin output level is low. Positive value if pin output is high.
303 */
304 __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
305
306 /**
307 * @brief Function for reading the sense configuration of a GPIO pin.
308 *
309 * @param pin_number Specifies the pin number to read.
310 *
311 * @retval Sense configuration.
312 */
313 __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
314
315 /**
316 * @brief Function for reading the direction configuration of a GPIO pin.
317 *
318 * @param pin_number Specifies the pin number to read.
319 *
320 * @retval Direction configuration.
321 */
322 __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
323
324 /**
325 * @brief Function for reading the pull configuration of a GPIO pin.
326 *
327 * @param pin_number Specifies the pin number to read.
328 *
329 * @retval Pull configuration.
330 */
331 __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
332
333 /**
334 * @brief Function for setting output direction on selected pins on a given port.
335 *
336 * @param p_reg Pointer to the peripheral registers structure.
337 * @param out_mask Mask specifying the pins to set as output.
338 *
339 */
340 __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
341
342 /**
343 * @brief Function for setting input direction on selected pins on a given port.
344 *
345 * @param p_reg Pointer to the peripheral registers structure.
346 * @param in_mask Mask specifying the pins to set as input.
347 *
348 */
349 __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
350
351 /**
352 * @brief Function for writing the direction configuration of GPIO pins in a given port.
353 *
354 * @param p_reg Pointer to the peripheral registers structure.
355 * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output.
356 *
357 */
358 __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
359
360 /**
361 * @brief Function for reading the direction configuration of a GPIO port.
362 *
363 * @param p_reg Pointer to the peripheral registers structure.
364 *
365 * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
366 */
367 __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
368
369 /**
370 * @brief Function for reading the input signals of GPIO pins on a given port.
371 *
372 * @param p_reg Pointer to the peripheral registers structure.
373 *
374 * @retval Port input values.
375 */
376 __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
377
378 /**
379 * @brief Function for reading the output signals of GPIO pins of a given port.
380 *
381 * @param p_reg Pointer to the peripheral registers structure.
382 *
383 * @retval Port output values.
384 */
385 __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
386
387 /**
388 * @brief Function for writing the GPIO pins output on a given port.
389 *
390 * @param p_reg Pointer to the peripheral registers structure.
391 * @param value Output port mask.
392 *
393 */
394 __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
395
396 /**
397 * @brief Function for setting high level on selected GPIO pins of a given port.
398 *
399 * @param p_reg Pointer to the peripheral registers structure.
400 * @param set_mask Mask with pins to set as logical high level.
401 *
402 */
403 __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
404
405 /**
406 * @brief Function for setting low level on selected GPIO pins of a given port.
407 *
408 * @param p_reg Pointer to the peripheral registers structure.
409 * @param clr_mask Mask with pins to set as logical low level.
410 *
411 */
412 __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
413
414 /**
415 * @brief Function for reading pins state of multiple consecutive ports.
416 *
417 * @param start_port Index of the first port to read.
418 * @param length Number of ports to read.
419 * @param p_masks Pointer to output array where port states will be stored.
420 */
421 __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks);
422
423 #if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__)
424 /**
425 * @brief Function for reading latch state of multiple consecutive ports.
426 *
427 * @param start_port Index of the first port to read.
428 * @param length Number of ports to read.
429 * @param p_masks Pointer to output array where latch states will be stored.
430 */
431 __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length,
432 uint32_t * p_masks);
433
434 /**
435 * @brief Function for reading latch state of single pin.
436 *
437 * @param pin_number Pin number.
438 * @return 0 if latch is not set. Positive value otherwise.
439 *
440 */
441 __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
442
443 /**
444 * @brief Function for clearing latch state of a single pin.
445 *
446 * @param pin_number Pin number.
447 *
448 */
449 __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
450 #endif
451
452 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
453
454 /**
455 * @brief Function for extracting port and relative pin number from absolute pin number.
456 *
457 * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number.
458 *
459 * @return Pointer to port register set.
460 *
461 */
nrf_gpio_pin_port_decode(uint32_t * p_pin)462 __STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
463 {
464 NRFX_ASSERT(*p_pin < NUMBER_OF_PINS);
465 #if (GPIO_COUNT == 1)
466 // The oldest definition case
467 return NRF_GPIO;
468 #else
469 if (*p_pin < P0_PIN_NUM)
470 {
471 return NRF_P0;
472 }
473 else
474 {
475 *p_pin = *p_pin & (P0_PIN_NUM - 1);
476 return NRF_P1;
477 }
478 #endif
479 }
480
481
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)482 __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
483 {
484 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
485 for (; pin_range_start <= pin_range_end; pin_range_start++)
486 {
487 nrf_gpio_cfg_output(pin_range_start);
488 }
489 }
490
491
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)492 __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
493 uint32_t pin_range_end,
494 nrf_gpio_pin_pull_t pull_config)
495 {
496 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
497 for (; pin_range_start <= pin_range_end; pin_range_start++)
498 {
499 nrf_gpio_cfg_input(pin_range_start, pull_config);
500 }
501 }
502
503
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)504 __STATIC_INLINE void nrf_gpio_cfg(
505 uint32_t pin_number,
506 nrf_gpio_pin_dir_t dir,
507 nrf_gpio_pin_input_t input,
508 nrf_gpio_pin_pull_t pull,
509 nrf_gpio_pin_drive_t drive,
510 nrf_gpio_pin_sense_t sense)
511 {
512 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
513
514 reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
515 | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
516 | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
517 | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
518 | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
519 }
520
521
nrf_gpio_cfg_output(uint32_t pin_number)522 __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
523 {
524 nrf_gpio_cfg(
525 pin_number,
526 NRF_GPIO_PIN_DIR_OUTPUT,
527 NRF_GPIO_PIN_INPUT_DISCONNECT,
528 NRF_GPIO_PIN_NOPULL,
529 NRF_GPIO_PIN_S0S1,
530 NRF_GPIO_PIN_NOSENSE);
531 }
532
533
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)534 __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
535 {
536 nrf_gpio_cfg(
537 pin_number,
538 NRF_GPIO_PIN_DIR_INPUT,
539 NRF_GPIO_PIN_INPUT_CONNECT,
540 pull_config,
541 NRF_GPIO_PIN_S0S1,
542 NRF_GPIO_PIN_NOSENSE);
543 }
544
545
nrf_gpio_cfg_default(uint32_t pin_number)546 __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
547 {
548 nrf_gpio_cfg(
549 pin_number,
550 NRF_GPIO_PIN_DIR_INPUT,
551 NRF_GPIO_PIN_INPUT_DISCONNECT,
552 NRF_GPIO_PIN_NOPULL,
553 NRF_GPIO_PIN_S0S1,
554 NRF_GPIO_PIN_NOSENSE);
555 }
556
557
nrf_gpio_cfg_watcher(uint32_t pin_number)558 __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
559 {
560 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
561 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
562 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
563
564 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
565 }
566
567
nrf_gpio_input_disconnect(uint32_t pin_number)568 __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
569 {
570 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
571 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
572 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
573
574 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
575 }
576
577
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)578 __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
579 nrf_gpio_pin_pull_t pull_config,
580 nrf_gpio_pin_sense_t sense_config)
581 {
582 nrf_gpio_cfg(
583 pin_number,
584 NRF_GPIO_PIN_DIR_INPUT,
585 NRF_GPIO_PIN_INPUT_CONNECT,
586 pull_config,
587 NRF_GPIO_PIN_S0S1,
588 sense_config);
589 }
590
591
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)592 __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
593 {
594 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
595
596 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
597 reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
598 reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
599 }
600
601
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)602 __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
603 {
604 if (direction == NRF_GPIO_PIN_DIR_INPUT)
605 {
606 nrf_gpio_cfg(
607 pin_number,
608 NRF_GPIO_PIN_DIR_INPUT,
609 NRF_GPIO_PIN_INPUT_CONNECT,
610 NRF_GPIO_PIN_NOPULL,
611 NRF_GPIO_PIN_S0S1,
612 NRF_GPIO_PIN_NOSENSE);
613 }
614 else
615 {
616 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
617 reg->DIRSET = (1UL << pin_number);
618 }
619 }
620
621
nrf_gpio_pin_set(uint32_t pin_number)622 __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
623 {
624 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
625
626 nrf_gpio_port_out_set(reg, 1UL << pin_number);
627 }
628
629
nrf_gpio_pin_clear(uint32_t pin_number)630 __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
631 {
632 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
633
634 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
635 }
636
637
nrf_gpio_pin_toggle(uint32_t pin_number)638 __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
639 {
640 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
641 uint32_t pins_state = reg->OUT;
642
643 reg->OUTSET = (~pins_state & (1UL << pin_number));
644 reg->OUTCLR = (pins_state & (1UL << pin_number));
645 }
646
647
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)648 __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
649 {
650 if (value == 0)
651 {
652 nrf_gpio_pin_clear(pin_number);
653 }
654 else
655 {
656 nrf_gpio_pin_set(pin_number);
657 }
658 }
659
660
nrf_gpio_pin_read(uint32_t pin_number)661 __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
662 {
663 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
664
665 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
666 }
667
668
nrf_gpio_pin_out_read(uint32_t pin_number)669 __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
670 {
671 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
672
673 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
674 }
675
676
nrf_gpio_pin_sense_get(uint32_t pin_number)677 __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
678 {
679 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
680
681 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
682 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
683 }
684
685
nrf_gpio_pin_dir_get(uint32_t pin_number)686 __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
687 {
688 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
689
690 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
691 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
692 }
693
694
nrf_gpio_pin_pull_get(uint32_t pin_number)695 __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
696 {
697 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
698
699 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
700 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
701 }
702
703
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)704 __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
705 {
706 p_reg->DIRSET = out_mask;
707 }
708
709
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)710 __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
711 {
712 p_reg->DIRCLR = in_mask;
713 }
714
715
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)716 __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
717 {
718 p_reg->DIR = value;
719 }
720
721
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)722 __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
723 {
724 return p_reg->DIR;
725 }
726
727
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)728 __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
729 {
730 return p_reg->IN;
731 }
732
733
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)734 __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
735 {
736 return p_reg->OUT;
737 }
738
739
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)740 __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
741 {
742 p_reg->OUT = value;
743 }
744
745
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)746 __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
747 {
748 p_reg->OUTSET = set_mask;
749 }
750
751
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)752 __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
753 {
754 p_reg->OUTCLR = clr_mask;
755 }
756
757
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)758 __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
759 {
760 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
761
762 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
763 uint32_t i;
764
765 for (i = start_port; i < (start_port + length); i++)
766 {
767 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
768 p_masks++;
769 }
770 }
771
772
773 #ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)774 __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
775 {
776 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
777 uint32_t i;
778
779 for (i = start_port; i < (start_port + length); i++)
780 {
781 *p_masks = gpio_regs[i]->LATCH;
782 p_masks++;
783 }
784 }
785
786
nrf_gpio_pin_latch_get(uint32_t pin_number)787 __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
788 {
789 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
790
791 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
792 }
793
794
nrf_gpio_pin_latch_clear(uint32_t pin_number)795 __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
796 {
797 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
798
799 reg->LATCH = (1 << pin_number);
800 }
801
802
803 #endif
804 #endif // SUPPRESS_INLINE_IMPLEMENTATION
805
806 /** @} */
807
808 #ifdef __cplusplus
809 }
810 #endif
811
812 #endif // NRF_GPIO_H__
813