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Searched defs:NVICState (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Darmv7m_nvic.h40 struct NVICState { struct
42 SysBusDevice parent_obj;
45 ARMCPU *cpu;
62 uint8_t num_prio_bits;
82 MemoryRegion sysregmem;
84 MemoryRegion systickmem;
86 MemoryRegion ras_mem;
87 MemoryRegion container;
90 uint32_t num_irq;
91 qemu_irq excpout;
[all …]
/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
40 struct NVICState { struct
42 SysBusDevice parent_obj;
45 ARMCPU *cpu;
62 uint8_t num_prio_bits;
82 MemoryRegion sysregmem;
84 MemoryRegion systickmem;
86 MemoryRegion container;
88 uint32_t num_irq;
89 qemu_irq excpout;
[all …]
/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h38 typedef struct NVICState { struct
40 SysBusDevice parent_obj;
43 ARMCPU *cpu;
45 VecInfo vectors[NVIC_MAX_VECTORS];
57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
59 uint32_t prigroup[M_REG_NUM_BANKS];
60 uint8_t num_prio_bits;
63 bool itns[NVIC_MAX_VECTORS];
91 } NVICState; argument
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/
H A Darmv7m_nvic.h38 typedef struct NVICState { struct
40 SysBusDevice parent_obj;
43 ARMCPU *cpu;
45 VecInfo vectors[NVIC_MAX_VECTORS];
57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
59 uint32_t prigroup[M_REG_NUM_BANKS];
60 uint8_t num_prio_bits;
63 bool itns[NVIC_MAX_VECTORS];
91 } NVICState; argument
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h38 typedef struct NVICState { struct
40 SysBusDevice parent_obj;
43 ARMCPU *cpu;
45 VecInfo vectors[NVIC_MAX_VECTORS];
57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
59 uint32_t prigroup[M_REG_NUM_BANKS];
60 uint8_t num_prio_bits;
63 bool itns[NVIC_MAX_VECTORS];
91 } NVICState; argument
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/
H A Darmv7m_nvic.h38 typedef struct NVICState { struct
40 SysBusDevice parent_obj;
43 ARMCPU *cpu;
45 VecInfo vectors[NVIC_MAX_VECTORS];
57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
59 uint32_t prigroup[M_REG_NUM_BANKS];
60 uint8_t num_prio_bits;
63 bool itns[NVIC_MAX_VECTORS];
91 } NVICState; typedef
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/intc/
H A Darmv7m_nvic.h38 typedef struct NVICState { struct
40 SysBusDevice parent_obj;
43 ARMCPU *cpu;
45 VecInfo vectors[NVIC_MAX_VECTORS];
57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
59 uint32_t prigroup[M_REG_NUM_BANKS];
60 uint8_t num_prio_bits;
63 bool itns[NVIC_MAX_VECTORS];
91 } NVICState; argument
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
40 struct NVICState { struct
42 SysBusDevice parent_obj;
45 ARMCPU *cpu;
62 uint8_t num_prio_bits;
65 bool itns[NVIC_MAX_VECTORS];
78 bool vectpending_is_s_banked;
82 MemoryRegion sysregmem;
84 uint32_t num_irq;
85 qemu_irq excpout;
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
40 struct NVICState { struct
42 SysBusDevice parent_obj;
45 ARMCPU *cpu;
62 uint8_t num_prio_bits;
65 bool itns[NVIC_MAX_VECTORS];
78 bool vectpending_is_s_banked;
82 MemoryRegion sysregmem;
84 uint32_t num_irq;
85 qemu_irq excpout;
[all …]