1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef __NVME_H__
30 #define __NVME_H__
31
32 #ifdef _KERNEL
33 #include <sys/types.h>
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/endian.h>
38
39 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
40 #define NVME_RESET_CONTROLLER _IO('n', 1)
41 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
42 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
43
44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
46
47 /* NB: Fabrics-specific ioctls defined in nvmf.h start at 200. */
48
49 /*
50 * Macros to deal with NVME revisions, as defined VS register
51 */
52 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
53 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
54 #define NVME_MINOR(r) (((r) >> 8) & 0xff)
55
56 /*
57 * Use to mark a command to apply to all namespaces, or to retrieve global
58 * log pages.
59 */
60 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
61
62 /* Host memory buffer sizes are always in 4096 byte chunks */
63 #define NVME_HMB_UNITS 4096
64
65 /* Many items are expressed in terms of power of two times MPS */
66 #define NVME_MPS_SHIFT 12
67
68 /* Limits on queue sizes: See 4.1.3 Queue Size in NVMe 1.4b. */
69 #define NVME_MIN_ADMIN_ENTRIES 2
70 #define NVME_MAX_ADMIN_ENTRIES 4096
71
72 #define NVME_MIN_IO_ENTRIES 2
73 #define NVME_MAX_IO_ENTRIES 65536
74
75 /* Register field definitions */
76 #define NVME_CAP_LO_REG_MQES_SHIFT (0)
77 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
78 #define NVME_CAP_LO_REG_CQR_SHIFT (16)
79 #define NVME_CAP_LO_REG_CQR_MASK (0x1)
80 #define NVME_CAP_LO_REG_AMS_SHIFT (17)
81 #define NVME_CAP_LO_REG_AMS_MASK (0x3)
82 #define NVME_CAP_LO_REG_TO_SHIFT (24)
83 #define NVME_CAP_LO_REG_TO_MASK (0xFF)
84 #define NVME_CAP_LO_MQES(x) \
85 NVMEV(NVME_CAP_LO_REG_MQES, x)
86 #define NVME_CAP_LO_CQR(x) \
87 NVMEV(NVME_CAP_LO_REG_CQR, x)
88 #define NVME_CAP_LO_AMS(x) \
89 NVMEV(NVME_CAP_LO_REG_AMS, x)
90 #define NVME_CAP_LO_TO(x) \
91 NVMEV(NVME_CAP_LO_REG_TO, x)
92
93 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
94 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
95 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
96 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
97 #define NVME_CAP_HI_REG_CSS_SHIFT (5)
98 #define NVME_CAP_HI_REG_CSS_MASK (0xff)
99 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
100 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
101 #define NVME_CAP_HI_REG_BPS_SHIFT (13)
102 #define NVME_CAP_HI_REG_BPS_MASK (0x1)
103 #define NVME_CAP_HI_REG_CPS_SHIFT (14)
104 #define NVME_CAP_HI_REG_CPS_MASK (0x3)
105 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
106 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
107 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
108 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
109 #define NVME_CAP_HI_REG_PMRS_SHIFT (24)
110 #define NVME_CAP_HI_REG_PMRS_MASK (0x1)
111 #define NVME_CAP_HI_REG_CMBS_SHIFT (25)
112 #define NVME_CAP_HI_REG_CMBS_MASK (0x1)
113 #define NVME_CAP_HI_REG_NSSS_SHIFT (26)
114 #define NVME_CAP_HI_REG_NSSS_MASK (0x1)
115 #define NVME_CAP_HI_REG_CRWMS_SHIFT (27)
116 #define NVME_CAP_HI_REG_CRWMS_MASK (0x1)
117 #define NVME_CAP_HI_REG_CRIMS_SHIFT (28)
118 #define NVME_CAP_HI_REG_CRIMS_MASK (0x1)
119 #define NVME_CAP_HI_DSTRD(x) \
120 NVMEV(NVME_CAP_HI_REG_DSTRD, x)
121 #define NVME_CAP_HI_NSSRS(x) \
122 NVMEV(NVME_CAP_HI_REG_NSSRS, x)
123 #define NVME_CAP_HI_CSS(x) \
124 NVMEV(NVME_CAP_HI_REG_CSS, x)
125 #define NVME_CAP_HI_CSS_NVM(x) \
126 NVMEV(NVME_CAP_HI_REG_CSS_NVM, x)
127 #define NVME_CAP_HI_BPS(x) \
128 NVMEV(NVME_CAP_HI_REG_BPS, x)
129 #define NVME_CAP_HI_CPS(x) \
130 NVMEV(NVME_CAP_HI_REG_CPS, x)
131 #define NVME_CAP_HI_MPSMIN(x) \
132 NVMEV(NVME_CAP_HI_REG_MPSMIN, x)
133 #define NVME_CAP_HI_MPSMAX(x) \
134 NVMEV(NVME_CAP_HI_REG_MPSMAX, x)
135 #define NVME_CAP_HI_PMRS(x) \
136 NVMEV(NVME_CAP_HI_REG_PMRS, x)
137 #define NVME_CAP_HI_CMBS(x) \
138 NVMEV(NVME_CAP_HI_REG_CMBS, x)
139 #define NVME_CAP_HI_NSSS(x) \
140 NVMEV(NVME_CAP_HI_REG_NSSS, x)
141 #define NVME_CAP_HI_CRWMS(x) \
142 NVMEV(NVME_CAP_HI_REG_CRWMS, x)
143 #define NVME_CAP_HI_CRIMS(x) \
144 NVMEV(NVME_CAP_HI_REG_CRIMS, x)
145
146 #define NVME_CC_REG_EN_SHIFT (0)
147 #define NVME_CC_REG_EN_MASK (0x1)
148 #define NVME_CC_REG_CSS_SHIFT (4)
149 #define NVME_CC_REG_CSS_MASK (0x7)
150 #define NVME_CC_REG_MPS_SHIFT (7)
151 #define NVME_CC_REG_MPS_MASK (0xF)
152 #define NVME_CC_REG_AMS_SHIFT (11)
153 #define NVME_CC_REG_AMS_MASK (0x7)
154 #define NVME_CC_REG_SHN_SHIFT (14)
155 #define NVME_CC_REG_SHN_MASK (0x3)
156 #define NVME_CC_REG_IOSQES_SHIFT (16)
157 #define NVME_CC_REG_IOSQES_MASK (0xF)
158 #define NVME_CC_REG_IOCQES_SHIFT (20)
159 #define NVME_CC_REG_IOCQES_MASK (0xF)
160 #define NVME_CC_REG_CRIME_SHIFT (24)
161 #define NVME_CC_REG_CRIME_MASK (0x1)
162
163 #define NVME_CSTS_REG_RDY_SHIFT (0)
164 #define NVME_CSTS_REG_RDY_MASK (0x1)
165 #define NVME_CSTS_REG_CFS_SHIFT (1)
166 #define NVME_CSTS_REG_CFS_MASK (0x1)
167 #define NVME_CSTS_REG_SHST_SHIFT (2)
168 #define NVME_CSTS_REG_SHST_MASK (0x3)
169 #define NVME_CSTS_REG_NVSRO_SHIFT (4)
170 #define NVME_CSTS_REG_NVSRO_MASK (0x1)
171 #define NVME_CSTS_REG_PP_SHIFT (5)
172 #define NVME_CSTS_REG_PP_MASK (0x1)
173 #define NVME_CSTS_REG_ST_SHIFT (6)
174 #define NVME_CSTS_REG_ST_MASK (0x1)
175
176 #define NVME_CSTS_GET_SHST(csts) \
177 NVMEV(NVME_CSTS_REG_SHST, csts)
178
179 #define NVME_AQA_REG_ASQS_SHIFT (0)
180 #define NVME_AQA_REG_ASQS_MASK (0xFFF)
181 #define NVME_AQA_REG_ACQS_SHIFT (16)
182 #define NVME_AQA_REG_ACQS_MASK (0xFFF)
183
184 #define NVME_PMRCAP_REG_RDS_SHIFT (3)
185 #define NVME_PMRCAP_REG_RDS_MASK (0x1)
186 #define NVME_PMRCAP_REG_WDS_SHIFT (4)
187 #define NVME_PMRCAP_REG_WDS_MASK (0x1)
188 #define NVME_PMRCAP_REG_BIR_SHIFT (5)
189 #define NVME_PMRCAP_REG_BIR_MASK (0x7)
190 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
191 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
192 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
193 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
194 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
195 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
196 #define NVME_PMRCAP_REG_CMSS_SHIFT (24)
197 #define NVME_PMRCAP_REG_CMSS_MASK (0x1)
198
199 #define NVME_PMRCAP_RDS(x) \
200 NVMEV(NVME_PMRCAP_REG_RDS, x)
201 #define NVME_PMRCAP_WDS(x) \
202 NVMEV(NVME_PMRCAP_REG_WDS, x)
203 #define NVME_PMRCAP_BIR(x) \
204 NVMEV(NVME_PMRCAP_REG_BIR, x)
205 #define NVME_PMRCAP_PMRTU(x) \
206 NVMEV(NVME_PMRCAP_REG_PMRTU, x)
207 #define NVME_PMRCAP_PMRWBM(x) \
208 NVMEV(NVME_PMRCAP_REG_PMRWBM, x)
209 #define NVME_PMRCAP_PMRTO(x) \
210 NVMEV(NVME_PMRCAP_REG_PMRTO, x)
211 #define NVME_PMRCAP_CMSS(x) \
212 NVMEV(NVME_PMRCAP_REG_CMSS, x)
213
214 /* Command field definitions */
215
216 enum nvme_fuse {
217 NVME_FUSE_NORMAL = 0x0,
218 NVME_FUSE_FIRST = 0x1,
219 NVME_FUSE_SECOND = 0x2
220 };
221 #define NVME_CMD_FUSE_SHIFT (0)
222 #define NVME_CMD_FUSE_MASK (0x3)
223
224 enum nvme_psdt {
225 NVME_PSDT_PRP = 0x0,
226 NVME_PSDT_SGL = 0x1,
227 NVME_PSDT_SGL_MPTR = 0x2
228 };
229 #define NVME_CMD_PSDT_SHIFT (6)
230 #define NVME_CMD_PSDT_MASK (0x3)
231
232
233 #define NVME_STATUS_P_SHIFT (0)
234 #define NVME_STATUS_P_MASK (0x1)
235 #define NVME_STATUS_SC_SHIFT (1)
236 #define NVME_STATUS_SC_MASK (0xFF)
237 #define NVME_STATUS_SCT_SHIFT (9)
238 #define NVME_STATUS_SCT_MASK (0x7)
239 #define NVME_STATUS_CRD_SHIFT (12)
240 #define NVME_STATUS_CRD_MASK (0x3)
241 #define NVME_STATUS_M_SHIFT (14)
242 #define NVME_STATUS_M_MASK (0x1)
243 #define NVME_STATUS_DNR_SHIFT (15)
244 #define NVME_STATUS_DNR_MASK (0x1)
245
246 #define NVME_STATUS_GET_P(st) \
247 NVMEV(NVME_STATUS_P, st)
248 #define NVME_STATUS_GET_SC(st) \
249 NVMEV(NVME_STATUS_SC, st)
250 #define NVME_STATUS_GET_SCT(st) \
251 NVMEV(NVME_STATUS_SCT, st)
252 #define NVME_STATUS_GET_CRD(st) \
253 NVMEV(NVME_STATUS_CRD, st)
254 #define NVME_STATUS_GET_M(st) \
255 NVMEV(NVME_STATUS_M, st)
256 #define NVME_STATUS_GET_DNR(st) \
257 NVMEV(NVME_STATUS_DNR, st)
258
259 #define NVME_PWR_ST_MPS_SHIFT (0)
260 #define NVME_PWR_ST_MPS_MASK (0x1)
261 #define NVME_PWR_ST_NOPS_SHIFT (1)
262 #define NVME_PWR_ST_NOPS_MASK (0x1)
263 #define NVME_PWR_ST_RRT_SHIFT (0)
264 #define NVME_PWR_ST_RRT_MASK (0x1F)
265 #define NVME_PWR_ST_RRL_SHIFT (0)
266 #define NVME_PWR_ST_RRL_MASK (0x1F)
267 #define NVME_PWR_ST_RWT_SHIFT (0)
268 #define NVME_PWR_ST_RWT_MASK (0x1F)
269 #define NVME_PWR_ST_RWL_SHIFT (0)
270 #define NVME_PWR_ST_RWL_MASK (0x1F)
271 #define NVME_PWR_ST_IPS_SHIFT (6)
272 #define NVME_PWR_ST_IPS_MASK (0x3)
273 #define NVME_PWR_ST_APW_SHIFT (0)
274 #define NVME_PWR_ST_APW_MASK (0x7)
275 #define NVME_PWR_ST_APS_SHIFT (6)
276 #define NVME_PWR_ST_APS_MASK (0x3)
277
278 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
279 /* More then one port */
280 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
281 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
282 /* More then one controller */
283 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
284 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
285 /* SR-IOV Virtual Function */
286 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
287 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
288 /* Asymmetric Namespace Access Reporting */
289 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
290 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
291
292 /** OAES - Optional Asynchronous Events Supported */
293 /* supports Namespace Attribute Notices event */
294 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
295 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
296 /* supports Firmware Activation Notices event */
297 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
298 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
299 /* supports Asymmetric Namespace Access Change Notices event */
300 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
301 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
302 /* supports Predictable Latency Event Aggregate Log Change Notices event */
303 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
304 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
305 /* supports LBA Status Information Notices event */
306 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
307 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
308 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */
309 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
310 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
311 /* supports Normal NVM Subsystem Shutdown event */
312 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
313 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
314 /* supports Zone Descriptor Changed Notices event */
315 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
316 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
317 /* supports Discovery Log Page Change Notification event */
318 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
319 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
320
321 /** CTRATT - Controller Attributes */
322 /* supports 128-bit Host Identifier */
323 #define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_SHIFT (0)
324 #define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_MASK (0x1)
325 /* supports Non-Operational Power State Permissive Mode */
326 #define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_SHIFT (1)
327 #define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_MASK (0x1)
328 /* supports NVM Sets */
329 #define NVME_CTRLR_DATA_CTRATT_NVM_SETS_SHIFT (2)
330 #define NVME_CTRLR_DATA_CTRATT_NVM_SETS_MASK (0x1)
331 /* supports Read Recovery Levels */
332 #define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_SHIFT (3)
333 #define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_MASK (0x1)
334 /* supports Endurance Groups */
335 #define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_SHIFT (4)
336 #define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_MASK (0x1)
337 /* supports Predictable Latency Mode */
338 #define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_SHIFT (5)
339 #define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_MASK (0x1)
340 /* supports Traffic Based Keep Alive Support */
341 #define NVME_CTRLR_DATA_CTRATT_TBKAS_SHIFT (6)
342 #define NVME_CTRLR_DATA_CTRATT_TBKAS_MASK (0x1)
343 /* supports Namespace Granularity */
344 #define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_SHIFT (7)
345 #define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_MASK (0x1)
346 /* supports SQ Associations */
347 #define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_SHIFT (8)
348 #define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_MASK (0x1)
349 /* supports UUID List */
350 #define NVME_CTRLR_DATA_CTRATT_UUID_LIST_SHIFT (9)
351 #define NVME_CTRLR_DATA_CTRATT_UUID_LIST_MASK (0x1)
352
353 /** OACS - optional admin command support */
354 /* supports security send/receive commands */
355 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
356 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
357 /* supports format nvm command */
358 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
359 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
360 /* supports firmware activate/download commands */
361 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
362 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
363 /* supports namespace management commands */
364 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
365 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
366 /* supports Device Self-test command */
367 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
368 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
369 /* supports Directives */
370 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
371 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
372 /* supports NVMe-MI Send/Receive */
373 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
374 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
375 /* supports Virtualization Management */
376 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
377 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
378 /* supports Doorbell Buffer Config */
379 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
380 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
381 /* supports Get LBA Status */
382 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
383 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
384
385 /** firmware updates */
386 /* first slot is read-only */
387 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
388 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
389 /* number of firmware slots */
390 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
391 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
392 /* firmware activation without reset */
393 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
394 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
395
396 /** log page attributes */
397 /* per namespace smart/health log page */
398 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
399 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
400 /* Commands Supported and Effects log page */
401 #define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_SHIFT (1)
402 #define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_MASK (0x1)
403 /* extended data for Get Log Page command */
404 #define NVME_CTRLR_DATA_LPA_EXT_DATA_SHIFT (2)
405 #define NVME_CTRLR_DATA_LPA_EXT_DATA_MASK (0x1)
406 /* telemetry */
407 #define NVME_CTRLR_DATA_LPA_TELEMETRY_SHIFT (3)
408 #define NVME_CTRLR_DATA_LPA_TELEMETRY_MASK (0x1)
409 /* persistent event */
410 #define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_SHIFT (4)
411 #define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_MASK (0x1)
412 /* Supported log pages, etc */
413 #define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_SHIFT (5)
414 #define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_MASK (0x1)
415 /* Data Area 4 for Telemetry */
416 #define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_SHIFT (6)
417 #define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_MASK (0x1)
418
419 /** AVSCC - admin vendor specific command configuration */
420 /* admin vendor specific commands use spec format */
421 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
422 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
423
424 /** Autonomous Power State Transition Attributes */
425 /* Autonomous Power State Transitions supported */
426 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
427 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
428
429 /** Sanitize Capabilities */
430 /* Crypto Erase Support */
431 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
432 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
433 /* Block Erase Support */
434 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
435 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
436 /* Overwrite Support */
437 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
438 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
439 /* No-Deallocate Inhibited */
440 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
441 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
442 /* No-Deallocate Modifies Media After Sanitize */
443 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
444 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
445 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
446 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
447 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
448
449 /** submission queue entry size */
450 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
451 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
452 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
453 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
454
455 /** completion queue entry size */
456 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
457 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
458 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
459 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
460
461 /** optional nvm command support */
462 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
463 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
464 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
465 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
466 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
467 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
468 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
469 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
470 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
471 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
472 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
473 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
474 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
475 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
476 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
477 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
478
479 /** Fused Operation Support */
480 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
481 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
482
483 /** Format NVM Attributes */
484 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
485 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
486 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
487 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
488 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
489 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
490
491 /** volatile write cache */
492 /* volatile write cache present */
493 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
494 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
495 /* flush all namespaces supported */
496 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
497 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
498 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
499 #define NVME_CTRLR_DATA_VWC_ALL_NO (2)
500 #define NVME_CTRLR_DATA_VWC_ALL_YES (3)
501
502 /** SGL Support */
503 /* NVM command set SGL support */
504 #define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_SHIFT (0)
505 #define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_MASK (0x3)
506 #define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_SHIFT (2)
507 #define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_MASK (0x1)
508 #define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_SHIFT (16)
509 #define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_MASK (0x1)
510 #define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_SHIFT (17)
511 #define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_MASK (0x1)
512 #define NVME_CTRLR_DATA_SGLS_OVERSIZED_SHIFT (18)
513 #define NVME_CTRLR_DATA_SGLS_OVERSIZED_MASK (0x1)
514 #define NVME_CTRLR_DATA_SGLS_MPTR_SGL_SHIFT (19)
515 #define NVME_CTRLR_DATA_SGLS_MPTR_SGL_MASK (0x1)
516 #define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_SHIFT (20)
517 #define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_MASK (0x1)
518 #define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_SHIFT (21)
519 #define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_MASK (0x1)
520
521 /** namespace features */
522 /* thin provisioning */
523 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
524 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
525 /* NAWUN, NAWUPF, and NACWU fields are valid */
526 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
527 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
528 /* Deallocated or Unwritten Logical Block errors supported */
529 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
530 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
531 /* NGUID and EUI64 fields are not reusable */
532 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
533 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
534 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
535 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
536 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
537
538 /** formatted lba size */
539 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
540 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
541 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
542 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
543
544 /** metadata capabilities */
545 /* metadata can be transferred as part of data prp list */
546 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
547 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
548 /* metadata can be transferred with separate metadata pointer */
549 #define NVME_NS_DATA_MC_POINTER_SHIFT (1)
550 #define NVME_NS_DATA_MC_POINTER_MASK (0x1)
551
552 /** end-to-end data protection capabilities */
553 /* protection information type 1 */
554 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
555 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
556 /* protection information type 2 */
557 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
558 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
559 /* protection information type 3 */
560 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
561 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
562 /* first eight bytes of metadata */
563 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
564 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
565 /* last eight bytes of metadata */
566 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
567 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
568
569 /** end-to-end data protection type settings */
570 /* protection information type */
571 #define NVME_NS_DATA_DPS_PIT_SHIFT (0)
572 #define NVME_NS_DATA_DPS_PIT_MASK (0x7)
573 /* 1 == protection info transferred at start of metadata */
574 /* 0 == protection info transferred at end of metadata */
575 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
576 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
577
578 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
579 /* the namespace may be attached to two or more controllers */
580 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
581 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
582
583 /** Reservation Capabilities */
584 /* Persist Through Power Loss */
585 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
586 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
587 /* supports the Write Exclusive */
588 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
589 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
590 /* supports the Exclusive Access */
591 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
592 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
593 /* supports the Write Exclusive – Registrants Only */
594 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
595 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
596 /* supports the Exclusive Access - Registrants Only */
597 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
598 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
599 /* supports the Write Exclusive – All Registrants */
600 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
601 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
602 /* supports the Exclusive Access - All Registrants */
603 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
604 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
605 /* Ignore Existing Key is used as defined in revision 1.3 or later */
606 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
607 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
608
609 /** Format Progress Indicator */
610 /* percentage of the Format NVM command that remains to be completed */
611 #define NVME_NS_DATA_FPI_PERC_SHIFT (0)
612 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
613 /* namespace supports the Format Progress Indicator */
614 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
615 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
616
617 /** Deallocate Logical Block Features */
618 /* deallocated logical block read behavior */
619 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
620 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
621 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
622 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
623 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
624 /* supports the Deallocate bit in the Write Zeroes */
625 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
626 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
627 /* Guard field for deallocated logical blocks is set to the CRC */
628 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
629 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
630
631 /** lba format support */
632 /* metadata size */
633 #define NVME_NS_DATA_LBAF_MS_SHIFT (0)
634 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
635 /* lba data size */
636 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
637 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
638 /* relative performance */
639 #define NVME_NS_DATA_LBAF_RP_SHIFT (24)
640 #define NVME_NS_DATA_LBAF_RP_MASK (0x3)
641
642 enum nvme_critical_warning_state {
643 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
644 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
645 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
646 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
647 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
648 NVME_CRIT_WARN_ST_PERSISTENT_MEMORY_REGION = 0x20,
649 };
650 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xC0)
651 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (1U << 8)
652 #define NVME_ASYNC_EVENT_FW_ACTIVATE (1U << 9)
653 #define NVME_ASYNC_EVENT_TELEMETRY_LOG (1U << 10)
654 #define NVME_ASYNC_EVENT_ASYM_NS_ACC (1U << 11)
655 #define NVME_ASYNC_EVENT_PRED_LAT_DELTA (1U << 12)
656 #define NVME_ASYNC_EVENT_LBA_STATUS (1U << 13)
657 #define NVME_ASYNC_EVENT_ENDURANCE_DELTA (1U << 14)
658 #define NVME_ASYNC_EVENT_NVM_SHUTDOWN (1U << 15)
659 #define NVME_ASYNC_EVENT_ZONE_DELTA (1U << 27)
660 #define NVME_ASYNC_EVENT_DISCOVERY_DELTA (1U << 31)
661
662 /* slot for current FW */
663 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
664 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
665
666 /* Commands Supported and Effects */
667 #define NVME_CE_PAGE_CSUP_SHIFT (0)
668 #define NVME_CE_PAGE_CSUP_MASK (0x1)
669 #define NVME_CE_PAGE_LBCC_SHIFT (1)
670 #define NVME_CE_PAGE_LBCC_MASK (0x1)
671 #define NVME_CE_PAGE_NCC_SHIFT (2)
672 #define NVME_CE_PAGE_NCC_MASK (0x1)
673 #define NVME_CE_PAGE_NIC_SHIFT (3)
674 #define NVME_CE_PAGE_NIC_MASK (0x1)
675 #define NVME_CE_PAGE_CCC_SHIFT (4)
676 #define NVME_CE_PAGE_CCC_MASK (0x1)
677 #define NVME_CE_PAGE_CSE_SHIFT (16)
678 #define NVME_CE_PAGE_CSE_MASK (0x7)
679 #define NVME_CE_PAGE_UUID_SHIFT (19)
680 #define NVME_CE_PAGE_UUID_MASK (0x1)
681
682 /* Sanitize Status */
683 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
684 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
685 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
686 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
687 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
688 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
689 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
690 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
691 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
692 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
693 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
694
695 /* Features */
696 /* Get Features */
697 #define NVME_FEAT_GET_SEL_SHIFT (8)
698 #define NVME_FEAT_GET_SEL_MASK (0x7)
699 #define NVME_FEAT_GET_FID_SHIFT (0)
700 #define NVME_FEAT_GET_FID_MASK (0xff)
701
702 /* Set Features */
703 #define NVME_FEAT_SET_SV_SHIFT (31)
704 #define NVME_FEAT_SET_SV_MASK (0x1)
705 #define NVME_FEAT_SET_FID_SHIFT (0)
706 #define NVME_FEAT_SET_FID_MASK (0xff)
707
708 /* Async Events */
709 #define NVME_ASYNC_EVENT_TYPE_SHIFT (0)
710 #define NVME_ASYNC_EVENT_TYPE_MASK (0x7)
711 #define NVME_ASYNC_EVENT_INFO_SHIFT (8)
712 #define NVME_ASYNC_EVENT_INFO_MASK (0xff)
713 #define NVME_ASYNC_EVENT_LOG_PAGE_ID_SHIFT (16)
714 #define NVME_ASYNC_EVENT_LOG_PAGE_ID_MASK (0xff)
715
716 /* Helper macro to combine *_MASK and *_SHIFT defines */
717 #define NVMEM(name) (name##_MASK << name##_SHIFT)
718
719 /* Helper macro to extract value from x */
720 #define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
721
722 /* Helper macro to construct a field value */
723 #define NVMEF(name, x) (((x) & name##_MASK) << name##_SHIFT)
724
725 /* CC register SHN field values */
726 enum shn_value {
727 NVME_SHN_NORMAL = 0x1,
728 NVME_SHN_ABRUPT = 0x2,
729 };
730
731 /* CSTS register SHST field values */
732 enum shst_value {
733 NVME_SHST_NORMAL = 0x0,
734 NVME_SHST_OCCURRING = 0x1,
735 NVME_SHST_COMPLETE = 0x2,
736 };
737
738 struct nvme_registers {
739 uint32_t cap_lo; /* controller capabilities */
740 uint32_t cap_hi;
741 uint32_t vs; /* version */
742 uint32_t intms; /* interrupt mask set */
743 uint32_t intmc; /* interrupt mask clear */
744 uint32_t cc; /* controller configuration */
745 uint32_t reserved1;
746 uint32_t csts; /* controller status */
747 uint32_t nssr; /* NVM Subsystem Reset */
748 uint32_t aqa; /* admin queue attributes */
749 uint64_t asq; /* admin submission queue base addr */
750 uint64_t acq; /* admin completion queue base addr */
751 uint32_t cmbloc; /* Controller Memory Buffer Location */
752 uint32_t cmbsz; /* Controller Memory Buffer Size */
753 uint32_t bpinfo; /* Boot Partition Information */
754 uint32_t bprsel; /* Boot Partition Read Select */
755 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
756 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
757 uint32_t cmbsts; /* Controller Memory Buffer Status */
758 uint32_t cmbebs; /* Controller Memory Buffer Elasticity Buffer Size */
759 uint32_t cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */
760 uint32_t nssd; /* NVM Subsystem Shutdown */
761 uint32_t crto; /* Controller Ready Timeouts */
762 uint8_t reserved3[3476]; /* 6Ch - DFFh */
763 uint32_t pmrcap; /* Persistent Memory Capabilities */
764 uint32_t pmrctl; /* Persistent Memory Region Control */
765 uint32_t pmrsts; /* Persistent Memory Region Status */
766 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
767 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
768 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
769 uint32_t pmrmsc_hi;
770 uint8_t reserved4[484]; /* E1Ch - FFFh */
771 struct {
772 uint32_t sq_tdbl; /* submission queue tail doorbell */
773 uint32_t cq_hdbl; /* completion queue head doorbell */
774 } doorbell[1];
775 };
776
777 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
778
779 #define NVME_SGL_SUBTYPE_SHIFT (0)
780 #define NVME_SGL_SUBTYPE_MASK (0xF)
781 #define NVME_SGL_TYPE_SHIFT (4)
782 #define NVME_SGL_TYPE_MASK (0xF)
783
784 #define NVME_SGL_TYPE(type, subtype) \
785 ((subtype) << NVME_SGL_SUBTYPE_SHIFT | (type) << NVME_SGL_TYPE_SHIFT)
786
787 enum nvme_sgl_type {
788 NVME_SGL_TYPE_DATA_BLOCK = 0x0,
789 NVME_SGL_TYPE_BIT_BUCKET = 0x1,
790 NVME_SGL_TYPE_SEGMENT = 0x2,
791 NVME_SGL_TYPE_LAST_SEGMENT = 0x3,
792 NVME_SGL_TYPE_KEYED_DATA_BLOCK = 0x4,
793 NVME_SGL_TYPE_TRANSPORT_DATA_BLOCK = 0x5,
794 };
795
796 enum nvme_sgl_subtype {
797 NVME_SGL_SUBTYPE_ADDRESS = 0x0,
798 NVME_SGL_SUBTYPE_OFFSET = 0x1,
799 NVME_SGL_SUBTYPE_TRANSPORT = 0xa,
800 };
801
802 struct nvme_sgl_descriptor {
803 uint64_t address;
804 uint32_t length;
805 uint8_t reserved[3];
806 uint8_t type;
807 };
808
809 _Static_assert(sizeof(struct nvme_sgl_descriptor) == 16, "bad size for nvme_sgl_descriptor");
810
811 struct nvme_command {
812 /* dword 0 */
813 uint8_t opc; /* opcode */
814 uint8_t fuse; /* fused operation */
815 uint16_t cid; /* command identifier */
816
817 /* dword 1 */
818 uint32_t nsid; /* namespace identifier */
819
820 /* dword 2-3 */
821 uint32_t rsvd2;
822 uint32_t rsvd3;
823
824 /* dword 4-5 */
825 uint64_t mptr; /* metadata pointer */
826
827 /* dword 6-9 */
828 union {
829 struct {
830 uint64_t prp1; /* prp entry 1 */
831 uint64_t prp2; /* prp entry 2 */
832 };
833 struct nvme_sgl_descriptor sgl;
834 };
835
836 /* dword 10-15 */
837 uint32_t cdw10; /* command-specific */
838 uint32_t cdw11; /* command-specific */
839 uint32_t cdw12; /* command-specific */
840 uint32_t cdw13; /* command-specific */
841 uint32_t cdw14; /* command-specific */
842 uint32_t cdw15; /* command-specific */
843 } __aligned(8);
844
845 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
846
847 struct nvme_completion {
848 /* dword 0 */
849 uint32_t cdw0; /* command-specific */
850
851 /* dword 1 */
852 uint32_t rsvd1;
853
854 /* dword 2 */
855 uint16_t sqhd; /* submission queue head pointer */
856 uint16_t sqid; /* submission queue identifier */
857
858 /* dword 3 */
859 uint16_t cid; /* command identifier */
860 uint16_t status;
861 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
862
863 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
864
865 struct nvme_dsm_range {
866 uint32_t attributes;
867 uint32_t length;
868 uint64_t starting_lba;
869 };
870
871 /* Largest DSM Trim that can be done */
872 #define NVME_MAX_DSM_TRIM 4096
873
874 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
875
876 /* status code types */
877 enum nvme_status_code_type {
878 NVME_SCT_GENERIC = 0x0,
879 NVME_SCT_COMMAND_SPECIFIC = 0x1,
880 NVME_SCT_MEDIA_ERROR = 0x2,
881 NVME_SCT_PATH_RELATED = 0x3,
882 /* 0x3-0x6 - reserved */
883 NVME_SCT_VENDOR_SPECIFIC = 0x7,
884 };
885
886 /* generic command status codes */
887 enum nvme_generic_command_status_code {
888 NVME_SC_SUCCESS = 0x00,
889 NVME_SC_INVALID_OPCODE = 0x01,
890 NVME_SC_INVALID_FIELD = 0x02,
891 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
892 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
893 NVME_SC_ABORTED_POWER_LOSS = 0x05,
894 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
895 NVME_SC_ABORTED_BY_REQUEST = 0x07,
896 NVME_SC_ABORTED_SQ_DELETION = 0x08,
897 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
898 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
899 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
900 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
901 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
902 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
903 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
904 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
905 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
906 NVME_SC_INVALID_USE_OF_CMB = 0x12,
907 NVME_SC_PRP_OFFET_INVALID = 0x13,
908 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
909 NVME_SC_OPERATION_DENIED = 0x15,
910 NVME_SC_SGL_OFFSET_INVALID = 0x16,
911 /* 0x17 - reserved */
912 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
913 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
914 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
915 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
916 NVME_SC_SANITIZE_FAILED = 0x1c,
917 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
918 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
919 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
920 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
921 NVME_SC_COMMAND_INTERRUPTED = 0x21,
922 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
923
924 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
925 NVME_SC_CAPACITY_EXCEEDED = 0x81,
926 NVME_SC_NAMESPACE_NOT_READY = 0x82,
927 NVME_SC_RESERVATION_CONFLICT = 0x83,
928 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
929 };
930
931 /* command specific status codes */
932 enum nvme_command_specific_status_code {
933 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
934 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
935 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
936 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
937 /* 0x04 - reserved */
938 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
939 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
940 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
941 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
942 NVME_SC_INVALID_LOG_PAGE = 0x09,
943 NVME_SC_INVALID_FORMAT = 0x0a,
944 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
945 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
946 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
947 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
948 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
949 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
950 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
951 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
952 NVME_SC_FW_ACT_PROHIBITED = 0x13,
953 NVME_SC_OVERLAPPING_RANGE = 0x14,
954 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
955 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
956 /* 0x17 - reserved */
957 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
958 NVME_SC_NS_IS_PRIVATE = 0x19,
959 NVME_SC_NS_NOT_ATTACHED = 0x1a,
960 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
961 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
962 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
963 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
964 NVME_SC_INVALID_CTRLR_ID = 0x1f,
965 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
966 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
967 NVME_SC_INVALID_RESOURCE_ID = 0x22,
968 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
969 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
970 NVME_SC_ANA_ATTACH_FAILED = 0x25,
971
972 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
973 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
974 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
975 };
976
977 /* media error status codes */
978 enum nvme_media_error_status_code {
979 NVME_SC_WRITE_FAULTS = 0x80,
980 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
981 NVME_SC_GUARD_CHECK_ERROR = 0x82,
982 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
983 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
984 NVME_SC_COMPARE_FAILURE = 0x85,
985 NVME_SC_ACCESS_DENIED = 0x86,
986 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
987 };
988
989 /* path related status codes */
990 enum nvme_path_related_status_code {
991 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
992 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
993 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
994 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
995 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
996 NVME_SC_HOST_PATHING_ERROR = 0x70,
997 NVME_SC_COMMAND_ABORTED_BY_HOST = 0x71,
998 };
999
1000 /* admin opcodes */
1001 enum nvme_admin_opcode {
1002 NVME_OPC_DELETE_IO_SQ = 0x00,
1003 NVME_OPC_CREATE_IO_SQ = 0x01,
1004 NVME_OPC_GET_LOG_PAGE = 0x02,
1005 /* 0x03 - reserved */
1006 NVME_OPC_DELETE_IO_CQ = 0x04,
1007 NVME_OPC_CREATE_IO_CQ = 0x05,
1008 NVME_OPC_IDENTIFY = 0x06,
1009 /* 0x07 - reserved */
1010 NVME_OPC_ABORT = 0x08,
1011 NVME_OPC_SET_FEATURES = 0x09,
1012 NVME_OPC_GET_FEATURES = 0x0a,
1013 /* 0x0b - reserved */
1014 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
1015 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
1016 /* 0x0e-0x0f - reserved */
1017 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
1018 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
1019 /* 0x12-0x13 - reserved */
1020 NVME_OPC_DEVICE_SELF_TEST = 0x14,
1021 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
1022 /* 0x16-0x17 - reserved */
1023 NVME_OPC_KEEP_ALIVE = 0x18,
1024 NVME_OPC_DIRECTIVE_SEND = 0x19,
1025 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
1026 /* 0x1b - reserved */
1027 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
1028 NVME_OPC_NVME_MI_SEND = 0x1d,
1029 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
1030 /* 0x1f - reserved */
1031 NVME_OPC_CAPACITY_MANAGEMENT = 0x20,
1032 /* 0x21-0x23 - reserved */
1033 NVME_OPC_LOCKDOWN = 0x24,
1034 /* 0x25-0x7b - reserved */
1035 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
1036 /* 0x7d-0x7e - reserved */
1037 NVME_OPC_FABRICS_COMMANDS = 0x7f,
1038
1039 NVME_OPC_FORMAT_NVM = 0x80,
1040 NVME_OPC_SECURITY_SEND = 0x81,
1041 NVME_OPC_SECURITY_RECEIVE = 0x82,
1042 /* 0x83 - reserved */
1043 NVME_OPC_SANITIZE = 0x84,
1044 /* 0x85 - reserved */
1045 NVME_OPC_GET_LBA_STATUS = 0x86,
1046 };
1047
1048 /* nvme nvm opcodes */
1049 enum nvme_nvm_opcode {
1050 NVME_OPC_FLUSH = 0x00,
1051 NVME_OPC_WRITE = 0x01,
1052 NVME_OPC_READ = 0x02,
1053 /* 0x03 - reserved */
1054 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
1055 NVME_OPC_COMPARE = 0x05,
1056 /* 0x06-0x07 - reserved */
1057 NVME_OPC_WRITE_ZEROES = 0x08,
1058 NVME_OPC_DATASET_MANAGEMENT = 0x09,
1059 /* 0x0a-0x0b - reserved */
1060 NVME_OPC_VERIFY = 0x0c,
1061 NVME_OPC_RESERVATION_REGISTER = 0x0d,
1062 NVME_OPC_RESERVATION_REPORT = 0x0e,
1063 /* 0x0f-0x10 - reserved */
1064 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
1065 /* 0x12-0x14 - reserved */
1066 NVME_OPC_RESERVATION_RELEASE = 0x15,
1067 /* 0x16-0x18 - reserved */
1068 NVME_OPC_COPY = 0x19,
1069 };
1070
1071 enum nvme_feature {
1072 /* 0x00 - reserved */
1073 NVME_FEAT_ARBITRATION = 0x01,
1074 NVME_FEAT_POWER_MANAGEMENT = 0x02,
1075 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
1076 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
1077 NVME_FEAT_ERROR_RECOVERY = 0x05,
1078 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
1079 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
1080 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
1081 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
1082 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
1083 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
1084 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
1085 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
1086 NVME_FEAT_TIMESTAMP = 0x0E,
1087 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
1088 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
1089 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
1090 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
1091 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
1092 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
1093 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
1094 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
1095 NVME_FEAT_SANITIZE_CONFIG = 0x17,
1096 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
1097 /* 0x19-0x77 - reserved */
1098 /* 0x78-0x7f - NVMe Management Interface */
1099 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
1100 NVME_FEAT_HOST_IDENTIFIER = 0x81,
1101 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
1102 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
1103 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
1104 /* 0x85-0xBF - command set specific (reserved) */
1105 /* 0xC0-0xFF - vendor specific */
1106 };
1107
1108 enum nvme_dsm_attribute {
1109 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
1110 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
1111 NVME_DSM_ATTR_DEALLOCATE = 0x4,
1112 };
1113
1114 enum nvme_activate_action {
1115 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
1116 NVME_AA_REPLACE_ACTIVATE = 0x1,
1117 NVME_AA_ACTIVATE = 0x2,
1118 };
1119
1120 struct nvme_power_state {
1121 /** Maximum Power */
1122 uint16_t mp; /* Maximum Power */
1123 uint8_t ps_rsvd1;
1124 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
1125
1126 uint32_t enlat; /* Entry Latency */
1127 uint32_t exlat; /* Exit Latency */
1128
1129 uint8_t rrt; /* Relative Read Throughput */
1130 uint8_t rrl; /* Relative Read Latency */
1131 uint8_t rwt; /* Relative Write Throughput */
1132 uint8_t rwl; /* Relative Write Latency */
1133
1134 uint16_t idlp; /* Idle Power */
1135 uint8_t ips; /* Idle Power Scale */
1136 uint8_t ps_rsvd8;
1137
1138 uint16_t actp; /* Active Power */
1139 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
1140 uint8_t ps_rsvd10[9];
1141 } __packed;
1142
1143 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
1144
1145 #define NVME_SERIAL_NUMBER_LENGTH 20
1146 #define NVME_MODEL_NUMBER_LENGTH 40
1147 #define NVME_FIRMWARE_REVISION_LENGTH 8
1148
1149 struct nvme_controller_data {
1150 /* bytes 0-255: controller capabilities and features */
1151
1152 /** pci vendor id */
1153 uint16_t vid;
1154
1155 /** pci subsystem vendor id */
1156 uint16_t ssvid;
1157
1158 /** serial number */
1159 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
1160
1161 /** model number */
1162 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
1163
1164 /** firmware revision */
1165 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
1166
1167 /** recommended arbitration burst */
1168 uint8_t rab;
1169
1170 /** ieee oui identifier */
1171 uint8_t ieee[3];
1172
1173 /** multi-interface capabilities */
1174 uint8_t mic;
1175
1176 /** maximum data transfer size */
1177 uint8_t mdts;
1178
1179 /** Controller ID */
1180 uint16_t ctrlr_id;
1181
1182 /** Version */
1183 uint32_t ver;
1184
1185 /** RTD3 Resume Latency */
1186 uint32_t rtd3r;
1187
1188 /** RTD3 Enter Latency */
1189 uint32_t rtd3e;
1190
1191 /** Optional Asynchronous Events Supported */
1192 uint32_t oaes; /* bitfield really */
1193
1194 /** Controller Attributes */
1195 uint32_t ctratt; /* bitfield really */
1196
1197 /** Read Recovery Levels Supported */
1198 uint16_t rrls;
1199
1200 uint8_t reserved1[9];
1201
1202 /** Controller Type */
1203 uint8_t cntrltype;
1204
1205 /** FRU Globally Unique Identifier */
1206 uint8_t fguid[16];
1207
1208 /** Command Retry Delay Time 1 */
1209 uint16_t crdt1;
1210
1211 /** Command Retry Delay Time 2 */
1212 uint16_t crdt2;
1213
1214 /** Command Retry Delay Time 3 */
1215 uint16_t crdt3;
1216
1217 uint8_t reserved2[122];
1218
1219 /* bytes 256-511: admin command set attributes */
1220
1221 /** optional admin command support */
1222 uint16_t oacs;
1223
1224 /** abort command limit */
1225 uint8_t acl;
1226
1227 /** asynchronous event request limit */
1228 uint8_t aerl;
1229
1230 /** firmware updates */
1231 uint8_t frmw;
1232
1233 /** log page attributes */
1234 uint8_t lpa;
1235
1236 /** error log page entries */
1237 uint8_t elpe;
1238
1239 /** number of power states supported */
1240 uint8_t npss;
1241
1242 /** admin vendor specific command configuration */
1243 uint8_t avscc;
1244
1245 /** Autonomous Power State Transition Attributes */
1246 uint8_t apsta;
1247
1248 /** Warning Composite Temperature Threshold */
1249 uint16_t wctemp;
1250
1251 /** Critical Composite Temperature Threshold */
1252 uint16_t cctemp;
1253
1254 /** Maximum Time for Firmware Activation */
1255 uint16_t mtfa;
1256
1257 /** Host Memory Buffer Preferred Size */
1258 uint32_t hmpre;
1259
1260 /** Host Memory Buffer Minimum Size */
1261 uint32_t hmmin;
1262
1263 /** Name space capabilities */
1264 struct {
1265 /* if nsmgmt, report tnvmcap and unvmcap */
1266 uint8_t tnvmcap[16];
1267 uint8_t unvmcap[16];
1268 } __packed untncap;
1269
1270 /** Replay Protected Memory Block Support */
1271 uint32_t rpmbs; /* Really a bitfield */
1272
1273 /** Extended Device Self-test Time */
1274 uint16_t edstt;
1275
1276 /** Device Self-test Options */
1277 uint8_t dsto; /* Really a bitfield */
1278
1279 /** Firmware Update Granularity */
1280 uint8_t fwug;
1281
1282 /** Keep Alive Support */
1283 uint16_t kas;
1284
1285 /** Host Controlled Thermal Management Attributes */
1286 uint16_t hctma; /* Really a bitfield */
1287
1288 /** Minimum Thermal Management Temperature */
1289 uint16_t mntmt;
1290
1291 /** Maximum Thermal Management Temperature */
1292 uint16_t mxtmt;
1293
1294 /** Sanitize Capabilities */
1295 uint32_t sanicap; /* Really a bitfield */
1296
1297 /** Host Memory Buffer Minimum Descriptor Entry Size */
1298 uint32_t hmminds;
1299
1300 /** Host Memory Maximum Descriptors Entries */
1301 uint16_t hmmaxd;
1302
1303 /** NVM Set Identifier Maximum */
1304 uint16_t nsetidmax;
1305
1306 /** Endurance Group Identifier Maximum */
1307 uint16_t endgidmax;
1308
1309 /** ANA Transition Time */
1310 uint8_t anatt;
1311
1312 /** Asymmetric Namespace Access Capabilities */
1313 uint8_t anacap;
1314
1315 /** ANA Group Identifier Maximum */
1316 uint32_t anagrpmax;
1317
1318 /** Number of ANA Group Identifiers */
1319 uint32_t nanagrpid;
1320
1321 /** Persistent Event Log Size */
1322 uint32_t pels;
1323
1324 uint8_t reserved3[156];
1325 /* bytes 512-703: nvm command set attributes */
1326
1327 /** submission queue entry size */
1328 uint8_t sqes;
1329
1330 /** completion queue entry size */
1331 uint8_t cqes;
1332
1333 /** Maximum Outstanding Commands */
1334 uint16_t maxcmd;
1335
1336 /** number of namespaces */
1337 uint32_t nn;
1338
1339 /** optional nvm command support */
1340 uint16_t oncs;
1341
1342 /** fused operation support */
1343 uint16_t fuses;
1344
1345 /** format nvm attributes */
1346 uint8_t fna;
1347
1348 /** volatile write cache */
1349 uint8_t vwc;
1350
1351 /** Atomic Write Unit Normal */
1352 uint16_t awun;
1353
1354 /** Atomic Write Unit Power Fail */
1355 uint16_t awupf;
1356
1357 /** NVM Vendor Specific Command Configuration */
1358 uint8_t nvscc;
1359
1360 /** Namespace Write Protection Capabilities */
1361 uint8_t nwpc;
1362
1363 /** Atomic Compare & Write Unit */
1364 uint16_t acwu;
1365 uint16_t reserved6;
1366
1367 /** SGL Support */
1368 uint32_t sgls;
1369
1370 /** Maximum Number of Allowed Namespaces */
1371 uint32_t mnan;
1372
1373 /* bytes 540-767: Reserved */
1374 uint8_t reserved7[224];
1375
1376 /** NVM Subsystem NVMe Qualified Name */
1377 uint8_t subnqn[256];
1378
1379 /* bytes 1024-1791: Reserved */
1380 uint8_t reserved8[768];
1381
1382 /* bytes 1792-2047: NVMe over Fabrics specification */
1383 uint32_t ioccsz;
1384 uint32_t iorcsz;
1385 uint16_t icdoff;
1386 uint8_t fcatt;
1387 uint8_t msdbd;
1388 uint16_t ofcs;
1389 uint8_t reserved9[242];
1390
1391 /* bytes 2048-3071: power state descriptors */
1392 struct nvme_power_state power_state[32];
1393
1394 /* bytes 3072-4095: vendor specific */
1395 uint8_t vs[1024];
1396 } __packed __aligned(4);
1397
1398 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1399
1400 struct nvme_namespace_data {
1401 /** namespace size */
1402 uint64_t nsze;
1403
1404 /** namespace capacity */
1405 uint64_t ncap;
1406
1407 /** namespace utilization */
1408 uint64_t nuse;
1409
1410 /** namespace features */
1411 uint8_t nsfeat;
1412
1413 /** number of lba formats */
1414 uint8_t nlbaf;
1415
1416 /** formatted lba size */
1417 uint8_t flbas;
1418
1419 /** metadata capabilities */
1420 uint8_t mc;
1421
1422 /** end-to-end data protection capabilities */
1423 uint8_t dpc;
1424
1425 /** end-to-end data protection type settings */
1426 uint8_t dps;
1427
1428 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1429 uint8_t nmic;
1430
1431 /** Reservation Capabilities */
1432 uint8_t rescap;
1433
1434 /** Format Progress Indicator */
1435 uint8_t fpi;
1436
1437 /** Deallocate Logical Block Features */
1438 uint8_t dlfeat;
1439
1440 /** Namespace Atomic Write Unit Normal */
1441 uint16_t nawun;
1442
1443 /** Namespace Atomic Write Unit Power Fail */
1444 uint16_t nawupf;
1445
1446 /** Namespace Atomic Compare & Write Unit */
1447 uint16_t nacwu;
1448
1449 /** Namespace Atomic Boundary Size Normal */
1450 uint16_t nabsn;
1451
1452 /** Namespace Atomic Boundary Offset */
1453 uint16_t nabo;
1454
1455 /** Namespace Atomic Boundary Size Power Fail */
1456 uint16_t nabspf;
1457
1458 /** Namespace Optimal IO Boundary */
1459 uint16_t noiob;
1460
1461 /** NVM Capacity */
1462 uint8_t nvmcap[16];
1463
1464 /** Namespace Preferred Write Granularity */
1465 uint16_t npwg;
1466
1467 /** Namespace Preferred Write Alignment */
1468 uint16_t npwa;
1469
1470 /** Namespace Preferred Deallocate Granularity */
1471 uint16_t npdg;
1472
1473 /** Namespace Preferred Deallocate Alignment */
1474 uint16_t npda;
1475
1476 /** Namespace Optimal Write Size */
1477 uint16_t nows;
1478
1479 /* bytes 74-91: Reserved */
1480 uint8_t reserved5[18];
1481
1482 /** ANA Group Identifier */
1483 uint32_t anagrpid;
1484
1485 /* bytes 96-98: Reserved */
1486 uint8_t reserved6[3];
1487
1488 /** Namespace Attributes */
1489 uint8_t nsattr;
1490
1491 /** NVM Set Identifier */
1492 uint16_t nvmsetid;
1493
1494 /** Endurance Group Identifier */
1495 uint16_t endgid;
1496
1497 /** Namespace Globally Unique Identifier */
1498 uint8_t nguid[16];
1499
1500 /** IEEE Extended Unique Identifier */
1501 uint8_t eui64[8];
1502
1503 /** lba format support */
1504 uint32_t lbaf[16];
1505
1506 uint8_t reserved7[192];
1507
1508 uint8_t vendor_specific[3712];
1509 } __packed __aligned(4);
1510
1511 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1512
1513 enum nvme_log_page {
1514 /* 0x00 - reserved */
1515 NVME_LOG_ERROR = 0x01,
1516 NVME_LOG_HEALTH_INFORMATION = 0x02,
1517 NVME_LOG_FIRMWARE_SLOT = 0x03,
1518 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1519 NVME_LOG_COMMAND_EFFECT = 0x05,
1520 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1521 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1522 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1523 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1524 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1525 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1526 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1527 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1528 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1529 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1530 NVME_LOG_DISCOVERY = 0x70,
1531 /* 0x06-0x7F - reserved */
1532 /* 0x80-0xBF - I/O command set specific */
1533 NVME_LOG_RES_NOTIFICATION = 0x80,
1534 NVME_LOG_SANITIZE_STATUS = 0x81,
1535 /* 0x82-0xBF - reserved */
1536 /* 0xC0-0xFF - vendor specific */
1537
1538 /*
1539 * The following are Intel Specific log pages, but they seem
1540 * to be widely implemented.
1541 */
1542 INTEL_LOG_READ_LAT_LOG = 0xc1,
1543 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1544 INTEL_LOG_TEMP_STATS = 0xc5,
1545 INTEL_LOG_ADD_SMART = 0xca,
1546 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1547
1548 /*
1549 * HGST log page, with lots ofs sub pages.
1550 */
1551 HGST_INFO_LOG = 0xc1,
1552 };
1553
1554 struct nvme_error_information_entry {
1555 uint64_t error_count;
1556 uint16_t sqid;
1557 uint16_t cid;
1558 uint16_t status;
1559 uint16_t error_location;
1560 uint64_t lba;
1561 uint32_t nsid;
1562 uint8_t vendor_specific;
1563 uint8_t trtype;
1564 uint16_t reserved30;
1565 uint64_t csi;
1566 uint16_t ttsi;
1567 uint8_t reserved[22];
1568 } __packed __aligned(4);
1569
1570 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1571
1572 struct nvme_health_information_page {
1573 uint8_t critical_warning;
1574 uint16_t temperature;
1575 uint8_t available_spare;
1576 uint8_t available_spare_threshold;
1577 uint8_t percentage_used;
1578
1579 uint8_t reserved[26];
1580
1581 /*
1582 * Note that the following are 128-bit values, but are
1583 * defined as an array of 2 64-bit values.
1584 */
1585 /* Data Units Read is always in 512-byte units. */
1586 uint64_t data_units_read[2];
1587 /* Data Units Written is always in 512-byte units. */
1588 uint64_t data_units_written[2];
1589 /* For NVM command set, this includes Compare commands. */
1590 uint64_t host_read_commands[2];
1591 uint64_t host_write_commands[2];
1592 /* Controller Busy Time is reported in minutes. */
1593 uint64_t controller_busy_time[2];
1594 uint64_t power_cycles[2];
1595 uint64_t power_on_hours[2];
1596 uint64_t unsafe_shutdowns[2];
1597 uint64_t media_errors[2];
1598 uint64_t num_error_info_log_entries[2];
1599 uint32_t warning_temp_time;
1600 uint32_t error_temp_time;
1601 uint16_t temp_sensor[8];
1602 /* Thermal Management Temperature 1 Transition Count */
1603 uint32_t tmt1tc;
1604 /* Thermal Management Temperature 2 Transition Count */
1605 uint32_t tmt2tc;
1606 /* Total Time For Thermal Management Temperature 1 */
1607 uint32_t ttftmt1;
1608 /* Total Time For Thermal Management Temperature 2 */
1609 uint32_t ttftmt2;
1610
1611 uint8_t reserved2[280];
1612 } __packed __aligned(8);
1613
1614 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1615
1616 struct nvme_firmware_page {
1617 uint8_t afi;
1618 uint8_t reserved[7];
1619 /* revisions for 7 slots */
1620 uint8_t revision[7][NVME_FIRMWARE_REVISION_LENGTH];
1621 uint8_t reserved2[448];
1622 } __packed __aligned(4);
1623
1624 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1625
1626 struct nvme_ns_list {
1627 uint32_t ns[1024];
1628 } __packed __aligned(4);
1629
1630 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1631
1632 struct nvme_command_effects_page {
1633 uint32_t acs[256];
1634 uint32_t iocs[256];
1635 uint8_t reserved[2048];
1636 } __packed __aligned(4);
1637
1638 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1639 "bad size for nvme_command_effects_page");
1640
1641 struct nvme_device_self_test_page {
1642 uint8_t curr_operation;
1643 uint8_t curr_compl;
1644 uint8_t rsvd2[2];
1645 struct {
1646 uint8_t status;
1647 uint8_t segment_num;
1648 uint8_t valid_diag_info;
1649 uint8_t rsvd3;
1650 uint64_t poh;
1651 uint32_t nsid;
1652 /* Define as an array to simplify alignment issues */
1653 uint8_t failing_lba[8];
1654 uint8_t status_code_type;
1655 uint8_t status_code;
1656 uint8_t vendor_specific[2];
1657 } __packed result[20];
1658 } __packed __aligned(4);
1659
1660 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1661 "bad size for nvme_device_self_test_page");
1662
1663 /*
1664 * Header structure for both host initiated telemetry (page 7) and controller
1665 * initiated telemetry (page 8).
1666 */
1667 struct nvme_telemetry_log_page {
1668 uint8_t identifier;
1669 uint8_t rsvd[4];
1670 uint8_t oui[3];
1671 uint16_t da1_last;
1672 uint16_t da2_last;
1673 uint16_t da3_last;
1674 uint8_t rsvd2[2];
1675 uint32_t da4_last;
1676 uint8_t rsvd3[361];
1677 uint8_t hi_gen;
1678 uint8_t ci_avail;
1679 uint8_t ci_gen;
1680 uint8_t reason[128];
1681 /* Blocks of telemetry data follow */
1682 } __packed __aligned(4);
1683
1684 _Static_assert(sizeof(struct nvme_telemetry_log_page) == 512,
1685 "bad size for nvme_telemetry_log");
1686
1687 struct nvme_discovery_log_entry {
1688 uint8_t trtype;
1689 uint8_t adrfam;
1690 uint8_t subtype;
1691 uint8_t treq;
1692 uint16_t portid;
1693 uint16_t cntlid;
1694 uint16_t aqsz;
1695 uint8_t reserved1[22];
1696 uint8_t trsvcid[32];
1697 uint8_t reserved2[192];
1698 uint8_t subnqn[256];
1699 uint8_t traddr[256];
1700 union {
1701 struct {
1702 uint8_t rdma_qptype;
1703 uint8_t rdma_prtype;
1704 uint8_t rdma_cms;
1705 uint8_t reserved[5];
1706 uint16_t rdma_pkey;
1707 } rdma;
1708 struct {
1709 uint8_t sectype;
1710 } tcp;
1711 uint8_t reserved[256];
1712 } tsas;
1713 } __packed __aligned(4);
1714
1715 _Static_assert(sizeof(struct nvme_discovery_log_entry) == 1024,
1716 "bad size for nvme_discovery_log_entry");
1717
1718 struct nvme_discovery_log {
1719 uint64_t genctr;
1720 uint64_t numrec;
1721 uint16_t recfmt;
1722 uint8_t reserved[1006];
1723 struct nvme_discovery_log_entry entries[];
1724 } __packed __aligned(4);
1725
1726 _Static_assert(sizeof(struct nvme_discovery_log) == 1024,
1727 "bad size for nvme_discovery_log");
1728
1729 struct nvme_res_notification_page {
1730 uint64_t log_page_count;
1731 uint8_t log_page_type;
1732 uint8_t available_log_pages;
1733 uint8_t reserved2;
1734 uint32_t nsid;
1735 uint8_t reserved[48];
1736 } __packed __aligned(4);
1737
1738 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1739 "bad size for nvme_res_notification_page");
1740
1741 struct nvme_sanitize_status_page {
1742 uint16_t sprog;
1743 uint16_t sstat;
1744 uint32_t scdw10;
1745 uint32_t etfo;
1746 uint32_t etfbe;
1747 uint32_t etfce;
1748 uint32_t etfownd;
1749 uint32_t etfbewnd;
1750 uint32_t etfcewnd;
1751 uint8_t reserved[480];
1752 } __packed __aligned(4);
1753
1754 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1755 "bad size for nvme_sanitize_status_page");
1756
1757 struct intel_log_temp_stats {
1758 uint64_t current;
1759 uint64_t overtemp_flag_last;
1760 uint64_t overtemp_flag_life;
1761 uint64_t max_temp;
1762 uint64_t min_temp;
1763 uint64_t _rsvd[5];
1764 uint64_t max_oper_temp;
1765 uint64_t min_oper_temp;
1766 uint64_t est_offset;
1767 } __packed __aligned(4);
1768
1769 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1770
1771 struct nvme_resv_reg_ctrlr {
1772 uint16_t ctrlr_id; /* Controller ID */
1773 uint8_t rcsts; /* Reservation Status */
1774 uint8_t reserved3[5];
1775 uint64_t hostid; /* Host Identifier */
1776 uint64_t rkey; /* Reservation Key */
1777 } __packed __aligned(4);
1778
1779 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1780
1781 struct nvme_resv_reg_ctrlr_ext {
1782 uint16_t ctrlr_id; /* Controller ID */
1783 uint8_t rcsts; /* Reservation Status */
1784 uint8_t reserved3[5];
1785 uint64_t rkey; /* Reservation Key */
1786 uint64_t hostid[2]; /* Host Identifier */
1787 uint8_t reserved32[32];
1788 } __packed __aligned(4);
1789
1790 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1791
1792 struct nvme_resv_status {
1793 uint32_t gen; /* Generation */
1794 uint8_t rtype; /* Reservation Type */
1795 uint8_t regctl[2]; /* Number of Registered Controllers */
1796 uint8_t reserved7[2];
1797 uint8_t ptpls; /* Persist Through Power Loss State */
1798 uint8_t reserved10[14];
1799 struct nvme_resv_reg_ctrlr ctrlr[0];
1800 } __packed __aligned(4);
1801
1802 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1803
1804 struct nvme_resv_status_ext {
1805 uint32_t gen; /* Generation */
1806 uint8_t rtype; /* Reservation Type */
1807 uint8_t regctl[2]; /* Number of Registered Controllers */
1808 uint8_t reserved7[2];
1809 uint8_t ptpls; /* Persist Through Power Loss State */
1810 uint8_t reserved10[14];
1811 uint8_t reserved24[40];
1812 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1813 } __packed __aligned(4);
1814
1815 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1816
1817 #define NVME_TEST_MAX_THREADS 128
1818
1819 struct nvme_io_test {
1820 enum nvme_nvm_opcode opc;
1821 uint32_t size;
1822 uint32_t time; /* in seconds */
1823 uint32_t num_threads;
1824 uint32_t flags;
1825 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1826 };
1827
1828 enum nvme_io_test_flags {
1829 /*
1830 * Specifies whether dev_refthread/dev_relthread should be
1831 * called during NVME_BIO_TEST. Ignored for other test
1832 * types.
1833 */
1834 NVME_TEST_FLAG_REFTHREAD = 0x1,
1835 };
1836
1837 struct nvme_pt_command {
1838 /*
1839 * cmd is used to specify a passthrough command to a controller or
1840 * namespace.
1841 *
1842 * The following fields from cmd may be specified by the caller:
1843 * * opc (opcode)
1844 * * nsid (namespace id) - for admin commands only
1845 * * cdw10-cdw15
1846 *
1847 * Remaining fields must be set to 0 by the caller.
1848 */
1849 struct nvme_command cmd;
1850
1851 /*
1852 * cpl returns completion status for the passthrough command
1853 * specified by cmd.
1854 *
1855 * The following fields will be filled out by the driver, for
1856 * consumption by the caller:
1857 * * cdw0
1858 * * status (except for phase)
1859 *
1860 * Remaining fields will be set to 0 by the driver.
1861 */
1862 struct nvme_completion cpl;
1863
1864 /* buf is the data buffer associated with this passthrough command. */
1865 void * buf;
1866
1867 /*
1868 * len is the length of the data buffer associated with this
1869 * passthrough command.
1870 */
1871 uint32_t len;
1872
1873 /*
1874 * is_read = 1 if the passthrough command will read data into the
1875 * supplied buffer from the controller.
1876 *
1877 * is_read = 0 if the passthrough command will write data from the
1878 * supplied buffer to the controller.
1879 */
1880 uint32_t is_read;
1881
1882 /*
1883 * driver_lock is used by the driver only. It must be set to 0
1884 * by the caller.
1885 */
1886 struct mtx * driver_lock;
1887 };
1888
1889 struct nvme_get_nsid {
1890 char cdev[SPECNAMELEN + 1];
1891 uint32_t nsid;
1892 };
1893
1894 struct nvme_hmb_desc {
1895 uint64_t addr;
1896 uint32_t size;
1897 uint32_t reserved;
1898 };
1899
1900 #define nvme_completion_is_error(cpl) \
1901 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1902
1903 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1904
1905 #ifdef _KERNEL
1906
1907 struct bio;
1908 struct thread;
1909
1910 struct nvme_namespace;
1911 struct nvme_controller;
1912 struct nvme_consumer;
1913 struct nvme_passthru_cmd;
1914
1915 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1916
1917 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1918 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1919 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1920 uint32_t, void *, uint32_t);
1921 typedef void (*nvme_cons_fail_fn_t)(void *);
1922
1923 enum nvme_namespace_flags {
1924 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
1925 NVME_NS_FLUSH_SUPPORTED = 0x2,
1926 };
1927
1928 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1929 struct nvme_pt_command *pt,
1930 uint32_t nsid, int is_user_buffer,
1931 int is_admin_cmd);
1932
1933 int nvme_ctrlr_linux_passthru_cmd(struct nvme_controller *ctrlr,
1934 struct nvme_passthru_cmd *npc,
1935 uint32_t nsid, bool is_user,
1936 bool is_admin);
1937
1938 /* Admin functions */
1939 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1940 uint8_t feature, uint32_t cdw11,
1941 uint32_t cdw12, uint32_t cdw13,
1942 uint32_t cdw14, uint32_t cdw15,
1943 void *payload, uint32_t payload_size,
1944 nvme_cb_fn_t cb_fn, void *cb_arg);
1945 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1946 uint8_t feature, uint32_t cdw11,
1947 void *payload, uint32_t payload_size,
1948 nvme_cb_fn_t cb_fn, void *cb_arg);
1949 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1950 uint8_t log_page, uint32_t nsid,
1951 void *payload, uint32_t payload_size,
1952 nvme_cb_fn_t cb_fn, void *cb_arg);
1953
1954 /* NVM I/O functions */
1955 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1956 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1957 void *cb_arg);
1958 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1959 nvme_cb_fn_t cb_fn, void *cb_arg);
1960 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1961 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1962 void *cb_arg);
1963 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1964 nvme_cb_fn_t cb_fn, void *cb_arg);
1965 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1966 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1967 void *cb_arg);
1968 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1969 void *cb_arg);
1970 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1971 size_t len);
1972
1973 /* Registration functions */
1974 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1975 nvme_cons_ctrlr_fn_t ctrlr_fn,
1976 nvme_cons_async_fn_t async_fn,
1977 nvme_cons_fail_fn_t fail_fn);
1978 void nvme_unregister_consumer(struct nvme_consumer *consumer);
1979
1980 /* Controller helper functions */
1981 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1982 const struct nvme_controller_data *
1983 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1984 static inline bool
nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data * cd)1985 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1986 {
1987 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1988 return (NVMEV(NVME_CTRLR_DATA_ONCS_DSM, cd->oncs) != 0);
1989 }
1990
1991 /* Namespace helper functions */
1992 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1993 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
1994 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1995 uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
1996 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
1997 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
1998 const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
1999 const struct nvme_namespace_data *
2000 nvme_ns_get_data(struct nvme_namespace *ns);
2001 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
2002
2003 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
2004 nvme_cb_fn_t cb_fn);
2005 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
2006 caddr_t arg, int flag, struct thread *td);
2007
2008 /*
2009 * Command building helper functions -- shared with CAM
2010 * These functions assume allocator zeros out cmd structure
2011 * CAM's xpt_get_ccb and the request allocator for nvme both
2012 * do zero'd allocations.
2013 */
2014 static inline
nvme_ns_flush_cmd(struct nvme_command * cmd,uint32_t nsid)2015 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
2016 {
2017
2018 cmd->opc = NVME_OPC_FLUSH;
2019 cmd->nsid = htole32(nsid);
2020 }
2021
2022 static inline
nvme_ns_rw_cmd(struct nvme_command * cmd,uint32_t rwcmd,uint32_t nsid,uint64_t lba,uint32_t count)2023 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
2024 uint64_t lba, uint32_t count)
2025 {
2026 cmd->opc = rwcmd;
2027 cmd->nsid = htole32(nsid);
2028 cmd->cdw10 = htole32(lba & 0xffffffffu);
2029 cmd->cdw11 = htole32(lba >> 32);
2030 cmd->cdw12 = htole32(count-1);
2031 }
2032
2033 static inline
nvme_ns_write_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)2034 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
2035 uint64_t lba, uint32_t count)
2036 {
2037 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
2038 }
2039
2040 static inline
nvme_ns_read_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)2041 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
2042 uint64_t lba, uint32_t count)
2043 {
2044 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
2045 }
2046
2047 static inline
nvme_ns_trim_cmd(struct nvme_command * cmd,uint32_t nsid,uint32_t num_ranges)2048 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
2049 uint32_t num_ranges)
2050 {
2051 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
2052 cmd->nsid = htole32(nsid);
2053 cmd->cdw10 = htole32(num_ranges - 1);
2054 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
2055 }
2056
2057 extern int nvme_use_nvd;
2058
2059 #endif /* _KERNEL */
2060
2061 /* Endianess conversion functions for NVMe structs */
2062 static inline
nvme_completion_swapbytes(struct nvme_completion * s __unused)2063 void nvme_completion_swapbytes(struct nvme_completion *s __unused)
2064 {
2065 #if _BYTE_ORDER != _LITTLE_ENDIAN
2066
2067 s->cdw0 = le32toh(s->cdw0);
2068 /* omit rsvd1 */
2069 s->sqhd = le16toh(s->sqhd);
2070 s->sqid = le16toh(s->sqid);
2071 /* omit cid */
2072 s->status = le16toh(s->status);
2073 #endif
2074 }
2075
2076 static inline
nvme_power_state_swapbytes(struct nvme_power_state * s __unused)2077 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
2078 {
2079 #if _BYTE_ORDER != _LITTLE_ENDIAN
2080
2081 s->mp = le16toh(s->mp);
2082 s->enlat = le32toh(s->enlat);
2083 s->exlat = le32toh(s->exlat);
2084 s->idlp = le16toh(s->idlp);
2085 s->actp = le16toh(s->actp);
2086 #endif
2087 }
2088
2089 static inline
nvme_controller_data_swapbytes(struct nvme_controller_data * s __unused)2090 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
2091 {
2092 #if _BYTE_ORDER != _LITTLE_ENDIAN
2093 int i;
2094
2095 s->vid = le16toh(s->vid);
2096 s->ssvid = le16toh(s->ssvid);
2097 s->ctrlr_id = le16toh(s->ctrlr_id);
2098 s->ver = le32toh(s->ver);
2099 s->rtd3r = le32toh(s->rtd3r);
2100 s->rtd3e = le32toh(s->rtd3e);
2101 s->oaes = le32toh(s->oaes);
2102 s->ctratt = le32toh(s->ctratt);
2103 s->rrls = le16toh(s->rrls);
2104 s->crdt1 = le16toh(s->crdt1);
2105 s->crdt2 = le16toh(s->crdt2);
2106 s->crdt3 = le16toh(s->crdt3);
2107 s->oacs = le16toh(s->oacs);
2108 s->wctemp = le16toh(s->wctemp);
2109 s->cctemp = le16toh(s->cctemp);
2110 s->mtfa = le16toh(s->mtfa);
2111 s->hmpre = le32toh(s->hmpre);
2112 s->hmmin = le32toh(s->hmmin);
2113 s->rpmbs = le32toh(s->rpmbs);
2114 s->edstt = le16toh(s->edstt);
2115 s->kas = le16toh(s->kas);
2116 s->hctma = le16toh(s->hctma);
2117 s->mntmt = le16toh(s->mntmt);
2118 s->mxtmt = le16toh(s->mxtmt);
2119 s->sanicap = le32toh(s->sanicap);
2120 s->hmminds = le32toh(s->hmminds);
2121 s->hmmaxd = le16toh(s->hmmaxd);
2122 s->nsetidmax = le16toh(s->nsetidmax);
2123 s->endgidmax = le16toh(s->endgidmax);
2124 s->anagrpmax = le32toh(s->anagrpmax);
2125 s->nanagrpid = le32toh(s->nanagrpid);
2126 s->pels = le32toh(s->pels);
2127 s->maxcmd = le16toh(s->maxcmd);
2128 s->nn = le32toh(s->nn);
2129 s->oncs = le16toh(s->oncs);
2130 s->fuses = le16toh(s->fuses);
2131 s->awun = le16toh(s->awun);
2132 s->awupf = le16toh(s->awupf);
2133 s->acwu = le16toh(s->acwu);
2134 s->sgls = le32toh(s->sgls);
2135 s->mnan = le32toh(s->mnan);
2136 s->ioccsz = le32toh(s->ioccsz);
2137 s->iorcsz = le32toh(s->iorcsz);
2138 s->icdoff = le16toh(s->icdoff);
2139 s->ofcs = le16toh(s->ofcs);
2140 for (i = 0; i < 32; i++)
2141 nvme_power_state_swapbytes(&s->power_state[i]);
2142 #endif
2143 }
2144
2145 static inline
nvme_namespace_data_swapbytes(struct nvme_namespace_data * s __unused)2146 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
2147 {
2148 #if _BYTE_ORDER != _LITTLE_ENDIAN
2149 int i;
2150
2151 s->nsze = le64toh(s->nsze);
2152 s->ncap = le64toh(s->ncap);
2153 s->nuse = le64toh(s->nuse);
2154 s->nawun = le16toh(s->nawun);
2155 s->nawupf = le16toh(s->nawupf);
2156 s->nacwu = le16toh(s->nacwu);
2157 s->nabsn = le16toh(s->nabsn);
2158 s->nabo = le16toh(s->nabo);
2159 s->nabspf = le16toh(s->nabspf);
2160 s->noiob = le16toh(s->noiob);
2161 s->npwg = le16toh(s->npwg);
2162 s->npwa = le16toh(s->npwa);
2163 s->npdg = le16toh(s->npdg);
2164 s->npda = le16toh(s->npda);
2165 s->nows = le16toh(s->nows);
2166 s->anagrpid = le32toh(s->anagrpid);
2167 s->nvmsetid = le16toh(s->nvmsetid);
2168 s->endgid = le16toh(s->endgid);
2169 for (i = 0; i < 16; i++)
2170 s->lbaf[i] = le32toh(s->lbaf[i]);
2171 #endif
2172 }
2173
2174 static inline
nvme_error_information_entry_swapbytes(struct nvme_error_information_entry * s __unused)2175 void nvme_error_information_entry_swapbytes(
2176 struct nvme_error_information_entry *s __unused)
2177 {
2178 #if _BYTE_ORDER != _LITTLE_ENDIAN
2179
2180 s->error_count = le64toh(s->error_count);
2181 s->sqid = le16toh(s->sqid);
2182 s->cid = le16toh(s->cid);
2183 s->status = le16toh(s->status);
2184 s->error_location = le16toh(s->error_location);
2185 s->lba = le64toh(s->lba);
2186 s->nsid = le32toh(s->nsid);
2187 s->csi = le64toh(s->csi);
2188 s->ttsi = le16toh(s->ttsi);
2189 #endif
2190 }
2191
2192 static inline
nvme_le128toh(void * p __unused)2193 void nvme_le128toh(void *p __unused)
2194 {
2195 #if _BYTE_ORDER != _LITTLE_ENDIAN
2196 /* Swap 16 bytes in place */
2197 char *tmp = (char*)p;
2198 char b;
2199 int i;
2200 for (i = 0; i < 8; i++) {
2201 b = tmp[i];
2202 tmp[i] = tmp[15-i];
2203 tmp[15-i] = b;
2204 }
2205 #endif
2206 }
2207
2208 static inline
nvme_health_information_page_swapbytes(struct nvme_health_information_page * s __unused)2209 void nvme_health_information_page_swapbytes(
2210 struct nvme_health_information_page *s __unused)
2211 {
2212 #if _BYTE_ORDER != _LITTLE_ENDIAN
2213 int i;
2214
2215 s->temperature = le16toh(s->temperature);
2216 nvme_le128toh((void *)s->data_units_read);
2217 nvme_le128toh((void *)s->data_units_written);
2218 nvme_le128toh((void *)s->host_read_commands);
2219 nvme_le128toh((void *)s->host_write_commands);
2220 nvme_le128toh((void *)s->controller_busy_time);
2221 nvme_le128toh((void *)s->power_cycles);
2222 nvme_le128toh((void *)s->power_on_hours);
2223 nvme_le128toh((void *)s->unsafe_shutdowns);
2224 nvme_le128toh((void *)s->media_errors);
2225 nvme_le128toh((void *)s->num_error_info_log_entries);
2226 s->warning_temp_time = le32toh(s->warning_temp_time);
2227 s->error_temp_time = le32toh(s->error_temp_time);
2228 for (i = 0; i < 8; i++)
2229 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
2230 s->tmt1tc = le32toh(s->tmt1tc);
2231 s->tmt2tc = le32toh(s->tmt2tc);
2232 s->ttftmt1 = le32toh(s->ttftmt1);
2233 s->ttftmt2 = le32toh(s->ttftmt2);
2234 #endif
2235 }
2236
2237 static inline
nvme_ns_list_swapbytes(struct nvme_ns_list * s __unused)2238 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2239 {
2240 #if _BYTE_ORDER != _LITTLE_ENDIAN
2241 int i;
2242
2243 for (i = 0; i < 1024; i++)
2244 s->ns[i] = le32toh(s->ns[i]);
2245 #endif
2246 }
2247
2248 static inline
nvme_command_effects_page_swapbytes(struct nvme_command_effects_page * s __unused)2249 void nvme_command_effects_page_swapbytes(
2250 struct nvme_command_effects_page *s __unused)
2251 {
2252 #if _BYTE_ORDER != _LITTLE_ENDIAN
2253 int i;
2254
2255 for (i = 0; i < 256; i++)
2256 s->acs[i] = le32toh(s->acs[i]);
2257 for (i = 0; i < 256; i++)
2258 s->iocs[i] = le32toh(s->iocs[i]);
2259 #endif
2260 }
2261
2262 static inline
nvme_res_notification_page_swapbytes(struct nvme_res_notification_page * s __unused)2263 void nvme_res_notification_page_swapbytes(
2264 struct nvme_res_notification_page *s __unused)
2265 {
2266 #if _BYTE_ORDER != _LITTLE_ENDIAN
2267 s->log_page_count = le64toh(s->log_page_count);
2268 s->nsid = le32toh(s->nsid);
2269 #endif
2270 }
2271
2272 static inline
nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page * s __unused)2273 void nvme_sanitize_status_page_swapbytes(
2274 struct nvme_sanitize_status_page *s __unused)
2275 {
2276 #if _BYTE_ORDER != _LITTLE_ENDIAN
2277 s->sprog = le16toh(s->sprog);
2278 s->sstat = le16toh(s->sstat);
2279 s->scdw10 = le32toh(s->scdw10);
2280 s->etfo = le32toh(s->etfo);
2281 s->etfbe = le32toh(s->etfbe);
2282 s->etfce = le32toh(s->etfce);
2283 s->etfownd = le32toh(s->etfownd);
2284 s->etfbewnd = le32toh(s->etfbewnd);
2285 s->etfcewnd = le32toh(s->etfcewnd);
2286 #endif
2287 }
2288
2289 static inline
nvme_resv_status_swapbytes(struct nvme_resv_status * s __unused,size_t size __unused)2290 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2291 size_t size __unused)
2292 {
2293 #if _BYTE_ORDER != _LITTLE_ENDIAN
2294 size_t i, n;
2295
2296 s->gen = le32toh(s->gen);
2297 n = (s->regctl[1] << 8) | s->regctl[0];
2298 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2299 for (i = 0; i < n; i++) {
2300 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2301 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2302 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2303 }
2304 #endif
2305 }
2306
2307 static inline
nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext * s __unused,size_t size __unused)2308 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2309 size_t size __unused)
2310 {
2311 #if _BYTE_ORDER != _LITTLE_ENDIAN
2312 size_t i, n;
2313
2314 s->gen = le32toh(s->gen);
2315 n = (s->regctl[1] << 8) | s->regctl[0];
2316 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2317 for (i = 0; i < n; i++) {
2318 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2319 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2320 nvme_le128toh((void *)s->ctrlr[i].hostid);
2321 }
2322 #endif
2323 }
2324
2325 static inline void
nvme_device_self_test_swapbytes(struct nvme_device_self_test_page * s __unused)2326 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2327 {
2328 #if _BYTE_ORDER != _LITTLE_ENDIAN
2329 uint8_t *tmp;
2330 uint32_t r, i;
2331 uint8_t b;
2332
2333 for (r = 0; r < 20; r++) {
2334 s->result[r].poh = le64toh(s->result[r].poh);
2335 s->result[r].nsid = le32toh(s->result[r].nsid);
2336 /* Unaligned 64-bit loads fail on some architectures */
2337 tmp = s->result[r].failing_lba;
2338 for (i = 0; i < 4; i++) {
2339 b = tmp[i];
2340 tmp[i] = tmp[7-i];
2341 tmp[7-i] = b;
2342 }
2343 }
2344 #endif
2345 }
2346
2347 static inline void
nvme_discovery_log_entry_swapbytes(struct nvme_discovery_log_entry * s __unused)2348 nvme_discovery_log_entry_swapbytes(struct nvme_discovery_log_entry *s __unused)
2349 {
2350 #if _BYTE_ORDER != _LITTLE_ENDIAN
2351 s->portid = le16toh(s->portid);
2352 s->cntlid = le16toh(s->cntlid);
2353 s->aqsz = le16toh(s->aqsz);
2354 if (s->trtype == 0x01 /* RDMA */) {
2355 s->tsas.rdma.rdma_pkey = le16toh(s->tsas.rdma.rdma_pkey);
2356 }
2357 #endif
2358 }
2359
2360 static inline void
nvme_discovery_log_swapbytes(struct nvme_discovery_log * s __unused)2361 nvme_discovery_log_swapbytes(struct nvme_discovery_log *s __unused)
2362 {
2363 #if _BYTE_ORDER != _LITTLE_ENDIAN
2364 s->genctr = le64toh(s->genctr);
2365 s->numrec = le64toh(s->numrec);
2366 s->recfmt = le16toh(s->recfmt);
2367 #endif
2368 }
2369 #endif /* __NVME_H__ */
2370