| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.h | 32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
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| H A D | RegAllocGreedy.cpp | 400 AllocationOrder &Order, in tryAssign()
534 const AllocationOrder &Order, in getOrderLimit()
580 AllocationOrder &Order, in tryEvict()
1063 AllocationOrder &Order, in tryRegionSplit()
1097 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1236 AllocationOrder &Order) { in trySplitAroundHintReg()
1296 AllocationOrder &Order, in tryBlockSplit()
1417 AllocationOrder &Order, in tryInstructionSplit()
1570 AllocationOrder &Order, in tryLocalSplit()
1957 AllocationOrder &Order, in tryLastChanceRecoloring()
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| H A D | AllocationOrder.cpp | 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
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| H A D | LocalStackSlotAllocation.cpp | 58 unsigned Order; member in __anon9aa42e250111::FrameRef
304 unsigned Order = 0; in insertFrameReferenceRegisters() local
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| H A D | RegAllocBasic.cpp | 265 auto Order = in selectOrSplit() local
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| H A D | BreakFalseDeps.cpp | 156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
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| H A D | RegAllocEvictionAdvisor.cpp | 276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
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| H A D | TargetRegisterInfo.cpp | 252 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
424 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| H A D | CriticalAntiDepBreaker.cpp | 399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister() local
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| H A D | MLRegAllocEvictAdvisor.cpp | 664 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
1085 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition()
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| H A D | AggressiveAntiDepBreaker.cpp | 609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters() local
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DynamicLibrary.cpp | 81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 149 unsigned Order; variable
245 unsigned Order; variable
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| H A D | ScheduleDAGSDNodes.cpp | 739 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
787 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
982 unsigned Order = Orders[i].first; in EmitSchedule() local
1028 unsigned Order = InstrOrder.first; in EmitSchedule() local
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| H A D | SelectionDAGDumper.cpp | 861 if (unsigned Order = getIROrder()) in print_details() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 36 std::unique_ptr<MCPhysReg[]> Order; member
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| H A D | ScheduleDAG.h | 56 Order ///< Any other ordering dependency. enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 222 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
248 unsigned Order = ~0u; variable
278 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion()
364 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
367 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, Constant *Addr, in OffloadEntryInfoDeviceGlobalVar()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 552 unsigned Order = 0; // Cache the sort key. member
794 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
798 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
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| H A D | RegisterInfoEmitter.cpp | 1024 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc() local
1060 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc() local
1225 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CodeLayout.cpp | 1001 std::vector<uint64_t> Order; in concatChains() local
1368 std::vector<uint64_t> Order; in concatChains() local
1428 double codelayout::calcExtTspScore(ArrayRef<uint64_t> Order, in calcExtTspScore()
1454 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInsertDelayAlu.cpp | 247 SmallVector<const_iterator, 8> Order; in dump() local
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 525 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
759 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp()
881 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
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| /freebsd/contrib/llvm-project/clang/lib/Format/ |
| H A D | QualifierAlignmentFixer.cpp | 578 const std::vector<std::string> &Order, std::vector<std::string> &LeftOrder, in prepareLeftRightOrderingForQualifierAlignmentFixer()
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