xref: /dragonfly/sys/bus/pci/pcireg.h (revision d650e218)
1 /*-
2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/pci/pcireg.h,v 1.64.2.4.2.1 2009/04/15 03:14:26 kensmith Exp $
27  */
28 
29 #ifndef _PCIREG_H_
30 #define _PCIREG_H_
31 
32 #ifndef _SYS_TYPES_H_
33 #include <sys/types.h>
34 #endif
35 
36 typedef u_int16_t pci_vendor_id_t;
37 typedef u_int16_t pci_product_id_t;
38 typedef u_int8_t pci_class_t;
39 typedef u_int8_t pci_subclass_t;
40 typedef u_int8_t pci_interface_t;
41 typedef u_int8_t pci_revision_t;
42 typedef u_int8_t pci_intr_pin_t;
43 typedef u_int8_t pci_intr_line_t;
44 typedef u_int32_t pcireg_t;             /* ~typical configuration space */
45 
46 /*
47  * PCIM_xxx: mask to locate subfield in register
48  * PCIR_xxx: config register offset
49  * PCIC_xxx: device class
50  * PCIS_xxx: device subclass
51  * PCIP_xxx: device programming interface
52  * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
53  * PCID_xxx: device ID
54  * PCIY_xxx: capability identification number
55  * PCIZ_xxx: extended capability identification number
56  */
57 
58 /* some PCI bus constants */
59 
60 #define	PCI_BUSMAX	255
61 #define	PCI_SLOTMAX	31
62 #define	PCI_FUNCMAX	7
63 #define	PCI_REGMAX	255
64 #define	PCIE_REGMAX	4095
65 #define	PCI_MAXHDRTYPE	2
66 
67 /* PCI config header registers for all devices */
68 
69 #define	PCIR_DEVVENDOR	0x00
70 #define	PCIR_VENDOR	0x00
71 #define	PCIR_DEVICE	0x02
72 #define	PCIR_COMMAND	0x04
73 #define PCIR_CARDBUSCIS 0x28
74 #define	PCIM_CMD_PORTEN		0x0001
75 #define	PCIM_CMD_MEMEN		0x0002
76 #define	PCIM_CMD_BUSMASTEREN	0x0004
77 #define	PCIM_CMD_SPECIALEN	0x0008
78 #define	PCIM_CMD_MWRICEN	0x0010
79 #define	PCIM_CMD_PERRESPEN	0x0040
80 #define	PCIM_CMD_SERRESPEN	0x0100
81 #define	PCIM_CMD_BACKTOBACK	0x0200
82 #define	PCIM_CMD_INTxDIS	0x0400
83 
84 #define	PCIR_STATUS	0x06
85 #define PCIM_STATUS_INTxSTATE	0x0008
86 #define	PCIM_STATUS_CAPPRESENT	0x0010
87 #define	PCIM_STATUS_66CAPABLE	0x0020
88 #define	PCIM_STATUS_BACKTOBACK	0x0080
89 #define	PCIM_STATUS_PERRREPORT	0x0100
90 #define	PCIM_STATUS_SEL_FAST	0x0000
91 #define	PCIM_STATUS_SEL_MEDIMUM	0x0200
92 #define	PCIM_STATUS_SEL_SLOW	0x0400
93 #define	PCIM_STATUS_SEL_MASK	0x0600
94 #define	PCIM_STATUS_STABORT	0x0800
95 #define	PCIM_STATUS_RTABORT	0x1000
96 #define	PCIM_STATUS_RMABORT	0x2000
97 #define	PCIM_STATUS_SERR	0x4000
98 #define	PCIM_STATUS_PERR	0x8000
99 
100 #define	PCIR_REVID	0x08
101 #define	PCIR_PROGIF	0x09
102 #define	PCIR_SUBCLASS	0x0a
103 #define	PCIR_CLASS	0x0b
104 #define	PCIR_CACHELNSZ	0x0c
105 #define	PCIR_LATTIMER	0x0d
106 #define	PCIR_HDRTYPE	0x0e
107 #define	PCIM_HDRTYPE		0x7f
108 #define	PCIM_HDRTYPE_NORMAL	0x00
109 #define	PCIM_HDRTYPE_BRIDGE	0x01
110 #define	PCIM_HDRTYPE_CARDBUS	0x02
111 #define	PCIM_MFDEV		0x80
112 #define	PCIR_BIST	0x0f
113 
114 /* Capability Register Offsets */
115 
116 #define	PCICAP_ID	0x0
117 #define	PCICAP_NEXTPTR	0x1
118 
119 /* Capability Identification Numbers */
120 
121 #define	PCIY_PMG	0x01	/* PCI Power Management */
122 #define	PCIY_AGP	0x02	/* AGP */
123 #define	PCIY_VPD	0x03	/* Vital Product Data */
124 #define	PCIY_SLOTID	0x04	/* Slot Identification */
125 #define	PCIY_MSI	0x05	/* Message Signaled Interrupts */
126 #define	PCIY_CHSWP	0x06	/* CompactPCI Hot Swap */
127 #define	PCIY_PCIX	0x07	/* PCI-X */
128 #define	PCIY_HT		0x08	/* HyperTransport */
129 #define	PCIY_VENDOR	0x09	/* Vendor Unique */
130 #define	PCIY_DEBUG	0x0a	/* Debug port */
131 #define	PCIY_CRES	0x0b	/* CompactPCI central resource control */
132 #define	PCIY_HOTPLUG	0x0c	/* PCI Hot-Plug */
133 #define	PCIY_SUBVENDOR	0x0d	/* PCI-PCI bridge subvendor ID */
134 #define	PCIY_AGP8X	0x0e	/* AGP 8x */
135 #define	PCIY_SECDEV	0x0f	/* Secure Device */
136 #define	PCIY_EXPRESS	0x10	/* PCI Express */
137 #define	PCIY_MSIX	0x11	/* MSI-X */
138 #define	PCIY_SATA	0x12	/* SATA */
139 #define	PCIY_PCIAF	0x13	/* PCI Advanced Features */
140 
141 /* Extended Capability Register Fields */
142 
143 #define	PCIR_EXTCAP	0x100
144 #define	PCIM_EXTCAP_ID		0x0000ffff
145 #define	PCIM_EXTCAP_VER		0x000f0000
146 #define	PCIM_EXTCAP_NEXTPTR	0xfff00000
147 #define	PCI_EXTCAP_ID(ecap)	((ecap) & PCIM_EXTCAP_ID)
148 #define	PCI_EXTCAP_VER(ecap)	(((ecap) & PCIM_EXTCAP_VER) >> 16)
149 #define	PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
150 
151 /* Extended Capability Identification Numbers */
152 
153 #define	PCIZ_AER	0x0001	/* Advanced Error Reporting */
154 #define	PCIZ_VC		0x0002	/* Virtual Channel */
155 #define	PCIZ_SERNUM	0x0003	/* Device Serial Number */
156 #define	PCIZ_PWRBDGT	0x0004	/* Power Budgeting */
157 #define	PCIZ_VENDOR	0x000b	/* Vendor Unique */
158 #define	PCIZ_ACS	0x000d	/* Access Control Services */
159 #define	PCIZ_ARI	0x000e	/* Alternative Routing-ID Interpretation */
160 #define	PCIZ_ATS	0x000f	/* Address Translation Services */
161 #define	PCIZ_SRIOV	0x0010	/* Single Root IO Virtualization */
162 
163 /* config registers for header type 0 devices */
164 
165 #define	PCIR_BARS	0x10
166 #define PCIR_MAPS       PCIR_BARS
167 #define	PCIR_BAR(x)		(PCIR_BARS + (x) * 4)
168 #define	PCIR_MAX_BAR_0		5
169 #define	PCI_RID2BAR(rid)	(((rid) - PCIR_BARS) / 4)
170 #define	PCI_BAR_IO(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
171 #define	PCI_BAR_MEM(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
172 #define	PCIM_BAR_SPACE		0x00000001
173 #define	PCIM_BAR_MEM_SPACE	0
174 #define	PCIM_BAR_IO_SPACE	1
175 #define	PCIM_BAR_MEM_TYPE	0x00000006
176 #define	PCIM_BAR_MEM_32		0
177 #define	PCIM_BAR_MEM_1MB	2	/* Locate below 1MB in PCI <= 2.1 */
178 #define	PCIM_BAR_MEM_64		4
179 #define	PCIM_BAR_MEM_PREFETCH	0x00000008
180 #define	PCIM_BAR_MEM_BASE	0xfffffff0
181 #define	PCIM_BAR_IO_RESERVED	0x00000002
182 #define	PCIM_BAR_IO_BASE	0xfffffffc
183 #define	PCIR_CIS	0x28
184 #define	PCIM_CIS_ASI_MASK	0x7
185 #define	PCIM_CIS_ASI_CONFIG	0
186 #define	PCIM_CIS_ASI_BAR0	1
187 #define	PCIM_CIS_ASI_BAR1	2
188 #define	PCIM_CIS_ASI_BAR2	3
189 #define	PCIM_CIS_ASI_BAR3	4
190 #define	PCIM_CIS_ASI_BAR4	5
191 #define	PCIM_CIS_ASI_BAR5	6
192 #define	PCIM_CIS_ASI_ROM	7
193 #define	PCIM_CIS_ADDR_MASK	0x0ffffff8
194 #define	PCIM_CIS_ROM_MASK	0xf0000000
195 #define PCIM_CIS_CONFIG_MASK	0xff
196 #define	PCIR_SUBVEND_0	0x2c
197 #define	PCIR_SUBDEV_0	0x2e
198 #define	PCIR_BIOS	0x30
199 #define	PCIM_BIOS_ENABLE	0x01
200 #define	PCIM_BIOS_ADDR_MASK	0xfffff800
201 #define	PCIR_CAP_PTR	0x34
202 #define	PCIR_INTLINE	0x3c
203 #define	PCIR_INTPIN	0x3d
204 #define	PCIR_MINGNT	0x3e
205 #define	PCIR_MAXLAT	0x3f
206 
207 #define PCI_PPBMEMBASE(h,l)	((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
208 #define PCI_PPBMEMLIMIT(h,l)	((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff)
209 #define PCI_PPBIOBASE(h,l)	((((h)<<16) + ((l)<<8)) & ~0xfff)
210 #define PCI_PPBIOLIMIT(h,l)	((((h)<<16) + ((l)<<8)) | 0xfff)
211 
212 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
213 
214 #define	PCIR_MAX_BAR_1	1
215 #define	PCIR_SECSTAT_1	0x1e
216 
217 #define	PCIR_PRIBUS_1	0x18
218 #define	PCIR_SECBUS_1	0x19
219 #define	PCIR_SUBBUS_1	0x1a
220 #define	PCIR_SECLAT_1	0x1b
221 
222 #define	PCIR_IOBASEL_1	0x1c
223 #define	PCIR_IOLIMITL_1	0x1d
224 #define	PCIR_IOBASEH_1	0x30
225 #define	PCIR_IOLIMITH_1	0x32
226 #define	PCIM_BRIO_16		0x0
227 #define	PCIM_BRIO_32		0x1
228 #define	PCIM_BRIO_MASK		0xf
229 
230 #define	PCIR_MEMBASE_1	0x20
231 #define	PCIR_MEMLIMIT_1	0x22
232 
233 #define	PCIR_PMBASEL_1	0x24
234 #define	PCIR_PMLIMITL_1	0x26
235 #define	PCIR_PMBASEH_1	0x28
236 #define	PCIR_PMLIMITH_1	0x2c
237 #define	PCIM_BRPM_32		0x0
238 #define	PCIM_BRPM_64		0x1
239 #define	PCIM_BRPM_MASK		0xf
240 
241 #define	PCIR_BRIDGECTL_1 0x3e
242 
243 /* config registers for header type 2 (CardBus) devices */
244 
245 #define	PCIR_MAX_BAR_2	0
246 #define	PCIR_CAP_PTR_2	0x14
247 #define	PCIR_SECSTAT_2	0x16
248 
249 #define	PCIR_PRIBUS_2	0x18
250 #define	PCIR_SECBUS_2	0x19
251 #define	PCIR_SUBBUS_2	0x1a
252 #define	PCIR_SECLAT_2	0x1b
253 
254 #define	PCIR_MEMBASE0_2	0x1c
255 #define	PCIR_MEMLIMIT0_2 0x20
256 #define	PCIR_MEMBASE1_2	0x24
257 #define	PCIR_MEMLIMIT1_2 0x28
258 #define	PCIR_IOBASE0_2	0x2c
259 #define	PCIR_IOLIMIT0_2	0x30
260 #define	PCIR_IOBASE1_2	0x34
261 #define	PCIR_IOLIMIT1_2	0x38
262 
263 #define PCIM_CBBIO_16           0x0
264 #define PCIM_CBBIO_32           0x1
265 #define PCIM_CBBIO_MASK         0x3
266 
267 #define	PCIR_BRIDGECTL_2 0x3e
268 
269 #define	PCIR_SUBVEND_2	0x40
270 #define	PCIR_SUBDEV_2	0x42
271 
272 #define	PCIR_PCCARDIF_2	0x44
273 
274 #define PCI_CBBMEMBASE(l)	((l) & ~0xfffff)
275 #define PCI_CBBMEMLIMIT(l)	((l) | 0xfffff)
276 #define PCI_CBBIOBASE(l)	((l) & ~0x3)
277 #define PCI_CBBIOLIMIT(l)	((l) | 0x3)
278 
279 /* PCI device class, subclass and programming interface definitions */
280 
281 #define	PCIC_OLD	0x00
282 #define	PCIS_OLD_NONVGA		0x00
283 #define	PCIS_OLD_VGA		0x01
284 
285 #define	PCIC_STORAGE	0x01
286 #define	PCIS_STORAGE_SCSI	0x00
287 #define	PCIS_STORAGE_IDE	0x01
288 #define	PCIP_STORAGE_IDE_MODEPRIM	0x01
289 #define	PCIP_STORAGE_IDE_PROGINDPRIM	0x02
290 #define	PCIP_STORAGE_IDE_MODESEC	0x04
291 #define	PCIP_STORAGE_IDE_PROGINDSEC	0x08
292 #define	PCIP_STORAGE_IDE_MASTERDEV	0x80
293 #define	PCIS_STORAGE_FLOPPY	0x02
294 #define	PCIS_STORAGE_IPI	0x03
295 #define	PCIS_STORAGE_RAID	0x04
296 #define	PCIS_STORAGE_ATA_ADMA	0x05
297 #define	PCIS_STORAGE_SATA	0x06
298 #define	PCIP_STORAGE_SATA_AHCI_1_0	0x01
299 #define	PCIS_STORAGE_SAS	0x07
300 #define PCIS_STORAGE_NVM	0x08
301 #define PCIP_STORAGE_NVM_NVMHCI_1_0		0x01
302 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0	0x02
303 #define	PCIS_STORAGE_OTHER	0x80
304 
305 #define	PCIC_NETWORK	0x02
306 #define	PCIS_NETWORK_ETHERNET	0x00
307 #define	PCIS_NETWORK_TOKENRING	0x01
308 #define	PCIS_NETWORK_FDDI	0x02
309 #define	PCIS_NETWORK_ATM	0x03
310 #define	PCIS_NETWORK_ISDN	0x04
311 #define	PCIS_NETWORK_WORLDFIP	0x05
312 #define	PCIS_NETWORK_PICMG	0x06
313 #define	PCIS_NETWORK_OTHER	0x80
314 
315 #define	PCIC_DISPLAY	0x03
316 #define	PCIS_DISPLAY_VGA	0x00
317 #define	PCIS_DISPLAY_XGA	0x01
318 #define	PCIS_DISPLAY_3D		0x02
319 #define	PCIS_DISPLAY_OTHER	0x80
320 
321 #define	PCIC_MULTIMEDIA	0x04
322 #define	PCIS_MULTIMEDIA_VIDEO	0x00
323 #define	PCIS_MULTIMEDIA_AUDIO	0x01
324 #define	PCIS_MULTIMEDIA_TELE	0x02
325 #define	PCIS_MULTIMEDIA_HDA	0x03
326 #define	PCIS_MULTIMEDIA_OTHER	0x80
327 
328 #define	PCIC_MEMORY	0x05
329 #define	PCIS_MEMORY_RAM		0x00
330 #define	PCIS_MEMORY_FLASH	0x01
331 #define	PCIS_MEMORY_OTHER	0x80
332 
333 #define	PCIC_BRIDGE	0x06
334 #define	PCIS_BRIDGE_HOST	0x00
335 #define	PCIS_BRIDGE_ISA		0x01
336 #define	PCIS_BRIDGE_EISA	0x02
337 #define	PCIS_BRIDGE_MCA		0x03
338 #define	PCIS_BRIDGE_PCI		0x04
339 #define	PCIP_BRIDGE_PCI_SUBTRACTIVE	0x01
340 #define	PCIS_BRIDGE_PCMCIA	0x05
341 #define	PCIS_BRIDGE_NUBUS	0x06
342 #define	PCIS_BRIDGE_CARDBUS	0x07
343 #define	PCIS_BRIDGE_RACEWAY	0x08
344 #define	PCIS_BRIDGE_PCI_TRANSPARENT 0x09
345 #define	PCIS_BRIDGE_INFINIBAND	0x0a
346 #define	PCIS_BRIDGE_OTHER	0x80
347 
348 #define	PCIC_SIMPLECOMM	0x07
349 #define	PCIS_SIMPLECOMM_UART	0x00
350 #define	PCIP_SIMPLECOMM_UART_8250	0x00
351 #define	PCIP_SIMPLECOMM_UART_16450A	0x01
352 #define	PCIP_SIMPLECOMM_UART_16550A	0x02
353 #define	PCIP_SIMPLECOMM_UART_16650A	0x03
354 #define	PCIP_SIMPLECOMM_UART_16750A	0x04
355 #define	PCIP_SIMPLECOMM_UART_16850A	0x05
356 #define	PCIP_SIMPLECOMM_UART_16950A	0x06
357 #define	PCIS_SIMPLECOMM_PAR	0x01
358 #define	PCIS_SIMPLECOMM_MULSER	0x02
359 #define	PCIS_SIMPLECOMM_MODEM	0x03
360 #define	PCIS_SIMPLECOMM_GPIB	0x04
361 #define	PCIS_SIMPLECOMM_SMART_CARD 0x05
362 #define	PCIS_SIMPLECOMM_OTHER	0x80
363 
364 #define	PCIC_BASEPERIPH	0x08
365 #define	PCIS_BASEPERIPH_PIC	0x00
366 #define	PCIP_BASEPERIPH_PIC_8259A	0x00
367 #define	PCIP_BASEPERIPH_PIC_ISA		0x01
368 #define	PCIP_BASEPERIPH_PIC_EISA	0x02
369 #define	PCIP_BASEPERIPH_PIC_IO_APIC	0x10
370 #define	PCIP_BASEPERIPH_PIC_IOX_APIC	0x20
371 #define	PCIS_BASEPERIPH_DMA	0x01
372 #define	PCIS_BASEPERIPH_TIMER	0x02
373 #define	PCIS_BASEPERIPH_RTC	0x03
374 #define	PCIS_BASEPERIPH_PCIHOT	0x04
375 #define	PCIS_BASEPERIPH_SDHC	0x05
376 #define	PCIS_BASEPERIPH_OTHER	0x80
377 
378 #define	PCIC_INPUTDEV	0x09
379 #define	PCIS_INPUTDEV_KEYBOARD	0x00
380 #define	PCIS_INPUTDEV_DIGITIZER	0x01
381 #define	PCIS_INPUTDEV_MOUSE	0x02
382 #define	PCIS_INPUTDEV_SCANNER	0x03
383 #define	PCIS_INPUTDEV_GAMEPORT	0x04
384 #define	PCIS_INPUTDEV_OTHER	0x80
385 
386 #define	PCIC_DOCKING	0x0a
387 #define	PCIS_DOCKING_GENERIC	0x00
388 #define	PCIS_DOCKING_OTHER	0x80
389 
390 #define	PCIC_PROCESSOR	0x0b
391 #define	PCIS_PROCESSOR_386	0x00
392 #define	PCIS_PROCESSOR_486	0x01
393 #define	PCIS_PROCESSOR_PENTIUM	0x02
394 #define	PCIS_PROCESSOR_ALPHA	0x10
395 #define	PCIS_PROCESSOR_POWERPC	0x20
396 #define	PCIS_PROCESSOR_MIPS	0x30
397 #define	PCIS_PROCESSOR_COPROC	0x40
398 
399 #define	PCIC_SERIALBUS	0x0c
400 #define	PCIS_SERIALBUS_FW	0x00
401 #define	PCIS_SERIALBUS_ACCESS	0x01
402 #define	PCIS_SERIALBUS_SSA	0x02
403 #define	PCIS_SERIALBUS_USB	0x03
404 #define	PCIP_SERIALBUS_USB_UHCI		0x00
405 #define	PCIP_SERIALBUS_USB_OHCI		0x10
406 #define	PCIP_SERIALBUS_USB_EHCI		0x20
407 #define	PCIP_SERIALBUS_USB_XHCI		0x30
408 #define	PCIP_SERIALBUS_USB_DEVICE	0xfe
409 #define	PCIS_SERIALBUS_FC	0x04
410 #define	PCIS_SERIALBUS_SMBUS	0x05
411 #define	PCIS_SERIALBUS_INFINIBAND 0x06
412 #define	PCIS_SERIALBUS_IPMI	0x07
413 #define	PCIP_SERIALBUS_IPMI_SMIC	0x00
414 #define	PCIP_SERIALBUS_IPMI_KCS		0x01
415 #define	PCIP_SERIALBUS_IPMI_BT		0x02
416 #define	PCIS_SERIALBUS_SERCOS	0x08
417 #define	PCIS_SERIALBUS_CANBUS	0x09
418 
419 #define	PCIC_WIRELESS	0x0d
420 #define	PCIS_WIRELESS_IRDA	0x00
421 #define	PCIS_WIRELESS_IR	0x01
422 #define	PCIS_WIRELESS_RF	0x10
423 #define	PCIS_WIRELESS_BLUETOOTH	0x11
424 #define	PCIS_WIRELESS_BROADBAND	0x12
425 #define	PCIS_WIRELESS_80211A	0x20
426 #define	PCIS_WIRELESS_80211B	0x21
427 #define	PCIS_WIRELESS_OTHER	0x80
428 
429 #define	PCIC_INTELLIIO	0x0e
430 #define	PCIS_INTELLIIO_I2O	0x00
431 
432 #define	PCIC_SATCOM	0x0f
433 #define	PCIS_SATCOM_TV		0x01
434 #define	PCIS_SATCOM_AUDIO	0x02
435 #define	PCIS_SATCOM_VOICE	0x03
436 #define	PCIS_SATCOM_DATA	0x04
437 
438 #define	PCIC_CRYPTO	0x10
439 #define	PCIS_CRYPTO_NETCOMP	0x00
440 #define	PCIS_CRYPTO_ENTERTAIN	0x10
441 #define	PCIS_CRYPTO_OTHER	0x80
442 
443 #define	PCIC_DASP	0x11
444 #define	PCIS_DASP_DPIO		0x00
445 #define	PCIS_DASP_PERFCNTRS	0x01
446 #define	PCIS_DASP_COMM_SYNC	0x10
447 #define	PCIS_DASP_MGMT_CARD	0x20
448 #define	PCIS_DASP_OTHER		0x80
449 
450 #define	PCIC_OTHER	0xff
451 
452 /* Bridge Control Values. */
453 #define	PCIB_BCR_PERR_ENABLE		0x0001
454 #define	PCIB_BCR_SERR_ENABLE		0x0002
455 #define	PCIB_BCR_ISA_ENABLE		0x0004
456 #define	PCIB_BCR_VGA_ENABLE		0x0008
457 #define	PCIB_BCR_MASTER_ABORT_MODE	0x0020
458 #define	PCIB_BCR_SECBUS_RESET		0x0040
459 #define	PCIB_BCR_SECBUS_BACKTOBACK	0x0080
460 #define	PCIB_BCR_PRI_DISCARD_TIMEOUT	0x0100
461 #define	PCIB_BCR_SEC_DISCARD_TIMEOUT	0x0200
462 #define	PCIB_BCR_DISCARD_TIMER_STATUS	0x0400
463 #define	PCIB_BCR_DISCARD_TIMER_SERREN	0x0800
464 
465 #define CBB_BCR_PERR_ENABLE		0x0001
466 #define CBB_BCR_SERR_ENABLE		0x0002
467 #define CBB_BCR_ISA_ENABLE		0x0004
468 #define CBB_BCR_VGA_ENABLE		0x0008
469 #define CBB_BCR_MASTER_ABORT_MODE	0x0020
470 #define CBB_BCR_CARDBUS_RESET		0x0040
471 #define CBB_BCR_IREQ_INT_ENABLE		0x0080
472 #define CBB_BCR_PREFETCH_0_ENABLE	0x0100
473 #define CBB_BCR_PREFETCH_1_ENABLE	0x0200
474 #define CBB_BCR_WRITE_POSTING_ENABLE	0x0400
475 
476 /* PCI power manangement */
477 #define	PCIR_POWER_CAP		0x2
478 #define	PCIM_PCAP_SPEC			0x0007
479 #define	PCIM_PCAP_PMEREQCLK		0x0008
480 #define	PCIM_PCAP_PMEREQPWR		0x0010
481 #define	PCIM_PCAP_DEVSPECINIT		0x0020
482 #define	PCIM_PCAP_DYNCLOCK		0x0040
483 #define	PCIM_PCAP_SECCLOCK		0x00c0
484 #define	PCIM_PCAP_CLOCKMASK		0x00c0
485 #define	PCIM_PCAP_REQFULLCLOCK		0x0100
486 #define	PCIM_PCAP_D1SUPP		0x0200
487 #define	PCIM_PCAP_D2SUPP		0x0400
488 #define	PCIM_PCAP_D0PME			0x0800
489 #define	PCIM_PCAP_D1PME			0x1000
490 #define	PCIM_PCAP_D2PME			0x2000
491 #define	PCIM_PCAP_D3PME_HOT		0x4000
492 #define	PCIM_PCAP_D3PME_COLD		0x8000
493 
494 #define	PCIR_POWER_STATUS	0x4
495 #define	PCIM_PSTAT_D0			0x0000
496 #define	PCIM_PSTAT_D1			0x0001
497 #define	PCIM_PSTAT_D2			0x0002
498 #define	PCIM_PSTAT_D3			0x0003
499 #define	PCIM_PSTAT_DMASK		0x0003
500 #define	PCIM_PSTAT_REPENABLE		0x0010
501 #define	PCIM_PSTAT_PMEENABLE		0x0100
502 #define	PCIM_PSTAT_D0POWER		0x0000
503 #define	PCIM_PSTAT_D1POWER		0x0200
504 #define	PCIM_PSTAT_D2POWER		0x0400
505 #define	PCIM_PSTAT_D3POWER		0x0600
506 #define	PCIM_PSTAT_D0HEAT		0x0800
507 #define	PCIM_PSTAT_D1HEAT		0x1000
508 #define	PCIM_PSTAT_D2HEAT		0x1200
509 #define	PCIM_PSTAT_D3HEAT		0x1400
510 #define	PCIM_PSTAT_DATAUNKN		0x0000
511 #define	PCIM_PSTAT_DATADIV10		0x2000
512 #define	PCIM_PSTAT_DATADIV100		0x4000
513 #define	PCIM_PSTAT_DATADIV1000		0x6000
514 #define	PCIM_PSTAT_DATADIVMASK		0x6000
515 #define	PCIM_PSTAT_PME			0x8000
516 
517 #define	PCIR_POWER_PMCSR	0x6
518 #define	PCIM_PMCSR_DCLOCK		0x10
519 #define	PCIM_PMCSR_B2SUPP		0x20
520 #define	PCIM_BMCSR_B3SUPP		0x40
521 #define	PCIM_BMCSR_BPCE			0x80
522 
523 #define	PCIR_POWER_DATA		0x7
524 
525 /* VPD capability registers */
526 #define	PCIR_VPD_ADDR		0x2
527 #define	PCIR_VPD_DATA		0x4
528 
529 /* PCI Message Signalled Interrupts (MSI) */
530 #define	PCIR_MSI_CTRL		0x2
531 #define	PCIM_MSICTRL_VECTOR		0x0100
532 #define	PCIM_MSICTRL_64BIT		0x0080
533 #define	PCIM_MSICTRL_MME_MASK		0x0070
534 #define	PCIM_MSICTRL_MME_1		0x0000
535 #define	PCIM_MSICTRL_MME_2		0x0010
536 #define	PCIM_MSICTRL_MME_4		0x0020
537 #define	PCIM_MSICTRL_MME_8		0x0030
538 #define	PCIM_MSICTRL_MME_16		0x0040
539 #define	PCIM_MSICTRL_MME_32		0x0050
540 #define	PCIM_MSICTRL_MMC_MASK		0x000E
541 #define	PCIM_MSICTRL_MMC_1		0x0000
542 #define	PCIM_MSICTRL_MMC_2		0x0002
543 #define	PCIM_MSICTRL_MMC_4		0x0004
544 #define	PCIM_MSICTRL_MMC_8		0x0006
545 #define	PCIM_MSICTRL_MMC_16		0x0008
546 #define	PCIM_MSICTRL_MMC_32		0x000A
547 #define	PCIM_MSICTRL_MSI_ENABLE		0x0001
548 #define	PCIR_MSI_ADDR		0x4
549 #define	PCIR_MSI_ADDR_HIGH	0x8
550 #define	PCIR_MSI_DATA		0x8
551 #define	PCIR_MSI_DATA_64BIT	0xc
552 #define	PCIR_MSI_MASK		0x10
553 #define	PCIR_MSI_PENDING	0x14
554 
555 /* PCI-X definitions */
556 
557 /* For header type 0 devices */
558 #define	PCIXR_COMMAND		0x2
559 #define	PCIXM_COMMAND_DPERR_E		0x0001	/* Data Parity Error Recovery */
560 #define	PCIXM_COMMAND_ERO		0x0002	/* Enable Relaxed Ordering */
561 #define	PCIXM_COMMAND_MAX_READ		0x000c	/* Maximum Burst Read Count */
562 #define	PCIXM_COMMAND_MAX_READ_512	0x0000
563 #define	PCIXM_COMMAND_MAX_READ_1024	0x0004
564 #define	PCIXM_COMMAND_MAX_READ_2048	0x0008
565 #define	PCIXM_COMMAND_MAX_READ_4096	0x000c
566 #define	PCIXM_COMMAND_MAX_SPLITS 	0x0070	/* Maximum Split Transactions */
567 #define	PCIXM_COMMAND_MAX_SPLITS_1	0x0000
568 #define	PCIXM_COMMAND_MAX_SPLITS_2	0x0010
569 #define	PCIXM_COMMAND_MAX_SPLITS_3	0x0020
570 #define	PCIXM_COMMAND_MAX_SPLITS_4	0x0030
571 #define	PCIXM_COMMAND_MAX_SPLITS_8	0x0040
572 #define	PCIXM_COMMAND_MAX_SPLITS_12	0x0050
573 #define	PCIXM_COMMAND_MAX_SPLITS_16	0x0060
574 #define	PCIXM_COMMAND_MAX_SPLITS_32	0x0070
575 #define	PCIXM_COMMAND_VERSION		0x3000
576 #define	PCIXR_STATUS		0x4
577 #define	PCIXM_STATUS_DEVFN		0x000000FF
578 #define	PCIXM_STATUS_BUS		0x0000FF00
579 #define	PCIXM_STATUS_64BIT		0x00010000
580 #define	PCIXM_STATUS_133CAP		0x00020000
581 #define	PCIXM_STATUS_SC_DISCARDED	0x00040000
582 #define	PCIXM_STATUS_UNEXP_SC		0x00080000
583 #define	PCIXM_STATUS_COMPLEX_DEV	0x00100000
584 #define	PCIXM_STATUS_MAX_READ		0x00600000
585 #define	PCIXM_STATUS_MAX_READ_512	0x00000000
586 #define	PCIXM_STATUS_MAX_READ_1024	0x00200000
587 #define	PCIXM_STATUS_MAX_READ_2048	0x00400000
588 #define	PCIXM_STATUS_MAX_READ_4096	0x00600000
589 #define	PCIXM_STATUS_MAX_SPLITS		0x03800000
590 #define	PCIXM_STATUS_MAX_SPLITS_1	0x00000000
591 #define	PCIXM_STATUS_MAX_SPLITS_2	0x00800000
592 #define	PCIXM_STATUS_MAX_SPLITS_3	0x01000000
593 #define	PCIXM_STATUS_MAX_SPLITS_4	0x01800000
594 #define	PCIXM_STATUS_MAX_SPLITS_8	0x02000000
595 #define	PCIXM_STATUS_MAX_SPLITS_12	0x02800000
596 #define	PCIXM_STATUS_MAX_SPLITS_16	0x03000000
597 #define	PCIXM_STATUS_MAX_SPLITS_32	0x03800000
598 #define	PCIXM_STATUS_MAX_CUM_READ	0x1C000000
599 #define	PCIXM_STATUS_RCVD_SC_ERR	0x20000000
600 #define	PCIXM_STATUS_266CAP		0x40000000
601 #define	PCIXM_STATUS_533CAP		0x80000000
602 
603 /* For header type 1 devices (PCI-X bridges) */
604 #define	PCIXR_SEC_STATUS	0x2
605 #define	PCIXM_SEC_STATUS_64BIT		0x0001
606 #define	PCIXM_SEC_STATUS_133CAP		0x0002
607 #define	PCIXM_SEC_STATUS_SC_DISC	0x0004
608 #define	PCIXM_SEC_STATUS_UNEXP_SC	0x0008
609 #define	PCIXM_SEC_STATUS_SC_OVERRUN	0x0010
610 #define	PCIXM_SEC_STATUS_SR_DELAYED	0x0020
611 #define	PCIXM_SEC_STATUS_BUS_MODE	0x03c0
612 #define	PCIXM_SEC_STATUS_VERSION	0x3000
613 #define	PCIXM_SEC_STATUS_266CAP		0x4000
614 #define	PCIXM_SEC_STATUS_533CAP		0x8000
615 #define	PCIXR_BRIDGE_STATUS	0x4
616 #define	PCIXM_BRIDGE_STATUS_DEVFN	0x000000FF
617 #define	PCIXM_BRIDGE_STATUS_BUS		0x0000FF00
618 #define	PCIXM_BRIDGE_STATUS_64BIT	0x00010000
619 #define	PCIXM_BRIDGE_STATUS_133CAP	0x00020000
620 #define	PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
621 #define	PCIXM_BRIDGE_STATUS_UNEXP_SC	0x00080000
622 #define	PCIXM_BRIDGE_STATUS_SC_OVERRUN	0x00100000
623 #define	PCIXM_BRIDGE_STATUS_SR_DELAYED	0x00200000
624 #define	PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
625 #define	PCIXM_BRIDGE_STATUS_266CAP	0x40000000
626 #define	PCIXM_BRIDGE_STATUS_533CAP	0x80000000
627 
628 /* HT (HyperTransport) Capability definitions */
629 #define	PCIR_HT_COMMAND		0x2
630 #define	PCIM_HTCMD_CAP_MASK		0xf800	/* Capability type. */
631 #define	PCIM_HTCAP_SLAVE		0x0000	/* 000xx */
632 #define	PCIM_HTCAP_HOST			0x2000	/* 001xx */
633 #define	PCIM_HTCAP_SWITCH		0x4000	/* 01000 */
634 #define	PCIM_HTCAP_INTERRUPT		0x8000	/* 10000 */
635 #define	PCIM_HTCAP_REVISION_ID		0x8800	/* 10001 */
636 #define	PCIM_HTCAP_UNITID_CLUMPING	0x9000	/* 10010 */
637 #define	PCIM_HTCAP_EXT_CONFIG_SPACE	0x9800	/* 10011 */
638 #define	PCIM_HTCAP_ADDRESS_MAPPING	0xa000	/* 10100 */
639 #define	PCIM_HTCAP_MSI_MAPPING		0xa800	/* 10101 */
640 #define	PCIM_HTCAP_DIRECT_ROUTE		0xb000	/* 10110 */
641 #define	PCIM_HTCAP_VCSET		0xb800	/* 10111 */
642 #define	PCIM_HTCAP_RETRY_MODE		0xc000	/* 11000 */
643 #define	PCIM_HTCAP_X86_ENCODING		0xc800	/* 11001 */
644 
645 /* HT MSI Mapping Capability definitions. */
646 #define	PCIM_HTCMD_MSI_ENABLE		0x0001
647 #define	PCIM_HTCMD_MSI_FIXED		0x0002
648 #define	PCIR_HTMSI_ADDRESS_LO	0x4
649 #define	PCIR_HTMSI_ADDRESS_HI	0x8
650 
651 /* PCI Vendor capability definitions */
652 #define	PCIR_VENDOR_LENGTH	0x2
653 #define	PCIR_VENDOR_DATA	0x3
654 
655 /* PCI EHCI Debug Port definitions */
656 #define	PCIR_DEBUG_PORT		0x2
657 #define	PCIM_DEBUG_PORT_OFFSET		0x1FFF
658 #define	PCIM_DEBUG_PORT_BAR		0xe000
659 
660 /* PCI-PCI Bridge Subvendor definitions */
661 #define	PCIR_SUBVENDCAP_ID	0x4
662 
663 /* MSI-X definitions */
664 #define	PCIR_MSIX_CTRL		0x2
665 #define	PCIM_MSIXCTRL_MSIX_ENABLE	0x8000
666 #define	PCIM_MSIXCTRL_FUNCTION_MASK	0x4000
667 #define	PCIM_MSIXCTRL_TABLE_SIZE	0x07FF
668 #define	PCIR_MSIX_TABLE		0x4
669 #define	PCIR_MSIX_PBA		0x8
670 #define	PCIM_MSIX_BIR_MASK		0x7
671 #define	PCIM_MSIX_BIR_BAR_10		0
672 #define	PCIM_MSIX_BIR_BAR_14		1
673 #define	PCIM_MSIX_BIR_BAR_18		2
674 #define	PCIM_MSIX_BIR_BAR_1C		3
675 #define	PCIM_MSIX_BIR_BAR_20		4
676 #define	PCIM_MSIX_BIR_BAR_24		5
677 #define	PCIM_MSIX_VCTRL_MASK		0x1
678 
679 /*
680  * PCI Express definitions
681  * According to
682  * PCI Express base specification, REV. 1.0a
683  */
684 
685 /* PCI Express capabilities, 16bits */
686 #define PCIER_CAPABILITY	0x2
687 #define PCIEM_CAP_VER_MASK	0x000f	/* Version */
688 #define PCIEM_CAP_VER_1		0x0001
689 #define PCIEM_CAP_VER_2		0x0002
690 #define PCIEM_CAP_PORT_TYPE	0x00f0	/* Port type mask */
691 #define PCIEM_CAP_SLOT_IMPL	0x0100	/* Slot implemented,
692 					 * valid only for root port and
693 					 * switch downstream port
694 					 */
695 #define PCIEM_CAP_IRQ_MSGNO	0x3e00
696 #define PCIEM_CAP_FLR		0x10000000
697 
698 /* PCI Express port types */
699 #define PCIE_END_POINT		0x0000	/* Endpoint device */
700 #define PCIE_LEG_END_POINT	0x0010	/* Legacy endpoint device */
701 #define PCIE_ROOT_PORT		0x0040	/* Root port */
702 #define PCIE_UP_STREAM_PORT	0x0050	/* Switch upstream port */
703 #define PCIE_DOWN_STREAM_PORT	0x0060	/* Switch downstream port */
704 #define PCIE_PCIE2PCI_BRIDGE	0x0070	/* PCI Express to PCI/PCI-X bridge */
705 #define PCIE_PCI2PCIE_BRIDGE	0x0080	/* PCI/PCI-X to PCI Express bridge */
706 #define PCIE_ROOT_END_POINT	0x0090	/* Root Complex Integrated Endpoint */
707 #define PCIE_ROOT_EVT_COLL	0x00a0	/* Root Complex Event Collector */
708 
709 /* PCI Express device capabilities, 32bits */
710 #define PCIER_DEVCAP			0x04
711 #define PCIEM_DEVCAP_MAX_PAYLOAD	0x0007
712 
713 /* PCI Express device control, 16bits */
714 #define PCIER_DEVCTRL			0x08
715 #define PCIEM_DEVCTL_COR_ENABLE		0x0001
716 #define PCIEM_DEVCTL_NFER_ENABLE	0x0002
717 #define PCIEM_DEVCTL_FER_ENABLE		0x0004
718 #define PCIEM_DEVCTL_URR_ENABLE		0x0008
719 #define PCIEM_DEVCTL_RELAX_ORDER	0x0010	/* Enable Relaxed Ordering */
720 #define PCIEM_DEVCTL_MAX_PAYLOAD_MASK	0x00e0	/* Max Payload Size */
721 #define PCIEM_DEVCTL_MAX_PAYLOAD_128	0x0000
722 #define PCIEM_DEVCTL_MAX_PAYLOAD_256	0x0020
723 #define PCIEM_DEVCTL_MAX_PAYLOAD_512	0x0040
724 #define PCIEM_DEVCTL_MAX_PAYLOAD_1024	0x0060
725 #define PCIEM_DEVCTL_MAX_PAYLOAD_2048	0x0080
726 #define PCIEM_DEVCTL_MAX_PAYLOAD_4096	0x00a0
727 #define PCIEM_DEVCTL_NOSNOOP		0x0800	/* Enable No Snoop */
728 #define PCIEM_DEVCTL_MAX_READRQ_MASK	0x7000	/* Max read request size */
729 #define PCIEM_DEVCTL_MAX_READRQ_128	0x0000
730 #define PCIEM_DEVCTL_MAX_READRQ_256	0x1000
731 #define PCIEM_DEVCTL_MAX_READRQ_512	0x2000
732 #define PCIEM_DEVCTL_MAX_READRQ_1024	0x3000
733 #define PCIEM_DEVCTL_MAX_READRQ_2048	0x4000
734 #define PCIEM_DEVCTL_MAX_READRQ_4096	0x5000
735 
736 /* PCI Express device status, 16bits */
737 #define PCIER_DEVSTS			0x0a
738 #define PCIEM_DEVSTS_CORR_ERR		0x1	/* Correctable Error */
739 #define PCIEM_DEVSTS_NFATAL_ERR		0x2	/* Non-Fatal Error */
740 #define PCIEM_DEVSTS_FATAL_ERR		0x4	/* Fatal Error */
741 #define PCIEM_DEVSTS_UNSUPP_REQ		0x8	/* Unsupported Request */
742 
743 /* PCI Express link capabilities, 32bits */
744 #define PCIER_LINKCAP			0x0c
745 #define PCIEM_LNKCAP_SPEED_MASK		0x000f	/* Supported link speeds */
746 #define PCIEM_LNKCAP_SPEED_2_5		0x1	/* 2.5GT/s */
747 #define PCIEM_LNKCAP_SPEED_5		0x2	/* 5.0GT/s and 2.5GT/s */
748 #define PCIEM_LNKCAP_MAXW_MASK		0x03f0	/* Maximum link width */
749 #define PCIEM_LNKCAP_MAXW_X1		0x0010
750 #define PCIEM_LNKCAP_MAXW_X2		0x0020
751 #define PCIEM_LNKCAP_MAXW_X4		0x0040
752 #define PCIEM_LNKCAP_MAXW_X8		0x0080
753 #define PCIEM_LNKCAP_MAXW_X12		0x00c0
754 #define PCIEM_LNKCAP_MAXW_X16		0x0100
755 #define PCIEM_LNKCAP_MAXW_X32		0x0200
756 #define PCIEM_LNKCAP_ASPM_MASK		0x0c00	/* ASPM */
757 #define PCIEM_LNKCAP_ASPM_L0S		0x0400
758 #define PCIEM_LNKCAP_ASPM_L1		0x0c00
759 
760 /* PCI Express link control, 32bits */
761 #define PCIER_LINKCTRL			0x10
762 #define PCIEM_LNKCTL_ASPM_MASK		0x3	/* ASPM */
763 #define PCIEM_LNKCTL_ASPM_DISABLE	0x0
764 #define PCIEM_LNKCTL_ASPM_L0S		0x1
765 #define PCIEM_LNKCTL_ASPM_L1		0x2
766 #define PCIEM_LNKCTL_RCB		0x8
767 #define PCIEM_LNKCTL_LINK_DIS		0x0010
768 #define PCIEM_LNKCTL_RETRAIN_LINK	0x0020
769 #define PCIEM_LNKCTL_COMMON_CLOCK	0x0040
770 #define PCIEM_LNKCTL_EXTENDED_SYNC	0x0080
771 #define PCIEM_LNKCTL_ECPM		0x0100
772 #define PCIEM_LNKCTL_HAWD		0x0200
773 #define PCIEM_LNKCTL_LBMIE		0x0400
774 #define PCIEM_LNKCTL_LABIE		0x0800
775 
776 /* PCI Express link status, 16bits */
777 #define PCIER_LINKSTAT			0x12
778 #define PCIEM_LNKSTAT_WIDTH		0x03f0
779 
780 /* PCI Express slot capabilities, 32bits */
781 #define PCIER_SLOTCAP		0x14
782 #define PCIEM_SLOTCAP_ATTEN_BTN	0x00000001 /* Attention button present */
783 #define PCIEM_SLOTCAP_PWR_CTRL	0x00000002 /* Power controller present */
784 #define PCIEM_SLOTCAP_MRL_SNS	0x00000004 /* MRL sensor present */
785 #define PCIEM_SLOTCAP_ATTEN_IND	0x00000008 /* Attention indicator present */
786 #define PCIEM_SLOTCAP_PWR_IND	0x00000010 /* Power indicator present */
787 #define PCIEM_SLOTCAP_HP_SURP	0x00000020 /* Hot-Plug surprise */
788 #define PCIEM_SLOTCAP_HP_CAP	0x00000040 /* Hot-Plug capable */
789 #define PCIEM_SLOTCAP_HP_MASK	0x0000007f /* Hot-Plug related bits */
790 #define PCIEM_SLOTCAP_SPLV	0x00007f80
791 #define PCIEM_SLOTCAP_SPLS	0x00018000
792 #define PCIEM_SLOTCAP_EIP	0x00020000
793 #define PCIEM_SLOTCAP_NCCS	0x00040000
794 #define PCIEM_SLOTCAP_PSN	0xfff80000
795 
796 /* PCI Express slot control, 16bits */
797 #define PCIER_SLOTCTL			0x18
798 #define PCIEM_SLOTCTL_HPINTR_MASK	0x001f	/* Hot-plug interrupts mask */
799 #define PCIEM_SLOTCTL_HPINTR_EN		0x0020	/* Enable hot-plug interrupts */
800 #define PCIEM_SLOTCTL_AIC		0x00c0
801 #define PCIEM_SLOTCTL_AI_ON		0x0040
802 #define PCIEM_SLOTCTL_AI_BLINK		0x0080
803 #define PCIEM_SLOTCTL_AI_OFF		0x00c0
804 #define PCIEM_SLOTCTL_PIC		0x0300
805 #define PCIEM_SLOTCTL_PI_ON		0x0100
806 #define PCIEM_SLOTCTL_PI_BLINK		0x0200
807 #define PCIEM_SLOTCTL_PI_OFF		0x0300
808 #define PCIEM_SLOTCTL_PCC		0x0400
809 #define PCIEM_SLOTCTL_PC_ON		0x0000
810 #define PCIEM_SLOTCTL_PC_OFF		0x0400
811 #define PCIEM_SLOTCTL_EIC		0x0800
812 #define PCIEM_SLOTCTL_DLLSCE		0x1000
813 
814 #define PCIER_SLOTSTA			0x1a
815 #define PCIEM_SLOTSTA_ABP		0x0001
816 #define PCIEM_SLOTSTA_PFD		0x0002
817 #define PCIEM_SLOTSTA_MRLSC		0x0004
818 #define PCIEM_SLOTSTA_PDC		0x0008
819 #define PCIEM_SLOTSTA_CC		0x0010
820 #define PCIEM_SLOTSTA_MRLSS		0x0020
821 #define PCIEM_SLOTSTA_PDS		0x0040
822 #define PCIEM_SLOTSTA_EIS		0x0080
823 #define PCIEM_SLOTSTA_DLLSC		0x0100
824 
825 /* PCI Express hot-plug interrupts */
826 #define PCIE_HPINTR_ATTEN_BTN		0x0001	/* Attention button intr */
827 #define PCIE_HPINTR_PWR_FAULT		0x0002	/* Power fault intr */
828 #define PCIE_HPINTR_MRL_SNS		0x0004	/* MRL sensor changed intr */
829 #define PCIE_HPINTR_PRSN_DETECT		0x0008	/* Presence detect intr */
830 #define PCIE_HPINTR_CMD_COMPL		0x0010	/* Command completed intr */
831 
832 /* PCI Express device capabilities 2, 32bits */
833 #define PCIER_DEVCAP2			0x24
834 #define PCIEM_DEVCAP2_COMP_TIMO_RANGES	0x0000000f
835 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_A	0x00000001
836 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_B	0x00000002
837 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_C	0x00000004
838 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_D	0x00000008
839 #define PCIEM_DEVCAP2_COMP_TIMO_DISABLE	0x00000010
840 #define PCIEM_DEVCAP2_ALT_RID_SUPP	0x00000020
841 #define PCIEM_DEVCAP2_LTR_SUPP		0x00000800
842 
843 /* PCI Express device control 2, 16bits */
844 #define PCIER_DEVCTRL2			0x28
845 #define PCIEM_DEVCTL2_COMP_TIMO_MASK	0x000f
846 #define PCIEM_DEVCTL2_COMP_TIMO_50MS	0x0000
847 #define PCIEM_DEVCTL2_COMP_TIMO_100US	0x0001
848 #define PCIEM_DEVCTL2_COMP_TIMO_10MS	0x0002
849 #define PCIEM_DEVCTL2_COMP_TIMO_55MS	0x0005
850 #define PCIEM_DEVCTL2_COMP_TIMO_210MS	0x0006
851 #define PCIEM_DEVCTL2_COMP_TIMO_900MS	0x0009
852 #define PCIEM_DEVCTL2_COMP_TIMO_3500MS	0x000a
853 #define PCIEM_DEVCTL2_COMP_TIMO_13S	0x000d
854 #define PCIEM_DEVCTL2_COMP_TIMO_64S	0x000e
855 #define PCIEM_DEVCTL2_COMP_TIMO_DISABLE	0x0010
856 #define PCIEM_DEVCTL2_ALT_RID_ENABLE	0x0020
857 #define PCIEM_DEVCTL2_LTR_ENABLE	0x0400
858 
859 /* PCI Express link capabilities 2, 32bits */
860 #define PCIER_LINK_CAP2			0x2c
861 
862 /* PCI Advanced Features definitions */
863 #define	PCIR_PCIAF_CAP		0x3
864 #define	PCIM_PCIAFCAP_TP	0x01
865 #define	PCIM_PCIAFCAP_FLR	0x02
866 #define	PCIR_PCIAF_CTRL		0x4
867 #define	PCIR_PCIAFCTRL_FLR	0x01
868 #define	PCIR_PCIAF_STATUS	0x5
869 #define	PCIR_PCIAFSTATUS_TP	0x01
870 
871 /* Advanced Error Reporting */
872 #define	PCIR_AER_UC_STATUS	0x04
873 #define	PCIM_AER_UC_TRAINING_ERROR		0x00000001
874 #define	PCIM_AER_UC_DL_PROTOCOL_ERROR		0x00000010
875 #define	PCIM_AER_UC_SURPRISE_LINK_DOWN		0x00000020
876 #define	PCIM_AER_UC_POISONED_TLP		0x00001000
877 #define	PCIM_AER_UC_FC_PROTOCOL_ERROR		0x00002000
878 #define	PCIM_AER_UC_COMPLETION_TIMEOUT		0x00004000
879 #define	PCIM_AER_UC_COMPLETER_ABORT		0x00008000
880 #define	PCIM_AER_UC_UNEXPECTED_COMPLETION	0x00010000
881 #define	PCIM_AER_UC_RECEIVER_OVERFLOW		0x00020000
882 #define	PCIM_AER_UC_MALFORMED_TLP		0x00040000
883 #define	PCIM_AER_UC_ECRC_ERROR			0x00080000
884 #define	PCIM_AER_UC_UNSUPPORTED_REQUEST		0x00100000
885 #define	PCIM_AER_UC_ACS_VIOLATION		0x00200000
886 #define PCIM_AER_UC_INTERNAL_ERROR		0x00400000
887 #define PCIM_AER_UC_MC_BLOCKED_TLP		0x00800000
888 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK		0x01000000
889 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED		0x02000000
890 
891 #define	PCIR_AER_UC_MASK	0x08	/* Shares bits with UC_STATUS */
892 #define	PCIR_AER_UC_SEVERITY	0x0c	/* Shares bits with UC_STATUS */
893 #define	PCIR_AER_COR_STATUS	0x10
894 
895 #define	PCIM_AER_COR_RECEIVER_ERROR	0x00000001
896 #define	PCIM_AER_COR_BAD_TLP		0x00000040
897 #define	PCIM_AER_COR_BAD_DLLP		0x00000080
898 #define	PCIM_AER_COR_REPLAY_ROLLOVER	0x00000100
899 #define	PCIM_AER_COR_REPLAY_TIMEOUT	0x00001000
900 #define	PCIM_AER_COR_ADVISORY_NF_ERROR	0x00002000
901 #define PCIM_AER_COR_INTERNAL_ERROR	0x00004000
902 #define PCIM_AER_COR_HEADER_LOG_OVFLOW	0x00008000
903 #define	PCIR_AER_COR_MASK	0x14	/* Shares bits with COR_STATUS */
904 
905 #define	PCIR_AER_CAP_CONTROL	0x18
906 #define	PCIM_AER_FIRST_ERROR_PTR	0x0000001f
907 #define	PCIM_AER_ECRC_GEN_CAPABLE	0x00000020
908 #define	PCIM_AER_ECRC_GEN_ENABLE	0x00000040
909 #define	PCIM_AER_ECRC_CHECK_CAPABLE	0x00000080
910 #define	PCIM_AER_ECRC_CHECK_ENABLE	0x00000100
911 #define PCIM_AER_MULT_HDR_CAPABLE	0x00000200
912 #define PCIM_AER_MULT_HDR_ENABLE	0x00000400
913 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT	0x00000800
914 
915 #define	PCIR_AER_HEADER_LOG	0x1c
916 #define	PCIR_AER_ROOTERR_CMD	0x2c	/* Only for root complex ports */
917 #define	PCIM_AER_ROOTERR_COR_ENABLE	0x00000001
918 #define	PCIM_AER_ROOTERR_NF_ENABLE	0x00000002
919 #define	PCIM_AER_ROOTERR_F_ENABLE	0x00000004
920 #define	PCIR_AER_ROOTERR_STATUS	0x30	/* Only for root complex ports */
921 #define	PCIM_AER_ROOTERR_COR_ERR	0x00000001
922 #define	PCIM_AER_ROOTERR_MULTI_COR_ERR	0x00000002
923 #define	PCIM_AER_ROOTERR_UC_ERR		0x00000004
924 #define	PCIM_AER_ROOTERR_MULTI_UC_ERR	0x00000008
925 #define	PCIM_AER_ROOTERR_FIRST_UC_FATAL	0x00000010
926 #define	PCIM_AER_ROOTERR_NF_ERR		0x00000020
927 #define	PCIM_AER_ROOTERR_F_ERR		0x00000040
928 #define	PCIM_AER_ROOTERR_INT_MESSAGE	0xf8000000
929 #define	PCIR_AER_COR_SOURCE_ID	0x34	/* Only for root complex ports */
930 #define	PCIR_AER_ERR_SOURCE_ID	0x36	/* Only for root complex ports */
931 
932 /* Virtual Channel definitions */
933 #define	PCIR_VC_CAP1		0x04
934 #define	PCIM_VC_CAP1_EXT_COUNT		0x00000007
935 #define	PCIM_VC_CAP1_LOWPRI_EXT_COUNT	0x00000070
936 #define	PCIR_VC_CAP2		0x08
937 #define	PCIR_VC_CONTROL		0x0C
938 #define	PCIR_VC_STATUS		0x0E
939 #define	PCIR_VC_RESOURCE_CAP(n)	(0x10 + (n) * 0x0C)
940 #define	PCIR_VC_RESOURCE_CTL(n)	(0x14 + (n) * 0x0C)
941 #define	PCIR_VC_RESOURCE_STA(n)	(0x18 + (n) * 0x0C)
942 
943 /* Serial Number definitions */
944 #define	PCIR_SERIAL_LOW		0x04
945 #define	PCIR_SERIAL_HIGH	0x08
946 
947 #endif	/* _PCIREG_H_ */
948