1 /* $OpenBSD: pcireg.h,v 1.63 2024/05/13 10:01:53 kettenis Exp $ */ 2 /* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 #define PCI_CONFIG_SPACE_SIZE 0x100 44 #define PCIE_CONFIG_SPACE_SIZE 0x1000 45 46 /* 47 * Device identification register; contains a vendor ID and a device ID. 48 */ 49 #define PCI_ID_REG 0x00 50 51 typedef u_int16_t pci_vendor_id_t; 52 typedef u_int16_t pci_product_id_t; 53 54 #define PCI_VENDOR_SHIFT 0 55 #define PCI_VENDOR_MASK 0xffff 56 #define PCI_VENDOR(id) \ 57 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 58 59 #define PCI_PRODUCT_SHIFT 16 60 #define PCI_PRODUCT_MASK 0xffff 61 #define PCI_PRODUCT(id) \ 62 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 63 64 #define PCI_ID_CODE(vid,pid) \ 65 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 66 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 67 68 /* 69 * Command and status register. 70 */ 71 #define PCI_COMMAND_STATUS_REG 0x04 72 73 #define PCI_COMMAND_IO_ENABLE 0x00000001 74 #define PCI_COMMAND_MEM_ENABLE 0x00000002 75 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 76 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 77 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 78 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 79 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 80 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 81 #define PCI_COMMAND_SERR_ENABLE 0x00000100 82 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 83 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 84 85 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 86 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 87 #define PCI_STATUS_UDF_SUPPORT 0x00400000 88 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 89 #define PCI_STATUS_PARITY_ERROR 0x01000000 90 #define PCI_STATUS_DEVSEL_FAST 0x00000000 91 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 92 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 93 #define PCI_STATUS_DEVSEL_MASK 0x06000000 94 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 95 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 96 #define PCI_STATUS_MASTER_ABORT 0x20000000 97 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 98 #define PCI_STATUS_PARITY_DETECT 0x80000000 99 100 #define PCI_COMMAND_STATUS_BITS \ 101 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 102 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 103 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 104 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 105 "\037SPECIAL_ERROR\040PARITY_DETECT") 106 /* 107 * PCI Class and Revision Register; defines type and revision of device. 108 */ 109 #define PCI_CLASS_REG 0x08 110 111 typedef u_int8_t pci_class_t; 112 typedef u_int8_t pci_subclass_t; 113 typedef u_int8_t pci_interface_t; 114 typedef u_int8_t pci_revision_t; 115 116 #define PCI_CLASS_SHIFT 24 117 #define PCI_CLASS_MASK 0xff 118 #define PCI_CLASS(cr) \ 119 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 120 121 #define PCI_SUBCLASS_SHIFT 16 122 #define PCI_SUBCLASS_MASK 0xff 123 #define PCI_SUBCLASS(cr) \ 124 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 125 126 #define PCI_INTERFACE_SHIFT 8 127 #define PCI_INTERFACE_MASK 0xff 128 #define PCI_INTERFACE(cr) \ 129 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 130 131 #define PCI_REVISION_SHIFT 0 132 #define PCI_REVISION_MASK 0xff 133 #define PCI_REVISION(cr) \ 134 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 135 136 /* base classes */ 137 #define PCI_CLASS_PREHISTORIC 0x00 138 #define PCI_CLASS_MASS_STORAGE 0x01 139 #define PCI_CLASS_NETWORK 0x02 140 #define PCI_CLASS_DISPLAY 0x03 141 #define PCI_CLASS_MULTIMEDIA 0x04 142 #define PCI_CLASS_MEMORY 0x05 143 #define PCI_CLASS_BRIDGE 0x06 144 #define PCI_CLASS_COMMUNICATIONS 0x07 145 #define PCI_CLASS_SYSTEM 0x08 146 #define PCI_CLASS_INPUT 0x09 147 #define PCI_CLASS_DOCK 0x0a 148 #define PCI_CLASS_PROCESSOR 0x0b 149 #define PCI_CLASS_SERIALBUS 0x0c 150 #define PCI_CLASS_WIRELESS 0x0d 151 #define PCI_CLASS_I2O 0x0e 152 #define PCI_CLASS_SATCOM 0x0f 153 #define PCI_CLASS_CRYPTO 0x10 154 #define PCI_CLASS_DASP 0x11 155 #define PCI_CLASS_ACCELERATOR 0x12 156 #define PCI_CLASS_INSTRUMENTATION 0x13 157 #define PCI_CLASS_UNDEFINED 0xff 158 159 /* 0x00 prehistoric subclasses */ 160 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 161 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 162 163 /* 0x01 mass storage subclasses */ 164 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 165 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 166 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 167 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 168 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 169 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 170 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 171 #define PCI_INTERFACE_SATA_AHCI10 0x01 172 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 173 #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 174 #define PCI_SUBCLASS_MASS_STORAGE_UFS 0x09 175 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 176 177 /* 0x02 network subclasses */ 178 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 179 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 180 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 181 #define PCI_SUBCLASS_NETWORK_ATM 0x03 182 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 183 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 184 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 185 #define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 186 #define PCI_SUBCLASS_NETWORK_MISC 0x80 187 188 /* 0x03 display subclasses */ 189 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 190 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 191 #define PCI_SUBCLASS_DISPLAY_3D 0x02 192 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 193 194 /* 0x04 multimedia subclasses */ 195 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 196 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 197 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 198 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 199 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 200 201 /* 0x05 memory subclasses */ 202 #define PCI_SUBCLASS_MEMORY_RAM 0x00 203 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 204 #define PCI_SUBCLASS_MEMORY_MISC 0x80 205 206 /* 0x06 bridge subclasses */ 207 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 208 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 209 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 210 #define PCI_SUBCLASS_BRIDGE_MC 0x03 211 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 212 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 213 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 214 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 215 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 216 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 217 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 218 #define PCI_SUBCLASS_BRIDGE_AS 0x0b 219 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 220 221 /* 0x07 communications subclasses */ 222 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 223 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 224 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 225 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 226 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 227 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 228 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 229 230 /* 0x08 system subclasses */ 231 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 232 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 233 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 234 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 235 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 236 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 237 #define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 238 #define PCI_SUBCLASS_SYSTEM_ROOTCOMPEVENT 0x07 239 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 240 241 /* 0x09 input subclasses */ 242 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 243 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 244 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 245 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 246 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 247 #define PCI_SUBCLASS_INPUT_MISC 0x80 248 249 /* 0x0a dock subclasses */ 250 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 251 #define PCI_SUBCLASS_DOCK_MISC 0x80 252 253 /* 0x0b processor subclasses */ 254 #define PCI_SUBCLASS_PROCESSOR_386 0x00 255 #define PCI_SUBCLASS_PROCESSOR_486 0x01 256 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 257 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 258 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 259 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 260 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 261 262 /* 0x0c serial bus subclasses */ 263 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 264 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 265 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 266 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 267 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 268 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 269 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 270 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 271 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 272 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 273 274 /* 0x0d wireless subclasses */ 275 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 276 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 277 #define PCI_SUBCLASS_WIRELESS_RF 0x10 278 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 279 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 280 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 281 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 282 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 283 284 /* 0x0e I2O (Intelligent I/O) subclasses */ 285 #define PCI_SUBCLASS_I2O_STANDARD 0x00 286 287 /* 0x0f satellite communication subclasses */ 288 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 289 #define PCI_SUBCLASS_SATCOM_TV 0x01 290 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 291 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 292 #define PCI_SUBCLASS_SATCOM_DATA 0x04 293 294 /* 0x10 encryption/decryption subclasses */ 295 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 296 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 297 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 298 299 /* 0x11 data acquisition and signal processing subclasses */ 300 #define PCI_SUBCLASS_DASP_DPIO 0x00 301 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 302 #define PCI_SUBCLASS_DASP_SYNC 0x10 303 #define PCI_SUBCLASS_DASP_MGMT 0x20 304 #define PCI_SUBCLASS_DASP_MISC 0x80 305 306 /* 307 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 308 */ 309 #define PCI_BHLC_REG 0x0c 310 311 #define PCI_BIST_SHIFT 24 312 #define PCI_BIST_MASK 0xff 313 #define PCI_BIST(bhlcr) \ 314 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 315 316 #define PCI_HDRTYPE_SHIFT 16 317 #define PCI_HDRTYPE_MASK 0xff 318 #define PCI_HDRTYPE(bhlcr) \ 319 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 320 321 #define PCI_HDRTYPE_TYPE(bhlcr) \ 322 (PCI_HDRTYPE(bhlcr) & 0x7f) 323 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 324 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 325 326 #define PCI_LATTIMER_SHIFT 8 327 #define PCI_LATTIMER_MASK 0xff 328 #define PCI_LATTIMER(bhlcr) \ 329 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 330 331 #define PCI_CACHELINE_SHIFT 0 332 #define PCI_CACHELINE_MASK 0xff 333 #define PCI_CACHELINE(bhlcr) \ 334 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 335 336 /* config registers for header type 0 devices */ 337 338 #define PCI_MAPS 0x10 339 #define PCI_CARDBUSCIS 0x28 340 #define PCI_SUBVEND_0 0x2c 341 #define PCI_SUBDEV_0 0x2e 342 #define PCI_EXROMADDR_0 0x30 343 #define PCI_INTLINE 0x3c 344 #define PCI_INTPIN 0x3d 345 #define PCI_MINGNT 0x3e 346 #define PCI_MAXLAT 0x3f 347 348 /* config registers for header type 1 devices */ 349 350 #define PCI_SECSTAT_1 0 /**/ 351 352 #define PCI_PRIBUS_1 0x18 353 #define PCI_SECBUS_1 0x19 354 #define PCI_SUBBUS_1 0x1a 355 #define PCI_SECLAT_1 0x1b 356 357 #define PCI_IOBASEL_1 0x1c 358 #define PCI_IOLIMITL_1 0x1d 359 #define PCI_IOBASEH_1 0 /**/ 360 #define PCI_IOLIMITH_1 0 /**/ 361 362 #define PCI_MEMBASE_1 0x20 363 #define PCI_MEMLIMIT_1 0x22 364 365 #define PCI_PMBASEL_1 0x24 366 #define PCI_PMLIMITL_1 0x26 367 #define PCI_PMBASEH_1 0 /**/ 368 #define PCI_PMLIMITH_1 0 /**/ 369 370 #define PCI_BRIDGECTL_1 0 /**/ 371 372 #define PCI_SUBVEND_1 0x34 373 #define PCI_SUBDEV_1 0x36 374 #define PCI_EXROMADDR_1 0x38 375 376 /* config registers for header type 2 devices */ 377 378 #define PCI_SECSTAT_2 0x16 379 380 #define PCI_PRIBUS_2 0x18 381 #define PCI_SECBUS_2 0x19 382 #define PCI_SUBBUS_2 0x1a 383 #define PCI_SECLAT_2 0x1b 384 385 #define PCI_MEMBASE0_2 0x1c 386 #define PCI_MEMLIMIT0_2 0x20 387 #define PCI_MEMBASE1_2 0x24 388 #define PCI_MEMLIMIT1_2 0x28 389 #define PCI_IOBASE0_2 0x2c 390 #define PCI_IOLIMIT0_2 0x30 391 #define PCI_IOBASE1_2 0x34 392 #define PCI_IOLIMIT1_2 0x38 393 394 #define PCI_BRIDGECTL_2 0x3e 395 396 #define PCI_SUBVEND_2 0x40 397 #define PCI_SUBDEV_2 0x42 398 399 #define PCI_PCCARDIF_2 0x44 400 401 /* 402 * Mapping registers 403 */ 404 #define PCI_MAPREG_START 0x10 405 #define PCI_MAPREG_END 0x28 406 #define PCI_MAPREG_PPB_END 0x18 407 #define PCI_MAPREG_PCB_END 0x14 408 409 #define PCI_MAPREG_TYPE(mr) \ 410 ((mr) & PCI_MAPREG_TYPE_MASK) 411 #define PCI_MAPREG_TYPE_MASK 0x00000001 412 413 #define PCI_MAPREG_TYPE_MEM 0x00000000 414 #define PCI_MAPREG_TYPE_IO 0x00000001 415 416 #define PCI_MAPREG_MEM_TYPE(mr) \ 417 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 418 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 419 420 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 421 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 422 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 423 424 #define _PCI_MAPREG_TYPEBITS(reg) \ 425 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 426 reg & PCI_MAPREG_TYPE_MASK : \ 427 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 428 429 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 430 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 431 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 432 433 #define PCI_MAPREG_MEM_ADDR(mr) \ 434 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 435 #define PCI_MAPREG_MEM_SIZE(mr) \ 436 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 437 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 438 439 #define PCI_MAPREG_MEM64_ADDR(mr) \ 440 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 441 #define PCI_MAPREG_MEM64_SIZE(mr) \ 442 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 443 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 444 445 #define PCI_MAPREG_IO_ADDR(mr) \ 446 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 447 #define PCI_MAPREG_IO_SIZE(mr) \ 448 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 449 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 450 451 /* 452 * Cardbus CIS pointer (PCI rev. 2.1) 453 */ 454 #define PCI_CARDBUS_CIS_REG 0x28 455 456 /* 457 * Subsystem identification register; contains a vendor ID and a device ID. 458 * Types/macros for PCI_ID_REG apply. 459 * (PCI rev. 2.1) 460 */ 461 #define PCI_SUBSYS_ID_REG 0x2c 462 463 /* 464 * Expansion ROM Base Address register 465 * (PCI rev. 2.0) 466 */ 467 #define PCI_ROM_REG 0x30 468 469 #define PCI_ROM_ENABLE 0x00000001 470 #define PCI_ROM_ADDR_MASK 0xfffff800 471 #define PCI_ROM_ADDR(mr) \ 472 ((mr) & PCI_ROM_ADDR_MASK) 473 #define PCI_ROM_SIZE(mr) \ 474 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 475 476 /* 477 * capabilities link list (PCI rev. 2.2) 478 */ 479 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 480 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 481 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 482 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 483 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 484 485 #define PCI_CAP_RESERVED 0x00 486 #define PCI_CAP_PWRMGMT 0x01 487 #define PCI_CAP_AGP 0x02 488 #define PCI_CAP_VPD 0x03 489 #define PCI_CAP_SLOTID 0x04 490 #define PCI_CAP_MSI 0x05 491 #define PCI_CAP_CPCI_HOTSWAP 0x06 492 #define PCI_CAP_PCIX 0x07 493 #define PCI_CAP_HT 0x08 494 #define PCI_CAP_VENDSPEC 0x09 495 #define PCI_CAP_DEBUGPORT 0x0a 496 #define PCI_CAP_CPCI_RSRCCTL 0x0b 497 #define PCI_CAP_HOTPLUG 0x0c 498 #define PCI_CAP_AGP8 0x0e 499 #define PCI_CAP_SECURE 0x0f 500 #define PCI_CAP_PCIEXPRESS 0x10 501 #define PCI_CAP_MSIX 0x11 502 #define PCI_CAP_SATA 0x12 503 504 /* 505 * Vital Product Data; access via capability pointer (PCI rev 2.2). 506 */ 507 #define PCI_VPD_ADDRESS_MASK 0x7fff 508 #define PCI_VPD_ADDRESS_SHIFT 16 509 #define PCI_VPD_ADDRESS(ofs) \ 510 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 511 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 512 #define PCI_VPD_OPFLAG 0x80000000 513 514 /* 515 * Message Signaled Interrupts; access via capability pointer. 516 */ 517 #define PCI_MSI_MC 0x00 518 #define PCI_MSI_MC_PVMASK 0x01000000 519 #define PCI_MSI_MC_C64 0x00800000 520 #define PCI_MSI_MC_MME_MASK 0x00700000 521 #define PCI_MSI_MC_MME_SHIFT 20 522 #define PCI_MSI_MC_MMC_MASK 0x000e0000 523 #define PCI_MSI_MC_MMC_SHIFT 17 524 #define PCI_MSI_MC_MSIE 0x00010000 525 #define PCI_MSI_MA 0x04 526 #define PCI_MSI_MAU32 0x08 527 #define PCI_MSI_MD32 0x08 528 #define PCI_MSI_MD64 0x0c 529 #define PCI_MSI_MASK32 0x0c 530 #define PCI_MSI_MASK64 0x10 531 532 /* 533 * Power Management Control Status Register; access via capability pointer. 534 */ 535 #define PCI_PMCSR 0x04 536 #define PCI_PMCSR_STATE_MASK 0x0003 537 #define PCI_PMCSR_STATE_D0 0x0000 538 #define PCI_PMCSR_STATE_D1 0x0001 539 #define PCI_PMCSR_STATE_D2 0x0002 540 #define PCI_PMCSR_STATE_D3 0x0003 541 #define PCI_PMCSR_PME_STATUS 0x8000 542 #define PCI_PMCSR_PME_EN 0x0100 543 544 /* 545 * HyperTransport; access via capability pointer. 546 */ 547 #define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 548 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 549 550 #define PCI_HT_CAP_SLAVE 0x00 551 #define PCI_HT_CAP_HOST 0x04 552 #define PCI_HT_CAP_INTR 0x10 553 #define PCI_HT_CAP_MSI 0x15 554 555 #define PCI_HT_MSI_ENABLED 0x00010000 556 #define PCI_HT_MSI_FIXED 0x00020000 557 558 #define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 559 560 #define PCI_HT_MSI_ADDR 0x04 561 #define PCI_HT_MSI_ADDR_HI32 0x08 562 563 #define PCI_HT_INTR_DATA 0x04 564 565 /* 566 * PCI Express; access via capability pointer. 567 */ 568 #define PCI_PCIE_XCAP 0x00 569 #define PCI_PCIE_XCAP_SI 0x01000000 570 #define PCI_PCIE_XCAP_VER(x) (((x) >> 16) & 0x0f) 571 #define PCI_PCIE_XCAP_TYPE(x) (((x) >> 20) & 0x0f) 572 #define PCI_PCIE_XCAP_TYPE_RP 0x4 573 #define PCI_PCIE_XCAP_TYPE_DOWN 0x6 574 #define PCI_PCIE_XCAP_TYPE_PCI2PCIE 0x8 575 #define PCI_PCIE_DCAP 0x04 576 #define PCI_PCIE_DCSR 0x08 577 #define PCI_PCIE_DCSR_ERO 0x00000010 578 #define PCI_PCIE_DCSR_ENS 0x00000800 579 #define PCI_PCIE_DCSR_MPS 0x00007000 580 #define PCI_PCIE_DCSR_CEE 0x00010000 581 #define PCI_PCIE_DCSR_NFE 0x00020000 582 #define PCI_PCIE_DCSR_FEE 0x00040000 583 #define PCI_PCIE_DCSR_URE 0x00080000 584 #define PCI_PCIE_LCAP 0x0c 585 #define PCI_PCIE_LCSR 0x10 586 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 587 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 588 #define PCI_PCIE_LCSR_RL 0x00000020 589 #define PCI_PCIE_LCSR_CCC 0x00000040 590 #define PCI_PCIE_LCSR_ES 0x00000080 591 #define PCI_PCIE_LCSR_ECPM 0x00000100 592 #define PCI_PCIE_LCSR_CLS 0x000f0000 593 #define PCI_PCIE_LCSR_CLS_2_5 0x00010000 594 #define PCI_PCIE_LCSR_CLS_5 0x00020000 595 #define PCI_PCIE_LCSR_CLS_8 0x00030000 596 #define PCI_PCIE_LCSR_CLS_16 0x00040000 597 #define PCI_PCIE_LCSR_CLS_32 0x00050000 598 #define PCI_PCIE_LCSR_LT 0x08000000 599 #define PCI_PCIE_LCSR_SCC 0x10000000 600 #define PCI_PCIE_SLCAP 0x14 601 #define PCI_PCIE_SLCAP_ABP 0x00000001 602 #define PCI_PCIE_SLCAP_PCP 0x00000002 603 #define PCI_PCIE_SLCAP_MSP 0x00000004 604 #define PCI_PCIE_SLCAP_AIP 0x00000008 605 #define PCI_PCIE_SLCAP_PIP 0x00000010 606 #define PCI_PCIE_SLCAP_HPS 0x00000020 607 #define PCI_PCIE_SLCAP_HPC 0x00000040 608 #define PCI_PCIE_SLCSR 0x18 609 #define PCI_PCIE_SLCSR_ABE 0x00000001 610 #define PCI_PCIE_SLCSR_PFE 0x00000002 611 #define PCI_PCIE_SLCSR_MSE 0x00000004 612 #define PCI_PCIE_SLCSR_PDE 0x00000008 613 #define PCI_PCIE_SLCSR_CCE 0x00000010 614 #define PCI_PCIE_SLCSR_HPE 0x00000020 615 #define PCI_PCIE_SLCSR_ABP 0x00010000 616 #define PCI_PCIE_SLCSR_PFD 0x00020000 617 #define PCI_PCIE_SLCSR_MSC 0x00040000 618 #define PCI_PCIE_SLCSR_PDC 0x00080000 619 #define PCI_PCIE_SLCSR_CC 0x00100000 620 #define PCI_PCIE_SLCSR_MS 0x00200000 621 #define PCI_PCIE_SLCSR_PDS 0x00400000 622 #define PCI_PCIE_SLCSR_LACS 0x01000000 623 #define PCI_PCIE_RCSR 0x1c 624 #define PCI_PCIE_DCSR2 0x28 625 #define PCI_PCIE_DCSR2_LTREN 0x00000400 626 #define PCI_PCIE_LCAP2 0x2c 627 #define PCI_PCIE_LCSR2 0x30 628 #define PCI_PCIE_LCSR2_TLS 0x0000000f 629 #define PCI_PCIE_LCSR2_TLS_2_5 0x00000001 630 #define PCI_PCIE_LCSR2_TLS_5 0x00000002 631 #define PCI_PCIE_LCSR2_TLS_8 0x00000003 632 #define PCI_PCIE_LCSR2_TLS_16 0x00000004 633 #define PCI_PCIE_LCSR2_TLS_32 0x00000005 634 635 /* 636 * PCI Express; enhanced capabilities 637 */ 638 #define PCI_PCIE_ECAP 0x100 639 #define PCI_PCIE_ECAP_ID(x) (((x) & 0x0000ffff)) 640 #define PCI_PCIE_ECAP_VER(x) (((x) >> 16) & 0x0f) 641 #define PCI_PCIE_ECAP_NEXT(x) (((x) >> 20) & 0xffc) 642 #define PCI_PCIE_ECAP_LAST 0x0 643 644 /* 645 * Extended Message Signaled Interrupts; access via capability pointer. 646 */ 647 #define PCI_MSIX_MC_MSIXE 0x80000000 648 #define PCI_MSIX_MC_FM 0x40000000 649 #define PCI_MSIX_MC_TBLSZ_MASK 0x07ff0000 650 #define PCI_MSIX_MC_TBLSZ_SHIFT 16 651 #define PCI_MSIX_MC_TBLSZ(reg) \ 652 (((reg) & PCI_MSIX_MC_TBLSZ_MASK) >> PCI_MSIX_MC_TBLSZ_SHIFT) 653 #define PCI_MSIX_TABLE 0x04 654 #define PCI_MSIX_TABLE_BIR 0x00000007 655 #define PCI_MSIX_TABLE_OFF ~(PCI_MSIX_TABLE_BIR) 656 657 #define PCI_MSIX_MA(i) ((i) * 16 + 0) 658 #define PCI_MSIX_MAU32(i) ((i) * 16 + 4) 659 #define PCI_MSIX_MD(i) ((i) * 16 + 8) 660 #define PCI_MSIX_VC(i) ((i) * 16 + 12) 661 #define PCI_MSIX_VC_MASK 0x00000001 662 663 /* 664 * Interrupt Configuration Register; contains interrupt pin and line. 665 */ 666 #define PCI_INTERRUPT_REG 0x3c 667 668 typedef u_int8_t pci_intr_pin_t; 669 typedef u_int8_t pci_intr_line_t; 670 671 #define PCI_INTERRUPT_PIN_SHIFT 8 672 #define PCI_INTERRUPT_PIN_MASK 0xff 673 #define PCI_INTERRUPT_PIN(icr) \ 674 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 675 676 #define PCI_INTERRUPT_LINE_SHIFT 0 677 #define PCI_INTERRUPT_LINE_MASK 0xff 678 #define PCI_INTERRUPT_LINE(icr) \ 679 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 680 681 #define PCI_MIN_GNT_SHIFT 16 682 #define PCI_MIN_GNT_MASK 0xff 683 #define PCI_MIN_GNT(icr) \ 684 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 685 686 #define PCI_MAX_LAT_SHIFT 24 687 #define PCI_MAX_LAT_MASK 0xff 688 #define PCI_MAX_LAT(icr) \ 689 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 690 691 #define PCI_INTERRUPT_PIN_NONE 0x00 692 #define PCI_INTERRUPT_PIN_A 0x01 693 #define PCI_INTERRUPT_PIN_B 0x02 694 #define PCI_INTERRUPT_PIN_C 0x03 695 #define PCI_INTERRUPT_PIN_D 0x04 696 #define PCI_INTERRUPT_PIN_MAX 0x04 697 698 /* 699 * Vital Product Data resource tags. 700 */ 701 struct pci_vpd_smallres { 702 uint8_t vpdres_byte0; /* length of data + tag */ 703 /* Actual data. */ 704 } __packed; 705 706 struct pci_vpd_largeres { 707 uint8_t vpdres_byte0; 708 uint8_t vpdres_len_lsb; /* length of data only */ 709 uint8_t vpdres_len_msb; 710 /* Actual data. */ 711 } __packed; 712 713 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 714 715 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 716 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 717 718 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 719 720 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 721 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 722 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 723 724 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 725 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 726 727 struct pci_vpd { 728 uint8_t vpd_key0; 729 uint8_t vpd_key1; 730 uint8_t vpd_len; /* length of data only */ 731 /* Actual data. */ 732 } __packed; 733 734 /* 735 * Recommended VPD fields: 736 * 737 * PN Part number of assembly 738 * FN FRU part number 739 * EC EC level of assembly 740 * MN Manufacture ID 741 * SN Serial Number 742 * 743 * Conditionally recommended VPD fields: 744 * 745 * LI Load ID 746 * RL ROM Level 747 * RM Alterable ROM Level 748 * NA Network Address 749 * DD Device Driver Level 750 * DG Diagnostic Level 751 * LL Loadable Microcode Level 752 * VI Vendor ID/Device ID 753 * FU Function Number 754 * SI Subsystem Vendor ID/Subsystem ID 755 * 756 * Additional VPD fields: 757 * 758 * Z0-ZZ User/Product Specific 759 */ 760 761 #endif /* _DEV_PCI_PCIREG_H_ */ 762