/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 103 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 103 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 103 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 103 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 104 #define PCI_PM_CTRL 0x04 macro
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/dports/net/ipxe/ipxe-2265a65/src/include/ipxe/ |
H A D | pci.h | 105 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 104 #define PCI_PM_CTRL 0x04 macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/include/ipxe/ |
H A D | pci.h | 104 #define PCI_PM_CTRL 0x04 macro
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/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/include/gpxe/ |
H A D | pci.h | 184 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/sysutils/rovclock/rovclock-0.6e/ |
H A D | pci.h | 206 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/lang/gnatdroid-sysroot-x86/android-19-x86/usr/include/linux/ |
H A D | pci_regs.h | 199 #define PCI_PM_CTRL 4 macro
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/dports/lang/gnatdroid-sysroot/android-19-arm/usr/include/linux/ |
H A D | pci_regs.h | 199 #define PCI_PM_CTRL 4 macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/ |
H A D | pci.h | 239 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/seabios-hppa/src/hw/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/qemu-palcode/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/seabios/src/hw/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/qemu-palcode/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/seabios-hppa/src/hw/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/seabios/src/hw/ |
H A D | pci_regs.h | 235 #define PCI_PM_CTRL 4 /* PM control and status register */ macro
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