1 /* $OpenBSD: octpcie.c,v 1.2 2019/09/22 04:43:24 visa Exp $ */
2
3 /*
4 * Copyright (c) 2019 Visa Hankala
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Driver for OCTEON II and OCTEON III PCIe controller.
21 */
22
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/extent.h>
27
28 #include <machine/autoconf.h>
29 #include <machine/octeonreg.h>
30 #include <machine/octeonvar.h>
31 #include <machine/octeon_model.h>
32
33 #include <dev/pci/pcidevs.h>
34 #include <dev/pci/pcireg.h>
35 #include <dev/pci/pcivar.h>
36 #include <dev/pci/ppbreg.h>
37
38 #include <octeon/dev/iobusvar.h>
39
40 #define PEM_BASE(port) (0x11800c0000000ULL + (port) * PEM_SIZE)
41 #define PEM_SIZE 0x01000000
42
43 #define PEM_BAR0_SIZE (1ULL << 14)
44 #define PEM_BAR2_SIZE (1ULL << 41)
45
46 #define PEM_CTL_STATUS 0x00000000
47 #define PEM_CTL_STATUS_LNK_ENB 0x0000000000000010ULL
48 #define PEM_CFG_WR 0x00000028
49 #define PEM_CFG_RD 0x00000030
50 #define PEM_P2P_BAR_START(i) (0x00000040 + (i) * 16)
51 #define PEM_P2P_BAR_END(i) (0x00000048 + (i) * 16)
52 #define PEM_P2N_BAR_START(i) (0x00000080 + (i) * 8)
53 #define PEM_BAR_CTL(cfg) ((cfg)->cfg_bar_ctl_reg)
54 #define PEM_BAR_CTL_BAR1_SIZ_M 0x0000000000000070ULL
55 #define PEM_BAR_CTL_BAR1_SIZ_256M 0x0000000000000030ULL
56 #define PEM_BAR_CTL_BAR2_ENB 0x0000000000000008ULL
57 #define PEM_BAR_CTL_BAR2_ESX_M 0x0000000000000006ULL
58 #define PEM_BAR_CTL_BAR2_ESX_S 1
59 #define PEM_BAR_CTL_BAR2_CAX 0x0000000000000001ULL
60 #define PEM_BAR1_INDEX(cfg, i) ((cfg)->cfg_bar1_index_reg + (i) * 8)
61 #define PEM_STRAP 0x00000408
62 #define PEM_STRAP_PIMODE_M 0x0000000000000003ULL
63 #define PEM_STRAP_PIMODE_RC 0x0000000000000003ULL
64
65 #define PCIERC_CFG001 0x00000004
66 #define PCIERC_CFG001_I_DIS 0x00000400U
67 #define PCIERC_CFG001_SEE 0x00000100U
68 #define PCIERC_CFG001_ME 0x00000004U
69 #define PCIERC_CFG001_MSAE 0x00000002U
70 #define PCIERC_CFG006 0x00000018
71 #define PCIERC_CFG008 0x00000020
72 #define PCIERC_CFG008_MLADDR_M 0xfff00000U
73 #define PCIERC_CFG008_MLADDR_S 20
74 #define PCIERC_CFG008_MBADDR_M 0x0000fff0U
75 #define PCIERC_CFG008_MBADDR_S 4
76 #define PCIERC_CFG009 0x00000024
77 #define PCIERC_CFG009_LMEM_LIMIT_M 0xfff00000U
78 #define PCIERC_CFG009_LMEM_LIMIT_S 20
79 #define PCIERC_CFG009_LMEM_BASE_M 0x0000fff0U
80 #define PCIERC_CFG009_LMEM_BASE_S 4
81 #define PCIERC_CFG010 0x00000028
82 #define PCIERC_CFG010_UMEM_BASE_M 0xffffffffU
83 #define PCIERC_CFG010_UMEM_BASE_S 0
84 #define PCIERC_CFG011 0x0000002c
85 #define PCIERC_CFG011_UMEM_LIMIT_M 0xffffffffU
86 #define PCIERC_CFG011_UMEM_LIMIT_S 0
87 #define PCIERC_CFG030 0x00000078
88 #define PCIERC_CFG030_MRRS_M 0x00007000U
89 #define PCIERC_CFG030_MRRS_S 12
90 #define PCIERC_CFG030_NS_EN 0x00000800U
91 #define PCIERC_CFG030_AP_EN 0x00000400U
92 #define PCIERC_CFG030_PF_EN 0x00000200U
93 #define PCIERC_CFG030_ETF_EN 0x00000100U
94 #define PCIERC_CFG030_MPS_M 0x000000e0U
95 #define PCIERC_CFG030_MPS_S 5
96 #define PCIERC_CFG030_RO_EN 0x00000010U
97 #define PCIERC_CFG030_UR_EN 0x00000008U
98 #define PCIERC_CFG030_FE_EN 0x00000004U
99 #define PCIERC_CFG030_NFE_EN 0x00000002U
100 #define PCIERC_CFG030_CE_EN 0x00000001U
101 #define PCIERC_CFG032 0x00000080
102 #define PCIERC_CFG032_DLLA 0x20000000U
103 #define PCIERC_CFG032_LT 0x08000000U
104 #define PCIERC_CFG032_ASLPC_M 0x00000003U
105 #define PCIERC_CFG032_ASLPC_S 0
106 #define PCIERC_CFG034 0x00000088
107 #define PCIERC_CFG034_DLLS_EN 0x00001000U
108 #define PCIERC_CFG034_CCINT_EN 0x00000010U
109 #define PCIERC_CFG035 0x0000008c
110 #define PCIERC_CFG035_PMEIE 0x00000008U
111 #define PCIERC_CFG035_SEFEE 0x00000004U
112 #define PCIERC_CFG035_SENFEE 0x00000002U
113 #define PCIERC_CFG035_SECEE 0x00000001U
114 #define PCIERC_CFG066 0x00000108
115 #define PCIERC_CFG069 0x00000114
116 #define PCIERC_CFG070 0x00000118
117 #define PCIERC_CFG070_CE 0x00000100U
118 #define PCIERC_CFG070_GE 0x00000040U
119 #define PCIERC_CFG075 0x0000012c
120 #define PCIERC_CFG075_FERE 0x00000004U
121 #define PCIERC_CFG075_NFERE 0x00000002U
122 #define PCIERC_CFG075_CERE 0x00000001U
123 #define PCIERC_CFG515 0x0000080c
124 #define PCIERC_CFG515_DSC 0x00000200U
125
126 #define DPI_BASE 0x1df0000000040ULL
127 #define DPI_SIZE 0x00001000
128 #define DPI_SLI_PRT_CFG(port) (0x00000900 + (port) * 8)
129 #define DPI_SLI_PRT_CFG_MOLR_M 0x0000000000003f00ULL
130 #define DPI_SLI_PRT_CFG_MOLR_S 8
131 #define DPI_SLI_PRT_CFG_MPS_M 0x0000000000000010ULL
132 #define DPI_SLI_PRT_CFG_MPS_S 4
133 #define DPI_SLI_PRT_CFG_MRRS_M 0x0000000000000003ULL
134 #define DPI_SLI_PRT_CFG_MRRS_S 0
135
136 #define SLI_BASE 0x11f0000000000ULL
137 #define SLI_SIZE 0x00020000
138 #define SLI_S2M_PORT_CTL(port) (0x00013d80 + (port) * 16)
139 #define SLI_S2M_PORT_CTL_MRRS_M 0x0000000000000007ULL
140 #define SLI_S2M_PORT_CTL_MRRS_S 0
141 #define SLI_MEM_ACCESS_CTL 0x000102f0U
142 #define SLI_MEM_ACCESS_CTL_MAXW_M 0x0000000000003c00ULL
143 #define SLI_MEM_ACCESS_CTL_MAXW_S 10
144 #define SLI_MEM_ACCESS_CTL_TIMER_M 0x00000000000003ffULL
145 #define SLI_MEM_ACCESS_CTL_TIMER_S 0
146 #define SLI_MEM_ACCESS_SUBID(i) (0x000000e0 + (i) * 16)
147 #define SLI_MEM_ACCESS_SUBID_PORT_M 0x0000038000000000ULL
148 #define SLI_MEM_ACCESS_SUBID_PORT_S 39
149 #define SLI_MEM_ACCESS_SUBID_NMERGE 0x0000004000000000ULL
150 #define SLI_MEM_ACCESS_SUBID_ESR_M 0x0000003000000000ULL
151 #define SLI_MEM_ACCESS_SUBID_ESR_S 36
152 #define SLI_MEM_ACCESS_SUBID_ESW_M 0x0000000c00000000ULL
153 #define SLI_MEM_ACCESS_SUBID_ESW_S 34
154 #define SLI_MEM_ACCESS_SUBID_WTYPE_M 0x0000000300000000ULL
155 #define SLI_MEM_ACCESS_SUBID_WTYPE_S 32
156 #define SLI_MEM_ACCESS_SUBID_RTYPE_M 0x00000000c0000000ULL
157 #define SLI_MEM_ACCESS_SUBID_RTYPE_S 30
158 #define SLI_MEM_ACCESS_SUBID_BA_M 0x000000003fffffffULL
159 #define SLI_MEM_ACCESS_SUBID_BA_S 0
160
161 #define SLI_PCIECFG_BASE(port) (0x1190c00000000ULL + (port) * SLI_PCIECFG_SIZE)
162 #define SLI_PCIECFG_SIZE (1ULL << 32)
163 #define SLI_PCIEIO_BASE(port) (0x11a0400000000ULL + (port) * SLI_PCIEIO_SIZE)
164 #define SLI_PCIEIO_SIZE (1ULL << 32)
165 #define SLI_PCIEMEM_BASE(port) (0x11b0000000000ULL + (port) * SLI_PCIEMEM_SIZE)
166 #define SLI_PCIEMEM_SIZE (1ULL << 40)
167
168 #define CIU_SOFT_PRST_ADDR 0x1070000000748ULL
169 #define CIU_SOFT_PRST1_ADDR 0x1070000000758ULL
170 #define RST_SOFT_PRST_ADDR(port) (0x11800060016c0ULL + (port) * 8)
171 #define PRST_SOFT_PRST 0x0000000000000001ULL
172
173 #define CIU3_PEM_INTSN_INTA(i) (((0xc0 + i) << 12) + 60)
174
175 struct octpcie_softc;
176
177 struct octpcie_config {
178 int cfg_nports;
179 uint32_t cfg_bar_ctl_reg;
180 uint32_t cfg_bar1_index_reg;
181 char cfg_has_ciu3;
182 };
183
184 struct octpcie_port {
185 struct mips_pci_chipset port_pc;
186 struct octpcie_softc *port_sc;
187 bus_space_tag_t port_iot;
188 bus_space_handle_t port_pem_ioh;
189 bus_space_handle_t port_pciecfg_ioh;
190 struct extent *port_ioex;
191 struct extent *port_memex;
192 char port_ioex_name[32];
193 char port_memex_name[32];
194 int port_index;
195 struct mips_bus_space port_bus_iot;
196 struct mips_bus_space port_bus_memt;
197 };
198
199 struct octpcie_softc {
200 struct device sc_dev;
201 bus_space_tag_t sc_iot;
202 bus_space_handle_t sc_dpi_ioh;
203 bus_space_handle_t sc_sli_ioh;
204 struct machine_bus_dma_tag *sc_dmat;
205 const struct octpcie_config *sc_cfg;
206 struct octpcie_port *sc_ports;
207 };
208
209 int octpcie_match(struct device *, void *, void *);
210 void octpcie_attach(struct device *, struct device *, void *);
211 int octpcie_print(void *, const char *);
212
213 void octpcie_attach_hook(struct device *, struct device *,
214 struct pcibus_attach_args *pba);
215 int octpcie_bus_maxdevs(void *, int);
216 pcitag_t octpcie_make_tag(void *, int, int, int);
217 void octpcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
218 int octpcie_conf_size(void *, pcitag_t);
219 pcireg_t octpcie_conf_read(void *, pcitag_t, int);
220 void octpcie_conf_write(void *, pcitag_t, int, pcireg_t);
221 int octpcie_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
222 const char *
223 octpcie_pci_intr_string(void *, pci_intr_handle_t);
224 void *octpcie_pci_intr_establish(void *, pci_intr_handle_t, int,
225 int (*)(void *), void *, char *);
226 void octpcie_pci_intr_disestablish(void *, void *);
227
228 int octpcie_io_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
229 bus_space_handle_t *);
230 int octpcie_mem_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
231 bus_space_handle_t *);
232
233 void octpcie_port_attach(struct octpcie_port *);
234 int octpcie_port_is_host(struct octpcie_port *);
235 int octpcie_port_reset(struct octpcie_port *);
236
237 uint32_t octpcie_cfgreg_read(struct octpcie_port *, uint32_t);
238 void octpcie_cfgreg_write(struct octpcie_port *, uint32_t, uint32_t);
239
240 const struct cfattach octpcie_ca = {
241 sizeof(struct octpcie_softc), octpcie_match, octpcie_attach
242 };
243
244 struct cfdriver octpcie_cd = {
245 NULL, "octpcie", DV_DULL
246 };
247
248 const struct octpcie_config cn61xx_config = {
249 .cfg_nports = 2,
250 .cfg_bar_ctl_reg = 0x00000128,
251 .cfg_bar1_index_reg = 0x000000a8,
252 };
253 const struct octpcie_config cn71xx_config = {
254 .cfg_nports = 3,
255 .cfg_bar_ctl_reg = 0x000000a8,
256 .cfg_bar1_index_reg = 0x00000100,
257 };
258 const struct octpcie_config cn78xx_config = {
259 .cfg_nports = 4,
260 .cfg_bar_ctl_reg = 0x000000a8,
261 .cfg_bar1_index_reg = 0x00000100,
262 .cfg_has_ciu3 = 1,
263 };
264
265 int
octpcie_match(struct device * parent,void * match,void * aux)266 octpcie_match(struct device *parent, void *match, void *aux)
267 {
268 struct iobus_attach_args *aa = aux;
269
270 if (strcmp(aa->aa_name, octpcie_cd.cd_name) != 0)
271 return 0;
272
273 return 1;
274 }
275
276 void
octpcie_attach(struct device * parent,struct device * self,void * aux)277 octpcie_attach(struct device *parent, struct device *self, void *aux)
278 {
279 struct iobus_attach_args *aa = aux;
280 const struct octpcie_config *cfg;
281 struct octpcie_port *port;
282 struct octpcie_softc *sc = (struct octpcie_softc *)self;
283 uint64_t val;
284 uint32_t chipid;
285 int pi;
286
287 sc->sc_iot = aa->aa_bust;
288 sc->sc_dmat = aa->aa_dmat;
289
290 chipid = octeon_get_chipid();
291 switch (octeon_model_family(chipid)) {
292 case OCTEON_MODEL_FAMILY_CN61XX:
293 case OCTEON_MODEL_FAMILY_CN63XX:
294 cfg = &cn61xx_config;
295 break;
296 case OCTEON_MODEL_FAMILY_CN71XX:
297 cfg = &cn71xx_config;
298 break;
299 case OCTEON_MODEL_FAMILY_CN73XX:
300 case OCTEON_MODEL_FAMILY_CN78XX:
301 cfg = &cn78xx_config;
302 break;
303 default:
304 printf(": unhandled chipid 0x%x\n", chipid);
305 return;
306 }
307 sc->sc_cfg = cfg;
308
309 if (bus_space_map(sc->sc_iot, DPI_BASE, DPI_SIZE, 0,
310 &sc->sc_dpi_ioh) != 0) {
311 printf(": can't map DPI registers\n");
312 return;
313 }
314
315 if (bus_space_map(sc->sc_iot, SLI_BASE, SLI_SIZE, 0,
316 &sc->sc_sli_ioh) != 0) {
317 printf(": can't map SLI registers\n");
318 goto error;
319 }
320
321 val = bus_space_read_8(sc->sc_iot, sc->sc_sli_ioh, SLI_MEM_ACCESS_CTL);
322 val &= ~SLI_MEM_ACCESS_CTL_MAXW_M;
323 val &= ~SLI_MEM_ACCESS_CTL_TIMER_M;
324 val |= 127 << SLI_MEM_ACCESS_CTL_TIMER_S;
325 bus_space_write_8(sc->sc_iot, sc->sc_sli_ioh, SLI_MEM_ACCESS_CTL, val);
326
327 printf(": %d ports\n", cfg->cfg_nports);
328
329 sc->sc_ports = mallocarray(cfg->cfg_nports, sizeof(*sc->sc_ports),
330 M_DEVBUF, M_WAITOK | M_ZERO);
331 for (pi = 0; pi < cfg->cfg_nports; pi++) {
332 port = &sc->sc_ports[pi];
333 port->port_sc = sc;
334 port->port_index = pi;
335 port->port_iot = sc->sc_iot;
336 octpcie_port_attach(port);
337 }
338 return;
339
340 error:
341 bus_space_unmap(sc->sc_iot, sc->sc_dpi_ioh, DPI_SIZE);
342 }
343
344 void
octpcie_port_attach(struct octpcie_port * port)345 octpcie_port_attach(struct octpcie_port *port)
346 {
347 struct pcibus_attach_args pba;
348 struct octpcie_softc *sc = port->port_sc;
349 pci_chipset_tag_t pc = &port->port_pc;
350
351 if (bus_space_map(port->port_iot, PEM_BASE(port->port_index),
352 PEM_SIZE, 0, &port->port_pem_ioh) != 0) {
353 printf("%s port %d: can't map PEM registers\n",
354 sc->sc_dev.dv_xname, port->port_index);
355 return;
356 }
357
358 if (bus_space_map(port->port_iot, SLI_PCIECFG_BASE(port->port_index),
359 SLI_PCIECFG_SIZE, 0, &port->port_pciecfg_ioh) != 0) {
360 printf("%s port %d: can't map PCIECFG registers\n",
361 sc->sc_dev.dv_xname, port->port_index);
362 goto error_pem;
363 }
364
365 if (octpcie_port_is_host(port) == 0)
366 goto error_pciecfg;
367
368 if (octpcie_port_reset(port) != 0) {
369 /* Error has been printed already. */
370 goto error_pciecfg;
371 }
372
373 snprintf(port->port_ioex_name, sizeof(port->port_ioex_name),
374 "%s port %d pciio", sc->sc_dev.dv_xname, port->port_index);
375 snprintf(port->port_memex_name, sizeof(port->port_memex_name),
376 "%s port %d pcimem", sc->sc_dev.dv_xname, port->port_index);
377 port->port_ioex = extent_create(port->port_ioex_name, 0, 0xffffffff,
378 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
379 port->port_memex = extent_create(port->port_memex_name, 0, (u_long)-1,
380 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
381
382 extent_free(port->port_ioex, 0, 0xffffffff, EX_WAITOK);
383 extent_free(port->port_memex, PEM_BAR0_SIZE, PEM_BAR2_SIZE - 1,
384 EX_WAITOK);
385
386 port->port_bus_iot = *port->port_iot;
387 port->port_bus_iot.bus_private = port;
388 port->port_bus_iot._space_map = octpcie_io_map;
389
390 port->port_bus_memt = *port->port_iot;
391 port->port_bus_memt.bus_private = port;
392 port->port_bus_memt._space_map = octpcie_mem_map;
393
394 pc->pc_conf_v = port;
395 pc->pc_attach_hook = octpcie_attach_hook;
396 pc->pc_bus_maxdevs = octpcie_bus_maxdevs;
397 pc->pc_make_tag = octpcie_make_tag;
398 pc->pc_decompose_tag = octpcie_decompose_tag;
399 pc->pc_conf_size = octpcie_conf_size;
400 pc->pc_conf_read = octpcie_conf_read;
401 pc->pc_conf_write = octpcie_conf_write;
402
403 pc->pc_intr_v = port;
404 pc->pc_intr_map = octpcie_pci_intr_map;
405 pc->pc_intr_string = octpcie_pci_intr_string;
406 pc->pc_intr_establish = octpcie_pci_intr_establish;
407 pc->pc_intr_disestablish = octpcie_pci_intr_disestablish;
408
409 memset(&pba, 0, sizeof(pba));
410 pba.pba_busname = "pci";
411 pba.pba_iot = &port->port_bus_iot;
412 pba.pba_memt = &port->port_bus_memt;
413 pba.pba_dmat = sc->sc_dmat;
414 pba.pba_pc = pc;
415 pba.pba_domain = pci_ndomains++;
416 pba.pba_bus = 0;
417 pba.pba_ioex = port->port_ioex;
418 pba.pba_memex = port->port_memex;
419 config_found(&sc->sc_dev, &pba, octpcie_print);
420 return;
421
422 error_pciecfg:
423 bus_space_unmap(port->port_iot, port->port_pciecfg_ioh,
424 SLI_PCIECFG_SIZE);
425 error_pem:
426 bus_space_unmap(port->port_iot, port->port_pem_ioh, PEM_SIZE);
427 }
428
429 int
octpcie_port_reset(struct octpcie_port * port)430 octpcie_port_reset(struct octpcie_port *port)
431 {
432 struct octpcie_softc *sc = port->port_sc;
433 const struct octpcie_config *cfg = sc->sc_cfg;
434 paddr_t ctl_reg, rst_reg;
435 uint64_t val;
436 uint32_t chipid, cr;
437 int i, timeout;
438
439 chipid = octeon_get_chipid();
440 switch (octeon_model_family(chipid)) {
441 case OCTEON_MODEL_FAMILY_CN61XX:
442 case OCTEON_MODEL_FAMILY_CN63XX:
443 case OCTEON_MODEL_FAMILY_CN66XX:
444 case OCTEON_MODEL_FAMILY_CN68XX:
445 ctl_reg = MIO_RST_CTL(port->port_index);
446 if (port->port_index == 0)
447 rst_reg = CIU_SOFT_PRST_ADDR;
448 else
449 rst_reg = CIU_SOFT_PRST1_ADDR;
450 break;
451 case OCTEON_MODEL_FAMILY_CN71XX:
452 case OCTEON_MODEL_FAMILY_CN73XX:
453 case OCTEON_MODEL_FAMILY_CN78XX:
454 ctl_reg = RST_CTL(port->port_index);
455 rst_reg = RST_SOFT_PRST_ADDR(port->port_index);
456 break;
457 default:
458 printf("%s port %d: unhandled chipid 0x%x\n",
459 sc->sc_dev.dv_xname, port->port_index, chipid);
460 return -1;
461 }
462
463 /* Put the hardware in reset. */
464 val = octeon_xkphys_read_8(rst_reg);
465 octeon_xkphys_write_8(rst_reg, val);
466 (void)octeon_xkphys_read_8(rst_reg);
467 delay(2000);
468
469 /* Take the hardware out of reset. */
470 val &= ~PRST_SOFT_PRST;
471 octeon_xkphys_write_8(rst_reg, val);
472 (void)octeon_xkphys_read_8(rst_reg);
473 delay(1000);
474
475 /* Wait until the reset has completed. */
476 for (timeout = 100000; timeout > 0; timeout--) {
477 val = octeon_xkphys_read_8(ctl_reg);
478 if (val & RST_CTL_RST_DONE)
479 break;
480 }
481 if (timeout == 0) {
482 printf("%s port %d: reset timeout\n",
483 sc->sc_dev.dv_xname, port->port_index);
484 return -1;
485 }
486
487 /*
488 * Initialize the configuration registers of the root complex.
489 */
490
491 cr = octpcie_cfgreg_read(port, PCIERC_CFG030);
492 cr &= ~PCIERC_CFG030_MPS_M;
493 cr &= ~PCIERC_CFG030_MRRS_M;
494 cr |= 0 << PCIERC_CFG030_MPS_S;
495 cr |= 3 << PCIERC_CFG030_MRRS_S;
496 cr |= PCIERC_CFG030_NS_EN;
497 cr |= PCIERC_CFG030_RO_EN;
498 cr |= PCIERC_CFG030_UR_EN;
499 cr |= PCIERC_CFG030_FE_EN;
500 cr |= PCIERC_CFG030_NFE_EN;
501 cr |= PCIERC_CFG030_CE_EN;
502 octpcie_cfgreg_write(port, PCIERC_CFG030, cr);
503
504 val = bus_space_read_8(sc->sc_iot, sc->sc_dpi_ioh,
505 DPI_SLI_PRT_CFG(port->port_index));
506 val &= ~DPI_SLI_PRT_CFG_MPS_M;
507 val &= ~DPI_SLI_PRT_CFG_MRRS_M;
508 val |= 0 << DPI_SLI_PRT_CFG_MPS_S;
509 val |= 3 << DPI_SLI_PRT_CFG_MRRS_S;
510 val &= ~DPI_SLI_PRT_CFG_MOLR_M;
511 val |= 32 << DPI_SLI_PRT_CFG_MOLR_S;
512 bus_space_write_8(sc->sc_iot, sc->sc_dpi_ioh,
513 DPI_SLI_PRT_CFG(port->port_index), val);
514 (void)bus_space_read_8(sc->sc_iot, sc->sc_dpi_ioh,
515 DPI_SLI_PRT_CFG(port->port_index));
516
517 val = bus_space_read_8(sc->sc_iot, sc->sc_sli_ioh,
518 SLI_S2M_PORT_CTL(port->port_index));
519 val &= ~SLI_S2M_PORT_CTL_MRRS_M;
520 val |= 32 << SLI_S2M_PORT_CTL_MRRS_S;
521 bus_space_write_8(sc->sc_iot, sc->sc_sli_ioh,
522 SLI_S2M_PORT_CTL(port->port_index), val);
523 (void)bus_space_read_8(sc->sc_iot, sc->sc_sli_ioh,
524 SLI_S2M_PORT_CTL(port->port_index));
525
526 cr = octpcie_cfgreg_read(port, PCIERC_CFG070);
527 cr |= PCIERC_CFG070_CE;
528 cr |= PCIERC_CFG070_GE;
529 octpcie_cfgreg_write(port, PCIERC_CFG070, cr);
530
531 cr = octpcie_cfgreg_read(port, PCIERC_CFG001);
532 cr |= PCIERC_CFG001_I_DIS;
533 cr |= PCIERC_CFG001_SEE;
534 cr |= PCIERC_CFG001_ME;
535 cr |= PCIERC_CFG001_MSAE;
536 octpcie_cfgreg_write(port, PCIERC_CFG001, cr);
537
538 octpcie_cfgreg_write(port, PCIERC_CFG066, 0);
539 octpcie_cfgreg_write(port, PCIERC_CFG069, 0);
540
541 cr = octpcie_cfgreg_read(port, PCIERC_CFG032);
542 cr &= ~PCIERC_CFG032_ASLPC_M;
543 octpcie_cfgreg_write(port, PCIERC_CFG032, cr);
544
545 octpcie_cfgreg_write(port, PCIERC_CFG006, 0);
546
547 cr = 0x100 << PCIERC_CFG008_MBADDR_S;
548 cr |= 0 << PCIERC_CFG008_MLADDR_S;
549 octpcie_cfgreg_write(port, PCIERC_CFG008, cr);
550
551 cr = octpcie_cfgreg_read(port, PCIERC_CFG009);
552 cr &= ~PCIERC_CFG009_LMEM_BASE_M;
553 cr |= 0x100 << PCIERC_CFG009_LMEM_BASE_S;
554 cr &= ~PCIERC_CFG009_LMEM_LIMIT_M;
555 octpcie_cfgreg_write(port, PCIERC_CFG009, cr);
556
557 cr = octpcie_cfgreg_read(port, PCIERC_CFG010);
558 cr &= ~PCIERC_CFG010_UMEM_BASE_M;
559 cr |= 0x100 << PCIERC_CFG010_UMEM_BASE_S;
560 octpcie_cfgreg_write(port, PCIERC_CFG010, cr);
561
562 cr = octpcie_cfgreg_read(port, PCIERC_CFG011);
563 cr &= ~PCIERC_CFG011_UMEM_LIMIT_M;
564 octpcie_cfgreg_write(port, PCIERC_CFG011, cr);
565
566 cr = octpcie_cfgreg_read(port, PCIERC_CFG035);
567 cr |= PCIERC_CFG035_SECEE;
568 cr |= PCIERC_CFG035_SEFEE;
569 cr |= PCIERC_CFG035_SENFEE;
570 cr |= PCIERC_CFG035_PMEIE;
571 octpcie_cfgreg_write(port, PCIERC_CFG035, cr);
572
573 cr = octpcie_cfgreg_read(port, PCIERC_CFG075);
574 cr |= PCIERC_CFG075_CERE;
575 cr |= PCIERC_CFG075_NFERE;
576 cr |= PCIERC_CFG075_FERE;
577 octpcie_cfgreg_write(port, PCIERC_CFG075, cr);
578
579 cr = octpcie_cfgreg_read(port, PCIERC_CFG034);
580 cr |= PCIERC_CFG034_DLLS_EN;
581 cr |= PCIERC_CFG034_CCINT_EN;
582 octpcie_cfgreg_write(port, PCIERC_CFG034, cr);
583
584 cr = octpcie_cfgreg_read(port, PCIERC_CFG515);
585 cr |= PCIERC_CFG515_DSC;
586 octpcie_cfgreg_write(port, PCIERC_CFG515, cr);
587
588 /* Enable the link. */
589 val = bus_space_read_8(port->port_iot, port->port_pem_ioh,
590 PEM_CTL_STATUS);
591 val |= PEM_CTL_STATUS_LNK_ENB;
592 bus_space_write_8(port->port_iot, port->port_pem_ioh,
593 PEM_CTL_STATUS, val);
594
595 /*
596 * Wait until link training finishes and
597 * data link layer activity begins.
598 */
599 for (timeout = 1000; timeout > 0; timeout--) {
600 cr = octpcie_cfgreg_read(port, PCIERC_CFG032);
601 if ((cr & PCIERC_CFG032_DLLA) != 0 &&
602 (cr & PCIERC_CFG032_LT) == 0)
603 break;
604 delay(1000);
605 }
606 if (timeout == 0) {
607 printf("%s port %d: link timeout\n",
608 sc->sc_dev.dv_xname, port->port_index);
609 return -1;
610 }
611
612 val = (uint64_t)port->port_index << SLI_MEM_ACCESS_SUBID_PORT_S;
613 val |= 3ULL << SLI_MEM_ACCESS_SUBID_ESR_S;
614 val |= 3ULL << SLI_MEM_ACCESS_SUBID_ESW_S;
615 for (i = 0; i < 4; i++) {
616 bus_space_write_8(sc->sc_iot, sc->sc_sli_ioh,
617 SLI_MEM_ACCESS_SUBID(i + port->port_index * 4), val);
618 val += 1ULL << SLI_MEM_ACCESS_SUBID_BA_S;
619 }
620
621 /* Disable forwarding between ports. */
622 for (i = 0; i < 4; i++) {
623 bus_space_write_8(port->port_iot, port->port_pem_ioh,
624 PEM_P2P_BAR_START(i), ~0ULL);
625 bus_space_write_8(port->port_iot, port->port_pem_ioh,
626 PEM_P2P_BAR_END(i), ~0ULL);
627 }
628
629 /*
630 * Set up forwarding of requests from PCI memory space.
631 *
632 * BAR0 (size 2^14) forwards to internal CSRs.
633 * BAR1 (size configurable) and BAR2 (size 2^41) forward to DRAM.
634 *
635 * This code relies on BAR2 to forward DRAM requests.
636 * Forwarding through BAR1 is disabled.
637 */
638
639 bus_space_write_8(port->port_iot, port->port_pem_ioh,
640 PEM_P2N_BAR_START(0), 0);
641 bus_space_write_8(port->port_iot, port->port_pem_ioh,
642 PEM_P2N_BAR_START(1), PEM_BAR2_SIZE);
643 bus_space_write_8(port->port_iot, port->port_pem_ioh,
644 PEM_P2N_BAR_START(2), 0);
645
646 /* Set BAR1 size to 256 MiB, enable BAR2. */
647 val = bus_space_read_8(port->port_iot, port->port_pem_ioh,
648 PEM_BAR_CTL(cfg));
649 val &= ~PEM_BAR_CTL_BAR1_SIZ_M;
650 val |= PEM_BAR_CTL_BAR1_SIZ_256M;
651 val |= PEM_BAR_CTL_BAR2_ENB;
652 val &= ~PEM_BAR_CTL_BAR2_ESX_M;
653 val |= 1UL << PEM_BAR_CTL_BAR2_ESX_S;
654 val |= PEM_BAR_CTL_BAR2_CAX;
655 bus_space_write_8(port->port_iot, port->port_pem_ioh,
656 PEM_BAR_CTL(cfg), val);
657
658 /* Disable BAR1 mappings. */
659 for (i = 0; i < 16; i++) {
660 bus_space_write_8(port->port_iot, port->port_pem_ioh,
661 PEM_BAR1_INDEX(cfg, i), 0);
662 }
663
664 return 0;
665 }
666
667 int
octpcie_port_is_host(struct octpcie_port * port)668 octpcie_port_is_host(struct octpcie_port *port)
669 {
670 uint32_t chipid;
671 int host = 0;
672
673 chipid = octeon_get_chipid();
674 switch (octeon_model_family(chipid)) {
675 case OCTEON_MODEL_FAMILY_CN61XX:
676 case OCTEON_MODEL_FAMILY_CN63XX:
677 case OCTEON_MODEL_FAMILY_CN66XX:
678 case OCTEON_MODEL_FAMILY_CN68XX:
679 if ((octeon_xkphys_read_8(MIO_RST_CTL(port->port_index)) &
680 MIO_RST_CTL_PRTMODE) != 0)
681 host = 1;
682 break;
683 case OCTEON_MODEL_FAMILY_CN71XX:
684 if ((octeon_xkphys_read_8(RST_CTL(port->port_index)) &
685 RST_CTL_HOST_MODE) != 0)
686 host = 1;
687 break;
688 case OCTEON_MODEL_FAMILY_CN73XX:
689 case OCTEON_MODEL_FAMILY_CN78XX:
690 if ((bus_space_read_8(port->port_iot, port->port_pem_ioh,
691 PEM_STRAP) & PEM_STRAP_PIMODE_M) == PEM_STRAP_PIMODE_RC)
692 host = 1;
693 default:
694 break;
695 }
696 return host;
697 }
698
699 int
octpcie_print(void * aux,const char * pnp)700 octpcie_print(void *aux, const char *pnp)
701 {
702 struct pcibus_attach_args *pba = aux;
703
704 if (pnp)
705 printf("%s at %s", pba->pba_busname, pnp);
706 printf(" bus %d", pba->pba_bus);
707
708 return UNCONF;
709 }
710
711 void
octpcie_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)712 octpcie_attach_hook(struct device *parent, struct device *self,
713 struct pcibus_attach_args *pba)
714 {
715 }
716
717 int
octpcie_bus_maxdevs(void * v,int busno)718 octpcie_bus_maxdevs(void *v, int busno)
719 {
720 return 1;
721 }
722
723 pcitag_t
octpcie_make_tag(void * unused,int b,int d,int f)724 octpcie_make_tag(void *unused, int b, int d, int f)
725 {
726 return (b << 16) | (d << 11) | (f << 8);
727 }
728
729 void
octpcie_decompose_tag(void * unused,pcitag_t tag,int * bp,int * dp,int * fp)730 octpcie_decompose_tag(void *unused, pcitag_t tag, int *bp, int *dp, int *fp)
731 {
732 if (bp != NULL)
733 *bp = (tag >> 16) & 0xff;
734 if (dp != NULL)
735 *dp = (tag >> 11) & 0x1f;
736 if (fp != NULL)
737 *fp = (tag >> 8) & 0x7;
738 }
739
740 int
octpcie_conf_size(void * v,pcitag_t tag)741 octpcie_conf_size(void *v, pcitag_t tag)
742 {
743 return PCIE_CONFIG_SPACE_SIZE;
744 }
745
746 pcireg_t
octpcie_conf_read(void * v,pcitag_t tag,int offset)747 octpcie_conf_read(void *v, pcitag_t tag, int offset)
748 {
749 struct octpcie_port * port = v;
750 int bus;
751
752 octpcie_decompose_tag(NULL, tag, &bus, NULL, NULL);
753 if (bus == 0) {
754 return bus_space_read_4(port->port_iot, port->port_pciecfg_ioh,
755 tag | (offset & 0xfffc));
756 }
757 return 0xffffffff;
758 }
759
760 void
octpcie_conf_write(void * v,pcitag_t tag,int offset,pcireg_t data)761 octpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
762 {
763 struct octpcie_port * port = v;
764 int bus;
765
766 octpcie_decompose_tag(NULL, tag, &bus, NULL, NULL);
767 if (bus == 0) {
768 bus_space_write_4(port->port_iot, port->port_pciecfg_ioh,
769 tag | (offset & 0xfffc), data);
770 }
771 }
772
773 int
octpcie_pci_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)774 octpcie_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
775 {
776 struct octpcie_port *port = pa->pa_pc->pc_conf_v;
777 struct octpcie_softc *sc = port->port_sc;
778 int dev, pin;
779
780 if (pa->pa_intrpin == 0 || pa->pa_intrpin > PCI_INTERRUPT_PIN_MAX)
781 return -1;
782
783 if (pa->pa_bridgetag != NULL) {
784 pci_decompose_tag(pa->pa_pc, pa->pa_tag, NULL, &dev, NULL);
785 pin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, dev);
786 if (pa->pa_bridgeih[pin - 1] == (pci_intr_handle_t)-1)
787 return -1;
788 *ihp = pa->pa_bridgeih[pin - 1];
789 return 0;
790 }
791
792 if (sc->sc_cfg->cfg_has_ciu3)
793 *ihp = pa->pa_intrpin - 1 +
794 CIU3_PEM_INTSN_INTA(port->port_index);
795 else
796 *ihp = pa->pa_intrpin - 1 + CIU_INT_PCI_INTA;
797 return 0;
798 }
799
800 const char *
octpcie_pci_intr_string(void * cookie,pci_intr_handle_t ih)801 octpcie_pci_intr_string(void *cookie, pci_intr_handle_t ih)
802 {
803 static char irqstr[16];
804
805 snprintf(irqstr, sizeof(irqstr), "irq %lu", ih);
806 return irqstr;
807 }
808
809 void *
octpcie_pci_intr_establish(void * cookie,pci_intr_handle_t ih,int level,int (* cb)(void *),void * cbarg,char * name)810 octpcie_pci_intr_establish(void *cookie, pci_intr_handle_t ih, int level,
811 int (*cb)(void *), void *cbarg, char *name)
812 {
813 return octeon_intr_establish(ih, level, cb, cbarg, name);
814 }
815
816 void
octpcie_pci_intr_disestablish(void * cookie,void * ihp)817 octpcie_pci_intr_disestablish(void *cookie, void *ihp)
818 {
819 octeon_intr_disestablish(ihp);
820 }
821
822 int
octpcie_io_map(bus_space_tag_t t,bus_addr_t offs,bus_size_t size,int flags,bus_space_handle_t * bshp)823 octpcie_io_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags,
824 bus_space_handle_t *bshp)
825 {
826 struct octpcie_port *port = t->bus_private;
827
828 if (offs + size > SLI_PCIEIO_SIZE)
829 return EINVAL;
830
831 return bus_space_map(port->port_iot,
832 SLI_PCIEIO_BASE(port->port_index) + offs, size, flags, bshp);
833 }
834
835 int
octpcie_mem_map(bus_space_tag_t t,bus_addr_t offs,bus_size_t size,int flags,bus_space_handle_t * bshp)836 octpcie_mem_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags,
837 bus_space_handle_t *bshp)
838 {
839 struct octpcie_port *port = t->bus_private;
840
841 if (offs + size > SLI_PCIEMEM_SIZE)
842 return EINVAL;
843
844 return bus_space_map(port->port_iot,
845 SLI_PCIEMEM_BASE(port->port_index) + offs, size, flags, bshp);
846 }
847
848 uint32_t
octpcie_cfgreg_read(struct octpcie_port * port,uint32_t off)849 octpcie_cfgreg_read(struct octpcie_port *port, uint32_t off)
850 {
851 uint64_t val;
852
853 bus_space_write_8(port->port_iot, port->port_pem_ioh, PEM_CFG_RD, off);
854 val = bus_space_read_8(port->port_iot, port->port_pem_ioh, PEM_CFG_RD);
855
856 return (uint32_t)(val >> 32);
857 }
858
859 void
octpcie_cfgreg_write(struct octpcie_port * port,uint32_t off,uint32_t val)860 octpcie_cfgreg_write(struct octpcie_port *port, uint32_t off, uint32_t val)
861 {
862 bus_space_write_4(port->port_iot, port->port_pem_ioh, PEM_CFG_WR,
863 ((uint64_t)val << 32) | off);
864 (void)bus_space_read_4(port->port_iot, port->port_pem_ioh, PEM_CFG_WR);
865 }
866