1 /* Copyright 2013-2014 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __P7IOC_REGS_H 18 #define __P7IOC_REGS_H 19 20 /* 21 * Register definitions 22 * 23 * We only define some registers here. Ideally we should auto-generate 24 * the full list from the spec. For now I add them as I need them 25 */ 26 27 /* RGC GEM registers */ 28 #define P7IOC_GEM_XFIR 0x3E0008 29 #define P7IOC_GEM_RFIR 0x3E0010 30 #define P7IOC_GEM_RIRQFIR 0x3E0018 31 #define P7IOC_GEM_MASK 0x3E0020 32 #define P7IOC_GEM_RWOF 0x3E0028 33 34 /* LEM register base */ 35 #define P7IOC_RGC_LEM_BASE 0x3E1E00 36 #define P7IOC_BI_UP_LEM_BASE 0x3C0000 37 #define P7IOC_BI_DOWN_LEM_BASE 0x3C0050 38 #define P7IOC_CI_PORTn_LEM_BASE(n) (0x3d0200 | ((n) * 0x1000)) 39 #define P7IOC_PHBn_LEM_BASE(n) (0x000C00 | ((n) * 0x10000)) 40 #define P7IOC_MISC_LEM_BASE 0x3EA000 41 #define P7IOC_I2C_LEM_BASE 0x3EB000 42 43 /* LEM register offset */ 44 #define P7IOC_LEM_FIR_OFFSET 0x00 45 #define P7IOC_LEM_FIR_AND_OFFSET 0x08 46 #define P7IOC_LEM_FIR_OR_OFFSET 0x10 47 #define P7IOC_LEM_ERR_MASK_OFFSET 0x18 48 #define P7IOC_LEM_ERR_MASK_AND_OFFSET 0x20 49 #define P7IOC_LEM_ERR_MASK_OR_OFFSET 0x28 50 #define P7IOC_LEM_ACTION_0_OFFSET 0x30 51 #define P7IOC_LEM_ACTION_1_OFFSET 0x38 52 #define P7IOC_LEM_WOF_OFFSET 0x40 53 54 /* HSS registers */ 55 #define P7IOC_HSS_BASE 0x3E8000 56 #define P7IOC_HSS_STRIDE 0x200 57 #define P7IOC_HSSn_CTL2_OFFSET 0x10 58 #define P7IOC_HSSn_CTL3_OFFSET 0x18 59 #define P7IOC_HSSn_CTL8_OFFSET 0x40 60 #define P7IOC_HSSn_CTL9_OFFSET 0x48 61 #define P7IOC_HSSn_CTL10_OFFSET 0x50 62 #define P7IOC_HSSn_CTL11_OFFSET 0x58 63 #define P7IOC_HSSn_CTL12_OFFSET 0x60 64 #define P7IOC_HSSn_CTL13_OFFSET 0x68 65 #define P7IOC_HSSn_CTL14_OFFSET 0x70 66 #define P7IOC_HSSn_CTL15_OFFSET 0x78 67 #define P7IOC_HSSn_CTL16_OFFSET 0x80 68 #define P7IOC_HSSn_CTL17_OFFSET 0x88 69 #define P7IOC_HSSn_CTL18_OFFSET 0x90 70 #define P7IOC_HSSn_CTL19_OFFSET 0x98 71 #define P7IOC_HSSn_CTL20_OFFSET 0xa0 72 #define P7IOC_HSSn_CTL21_OFFSET 0xa8 73 #define P7IOC_HSSn_CTL22_OFFSET 0xb0 74 #define P7IOC_HSSn_CTL23_OFFSET 0xb8 75 76 /* CI Routing registers & helper macros */ 77 #define P7IOC_CI_RMATC_REG(i) (0x3D0400ul + ((i) << 4)) 78 #define P7IOC_CI_RMASK_REG(i) (0x3D0408ul + ((i) << 4)) 79 80 #define P7IOC_CI_RMATC_PORT(n) PPC_BIT(n) 81 #define P7IOC_CI_RMATC_ADDR_VALID PPC_BIT(16) 82 #define P7IOC_CI_RMATC_BUID_VALID PPC_BIT(17) 83 #define P7IOC_CI_RMATC_TYPE_VALID PPC_BIT(18) 84 85 /* AIB Addresses are 48-bit, the top 32 are used in 86 * the routing tables, we thus shift by 16 87 */ 88 #define P7IOC_CI_RMATC_ENCODE_ADDR(addr) ((uint32_t)((addr) >> 16)) 89 #define P7IOC_CI_RMATC_ENCODE_BUID(buid) ((uint32_t)((buid) << 20)) 90 #define P7IOC_CI_RMATC_ENCODE_TYPE(type) ((uint32_t)(type)) 91 92 /* CI port numbers */ 93 #define P7IOC_CI_PHB_PORT(pnum) ((pnum) + 2) 94 #define P7IOC_CI_UPSTREAM_PORT 0 95 #define P7IOC_CI_RGC_PORT 1 96 97 /* Other random chip registers */ 98 #define P7IOC_CHIP_FENCE_SHADOW 0x3ec010 99 #define P7IOC_CHIP_FENCE_WOF 0x3ec018 100 #define P7IOC_CCRR 0x3e1c00 101 102 /* CI registers */ 103 #define P7IOC_CIn_BASE(n) (0x3d0000 | ((n) * 0x1000)) 104 #define P7IOC_CIn_LEM_FIR(n) (P7IOC_CIn_BASE(n) + 0x200) 105 #define P7IOC_CIn_LEM_FIR_AND(n) (P7IOC_CIn_BASE(n) + 0x208) 106 #define P7IOC_CIn_LEM_FIR_OR(n) (P7IOC_CIn_BASE(n) + 0x210) 107 #define P7IOC_CIn_LEM_ERR_MASK(n) (P7IOC_CIn_BASE(n) + 0x218) 108 #define P7IOC_CIn_LEM_ERR_MASK_AND(n) (P7IOC_CIn_BASE(n) + 0x220) 109 #define P7IOC_CIn_LEM_ERR_MASK_OR(n) (P7IOC_CIn_BASE(n) + 0x228) 110 111 /* 112 * PHB registers 113 */ 114 115 /* PHB Fundamental register set A */ 116 #define PHB_BUID 0x100 117 #define PHB_BUID_LSI PPC_BITMASK(7,15) 118 #define PHB_BUID_MSI PPC_BITMASK(23,31) 119 #define PHB_DMA_CHAN_STATUS 0x110 120 #define PHB_CPU_LOADSTORE_STATUS 0x120 121 #define PHB_CONFIG_DATA 0x130 122 #define PHB_LOCK0 0x138 123 #define PHB_CONFIG_ADDRESS 0x140 124 #define PHB_CA_ENABLE PPC_BIT(0) 125 #define PHB_CA_BUS PPC_BITMASK(4,11) 126 #define PHB_CA_DEV PPC_BITMASK(12,16) 127 #define PHB_CA_FUNC PPC_BITMASK(17,19) 128 #define PHB_CA_BDFN PPC_BITMASK(4,19) /* bus,dev,func */ 129 #define PHB_CA_REG PPC_BITMASK(20,31) 130 #define PHB_LOCK1 0x148 131 #define PHB_PHB2_CONFIG 0x160 132 #define PHB_PHB2C_64B_TCE_EN PPC_BIT(2) 133 #define PHB_PHB2C_32BIT_MSI_EN PPC_BIT(8) 134 #define PHB_PHB2C_IO_EN PPC_BIT(12) 135 #define PHB_PHB2C_64BIT_MSI_EN PPC_BIT(14) 136 #define PHB_PHB2C_M32_EN PPC_BIT(16) 137 #define PHB_IO_BASE_ADDR 0x170 138 #define PHB_IO_BASE_MASK 0x178 139 #define PHB_IO_START_ADDR 0x180 140 #define PHB_M32_BASE_ADDR 0x190 141 #define PHB_M32_BASE_MASK 0x198 142 #define PHB_M32_START_ADDR 0x1a0 143 #define PHB_M64_UPPER_BITS 0x1f0 144 #define PHB_TCE_KILL 0x210 145 #define PHB_TCEKILL_PAIR PPC_BIT(0) 146 #define PHB_TCEKILL_ADDR PPC_BITMASK(16,59) 147 #define PHB_TCE_PREFETCH 0x218 148 #define PHB_IODA_ADDR 0x220 149 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 150 #define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) 151 #define PHB_IODA_AD_TADR PPC_BITMASK(48,63) 152 #define PHB_IODA_DATA0 0x228 153 #define PHB_IODA_DATA1 0x230 154 #define PHB_LOCK2 0x240 155 #define PHB_XIVE_UPDATE 0x248 156 #define PHB_PHB2_GEN_CAP 0x250 157 #define PHB_PHB2_TCE_CAP 0x258 158 #define PHB_PHB2_IRQ_CAP 0x260 159 #define PHB_PHB2_EEH_CAP 0x268 160 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 161 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 162 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 163 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 164 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 165 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 166 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 167 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 168 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 169 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 170 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) 171 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,39) /* 16M aligned */ 172 #define PHB_PAPR_ERR_INJ_MASK_IO PPC_BITMASK(16,47) /* 64K aligned */ 173 #define PHB_PAPR_ERR_INJ_MASK_DMA PPC_BITMASK(60,63) /* 16 window */ 174 #define PHB_ETU_ERR_SUMMARY 0x2c8 175 176 /* UTL registers */ 177 #define UTL_SYS_BUS_CONTROL 0x400 178 #define UTL_STATUS 0x408 179 #define UTL_SYS_BUS_AGENT_STATUS 0x410 180 #define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418 181 #define UTL_SYS_BUS_AGENT_IRQ_EN 0x420 182 #define UTL_SYS_BUS_BURST_SZ_CONF 0x440 183 #define UTL_REVISION_ID 0x448 184 #define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0 185 #define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0 186 #define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0 187 #define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0 188 #define UTL_OUT_NP_BUF_ALLOC 0x500 189 #define UTL_IN_NP_BUF_ALLOC 0x510 190 #define UTL_PCIE_TAGS_ALLOC 0x520 191 #define UTL_GBIF_READ_TAGS_ALLOC 0x530 192 #define UTL_PCIE_PORT_CONTROL 0x540 193 #define UTL_PCIE_PORT_STATUS 0x548 194 #define UTL_PCIE_PORT_ERROR_SEV 0x550 195 #define UTL_PCIE_PORT_IRQ_EN 0x558 196 #define UTL_RC_STATUS 0x560 197 #define UTL_RC_ERR_SEVERITY 0x568 198 #define UTL_RC_IRQ_EN 0x570 199 #define UTL_EP_STATUS 0x578 200 #define UTL_EP_ERR_SEVERITY 0x580 201 #define UTL_EP_ERR_IRQ_EN 0x588 202 #define UTL_PCI_PM_CTRL1 0x590 203 #define UTL_PCI_PM_CTRL2 0x598 204 #define UTL_GP_CTL1 0x5a0 205 #define UTL_GP_CTL2 0x5a8 206 207 /* PCI-E Stack registers */ 208 #define PHB_PCIE_SYSTEM_CONFIG 0x600 209 #define PHB_PCIE_BUS_NUMBER 0x608 210 #define PHB_PCIE_SYSTEM_TEST 0x618 211 #define PHB_PCIE_LINK_MANAGEMENT 0x630 212 #define PHB_PCIE_DLP_TRAIN_CTL 0x640 213 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1) 214 #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16) 215 #define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21) 216 #define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22) 217 #define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23) 218 #define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648 219 #define PHB_PCIE_AER_CONTROL 0x650 220 #define PHB_PCIE_AUX_POWER_CONTROL 0x658 221 #define PHB_PCIE_SLOTCTL1 0x660 222 #define PHB_PCIE_SLOTCTL2 0x668 223 #define PHB_PCIE_SLOTCTL2_SLOTWAKE PPC_BIT(16) 224 #define PHB_PCIE_SLOTCTL2_PWR_EN_STAT PPC_BIT(17) 225 #define PHB_PCIE_SLOTCTL2_RCK_EN_STAT PPC_BIT(18) 226 #define PHB_PCIE_SLOTCTL2_PERST_STAT PPC_BIT(19) 227 #define PHB_PCIE_SLOTCTL2_PLED_S PPC_BITMASK(20,21) /* use PCIE_INDIC_* */ 228 #define PHB_PCIE_SLOTCTL2_ALED_S PPC_BITMASK(22,23) 229 #define PHB_PCIE_SLOTCTL2_PRSTN_STAT PPC_BIT(24) 230 #define PHB_PCIE_SLOTCTL2_PWRFLT_STAT PPC_BIT(25) 231 #define PHB_PCIE_UTL_CONFIG 0x670 232 #define PHB_PCIE_DLP_CONTROL 0x678 233 #define PHB_PCIE_UTL_ERRLOG1 0x680 234 #define PHB_PCIE_UTL_ERRLOG2 0x688 235 #define PHB_PCIE_UTL_ERRLOG3 0x690 236 #define PHB_PCIE_UTL_ERRLOG4 0x698 237 #define PHB_PCIE_DLP_ERRLOG1 0x6a0 238 #define PHB_PCIE_DLP_ERRLOG2 0x6a8 239 #define PHB_PCIE_UTL_ERR_INJECT 0x6c0 240 #define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8 241 #define PHB_PCIE_STRAPPING 0x700 242 243 /* Fundamental register set B */ 244 #define PHB_VERSION 0x800 245 #define PHB_RESET 0x808 246 #define PHB_CONTROL 0x810 247 #define PHB_AIB_RX_CRED_INIT_TIMER 0x818 248 #define PHB_AIB_RX_CMD_CRED 0x820 249 #define PHB_AIB_RX_DATA_CRED 0x828 250 #define PHB_AIB_TX_CMD_CRED 0x830 251 #define PHB_AIB_TX_DATA_CRED 0x838 252 #define PHB_AIB_TX_CHAN_MAPPING 0x840 253 #define PHB_AIB_TX_CRED_SYNC_CTRL 0x848 254 #define PHB_LEGACY_CTRL 0x850 255 #define PHB_AIB_TAG_ENABLE 0x858 256 #define PHB_AIB_FENCE_CTRL 0x860 257 #define PHB_TCE_TAG_ENABLE 0x868 258 #define PHB_TCE_WATERMARK 0x870 259 #define PHB_TIMEOUT_CTRL1 0x878 260 #define PHB_TIMEOUT_CTRL2 0x880 261 #define PHB_QUIESCE_DMA_G 0x888 262 #define PHB_AIB_TAG_STATUS 0x900 263 #define PHB_TCE_TAG_STATUS 0x908 264 265 /* FIR & Error registers */ 266 #define PHB_LEM_FIR_ACCUM 0xc00 267 #define PHB_LEM_FIR_AND_MASK 0xc08 268 #define PHB_LEM_FIR_OR_MASK 0xc10 269 #define PHB_LEM_ERROR_MASK 0xc18 270 #define PHB_LEM_ERROR_AND_MASK 0xc20 271 #define PHB_LEM_ERROR_OR_MASK 0xc28 272 #define PHB_LEM_ACTION0 0xc30 273 #define PHB_LEM_ACTION1 0xc38 274 #define PHB_LEM_WOF 0xc40 275 #define PHB_ERR_STATUS 0xc80 276 #define PHB_ERR1_STATUS 0xc88 277 #define PHB_ERR_INJECT 0xc90 278 #define PHB_ERR_LEM_ENABLE 0xc98 279 #define PHB_ERR_IRQ_ENABLE 0xca0 280 #define PHB_ERR_FREEZE_ENABLE 0xca8 281 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 282 #define PHB_ERR_LOG_0 0xcc0 283 #define PHB_ERR_LOG_1 0xcc8 284 #define PHB_ERR_STATUS_MASK 0xcd0 285 #define PHB_ERR1_STATUS_MASK 0xcd8 286 287 #define PHB_OUT_ERR_STATUS 0xd00 288 #define PHB_OUT_ERR1_STATUS 0xd08 289 #define PHB_OUT_ERR_INJECT 0xd10 290 #define PHB_OUT_ERR_LEM_ENABLE 0xd18 291 #define PHB_OUT_ERR_IRQ_ENABLE 0xd20 292 #define PHB_OUT_ERR_FREEZE_ENABLE 0xd28 293 #define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30 294 #define PHB_OUT_ERR_LOG_0 0xd40 295 #define PHB_OUT_ERR_LOG_1 0xd48 296 #define PHB_OUT_ERR_STATUS_MASK 0xd50 297 #define PHB_OUT_ERR1_STATUS_MASK 0xd58 298 299 #define PHB_INA_ERR_STATUS 0xd80 300 #define PHB_INA_ERR1_STATUS 0xd88 301 #define PHB_INA_ERR_INJECT 0xd90 302 #define PHB_INA_ERR_LEM_ENABLE 0xd98 303 #define PHB_INA_ERR_IRQ_ENABLE 0xda0 304 #define PHB_INA_ERR_FREEZE_ENABLE 0xda8 305 #define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0 306 #define PHB_INA_ERR_LOG_0 0xdc0 307 #define PHB_INA_ERR_LOG_1 0xdc8 308 #define PHB_INA_ERR_STATUS_MASK 0xdd0 309 #define PHB_INA_ERR1_STATUS_MASK 0xdd8 310 311 #define PHB_INB_ERR_STATUS 0xe00 312 #define PHB_INB_ERR1_STATUS 0xe08 313 #define PHB_INB_ERR_INJECT 0xe10 314 #define PHB_INB_ERR_LEM_ENABLE 0xe18 315 #define PHB_INB_ERR_IRQ_ENABLE 0xe20 316 #define PHB_INB_ERR_FREEZE_ENABLE 0xe28 317 #define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30 318 #define PHB_INB_ERR_LOG_0 0xe40 319 #define PHB_INB_ERR_LOG_1 0xe48 320 #define PHB_INB_ERR_STATUS_MASK 0xe50 321 #define PHB_INB_ERR1_STATUS_MASK 0xe58 322 323 /* Performance monitor & Debug registers */ 324 #define PHB_TRACE_CONTROL 0xf80 325 #define PHB_PERFMON_CONFIG 0xf88 326 #define PHB_PERFMON_CTR0 0xf90 327 #define PHB_PERFMON_CTR1 0xf98 328 #define PHB_PERFMON_CTR2 0xfa0 329 #define PHB_PERFMON_CTR3 0xfa8 330 #define PHB_HOTPLUG_OVERRIDE 0xfb0 331 332 /* 333 * IODA tables 334 */ 335 336 #define IODA_TBL_HRT 0 337 #define IODA_TBL_LIST 1 338 #define IODA_TBL_LXIVT 2 339 #define IODA_TBL_MIST 3 340 #define IODA_TBL_MXIVT 4 341 #define IODA_TBL_MVT 5 342 #define IODA_TBL_PELTM 6 343 #define IODA_TBL_PESTA 7 344 #define IODA_TBL_PESTB 8 345 #define IODA_TBL_TVT 9 346 #define IODA_TBL_TCAM 10 347 #define IODA_TBL_TDR 11 348 #define IODA_TBL_PELTV 12 349 #define IODA_TBL_M64BT 16 350 #define IODA_TBL_IODT 17 351 #define IODA_TBL_M32DT 18 352 #define IODA_TBL_M64DT 19 353 #define IODA_TBL_PEEV 20 354 355 /* L/M XIVT */ 356 #define IODA_XIVT_SERVER PPC_BITMASK(8,23) 357 #define IODA_XIVT_PRIORITY PPC_BITMASK(24,31) 358 #define IODA_XIVT_PENUM PPC_BITMASK(41,47) 359 #define IODA_XIVT_HUBNUM PPC_BITMASK(58,59) 360 361 /* M64BT */ 362 #define IODA_M64BT_ENABLE PPC_BIT(0) 363 #define IODA_M64BT_BASE PPC_BITMASK(8,31) 364 #define IODA_M64BT_MASK PPC_BITMASK(40,63) 365 366 /* IODT/M32DT/M64DX */ 367 #define IODA_XXDT_PE PPC_BITMASK(0,6) 368 369 /* PELTM */ 370 #define IODA_PELTM_BUS PPC_BITMASK(0,7) 371 #define IODA_PELTM_DEV PPC_BITMASK(8,12) 372 #define IODA_PELTM_FUNC PPC_BITMASK(13,15) 373 #define IODA_PELTM_BUS_VALID PPC_BITMASK(16,18) 374 #define IODA_BUS_VALID_ANY 0 375 #define IODA_BUS_VALID_3_BITS 2 376 #define IODA_BUS_VALID_4_BITS 3 377 #define IODA_BUS_VALID_5_BITS 4 378 #define IODA_BUS_VALID_6_BITS 5 379 #define IODA_BUS_VALID_7_BITS 6 380 #define IODA_BUS_VALID_ALL 7 381 #define IODA_PELTM_DEV_VALID PPC_BIT(19) 382 #define IODA_PELTM_FUNC_VALID PPC_BIT(20) 383 384 /* TVT */ 385 #define IODA_TVT0_TABLE_ADDR PPC_BITMASK(0,47) 386 #define IODA_TVT0_BUS_VALID PPC_BITMASK(48,50) 387 #define IODA_TVT0_TCE_TABLE_SIZE PPC_BITMASK(51,55) 388 #define IODA_TVT0_BUS_NUM PPC_BITMASK(56,63) 389 #define IODA_TVT1_DEV_VALID PPC_BIT(2) 390 #define IODA_TVT1_DEV_NUM PPC_BITMASK(3,7) 391 #define IODA_TVT1_HUB_NUM PPC_BITMASK(10,11) 392 #define IODA_TVT1_FUNC_VALID PPC_BIT(12) 393 #define IODA_TVT1_FUNC_NUM PPC_BITMASK(13,15) 394 #define IODA_TVT1_IO_PSIZE PPC_BITMASK(19,23) 395 #define IODA_TVT1_PE_NUM PPC_BITMASK(57,63) 396 397 /* MVT */ 398 #define IODA_MVT_VALID PPC_BIT(0) 399 #define IODA_MVT_BUS_VALID PPC_BITMASK(21,23) 400 #define IODA_MVT_BUS_NUM PPC_BITMASK(24,31) 401 #define IODA_MVT_PE_NUM PPC_BITMASK(41,47) 402 #define IODA_MVT_DEV_VALID PPC_BIT(50) 403 #define IODA_MVT_DEV_NUM PPC_BITMASK(51,55) 404 #define IODA_MVT_FUNC_VALID PPC_BIT(60) 405 #define IODA_MVT_FUNC_NUM PPC_BITMASK(61,63) 406 407 /* PESTA */ 408 #define IODA_PESTA_MMIO_FROZEN PPC_BIT(0) 409 #define IODA_PESTA_MMIO_CAUSE PPC_BIT(2) 410 #define IODA_PESTA_CFG_READ PPC_BIT(3) 411 #define IODA_PESTA_CFG_WRITE PPC_BIT(4) 412 #define IODA_PESTA_TTYPE PPC_BITMASK(5,7) 413 #define PESTA_TTYPE_DMA_WRITE 0 414 #define PESTA_TTYPE_MSI 1 415 #define PESTA_TTYPE_DMA_READ 2 416 #define PESTA_TTYPE_DMA_READ_RESP 3 417 #define PESTA_TTYPE_MMIO_LOAD 4 418 #define PESTA_TTYPE_MMIO_STORE 5 419 #define PESTA_TTYPE_OTHER 7 420 #define IODA_PESTA_CA_RETURN PPC_BIT(8) 421 #define IODA_PESTA_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */ 422 #define IODA_PESTA_UR_RETURN PPC_BIT(9) 423 #define IODA_PESTA_UTL_NONFATAL PPC_BIT(10) 424 #define IODA_PESTA_UTL_FATAL PPC_BIT(11) 425 #define IODA_PESTA_TAG_REUSE_ERROR PPC_BIT(12) 426 #define IODA_PESTA_PARITY_UE PPC_BIT(13) 427 #define IODA_PESTA_UTL_CORRECTABLE PPC_BIT(14) 428 #define IODA_PESTA_UTL_INTERRUPT PPC_BIT(15) 429 #define IODA_PESTA_MMIO_XLATE PPC_BIT(16) 430 #define IODA_PESTA_IODA_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 431 #define IODA_PESTA_TVT_EXT_ERROR PPC_BIT(17) 432 #define IODA_PESTA_TCE_PAGE_FAULT PPC_BIT(18) 433 #define IODA_PESTA_TCE_ACCESS_FAULT PPC_BIT(19) 434 #define IODA_PESTA_DMA_RESP_TIMEOUT PPC_BIT(20) 435 #define IODA_PESTA_AIB_SIZE_INVALID PPC_BIT(21) 436 #define IODA_PESTA_LEM_BIT PPC_BITMASK(26,31) 437 #define IODA_PESTA_RID PPC_BITMASK(32,47) 438 #define IODA_PESTA_MSI_DATA PPC_BITMASK(48,63) 439 440 /* PESTB */ 441 #define IODA_PESTB_DMA_STOPPED PPC_BIT(0) 442 #define IODA_PESTB_FAIL_ADDR PPC_BITMASK(3,63) 443 444 #endif /* __P7IOC_REGS_H */ 445