1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
25
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/perf/u_trace.h"
29 #include "util/set.h"
30 #include "util/slab.h"
31 #include "util/u_debug.h"
32 #include "util/u_threaded_context.h"
33 #include "intel/blorp/blorp.h"
34 #include "intel/dev/intel_debug.h"
35 #include "intel/common/intel_l3_config.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "intel/ds/intel_driver_ds.h"
38 #include "iris_batch.h"
39 #include "iris_binder.h"
40 #include "iris_fence.h"
41 #include "iris_resource.h"
42 #include "iris_screen.h"
43
44 struct iris_bo;
45 struct iris_context;
46 struct blorp_batch;
47 struct blorp_params;
48
49 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
50 #define IRIS_MAX_TEXTURE_SAMPLERS 32
51 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
52 #define IRIS_MAX_ABOS 16
53 #define IRIS_MAX_SSBOS 16
54 #define IRIS_MAX_VIEWPORTS 16
55 #define IRIS_MAX_CLIP_PLANES 8
56 #define IRIS_MAX_GLOBAL_BINDINGS 32
57
58 enum iris_param_domain {
59 BRW_PARAM_DOMAIN_BUILTIN = 0,
60 BRW_PARAM_DOMAIN_IMAGE,
61 };
62
63 enum {
64 DRI_CONF_BO_REUSE_DISABLED,
65 DRI_CONF_BO_REUSE_ALL
66 };
67
68 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
69 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
70 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
71 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
72 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
73 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
74
75 /**
76 * Dirty flags. When state changes, we flag some combination of these
77 * to indicate that particular GPU commands need to be re-emitted.
78 *
79 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
80 * in rare cases they map to a group of related packets that need to be
81 * emitted together.
82 *
83 * See iris_upload_render_state().
84 */
85 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
86 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
87 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
88 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
89 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
90 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
91 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
92 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
93 #define IRIS_DIRTY_RASTER (1ull << 8)
94 #define IRIS_DIRTY_CLIP (1ull << 9)
95 #define IRIS_DIRTY_SBE (1ull << 10)
96 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
97 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
98 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
99 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
100 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
101 #define IRIS_DIRTY_URB (1ull << 16)
102 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17)
103 #define IRIS_DIRTY_WM (1ull << 18)
104 #define IRIS_DIRTY_SO_BUFFERS (1ull << 19)
105 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 20)
106 #define IRIS_DIRTY_STREAMOUT (1ull << 21)
107 #define IRIS_DIRTY_VF_SGVS (1ull << 22)
108 #define IRIS_DIRTY_VF (1ull << 23)
109 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24)
110 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25)
111 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26)
112 #define IRIS_DIRTY_VF_STATISTICS (1ull << 27)
113 #define IRIS_DIRTY_PMA_FIX (1ull << 28)
114 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29)
115 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 30)
116 #define IRIS_DIRTY_STENCIL_REF (1ull << 31)
117 #define IRIS_DIRTY_VERTEX_BUFFER_FLUSHES (1ull << 32)
118 #define IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES (1ull << 33)
119 #define IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES (1ull << 34)
120 #define IRIS_DIRTY_VFG (1ull << 35)
121
122 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES | \
123 IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
124
125 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
126
127 /**
128 * Per-stage dirty flags. When state changes, we flag some combination of
129 * these to indicate that particular GPU commands need to be re-emitted.
130 * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
131 * indexed by shifting the mask by the shader stage index.
132 *
133 * See iris_upload_render_state().
134 */
135 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0)
136 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1)
137 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2)
138 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3)
139 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4)
140 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5)
141 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6)
142 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7)
143 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8)
144 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9)
145 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10)
146 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11)
147 #define IRIS_STAGE_DIRTY_VS (1ull << 12)
148 #define IRIS_STAGE_DIRTY_TCS (1ull << 13)
149 #define IRIS_STAGE_DIRTY_TES (1ull << 14)
150 #define IRIS_STAGE_DIRTY_GS (1ull << 15)
151 #define IRIS_STAGE_DIRTY_FS (1ull << 16)
152 #define IRIS_STAGE_DIRTY_CS (1ull << 17)
153 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18
154 #define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18)
155 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19)
156 #define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20)
157 #define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21)
158 #define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22)
159 #define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23)
160 #define IRIS_SHIFT_FOR_STAGE_DIRTY_BINDINGS 24
161 #define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24)
162 #define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25)
163 #define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26)
164 #define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27)
165 #define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28)
166 #define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29)
167
168 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
169 IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
170 IRIS_STAGE_DIRTY_UNCOMPILED_CS | \
171 IRIS_STAGE_DIRTY_CONSTANTS_CS | \
172 IRIS_STAGE_DIRTY_BINDINGS_CS)
173
174 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
175
176 #define IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER (IRIS_STAGE_DIRTY_BINDINGS_VS | \
177 IRIS_STAGE_DIRTY_BINDINGS_TCS | \
178 IRIS_STAGE_DIRTY_BINDINGS_TES | \
179 IRIS_STAGE_DIRTY_BINDINGS_GS | \
180 IRIS_STAGE_DIRTY_BINDINGS_FS)
181
182 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_ALL_STAGE_DIRTY_BINDINGS_FOR_RENDER | \
183 IRIS_STAGE_DIRTY_BINDINGS_CS)
184
185 /**
186 * Non-orthogonal state (NOS) dependency flags.
187 *
188 * Shader programs may depend on non-orthogonal state. These flags are
189 * used to indicate that a shader's key depends on the state provided by
190 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
191 * cause the driver to re-compute the shader key, possibly triggering a
192 * shader recompile.
193 */
194 enum iris_nos_dep {
195 IRIS_NOS_FRAMEBUFFER,
196 IRIS_NOS_DEPTH_STENCIL_ALPHA,
197 IRIS_NOS_RASTERIZER,
198 IRIS_NOS_BLEND,
199 IRIS_NOS_LAST_VUE_MAP,
200
201 IRIS_NOS_COUNT,
202 };
203
204 /** @{
205 *
206 * Program cache keys for state based recompiles.
207 */
208
209 struct iris_base_prog_key {
210 unsigned program_string_id;
211 };
212
213 /**
214 * Note, we need to take care to have padding explicitly declared
215 * for key since we will directly memcmp the whole struct.
216 */
217 struct iris_vue_prog_key {
218 struct iris_base_prog_key base;
219
220 unsigned nr_userclip_plane_consts:4;
221 unsigned padding:28;
222 };
223
224 struct iris_vs_prog_key {
225 struct iris_vue_prog_key vue;
226 };
227
228 struct iris_tcs_prog_key {
229 struct iris_vue_prog_key vue;
230
231 enum tess_primitive_mode _tes_primitive_mode;
232
233 uint8_t input_vertices;
234
235 bool quads_workaround;
236
237 /** A bitfield of per-patch outputs written. */
238 uint32_t patch_outputs_written;
239
240 /** A bitfield of per-vertex outputs written. */
241 uint64_t outputs_written;
242 };
243
244 struct iris_tes_prog_key {
245 struct iris_vue_prog_key vue;
246
247 /** A bitfield of per-patch inputs read. */
248 uint32_t patch_inputs_read;
249
250 /** A bitfield of per-vertex inputs read. */
251 uint64_t inputs_read;
252 };
253
254 struct iris_gs_prog_key {
255 struct iris_vue_prog_key vue;
256 };
257
258 struct iris_fs_prog_key {
259 struct iris_base_prog_key base;
260
261 unsigned nr_color_regions:5;
262 bool flat_shade:1;
263 bool alpha_test_replicate_alpha:1;
264 bool alpha_to_coverage:1;
265 bool clamp_fragment_color:1;
266 bool persample_interp:1;
267 bool multisample_fbo:1;
268 bool force_dual_color_blend:1;
269 bool coherent_fb_fetch:1;
270
271 uint8_t color_outputs_valid;
272 uint64_t input_slots_valid;
273 };
274
275 struct iris_cs_prog_key {
276 struct iris_base_prog_key base;
277 };
278
279 union iris_any_prog_key {
280 struct iris_base_prog_key base;
281 struct iris_vue_prog_key vue;
282 struct iris_vs_prog_key vs;
283 struct iris_tcs_prog_key tcs;
284 struct iris_tes_prog_key tes;
285 struct iris_gs_prog_key gs;
286 struct iris_fs_prog_key fs;
287 struct iris_cs_prog_key cs;
288 };
289
290 /** @} */
291
292 struct iris_depth_stencil_alpha_state;
293
294 /**
295 * Cache IDs for the in-memory program cache (ice->shaders.cache).
296 */
297 enum iris_program_cache_id {
298 IRIS_CACHE_VS = MESA_SHADER_VERTEX,
299 IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
300 IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
301 IRIS_CACHE_GS = MESA_SHADER_GEOMETRY,
302 IRIS_CACHE_FS = MESA_SHADER_FRAGMENT,
303 IRIS_CACHE_CS = MESA_SHADER_COMPUTE,
304 IRIS_CACHE_BLORP,
305 };
306
307 /** @{
308 *
309 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
310 * synchronization, pipelined memory writes, and so on.
311 *
312 * The bits here are not the actual hardware values. The actual fields
313 * move between various generations, so we just have flags for each
314 * potential operation, and use genxml to encode the actual packet.
315 */
316 enum pipe_control_flags
317 {
318 PIPE_CONTROL_FLUSH_LLC = (1 << 1),
319 PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2),
320 PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3),
321 PIPE_CONTROL_CS_STALL = (1 << 4),
322 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5),
323 PIPE_CONTROL_SYNC_GFDT = (1 << 6),
324 PIPE_CONTROL_TLB_INVALIDATE = (1 << 7),
325 PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8),
326 PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9),
327 PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10),
328 PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11),
329 PIPE_CONTROL_DEPTH_STALL = (1 << 12),
330 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
331 PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14),
332 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15),
333 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
334 PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17),
335 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18),
336 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
337 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20),
338 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21),
339 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22),
340 PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23),
341 PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24),
342 PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25),
343 PIPE_CONTROL_FLUSH_HDC = (1 << 26),
344 PIPE_CONTROL_PSS_STALL_SYNC = (1 << 27),
345 };
346
347 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
348 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
349 PIPE_CONTROL_DATA_CACHE_FLUSH | \
350 PIPE_CONTROL_TILE_CACHE_FLUSH | \
351 PIPE_CONTROL_RENDER_TARGET_FLUSH)
352
353 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
354 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
355 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
356 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
357 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
358 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
359
360 enum iris_predicate_state {
361 /* The first two states are used if we can determine whether to draw
362 * without having to look at the values in the query object buffer. This
363 * will happen if there is no conditional render in progress, if the query
364 * object is already completed or if something else has already added
365 * samples to the preliminary result.
366 */
367 IRIS_PREDICATE_STATE_RENDER,
368 IRIS_PREDICATE_STATE_DONT_RENDER,
369
370 /* In this case whether to draw or not depends on the result of an
371 * MI_PREDICATE command so the predicate enable bit needs to be checked.
372 */
373 IRIS_PREDICATE_STATE_USE_BIT,
374 };
375
376 /** @} */
377
378 /**
379 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
380 * It primarily contains the NIR for the shader.
381 *
382 * Each API-facing shader can be compiled into multiple shader variants,
383 * based on non-orthogonal state dependencies, recorded in the shader key.
384 *
385 * See iris_compiled_shader, which represents a compiled shader variant.
386 */
387 struct iris_uncompiled_shader {
388 struct pipe_reference ref;
389
390 /**
391 * NIR for the shader.
392 *
393 * Even for shaders that originate as TGSI, this pointer will be non-NULL.
394 */
395 struct nir_shader *nir;
396
397 struct pipe_stream_output_info stream_output;
398
399 /* A SHA1 of the serialized NIR for the disk cache. */
400 unsigned char nir_sha1[20];
401
402 unsigned program_id;
403
404 /** Bitfield of (1 << IRIS_NOS_*) flags. */
405 unsigned nos;
406
407 /** Have any shader variants been compiled yet? */
408 bool compiled_once;
409
410 /* Whether shader uses atomic operations. */
411 bool uses_atomic_load_store;
412
413 /** Size (in bytes) of the kernel input data */
414 unsigned kernel_input_size;
415
416 /** Size (in bytes) of the local (shared) data passed as kernel inputs */
417 unsigned kernel_shared_size;
418
419 /** List of iris_compiled_shader variants */
420 struct list_head variants;
421
422 /** Lock for the variants list */
423 simple_mtx_t lock;
424
425 /** For parallel shader compiles */
426 struct util_queue_fence ready;
427 };
428
429 enum iris_surface_group {
430 IRIS_SURFACE_GROUP_RENDER_TARGET,
431 IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
432 IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
433 IRIS_SURFACE_GROUP_TEXTURE,
434 IRIS_SURFACE_GROUP_IMAGE,
435 IRIS_SURFACE_GROUP_UBO,
436 IRIS_SURFACE_GROUP_SSBO,
437
438 IRIS_SURFACE_GROUP_COUNT,
439 };
440
441 enum {
442 /* Invalid value for a binding table index. */
443 IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
444 };
445
446 struct iris_binding_table {
447 uint32_t size_bytes;
448
449 /** Number of surfaces in each group, before compacting. */
450 uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
451
452 /** Initial offset of each group. */
453 uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
454
455 /** Mask of surfaces used in each group. */
456 uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
457 };
458
459 /**
460 * A compiled shader variant, containing a pointer to the GPU assembly,
461 * as well as program data and other packets needed by state upload.
462 *
463 * There can be several iris_compiled_shader variants per API-level shader
464 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
465 */
466 struct iris_compiled_shader {
467 struct pipe_reference ref;
468
469 /** Link in the iris_uncompiled_shader::variants list */
470 struct list_head link;
471
472 /** Key for this variant (but not for BLORP programs) */
473 union iris_any_prog_key key;
474
475 /**
476 * Is the variant fully compiled and ready?
477 *
478 * Variants are added to \c iris_uncompiled_shader::variants before
479 * compilation actually occurs. This signals that compilation has
480 * completed.
481 */
482 struct util_queue_fence ready;
483
484 /** Variant is ready, but compilation failed. */
485 bool compilation_failed;
486
487 /** Reference to the uploaded assembly. */
488 struct iris_state_ref assembly;
489
490 /** Pointer to the assembly in the BO's map. */
491 void *map;
492
493 /** The program data (owned by the program cache hash table) */
494 struct brw_stage_prog_data *prog_data;
495
496 /** A list of system values to be uploaded as uniforms. */
497 enum brw_param_builtin *system_values;
498 unsigned num_system_values;
499
500 /** Size (in bytes) of the kernel input data */
501 unsigned kernel_input_size;
502
503 /** Number of constbufs expected by the shader. */
504 unsigned num_cbufs;
505
506 /**
507 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
508 * (the VUE-based information for transform feedback outputs).
509 */
510 uint32_t *streamout;
511
512 struct iris_binding_table bt;
513
514 /**
515 * Shader packets and other data derived from prog_data. These must be
516 * completely determined from prog_data.
517 */
518 uint8_t derived_data[0];
519 };
520
521 /**
522 * API context state that is replicated per shader stage.
523 */
524 struct iris_shader_state {
525 /** Uniform Buffers */
526 struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
527 struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
528
529 bool sysvals_need_upload;
530
531 /** Shader Storage Buffers */
532 struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
533 struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
534
535 /** Shader Storage Images (image load store) */
536 struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
537
538 struct iris_state_ref sampler_table;
539 struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
540 struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
541
542 /** Bitfield of which constant buffers are bound (non-null). */
543 uint32_t bound_cbufs;
544 uint32_t dirty_cbufs;
545
546 /** Bitfield of which image views are bound (non-null). */
547 uint32_t bound_image_views;
548
549 /** Bitfield of which sampler views are bound (non-null). */
550 uint32_t bound_sampler_views;
551
552 /** Bitfield of which shader storage buffers are bound (non-null). */
553 uint32_t bound_ssbos;
554
555 /** Bitfield of which shader storage buffers are writable. */
556 uint32_t writable_ssbos;
557 };
558
559 /**
560 * Gallium CSO for stream output (transform feedback) targets.
561 */
562 struct iris_stream_output_target {
563 struct pipe_stream_output_target base;
564
565 /** Storage holding the offset where we're writing in the buffer */
566 struct iris_state_ref offset;
567
568 /** Stride (bytes-per-vertex) during this transform feedback operation */
569 uint16_t stride;
570
571 /** Does the next 3DSTATE_SO_BUFFER need to zero the offsets? */
572 bool zero_offset;
573 };
574
575 /**
576 * The API context (derived from pipe_context).
577 *
578 * Most driver state is tracked here.
579 */
580 struct iris_context {
581 struct pipe_context ctx;
582 struct threaded_context *thrctx;
583
584 /** A debug callback for KHR_debug output. */
585 struct pipe_debug_callback dbg;
586
587 /** A device reset status callback for notifying that the GPU is hosed. */
588 struct pipe_device_reset_callback reset;
589
590 /** A set of dmabuf resources dirtied beyond their default aux-states. */
591 struct set *dirty_dmabufs;
592
593 /** Slab allocator for iris_transfer_map objects. */
594 struct slab_child_pool transfer_pool;
595
596 /** Slab allocator for threaded_context's iris_transfer_map objects */
597 struct slab_child_pool transfer_pool_unsync;
598
599 struct blorp_context blorp;
600
601 struct iris_batch batches[IRIS_BATCH_COUNT];
602
603 struct u_upload_mgr *query_buffer_uploader;
604
605 struct intel_ds_device ds;
606
607 struct {
608 struct {
609 /**
610 * Either the value of BaseVertex for indexed draw calls or the value
611 * of the argument <first> for non-indexed draw calls.
612 */
613 int firstvertex;
614 int baseinstance;
615 } params;
616
617 /**
618 * Are the above values the ones stored in the draw_params buffer?
619 * If so, we can compare them against new values to see if anything
620 * changed. If not, we need to assume they changed.
621 */
622 bool params_valid;
623
624 /**
625 * Resource and offset that stores draw_parameters from the indirect
626 * buffer or to the buffer that stures the previous values for non
627 * indirect draws.
628 */
629 struct iris_state_ref draw_params;
630
631 struct {
632 /**
633 * The value of DrawID. This always comes in from it's own vertex
634 * buffer since it's not part of the indirect draw parameters.
635 */
636 int drawid;
637
638 /**
639 * Stores if an indexed or non-indexed draw (~0/0). Useful to
640 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
641 */
642 int is_indexed_draw;
643 } derived_params;
644
645 /**
646 * Resource and offset used for GL_ARB_shader_draw_parameters which
647 * contains parameters that are not present in the indirect buffer as
648 * drawid and is_indexed_draw. They will go in their own vertex element.
649 */
650 struct iris_state_ref derived_draw_params;
651 } draw;
652
653 struct {
654 struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
655 struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
656 struct iris_compiled_shader *last_vue_shader;
657 struct {
658 unsigned size[4];
659 unsigned entries[4];
660 unsigned start[4];
661 bool constrained;
662 } urb;
663
664 /** Uploader for shader assembly from the driver thread */
665 struct u_upload_mgr *uploader_driver;
666 /** Uploader for shader assembly from the threaded context */
667 struct u_upload_mgr *uploader_unsync;
668 struct hash_table *cache;
669
670 /** Is a GS or TES outputting points or lines? */
671 bool output_topology_is_points_or_lines;
672
673 /**
674 * Scratch buffers for various sizes and stages.
675 *
676 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
677 * and shader stage.
678 */
679 struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
680
681 /**
682 * Scratch buffer surface states on Gfx12.5+
683 */
684 struct iris_state_ref scratch_surfs[1 << 4];
685 } shaders;
686
687 struct intel_perf_context *perf_ctx;
688
689 /** Frame number for debug prints */
690 uint32_t frame;
691
692 struct {
693 uint64_t dirty;
694 uint64_t stage_dirty;
695 uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT];
696
697 unsigned num_viewports;
698 unsigned sample_mask;
699 struct iris_blend_state *cso_blend;
700 struct iris_rasterizer_state *cso_rast;
701 struct iris_depth_stencil_alpha_state *cso_zsa;
702 struct iris_vertex_element_state *cso_vertex_elements;
703 struct pipe_blend_color blend_color;
704 struct pipe_poly_stipple poly_stipple;
705 struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
706 struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
707 struct pipe_stencil_ref stencil_ref;
708 struct pipe_framebuffer_state framebuffer;
709 struct pipe_clip_state clip_planes;
710
711 float default_outer_level[4];
712 float default_inner_level[2];
713
714 /** Bitfield of which vertex buffers are bound (non-null). */
715 uint64_t bound_vertex_buffers;
716
717 uint8_t patch_vertices;
718 bool primitive_restart;
719 unsigned cut_index;
720 enum pipe_prim_type prim_mode:8;
721 bool prim_is_points_or_lines;
722 uint8_t vertices_per_patch;
723
724 bool window_space_position;
725
726 /** The last compute group size */
727 uint32_t last_block[3];
728
729 /** The last compute grid size */
730 uint32_t last_grid[3];
731 /** Reference to the BO containing the compute grid size */
732 struct iris_state_ref grid_size;
733 /** Reference to the SURFACE_STATE for the compute grid resource */
734 struct iris_state_ref grid_surf_state;
735
736 /**
737 * Array of aux usages for drawing, altered to account for any
738 * self-dependencies from resources bound for sampling and rendering.
739 */
740 enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
741
742 /** Aux usage of the fb's depth buffer (which may or may not exist). */
743 enum isl_aux_usage hiz_usage;
744
745 enum intel_urb_deref_block_size urb_deref_block_size;
746
747 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
748 bool depth_writes_enabled;
749
750 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
751 bool stencil_writes_enabled;
752
753 /** GenX-specific current state */
754 struct iris_genx_state *genx;
755
756 struct iris_shader_state shaders[MESA_SHADER_STAGES];
757
758 /** Do vertex shader uses shader draw parameters ? */
759 bool vs_uses_draw_params;
760 bool vs_uses_derived_draw_params;
761 bool vs_needs_sgvs_element;
762
763 /** Do vertex shader uses edge flag ? */
764 bool vs_needs_edge_flag;
765
766 /** Do any samplers need border color? One bit per shader stage. */
767 uint8_t need_border_colors;
768
769 /** Global resource bindings */
770 struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS];
771
772 struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
773 bool streamout_active;
774
775 bool statistics_counters_enabled;
776
777 /** Current conditional rendering mode */
778 enum iris_predicate_state predicate;
779
780 /**
781 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
782 * render context that needs to be uploaded to the compute context.
783 */
784 struct iris_bo *compute_predicate;
785
786 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
787 bool prims_generated_query_active;
788
789 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
790 uint32_t *streamout;
791
792 /** The SURFACE_STATE for a 1x1x1 null surface. */
793 struct iris_state_ref unbound_tex;
794
795 /** The SURFACE_STATE for a framebuffer-sized null surface. */
796 struct iris_state_ref null_fb;
797
798 struct u_upload_mgr *surface_uploader;
799 struct u_upload_mgr *bindless_uploader;
800 struct u_upload_mgr *dynamic_uploader;
801
802 struct iris_binder binder;
803
804 /** The high 16-bits of the last VBO/index buffer addresses */
805 uint16_t last_vbo_high_bits[33];
806 uint16_t last_index_bo_high_bits;
807
808 /**
809 * Resources containing streamed state which our render context
810 * currently points to. Used to re-add these to the validation
811 * list when we start a new batch and haven't resubmitted commands.
812 */
813 struct {
814 struct pipe_resource *cc_vp;
815 struct pipe_resource *sf_cl_vp;
816 struct pipe_resource *color_calc;
817 struct pipe_resource *scissor;
818 struct pipe_resource *blend;
819 struct pipe_resource *index_buffer;
820 struct pipe_resource *cs_thread_ids;
821 struct pipe_resource *cs_desc;
822 } last_res;
823
824 /** Records the size of variable-length state for INTEL_DEBUG=bat */
825 struct hash_table_u64 *sizes;
826
827 /** Last rendering scale argument provided to genX(emit_hashing_mode). */
828 unsigned current_hash_scale;
829
830 /** Resource holding the pixel pipe hashing tables. */
831 struct pipe_resource *pixel_hashing_tables;
832 } state;
833 };
834
835 #define perf_debug(dbg, ...) do { \
836 if (INTEL_DEBUG(DEBUG_PERF)) \
837 dbg_printf(__VA_ARGS__); \
838 if (unlikely(dbg)) \
839 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
840 } while(0)
841
842 struct pipe_context *
843 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
844 void iris_destroy_context(struct pipe_context *ctx);
845
846 void iris_lost_context_state(struct iris_batch *batch);
847
848 void iris_mark_dirty_dmabuf(struct iris_context *ice,
849 struct pipe_resource *res);
850 void iris_flush_dirty_dmabufs(struct iris_context *ice);
851
852 void iris_init_blit_functions(struct pipe_context *ctx);
853 void iris_init_clear_functions(struct pipe_context *ctx);
854 void iris_init_program_functions(struct pipe_context *ctx);
855 void iris_init_screen_program_functions(struct pipe_screen *pscreen);
856 void iris_init_resource_functions(struct pipe_context *ctx);
857 void iris_init_perfquery_functions(struct pipe_context *ctx);
858 void iris_update_compiled_shaders(struct iris_context *ice);
859 void iris_update_compiled_compute_shader(struct iris_context *ice);
860 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
861 unsigned threads,
862 uint32_t *dst);
863
864
865 /* iris_blit.c */
866 void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
867 struct blorp_surf *surf,
868 struct pipe_resource *p_res,
869 enum isl_aux_usage aux_usage,
870 unsigned level,
871 bool is_render_target);
872 void iris_copy_region(struct blorp_context *blorp,
873 struct iris_batch *batch,
874 struct pipe_resource *dst,
875 unsigned dst_level,
876 unsigned dstx, unsigned dsty, unsigned dstz,
877 struct pipe_resource *src,
878 unsigned src_level,
879 const struct pipe_box *src_box);
880
881 static inline enum blorp_batch_flags
iris_blorp_flags_for_batch(struct iris_batch * batch)882 iris_blorp_flags_for_batch(struct iris_batch *batch)
883 {
884 if (batch->name == IRIS_BATCH_COMPUTE)
885 return BLORP_BATCH_USE_COMPUTE;
886
887 if (batch->name == IRIS_BATCH_BLITTER)
888 return BLORP_BATCH_USE_BLITTER;
889
890 return 0;
891 }
892
893 /* iris_draw.c */
894
895 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
896 unsigned drawid_offset,
897 const struct pipe_draw_indirect_info *indirect,
898 const struct pipe_draw_start_count_bias *draws,
899 unsigned num_draws);
900 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
901
902 /* iris_pipe_control.c */
903
904 void iris_emit_pipe_control_flush(struct iris_batch *batch,
905 const char *reason, uint32_t flags);
906 void iris_emit_pipe_control_write(struct iris_batch *batch,
907 const char *reason, uint32_t flags,
908 struct iris_bo *bo, uint32_t offset,
909 uint64_t imm);
910 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
911 const char *reason, uint32_t flags);
912 void iris_emit_buffer_barrier_for(struct iris_batch *batch,
913 struct iris_bo *bo,
914 enum iris_domain access);
915 void iris_flush_all_caches(struct iris_batch *batch);
916
917 #define iris_handle_always_flush_cache(batch) \
918 if (unlikely(batch->screen->driconf.always_flush_cache)) \
919 iris_flush_all_caches(batch);
920
921 void iris_init_flush_functions(struct pipe_context *ctx);
922
923 /* iris_program.c */
924 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
925 struct pipe_shader_buffer *buf,
926 struct iris_state_ref *surf_state,
927 isl_surf_usage_flags_t usage);
928 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
929 gl_shader_stage stage);
930 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
931 unsigned per_thread_scratch,
932 gl_shader_stage stage);
933 const struct iris_state_ref *iris_get_scratch_surf(struct iris_context *ice,
934 unsigned per_thread_scratch);
935 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
936 enum iris_surface_group group,
937 uint32_t index);
938 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
939 enum iris_surface_group group,
940 uint32_t bti);
941
942 /* iris_disk_cache.c */
943
944 void iris_disk_cache_store(struct disk_cache *cache,
945 const struct iris_uncompiled_shader *ish,
946 const struct iris_compiled_shader *shader,
947 const void *prog_key,
948 uint32_t prog_key_size);
949 bool
950 iris_disk_cache_retrieve(struct iris_screen *screen,
951 struct u_upload_mgr *uploader,
952 struct iris_uncompiled_shader *ish,
953 struct iris_compiled_shader *shader,
954 const void *prog_key,
955 uint32_t prog_key_size);
956
957 /* iris_program_cache.c */
958
959 void iris_init_program_cache(struct iris_context *ice);
960 void iris_destroy_program_cache(struct iris_context *ice);
961 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
962 enum iris_program_cache_id,
963 uint32_t key_size,
964 const void *key);
965
966 struct iris_compiled_shader *iris_create_shader_variant(const struct iris_screen *,
967 void *mem_ctx,
968 enum iris_program_cache_id cache_id,
969 uint32_t key_size,
970 const void *key);
971
972 void iris_finalize_program(struct iris_compiled_shader *shader,
973 struct brw_stage_prog_data *prog_data,
974 uint32_t *streamout,
975 enum brw_param_builtin *system_values,
976 unsigned num_system_values,
977 unsigned kernel_input_size,
978 unsigned num_cbufs,
979 const struct iris_binding_table *bt);
980
981 void iris_upload_shader(struct iris_screen *screen,
982 struct iris_uncompiled_shader *,
983 struct iris_compiled_shader *,
984 struct hash_table *driver_ht,
985 struct u_upload_mgr *uploader,
986 enum iris_program_cache_id,
987 uint32_t key_size,
988 const void *key,
989 const void *assembly);
990 void iris_delete_shader_variant(struct iris_compiled_shader *shader);
991
992 void iris_destroy_shader_state(struct pipe_context *ctx, void *state);
993
994 static inline void
iris_uncompiled_shader_reference(struct pipe_context * ctx,struct iris_uncompiled_shader ** dst,struct iris_uncompiled_shader * src)995 iris_uncompiled_shader_reference(struct pipe_context *ctx,
996 struct iris_uncompiled_shader **dst,
997 struct iris_uncompiled_shader *src)
998 {
999 if (*dst == src)
1000 return;
1001
1002 struct iris_uncompiled_shader *old_dst = *dst;
1003
1004 if (pipe_reference(old_dst != NULL ? &old_dst->ref : NULL,
1005 src != NULL ? &src->ref : NULL)) {
1006 iris_destroy_shader_state(ctx, *dst);
1007 }
1008
1009 *dst = src;
1010 }
1011
1012 static inline void
iris_shader_variant_reference(struct iris_compiled_shader ** dst,struct iris_compiled_shader * src)1013 iris_shader_variant_reference(struct iris_compiled_shader **dst,
1014 struct iris_compiled_shader *src)
1015 {
1016 struct iris_compiled_shader *old_dst = *dst;
1017
1018 if (pipe_reference(old_dst ? &old_dst->ref: NULL, src ? &src->ref : NULL))
1019 iris_delete_shader_variant(old_dst);
1020
1021 *dst = src;
1022 }
1023
1024 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
1025 const void *key,
1026 uint32_t key_size,
1027 uint32_t *kernel_out,
1028 void *prog_data_out);
1029 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
1030 const void *key, uint32_t key_size,
1031 const void *kernel, uint32_t kernel_size,
1032 const struct brw_stage_prog_data *prog_data,
1033 uint32_t prog_data_size,
1034 uint32_t *kernel_out,
1035 void *prog_data_out);
1036
1037 /* iris_resolve.c */
1038
1039 void iris_predraw_resolve_inputs(struct iris_context *ice,
1040 struct iris_batch *batch,
1041 bool *draw_aux_buffer_disabled,
1042 gl_shader_stage stage,
1043 bool consider_framebuffer);
1044 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
1045 struct iris_batch *batch,
1046 bool *draw_aux_buffer_disabled);
1047 void iris_predraw_flush_buffers(struct iris_context *ice,
1048 struct iris_batch *batch,
1049 gl_shader_stage stage);
1050 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
1051 struct iris_batch *batch);
1052 void iris_cache_flush_for_render(struct iris_batch *batch,
1053 struct iris_bo *bo,
1054 enum isl_aux_usage aux_usage);
1055 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
1056 struct pipe_driver_query_info *info);
1057 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
1058 unsigned index,
1059 struct pipe_driver_query_group_info *info);
1060
1061 /* iris_state.c */
1062 void gfx9_toggle_preemption(struct iris_context *ice,
1063 struct iris_batch *batch,
1064 const struct pipe_draw_info *draw);
1065
1066
1067
1068 #ifdef genX
1069 # include "iris_genx_protos.h"
1070 #else
1071 # define genX(x) gfx4_##x
1072 # include "iris_genx_protos.h"
1073 # undef genX
1074 # define genX(x) gfx5_##x
1075 # include "iris_genx_protos.h"
1076 # undef genX
1077 # define genX(x) gfx6_##x
1078 # include "iris_genx_protos.h"
1079 # undef genX
1080 # define genX(x) gfx7_##x
1081 # include "iris_genx_protos.h"
1082 # undef genX
1083 # define genX(x) gfx75_##x
1084 # include "iris_genx_protos.h"
1085 # undef genX
1086 # define genX(x) gfx8_##x
1087 # include "iris_genx_protos.h"
1088 # undef genX
1089 # define genX(x) gfx9_##x
1090 # include "iris_genx_protos.h"
1091 # undef genX
1092 # define genX(x) gfx11_##x
1093 # include "iris_genx_protos.h"
1094 # undef genX
1095 # define genX(x) gfx12_##x
1096 # include "iris_genx_protos.h"
1097 # undef genX
1098 # define genX(x) gfx125_##x
1099 # include "iris_genx_protos.h"
1100 # undef genX
1101 #endif
1102
1103 #endif
1104