1 #ifndef TARGET_PPC_CPU_INIT_H 2 #define TARGET_PPC_CPU_INIT_H 3 4 #define PPC_INSNS_FLAGS_POWER9 \ 5 (PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \ 6 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ 7 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \ 8 PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | \ 9 PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ 10 PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \ 11 PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \ 12 PPC_CILDST) 13 14 #define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 15 #define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 16 17 #define PPC_INSNS_FLAGS2_POWER_COMMON \ 18 (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ 19 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ 20 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ 21 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ 22 PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ 23 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) 24 25 #define PPC_INSNS_FLAGS2_POWER9 \ 26 (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM) 27 #define PPC_INSNS_FLAGS2_POWER10 \ 28 (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310) 29 #define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10 30 31 #define PPC_MSR_MASK_POWER_COMMON \ 32 ((1ull << MSR_SF) | \ 33 (1ull << MSR_HV) | \ 34 (1ull << MSR_VR) | \ 35 (1ull << MSR_VSX) | \ 36 (1ull << MSR_EE) | \ 37 (1ull << MSR_PR) | \ 38 (1ull << MSR_FP) | \ 39 (1ull << MSR_ME) | \ 40 (1ull << MSR_FE0) | \ 41 (1ull << MSR_SE) | \ 42 (1ull << MSR_DE) | \ 43 (1ull << MSR_FE1) | \ 44 (1ull << MSR_IR) | \ 45 (1ull << MSR_DR) | \ 46 (1ull << MSR_PMM) | \ 47 (1ull << MSR_RI) | \ 48 (1ull << MSR_LE)) 49 50 #define PPC_MSR_MASK_POWER9 \ 51 (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM)) 52 #define PPC_MSR_MASK_POWER10 \ 53 PPC_MSR_MASK_POWER_COMMON 54 #define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10 55 56 #define PPC_PCR_MASK_POWER9 \ 57 (PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07) 58 #define PPC_PCR_MASK_POWER10 \ 59 (PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00) 60 #define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10 61 62 #define PPC_PCR_SUPPORTED_POWER9 \ 63 (PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05) 64 #define PPC_PCR_SUPPORTED_POWER10 \ 65 (PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10) 66 #define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10 67 68 #define PPC_LPCR_MASK_POWER9 \ 69 (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \ 70 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | \ 71 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | \ 72 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | \ 73 LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | \ 74 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE) 75 /* DD2 adds an extra HAIL bit */ 76 #define PPC_LPCR_MASK_POWER10 \ 77 (PPC_LPCR_MASK_POWER9 | LPCR_HAIL) 78 #define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10 79 80 #define POWERPC_FLAGS_POWER_COMMON \ 81 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ 82 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \ 83 POWERPC_FLAG_VSX | POWERPC_FLAG_SCV) 84 85 #define POWERPC_FLAGS_POWER9 \ 86 (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM) 87 #define POWERPC_FLAGS_POWER10 \ 88 (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB) 89 #define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10 90 91 #endif /* TARGET_PPC_CPU_INIT_H */ 92