1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2017-2019, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_vdenc_hwcmd_g12_X.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of g12_X as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 #ifndef __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 31 #define __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 32 33 #pragma once 34 #pragma pack(1) 35 36 #include <cstdint> 37 #include <cstddef> 38 39 class mhw_vdbox_vdenc_g12_X 40 { 41 public: 42 // Internal Macros 43 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 44 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 45 #define __CODEGEN_OP_LENGTH_BIAS 2 46 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 47 GetOpLength(uint32_t uiLength)48 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 49 50 //! 51 //! \brief VDENC_64B_Aligned_Lower_Address 52 //! \details 53 //! 54 //! 55 struct VDENC_64B_Aligned_Lower_Address_CMD 56 { 57 union 58 { 59 //!< DWORD 0 60 struct 61 { 62 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 63 uint32_t Address : __CODEGEN_BITFIELD( 6, 31) ; //!< Address 64 }; 65 uint32_t Value; 66 } DW0; 67 68 //! \name Local enumerations 69 70 //! \name Initializations 71 72 //! \brief Explicit member initialization function 73 VDENC_64B_Aligned_Lower_Address_CMD(); 74 75 static const size_t dwSize = 1; 76 static const size_t byteSize = 4; 77 }; 78 79 //! 80 //! \brief VDENC_64B_Aligned_Upper_Address 81 //! \details 82 //! 83 //! 84 struct VDENC_64B_Aligned_Upper_Address_CMD 85 { 86 union 87 { 88 //!< DWORD 0 89 struct 90 { 91 uint32_t AddressUpperDword : __CODEGEN_BITFIELD( 0, 15) ; //!< Address Upper DWord 92 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW0; 96 97 //! \name Local enumerations 98 99 //! \name Initializations 100 101 //! \brief Explicit member initialization function 102 VDENC_64B_Aligned_Upper_Address_CMD(); 103 104 static const size_t dwSize = 1; 105 static const size_t byteSize = 4; 106 }; 107 108 //! 109 //! \brief VDENC_Surface_Control_Bits 110 //! \details 111 //! 112 //! 113 struct VDENC_Surface_Control_Bits_CMD 114 { 115 union 116 { 117 //!< DWORD 0 118 struct 119 { 120 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Index to Memory Object Control State (MOCS) Tables: 121 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ARBITRATION_PRIORITY_CONTROL 122 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MEMORY_COMPRESSION_ENABLE 123 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< Compression Type 124 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 125 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< CACHE_SELECT 126 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILED_RESOURCE_MODE 127 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 128 }; 129 uint32_t Value; 130 } DW0; 131 132 //! \name Local enumerations 133 134 //! \brief ARBITRATION_PRIORITY_CONTROL 135 //! \details 136 //! This field controls the priority of arbitration used in the GAC/GAM 137 //! pipeline for this surface. 138 enum ARBITRATION_PRIORITY_CONTROL 139 { 140 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 141 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 142 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 143 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 144 }; 145 146 //! \brief MEMORY_COMPRESSION_ENABLE 147 //! \details 148 //! Memory compression will be attempted for this surface. 149 enum MEMORY_COMPRESSION_ENABLE 150 { 151 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 152 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 153 }; 154 155 //! \brief MEMORY_COMPRESSION_MODE 156 //! \details 157 //! Distinguishes Vertical from Horizontal compression. Please refer to 158 //! vol1a <b>Memory Data</b>. 159 enum MEMORY_COMPRESSION_MODE 160 { 161 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 162 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 163 }; 164 165 //! \brief CACHE_SELECT 166 //! \details 167 //! This field controls if the Row Store is going to store inside Media 168 //! Cache (rowstore cache) or to LLC. 169 enum CACHE_SELECT 170 { 171 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 172 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 173 }; 174 175 //! \brief TILED_RESOURCE_MODE 176 //! \details 177 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 178 enum TILED_RESOURCE_MODE 179 { 180 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 181 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 182 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 183 }; 184 185 //! \name Initializations 186 187 //! \brief Explicit member initialization function 188 VDENC_Surface_Control_Bits_CMD(); 189 190 static const size_t dwSize = 1; 191 static const size_t byteSize = 4; 192 }; 193 194 //! 195 //! \brief VDENC_Sub_Mb_Pred_Mode 196 //! \details 197 //! 198 //! 199 struct VDENC_Sub_Mb_Pred_Mode_CMD 200 { 201 union 202 { 203 //!< WORD 0 204 struct 205 { 206 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD( 0, 1) ; //!< SubMbPredMode[0] 207 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD( 2, 3) ; //!< SubMbPredMode[1] 208 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD( 4, 5) ; //!< SubMbPredMode[2] 209 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD( 6, 7) ; //!< SubMbPredMode[3] 210 }; 211 uint8_t Value; 212 } DW0; 213 214 //! \name Local enumerations 215 216 //! \name Initializations 217 218 //! \brief Explicit member initialization function 219 VDENC_Sub_Mb_Pred_Mode_CMD(); 220 221 static const size_t dwSize = 0; 222 static const size_t byteSize = 1; 223 }; 224 225 //! 226 //! \brief VDENC_Block_8x8_4 227 //! \details 228 //! 229 //! 230 struct VDENC_Block_8x8_4_CMD 231 { 232 union 233 { 234 //!< WORD 0 235 struct 236 { 237 uint16_t Block8X80 : __CODEGEN_BITFIELD( 0, 3) ; //!< Block8x8[0] 238 uint16_t Block8X81 : __CODEGEN_BITFIELD( 4, 7) ; //!< Block8x8[1] 239 uint16_t Block8X82 : __CODEGEN_BITFIELD( 8, 11) ; //!< Block8x8[2] 240 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15) ; //!< Block8x8[3] 241 }; 242 uint16_t Value; 243 } DW0; 244 245 //! \name Local enumerations 246 247 //! \name Initializations 248 249 //! \brief Explicit member initialization function 250 VDENC_Block_8x8_4_CMD(); 251 252 static const size_t dwSize = 0; 253 static const size_t byteSize = 2; 254 }; 255 256 //! 257 //! \brief VDENC_Delta_MV_XY 258 //! \details 259 //! 260 //! 261 //! Calculates the difference between the actual MV for the Sub Macroblock 262 //! and the predicted MV based on the availability of the neighbors. 263 //! 264 //! This is calculated and populated for Inter frames only. In case of an 265 //! Intra MB in Inter frames, this value should be 0. 266 //! 267 struct VDENC_Delta_MV_XY_CMD 268 { 269 union 270 { 271 //!< DWORD 0 272 struct 273 { 274 uint32_t X0 : __CODEGEN_BITFIELD( 0, 15) ; //!< X0 275 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31) ; //!< Y0 276 }; 277 uint32_t Value; 278 } DW0; 279 union 280 { 281 //!< DWORD 1 282 struct 283 { 284 uint32_t X1 : __CODEGEN_BITFIELD( 0, 15) ; //!< X1 285 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31) ; //!< Y1 286 }; 287 uint32_t Value; 288 } DW1; 289 union 290 { 291 //!< DWORD 2 292 struct 293 { 294 uint32_t X2 : __CODEGEN_BITFIELD( 0, 15) ; //!< X2 295 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31) ; //!< Y2 296 }; 297 uint32_t Value; 298 } DW2; 299 union 300 { 301 //!< DWORD 3 302 struct 303 { 304 uint32_t X3 : __CODEGEN_BITFIELD( 0, 15) ; //!< X3 305 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31) ; //!< Y3 306 }; 307 uint32_t Value; 308 } DW3; 309 310 //! \name Local enumerations 311 312 //! \brief X0 313 //! \details 314 enum X0 315 { 316 X0_UNNAMED0 = 0, //!< No additional details 317 }; 318 319 //! \brief Y0 320 //! \details 321 enum Y0 322 { 323 Y0_UNNAMED0 = 0, //!< No additional details 324 }; 325 326 //! \brief X1 327 //! \details 328 enum X1 329 { 330 X1_UNNAMED0 = 0, //!< No additional details 331 }; 332 333 //! \brief Y1 334 //! \details 335 enum Y1 336 { 337 Y1_UNNAMED0 = 0, //!< No additional details 338 }; 339 340 //! \brief X2 341 //! \details 342 enum X2 343 { 344 X2_UNNAMED0 = 0, //!< No additional details 345 }; 346 347 //! \brief Y2 348 //! \details 349 enum Y2 350 { 351 Y2_UNNAMED0 = 0, //!< No additional details 352 }; 353 354 //! \brief X3 355 //! \details 356 enum X3 357 { 358 X3_UNNAMED0 = 0, //!< No additional details 359 }; 360 361 //! \brief Y3 362 //! \details 363 enum Y3 364 { 365 Y3_UNNAMED0 = 0, //!< No additional details 366 }; 367 368 //! \name Initializations 369 370 //! \brief Explicit member initialization function 371 VDENC_Delta_MV_XY_CMD(); 372 373 static const size_t dwSize = 4; 374 static const size_t byteSize = 16; 375 }; 376 377 //! 378 //! \brief VDENC_Colocated_MV_Picture 379 //! \details 380 //! 381 //! 382 struct VDENC_Colocated_MV_Picture_CMD 383 { 384 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 385 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 386 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 387 388 //! \name Local enumerations 389 390 //! \name Initializations 391 392 //! \brief Explicit member initialization function 393 VDENC_Colocated_MV_Picture_CMD(); 394 395 static const size_t dwSize = 3; 396 static const size_t byteSize = 12; 397 }; 398 399 //! 400 //! \brief VDENC_Down_Scaled_Reference_Picture 401 //! \details 402 //! 403 //! 404 struct VDENC_Down_Scaled_Reference_Picture_CMD 405 { 406 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 407 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 408 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 409 410 //! \name Local enumerations 411 412 //! \name Initializations 413 414 //! \brief Explicit member initialization function 415 VDENC_Down_Scaled_Reference_Picture_CMD(); 416 417 static const size_t dwSize = 3; 418 static const size_t byteSize = 12; 419 }; 420 421 //! 422 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 423 //! \details 424 //! 425 //! 426 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 427 { 428 union 429 { 430 //!< DWORD 0 431 struct 432 { 433 uint32_t SumSadHaarForBestMbChoice ; //!< Sum sad\haar for best MB choice 434 }; 435 uint32_t Value; 436 } DW0; 437 union 438 { 439 //!< DWORD 1 440 struct 441 { 442 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 16x16 MB count 443 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra MB count 444 }; 445 uint32_t Value; 446 } DW1; 447 union 448 { 449 //!< DWORD 2 450 struct 451 { 452 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 4x4 MB count 453 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra iso 8x8 MB count 454 }; 455 uint32_t Value; 456 } DW2; 457 union 458 { 459 //!< DWORD 3 460 struct 461 { 462 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 0 463 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 1 464 }; 465 uint32_t Value; 466 } DW3; 467 union 468 { 469 //!< DWORD 4 470 struct 471 { 472 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 2 473 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 3 474 }; 475 uint32_t Value; 476 } DW4; 477 478 uint32_t Reserved160[12]; //!< Reserved 479 480 union 481 { 482 //!< DWORD 17 483 struct 484 { 485 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation ; //!< Sum sad\haar for best MB choice bottom half population 486 }; 487 uint32_t Value; 488 } DW17; 489 union 490 { 491 //!< DWORD 18 492 struct 493 { 494 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation ; //!< Sum sad\haar for best MB choice top half population 495 }; 496 uint32_t Value; 497 } DW18; 498 union 499 { 500 //!< DWORD 19 501 struct 502 { 503 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 504 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 505 }; 506 uint32_t Value; 507 } DW19; 508 509 //! \name Local enumerations 510 511 //! \name Initializations 512 513 //! \brief Explicit member initialization function 514 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 515 516 static const size_t dwSize = 20; 517 static const size_t byteSize = 80; 518 }; 519 520 //! 521 //! \brief VDENC_Mode_StreamOut_Data 522 //! \details 523 //! 524 //! 525 struct VDENC_Mode_StreamOut_Data_CMD 526 { 527 union 528 { 529 //!< DWORD 0 530 struct 531 { 532 uint32_t MbX : __CODEGEN_BITFIELD( 0, 7) ; //!< MB.X 533 uint32_t MbY : __CODEGEN_BITFIELD( 8, 15) ; //!< MB.Y 534 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31) ; //!< Minimal Distortion 535 }; 536 uint32_t Value; 537 } DW0; 538 union 539 { 540 //!< DWORD 1 541 struct 542 { 543 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< SkipRawDistortion 544 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31) ; //!< InterRawDistortion 545 }; 546 uint32_t Value; 547 } DW1; 548 union 549 { 550 //!< DWORD 2 551 struct 552 { 553 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< BestIntraRawDistortion 554 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17) ; //!< INTERMBMODECHROMA_PREDICTION_MODE 555 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19) ; //!< INTRAMBMODE 556 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20) ; //!< INTRAMBFLAG 557 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21) ; //!< LASTMBFLAG 558 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22) ; //!< Coefficient Clamp Occurred 559 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23) ; //!< Conformance Violation 560 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31) ; //!< SubMbPredMode 561 }; 562 uint32_t Value; 563 } DW2; 564 union 565 { 566 //!< DWORD 3 567 struct 568 { 569 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[0] 570 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[1] 571 }; 572 uint32_t Value; 573 } DW3; 574 union 575 { 576 //!< DWORD 4 577 struct 578 { 579 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[2] 580 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[3] 581 }; 582 uint32_t Value; 583 } DW4; 584 VDENC_Delta_MV_XY_CMD DeltaMv0 ; //!< Delta MV0 585 VDENC_Delta_MV_XY_CMD DeltaMv1 ; //!< Delta MV1 586 union 587 { 588 //!< DWORD 13 589 struct 590 { 591 uint32_t FwdRefids : __CODEGEN_BITFIELD( 0, 15) ; //!< FWD REFIDs 592 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31) ; //!< BWD REFIDs 593 }; 594 uint32_t Value; 595 } DW13; 596 union 597 { 598 //!< DWORD 14 599 struct 600 { 601 uint32_t QpY : __CODEGEN_BITFIELD( 0, 5) ; //!< QP_y 602 uint32_t MbBitCount : __CODEGEN_BITFIELD( 6, 18) ; //!< MB_Bit_Count 603 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31) ; //!< MB_Header_Count 604 }; 605 uint32_t Value; 606 } DW14; 607 union 608 { 609 //!< DWORD 15 610 struct 611 { 612 uint32_t MbType : __CODEGEN_BITFIELD( 0, 4) ; //!< MB Type 613 uint32_t BlockCbp : __CODEGEN_BITFIELD( 5, 30) ; //!< Block CBP 614 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31) ; //!< SkipMbFlag 615 }; 616 uint32_t Value; 617 } DW15; 618 619 //! \name Local enumerations 620 621 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 622 //! \details 623 //! This field indicates the InterMB Parition type for Inter MB. 624 //! <br>OR</br> 625 //! This field indicates Chroma Prediction Mode for Intra MB. 626 enum INTERMBMODECHROMA_PREDICTION_MODE 627 { 628 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 629 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 630 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 631 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 632 }; 633 634 //! \brief INTRAMBMODE 635 //! \details 636 //! This field indicates the Best Intra Partition. 637 enum INTRAMBMODE 638 { 639 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 640 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 641 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 642 }; 643 644 //! \brief INTRAMBFLAG 645 //! \details 646 //! This field specifies whether the current macroblock is an Intra (I) 647 //! macroblock. 648 enum INTRAMBFLAG 649 { 650 INTRAMBFLAG_INTER = 0, //!< inter macroblock 651 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 652 }; 653 654 enum LASTMBFLAG 655 { 656 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 657 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 658 }; 659 660 //! \name Initializations 661 662 //! \brief Explicit member initialization function 663 VDENC_Mode_StreamOut_Data_CMD(); 664 665 static const size_t dwSize = 16; 666 static const size_t byteSize = 64; 667 }; 668 669 //! 670 //! \brief VDENC_Original_Uncompressed_Picture 671 //! \details 672 //! 673 //! 674 struct VDENC_Original_Uncompressed_Picture_CMD 675 { 676 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 677 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 678 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 679 680 //! \name Local enumerations 681 682 //! \name Initializations 683 684 //! \brief Explicit member initialization function 685 VDENC_Original_Uncompressed_Picture_CMD(); 686 687 static const size_t dwSize = 3; 688 static const size_t byteSize = 12; 689 }; 690 691 //! 692 //! \brief VDENC_Reference_Picture 693 //! \details 694 //! 695 //! 696 struct VDENC_Reference_Picture_CMD 697 { 698 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 699 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 700 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 701 702 //! \name Local enumerations 703 704 //! \name Initializations 705 706 //! \brief Explicit member initialization function 707 VDENC_Reference_Picture_CMD(); 708 709 static const size_t dwSize = 3; 710 static const size_t byteSize = 12; 711 }; 712 713 //! 714 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 715 //! \details 716 //! 717 //! 718 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 719 { 720 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 721 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 722 VDENC_Surface_Control_Bits_CMD BufferPictureFields ; //!< Buffer Picture Fields 723 724 //! \name Local enumerations 725 726 //! \name Initializations 727 728 //! \brief Explicit member initialization function 729 VDENC_Row_Store_Scratch_Buffer_Picture_CMD(); 730 731 static const size_t dwSize = 3; 732 static const size_t byteSize = 12; 733 }; 734 735 //! 736 //! \brief VDENC_Statistics_Streamout 737 //! \details 738 //! 739 //! 740 struct VDENC_Statistics_Streamout_CMD 741 { 742 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 743 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 744 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 745 746 //! \name Local enumerations 747 748 //! \name Initializations 749 750 //! \brief Explicit member initialization function 751 VDENC_Statistics_Streamout_CMD(); 752 753 static const size_t dwSize = 3; 754 static const size_t byteSize = 12; 755 }; 756 757 //! 758 //! \brief VDENC_Streamin_Data_Picture 759 //! \details 760 //! 761 //! 762 struct VDENC_Streamin_Data_Picture_CMD 763 { 764 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 765 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 766 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 767 768 //! \name Local enumerations 769 770 //! \name Initializations 771 772 //! \brief Explicit member initialization function 773 VDENC_Streamin_Data_Picture_CMD(); 774 775 static const size_t dwSize = 3; 776 static const size_t byteSize = 12; 777 }; 778 779 //! 780 //! \brief VDENC_STREAMIN_STATE 781 //! \details 782 //! 783 //! 784 struct VDENC_STREAMIN_STATE_CMD 785 { 786 union 787 { 788 //!< DWORD 0 789 struct 790 { 791 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD( 0, 7) ; //!< Region of Interest (ROI) Selection 792 uint32_t Forceintra : __CODEGEN_BITFIELD( 8, 8) ; //!< FORCEINTRA 793 uint32_t Forceskip : __CODEGEN_BITFIELD( 9, 9) ; //!< FORCESKIP 794 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 795 }; 796 uint32_t Value; 797 } DW0; 798 union 799 { 800 //!< DWORD 1 801 struct 802 { 803 uint32_t Qpprimey : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY 804 uint32_t Targetsizeinword : __CODEGEN_BITFIELD( 8, 15) ; //!< TargetSizeInWord 805 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< MaxSizeInWord 806 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 807 }; 808 uint32_t Value; 809 } DW1; 810 union 811 { 812 //!< DWORD 2 813 struct 814 { 815 uint32_t FwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Fwd Predictor.X 816 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Fwd Predictor.Y 817 }; 818 uint32_t Value; 819 } DW2; 820 union 821 { 822 //!< DWORD 3 823 struct 824 { 825 uint32_t BwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Bwd Predictor.X 826 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Bwd Predictor.Y 827 }; 828 uint32_t Value; 829 } DW3; 830 union 831 { 832 //!< DWORD 4 833 struct 834 { 835 uint32_t FwdRefid0 : __CODEGEN_BITFIELD( 0, 3) ; //!< Fwd RefID0 836 uint32_t BwdRefid0 : __CODEGEN_BITFIELD( 4, 7) ; //!< Bwd RefID0 837 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 838 }; 839 uint32_t Value; 840 } DW4; 841 842 uint32_t Reserved160[11]; //!< Reserved 843 844 845 //! \name Local enumerations 846 847 //! \brief FORCEINTRA 848 //! \details 849 //! This field specifies whether current macroblock should be coded as an 850 //! intra macroblock. 851 //! It is illegal to enable both ForceSkip and ForceIntra for 852 //! the same macroblock. 853 //! This should be disabled if Rolling-I is enabled in the 854 //! VDEnc Image State. 855 enum FORCEINTRA 856 { 857 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 858 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 859 }; 860 861 //! \brief FORCESKIP 862 //! \details 863 //! This field specifies whether current macroblock should be coded as a 864 //! skipped macroblock. 865 //! It is illegal to enable both ForceSkip and ForceIntra for 866 //! the same macroblock. 867 //! This should be disabled if Rolling-I is enabled in the 868 //! VDEnc Image State. 869 //! It is illegal to enable ForceSkip for I-Frames. 870 enum FORCESKIP 871 { 872 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 873 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 874 }; 875 876 //! \brief QPPRIMEY 877 //! \details 878 //! Quantization parameter for Y. 879 enum QPPRIMEY 880 { 881 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 882 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 883 }; 884 885 //! \name Initializations 886 887 //! \brief Explicit member initialization function 888 VDENC_STREAMIN_STATE_CMD(); 889 890 static const size_t dwSize = 16; 891 static const size_t byteSize = 64; 892 }; 893 894 //! 895 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 896 //! \details 897 //! 898 //! 899 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 900 { 901 union 902 { 903 //!< DWORD 0 904 struct 905 { 906 uint32_t SumSadHaarForBestModeDecision ; //!< Sum sad\haar for best mode decision 907 }; 908 uint32_t Value; 909 } DW0; 910 union 911 { 912 //!< DWORD 1 913 struct 914 { 915 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Intra CU count normalized 916 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 917 }; 918 uint32_t Value; 919 } DW1; 920 union 921 { 922 //!< DWORD 2 923 struct 924 { 925 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Non-skip Inter CU count normalized 926 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 927 }; 928 uint32_t Value; 929 } DW2; 930 union 931 { 932 //!< DWORD 3 933 struct 934 { 935 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 0 936 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 937 }; 938 uint32_t Value; 939 } DW3; 940 union 941 { 942 //!< DWORD 4 943 struct 944 { 945 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 1 946 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 947 }; 948 uint32_t Value; 949 } DW4; 950 union 951 { 952 //!< DWORD 5 953 struct 954 { 955 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 2 956 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 957 }; 958 uint32_t Value; 959 } DW5; 960 union 961 { 962 //!< DWORD 6 963 struct 964 { 965 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 3 966 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 967 }; 968 uint32_t Value; 969 } DW6; 970 union 971 { 972 //!< DWORD 7 973 struct 974 { 975 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 0 (.25x,.25x) 976 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 0 (.25x,.25x) 977 }; 978 uint32_t Value; 979 } DW7; 980 union 981 { 982 //!< DWORD 8 983 struct 984 { 985 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 1 (.25x,.25x) 986 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 1 (.25x,.25x) 987 }; 988 uint32_t Value; 989 } DW8; 990 union 991 { 992 //!< DWORD 9 993 struct 994 { 995 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 2 (.25x,.25x) 996 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 2 (.25x,.25x) 997 }; 998 uint32_t Value; 999 } DW9; 1000 union 1001 { 1002 //!< DWORD 10 1003 struct 1004 { 1005 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 3 (.25x,.25x) 1006 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 3 (.25x,.25x) 1007 }; 1008 uint32_t Value; 1009 } DW10; 1010 union 1011 { 1012 //!< DWORD 11 1013 struct 1014 { 1015 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 4 (.25x,.25x) 1016 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 4 (.25x,.25x) 1017 }; 1018 uint32_t Value; 1019 } DW11; 1020 union 1021 { 1022 //!< DWORD 12 1023 struct 1024 { 1025 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 5 (.25x,.25x) 1026 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 5 (.25x,.25x) 1027 }; 1028 uint32_t Value; 1029 } DW12; 1030 union 1031 { 1032 //!< DWORD 13 1033 struct 1034 { 1035 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 6 (.25x,.25x) 1036 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 6 (.25x,.25x) 1037 }; 1038 uint32_t Value; 1039 } DW13; 1040 union 1041 { 1042 //!< DWORD 14 1043 struct 1044 { 1045 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 7 (.25x,.25x) 1046 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 7 (.25x,.25x) 1047 }; 1048 uint32_t Value; 1049 } DW14; 1050 union 1051 { 1052 //!< DWORD 15 1053 struct 1054 { 1055 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 8 (.25x,.25x) 1056 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 8 (.25x,.25x) 1057 }; 1058 uint32_t Value; 1059 } DW15; 1060 union 1061 { 1062 //!< DWORD 16 1063 struct 1064 { 1065 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD( 0, 1) ; //!< RefID for GlobalME sample 0 1066 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD( 2, 17) ; //!< RefID for GlobalME sample 1-8 1067 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 1068 }; 1069 uint32_t Value; 1070 } DW16; 1071 union 1072 { 1073 //!< DWORD 17 1074 struct 1075 { 1076 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Palette CU Count Normalized 1077 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1078 }; 1079 uint32_t Value; 1080 } DW17; 1081 union 1082 { 1083 //!< DWORD 18 1084 struct 1085 { 1086 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< IBC CU Count Normalized 1087 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1088 }; 1089 uint32_t Value; 1090 } DW18; 1091 union 1092 { 1093 //!< DWORD 19 1094 struct 1095 { 1096 uint32_t NumberOfSecondaryColorsChannel1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel1) 1097 uint32_t NumberOfPrimaryColorsChannel0 : __CODEGEN_BITFIELD(16, 31) ; //!< Number of primary colors (Channel0) 1098 }; 1099 uint32_t Value; 1100 } DW19; 1101 union 1102 { 1103 //!< DWORD 20 1104 struct 1105 { 1106 uint32_t NumberOfSecondaryColorsChannel2 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel2) 1107 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1108 }; 1109 uint32_t Value; 1110 } DW20; 1111 union 1112 { 1113 //!< DWORD 21 1114 struct 1115 { 1116 uint32_t Reserved672 ; //!< Reserved 1117 }; 1118 uint32_t Value; 1119 } DW21; 1120 union 1121 { 1122 //!< DWORD 22 1123 struct 1124 { 1125 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD( 0, 15) ; //!< Position of Timer expiration 1126 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16) ; //!< Timer Expire status 1127 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1128 }; 1129 uint32_t Value; 1130 } DW22; 1131 union 1132 { 1133 //!< DWORD 23 1134 struct 1135 { 1136 uint32_t LocationOfPanic : __CODEGEN_BITFIELD( 0, 15) ; //!< Location of panic 1137 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16) ; //!< Panic detected 1138 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1139 }; 1140 uint32_t Value; 1141 } DW23; 1142 1143 uint32_t Reserved768[5]; //!< Reserved 1144 1145 union 1146 { 1147 //!< DWORD 29 1148 struct 1149 { 1150 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation ; //!< Sum sad\haar for best mode decision bottom half population 1151 }; 1152 uint32_t Value; 1153 } DW29; 1154 union 1155 { 1156 //!< DWORD 30 1157 struct 1158 { 1159 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation ; //!< Sum sad\haar for best mode decision top half population 1160 }; 1161 uint32_t Value; 1162 } DW30; 1163 union 1164 { 1165 //!< DWORD 31 1166 struct 1167 { 1168 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 1169 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 1170 }; 1171 uint32_t Value; 1172 } DW31; 1173 1174 //! \name Local enumerations 1175 1176 //! \name Initializations 1177 1178 //! \brief Explicit member initialization function 1179 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 1180 1181 static const size_t dwSize = 32; 1182 static const size_t byteSize = 128; 1183 }; 1184 1185 //! 1186 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 1187 //! \details 1188 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 1189 //! following configurations are valid. 1190 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 1191 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 1192 //! [64x64 --> 16x16]. 1193 //! 1194 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 1195 { 1196 union 1197 { 1198 //!< DWORD 0 1199 struct 1200 { 1201 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD( 0, 7) ; //!< ROI 32x32_0 16x16_03 1202 uint32_t Maxtusize : __CODEGEN_BITFIELD( 8, 9) ; //!< MaxTUSize 1203 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11) ; //!< MaxCUSize 1204 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15) ; //!< NUMIMEPREDICTORS 1205 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31) ; //!< PU Type 32x32_0 16x16_03 1206 }; 1207 uint32_t Value; 1208 } DW0; 1209 union 1210 { 1211 //!< DWORD 1 1212 struct 1213 { 1214 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_0 1215 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_0 1216 }; 1217 uint32_t Value; 1218 } DW1; 1219 union 1220 { 1221 //!< DWORD 2 1222 struct 1223 { 1224 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_1 1225 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_1 1226 }; 1227 uint32_t Value; 1228 } DW2; 1229 union 1230 { 1231 //!< DWORD 3 1232 struct 1233 { 1234 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_2 1235 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_2 1236 }; 1237 uint32_t Value; 1238 } DW3; 1239 union 1240 { 1241 //!< DWORD 4 1242 struct 1243 { 1244 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_3 1245 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_3 1246 }; 1247 uint32_t Value; 1248 } DW4; 1249 union 1250 { 1251 //!< DWORD 5 1252 struct 1253 { 1254 uint32_t Reserved160 ; //!< Reserved 1255 }; 1256 uint32_t Value; 1257 } DW5; 1258 union 1259 { 1260 //!< DWORD 6 1261 struct 1262 { 1263 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD( 0, 3) ; //!< force_mv refidx 32x32_0 16x16_0 1264 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD( 4, 15) ; //!< force_mv refidx 32x32_0 16x16_1-3 1265 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19) ; //!< NumMergeCandidateCU8x8 1266 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23) ; //!< NumMergeCandidateCU16x16 1267 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27) ; //!< NumMergeCandidateCU32x32 1268 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31) ; //!< NumMergeCandidateCU64x64 1269 }; 1270 uint32_t Value; 1271 } DW6; 1272 union 1273 { 1274 //!< DWORD 7 1275 struct 1276 { 1277 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD( 0, 15) ; //!< SegID 32x32_0 16x16_03 (VP9 only) 1278 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19) ; //!< QP_En 32x32_0 16x16_03 1279 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20) ; //!< SegID Enable 1280 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22) ; //!< Reserved 1281 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23) ; //!< Force Refid Enable (32x32_0) 1282 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31) ; //!< IME predictor/refid Select0-3 32x32_0 1283 }; 1284 uint32_t Value; 1285 } DW7; 1286 union 1287 { 1288 //!< DWORD 8 1289 struct 1290 { 1291 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_0 1292 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_0 1293 }; 1294 uint32_t Value; 1295 } DW8; 1296 union 1297 { 1298 //!< DWORD 9 1299 struct 1300 { 1301 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_1 1302 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_1 1303 }; 1304 uint32_t Value; 1305 } DW9; 1306 union 1307 { 1308 //!< DWORD 10 1309 struct 1310 { 1311 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_2 1312 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_2 1313 }; 1314 uint32_t Value; 1315 } DW10; 1316 union 1317 { 1318 //!< DWORD 11 1319 struct 1320 { 1321 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_3 1322 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_3 1323 }; 1324 uint32_t Value; 1325 } DW11; 1326 union 1327 { 1328 //!< DWORD 12 1329 struct 1330 { 1331 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD( 0, 3) ; //!< ime_predictor0 refidx 32x32_0 1332 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD( 4, 15) ; //!< ime_predictor1-3 refidx 32x32_1-3 1333 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1334 }; 1335 uint32_t Value; 1336 } DW12; 1337 union 1338 { 1339 //!< DWORD 13 1340 struct 1341 { 1342 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeLCUThreshold 1343 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1344 }; 1345 uint32_t Value; 1346 } DW13; 1347 union 1348 { 1349 //!< DWORD 14 1350 struct 1351 { 1352 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Force QP Value 16x16_0 1353 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD( 8, 15) ; //!< Force QP Value 16x16_1 1354 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23) ; //!< Force QP Value 16x16_2 1355 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31) ; //!< Force QP Value 16x16_3 1356 }; 1357 uint32_t Value; 1358 } DW14; 1359 union 1360 { 1361 //!< DWORD 15 1362 struct 1363 { 1364 uint32_t Reserved480 ; //!< Reserved 1365 }; 1366 uint32_t Value; 1367 } DW15; 1368 1369 //! \name Local enumerations 1370 1371 //! \brief NUMIMEPREDICTORS 1372 //! \details 1373 //! <p>This parameter specifes the number of IME predictors to be processed 1374 //! in stage3 IME.</p> 1375 //! <p></p> 1376 enum NUMIMEPREDICTORS 1377 { 1378 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 1379 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 1380 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 1381 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 1382 }; 1383 1384 //! \name Initializations 1385 1386 //! \brief Explicit member initialization function 1387 VDENC_HEVC_VP9_STREAMIN_STATE_CMD(); 1388 1389 static const size_t dwSize = 16; 1390 static const size_t byteSize = 64; 1391 }; 1392 1393 //! 1394 //! \brief VDENC_Surface_State_Fields 1395 //! \details 1396 //! 1397 //! 1398 struct VDENC_Surface_State_Fields_CMD 1399 { 1400 union 1401 { 1402 //!< DWORD 0 1403 struct 1404 { 1405 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 1406 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD( 2, 2) ; //!< Surface Format Byte Swizzle 1407 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD( 3, 3) ; //!< Color space selection 1408 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1409 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1410 }; 1411 uint32_t Value; 1412 } DW0; 1413 union 1414 { 1415 //!< DWORD 1 1416 struct 1417 { 1418 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 1419 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 1420 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< HALF_PITCH_FOR_CHROMA 1421 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 1422 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22) ; //!< Chroma Downsample Filter Control 1423 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 1424 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1425 }; 1426 uint32_t Value; 1427 } DW1; 1428 union 1429 { 1430 //!< DWORD 2 1431 struct 1432 { 1433 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 1434 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1435 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 1436 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1437 }; 1438 uint32_t Value; 1439 } DW2; 1440 union 1441 { 1442 //!< DWORD 3 1443 struct 1444 { 1445 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 1446 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 1447 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1448 }; 1449 uint32_t Value; 1450 } DW3; 1451 1452 //! \name Local enumerations 1453 1454 //! \brief TILE_WALK 1455 //! \details 1456 //! (This field must be set to 1: TILEWALK_YMAJOR.) This field specifies the 1457 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 1458 //! See Memory Interface Functions for details on memory tiling and restrictions. 1459 //! This field is ignored when the surface is linear. Internally H/W always 1460 //! treats this as set to 1 for all VDEnc usage. 1461 enum TILE_WALK 1462 { 1463 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 1464 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 1465 }; 1466 1467 //! \brief TILED_SURFACE 1468 //! \details 1469 //! (This field must be set to TRUE: Tiled.) This field specifies whether 1470 //! the surface is tiled. This field is ignored by VDEnc usage. 1471 enum TILED_SURFACE 1472 { 1473 TILED_SURFACE_FALSE = 0, //!< Linear 1474 TILED_SURFACE_TRUE = 1, //!< Tiled 1475 }; 1476 1477 //! \brief HALF_PITCH_FOR_CHROMA 1478 //! \details 1479 //! (This field must be set to Disable.) This field indicates that the 1480 //! chroma plane(s) will use a pitch equal to half the value specified 1481 //! in the Surface Pitch field. This field is only used for PLANAR 1482 //! surface formats. This field is igored by VDEnc (unless we support YV12). 1483 enum HALF_PITCH_FOR_CHROMA 1484 { 1485 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 1486 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 1487 }; 1488 1489 //! \brief SURFACE_FORMAT 1490 //! \details 1491 //! Specifies the format of the surface. 1492 enum SURFACE_FORMAT 1493 { 1494 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 1495 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 1496 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 1497 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 1498 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1499 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 1500 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 1501 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 1502 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 1503 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 1504 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 1505 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 1506 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 1507 }; 1508 1509 //! \name Initializations 1510 1511 //! \brief Explicit member initialization function 1512 VDENC_Surface_State_Fields_CMD(); 1513 1514 static const size_t dwSize = 4; 1515 static const size_t byteSize = 16; 1516 }; 1517 1518 //! 1519 //! \brief VD_PIPELINE_FLUSH 1520 //! \details 1521 //! 1522 //! 1523 struct VD_PIPELINE_FLUSH_CMD 1524 { 1525 union 1526 { 1527 //!< DWORD 0 1528 struct 1529 { 1530 uint32_t DwordCountN : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_COUNT_N 1531 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1532 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1533 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1534 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1535 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1536 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1537 }; 1538 uint32_t Value; 1539 } DW0; 1540 union 1541 { 1542 //!< DWORD 1 1543 struct 1544 { 1545 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD( 0, 0) ; //!< HEVC pipeline Done 1546 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD( 1, 1) ; //!< VD-ENC pipeline Done 1547 uint32_t MflPipelineDone : __CODEGEN_BITFIELD( 2, 2) ; //!< MFL pipeline Done 1548 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD( 3, 3) ; //!< MFX pipeline Done 1549 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD( 4, 4) ; //!< VD command/message parser Done 1550 uint32_t AvpPipelineDone : __CODEGEN_BITFIELD( 5, 5) ; //!< AVP Pipeline Done 1551 uint32_t Reserved37 : __CODEGEN_BITFIELD( 6, 15) ; //!< Reserved 1552 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16) ; //!< HEVC pipeline command flush 1553 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17) ; //!< VD-ENC pipeline command flush 1554 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18) ; //!< MFL pipeline command flush 1555 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19) ; //!< MFX pipeline command flush 1556 uint32_t AvpPipelineCommandFlush : __CODEGEN_BITFIELD(20, 20) ; //!< AVP Pipeline Command Flush 1557 uint32_t Reserved52 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 1558 }; 1559 uint32_t Value; 1560 } DW1; 1561 1562 //! \name Local enumerations 1563 1564 //! \brief DWORD_COUNT_N 1565 //! \details 1566 //! Total Length - 2 1567 enum DWORD_COUNT_N 1568 { 1569 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 1570 }; 1571 1572 enum SUBOPCODEB 1573 { 1574 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 1575 }; 1576 1577 enum SUBOPCODEA 1578 { 1579 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 1580 }; 1581 1582 enum MEDIA_COMMAND_OPCODE 1583 { 1584 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 1585 }; 1586 1587 enum PIPELINE 1588 { 1589 PIPELINE_MEDIA = 2, //!< No additional details 1590 }; 1591 1592 enum COMMAND_TYPE 1593 { 1594 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1595 }; 1596 1597 //! \name Initializations 1598 1599 //! \brief Explicit member initialization function 1600 VD_PIPELINE_FLUSH_CMD(); 1601 1602 static const size_t dwSize = 2; 1603 static const size_t byteSize = 8; 1604 }; 1605 1606 //! 1607 //! \brief VDENC_WEIGHTSOFFSETS_STATE 1608 //! \details 1609 //! 1610 //! 1611 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 1612 { 1613 union 1614 { 1615 //!< DWORD 0 1616 struct 1617 { 1618 uint32_t DwLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DW_LENGTH 1619 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1620 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1621 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1622 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1623 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1624 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1625 }; 1626 uint32_t Value; 1627 } DW0; 1628 union 1629 { 1630 //!< DWORD 1 1631 struct 1632 { 1633 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference0 1634 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference0 1635 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< Weights Forward Reference1 1636 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< Offset Forward Reference1 1637 }; 1638 uint32_t Value; 1639 } DW1; 1640 union 1641 { 1642 //!< DWORD 2 1643 struct 1644 { 1645 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference2 1646 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference2 1647 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1648 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1649 }; 1650 uint32_t Value; 1651 } DW2; 1652 1653 //! \name Local enumerations 1654 1655 //! \brief DW_LENGTH 1656 //! \details 1657 //! Total Length - 2 1658 enum DW_LENGTH 1659 { 1660 DW_LENGTH_DWORDCOUNTN = 1, //!< Excludes DWord (0,1) 1661 }; 1662 1663 enum SUBOPB 1664 { 1665 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 1666 }; 1667 1668 enum SUBOPA 1669 { 1670 SUBOPA_UNNAMED0 = 0, //!< No additional details 1671 }; 1672 1673 enum OPCODE 1674 { 1675 OPCODE_VDENCPIPE = 1, //!< No additional details 1676 }; 1677 1678 enum PIPELINE 1679 { 1680 PIPELINE_MFXCOMMON = 2, //!< No additional details 1681 }; 1682 1683 enum COMMAND_TYPE 1684 { 1685 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1686 }; 1687 1688 //! \name Initializations 1689 1690 //! \brief Explicit member initialization function 1691 VDENC_WEIGHTSOFFSETS_STATE_CMD(); 1692 1693 static const size_t dwSize = 3; 1694 static const size_t byteSize = 12; 1695 }; 1696 1697 //! 1698 //! \brief VDENC_CONST_QPT_STATE 1699 //! \details 1700 //! This commands provides the tables for frame constants to the VDEnc HW. 1701 //! The specific parameter value is picked by the VDEnc HW based on the 1702 //! frame level QP. The QP Lambda array for costing (motion-vectors and mode 1703 //! costs) has 42 entires. Skip Threshold tables has 27 entries. 7 FTQ 1704 //! thresholds [0-6] are programmed using 4 sets of tables with 27 entires 1705 //! each. 1706 //! 1707 struct VDENC_CONST_QPT_STATE_CMD 1708 { 1709 union 1710 { 1711 //!< DWORD 0 1712 struct 1713 { 1714 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1715 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1716 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1717 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1718 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1719 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1720 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1721 }; 1722 uint32_t Value; 1723 } DW0; 1724 union { 1725 //!< DWORD 1..10 1726 struct { 1727 uint8_t QpLambdaArrayIndex[40]; //!< QP Lambda Array Index[n] 1728 }; 1729 uint32_t Value[10]; 1730 } DW1_10; 1731 union { 1732 //!< DWORD 11 1733 struct { 1734 uint32_t QpLambdaArrayIndex40 : __CODEGEN_BITFIELD(0, 7); 1735 uint32_t QpLambdaArrayIndex41 : __CODEGEN_BITFIELD(8, 15); 1736 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1737 }; 1738 uint32_t Value; 1739 } DW11; 1740 union { 1741 //!< DWORD 12..24 1742 struct { 1743 uint16_t SkipThresholdArrayIndex[26]; //!< Skip Threshold Array Index[n] 1744 }; 1745 uint32_t Value[13]; 1746 } DW12_24; 1747 union { 1748 //!< DWORD 25 1749 struct { 1750 uint32_t SkipThresholdArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1751 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1752 }; 1753 uint32_t Value; 1754 } DW25; 1755 union { 1756 //!< DWORD 26..38 1757 struct { 1758 uint16_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex[26]; //!< SIC Forward Transform Coeff Threshold Matrix0 Array Index[n] 1759 }; 1760 uint32_t Value[13]; 1761 } DW26_38; 1762 union { 1763 //!< DWORD 39 1764 struct { 1765 uint32_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1766 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1767 }; 1768 uint32_t Value; 1769 } DW39; 1770 union { 1771 //!< DWORD 40..45 1772 struct { 1773 uint8_t SicForwardTransformCoeffThresholdMatrix135ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix1/3/5 Array Index[n] 1774 }; 1775 uint32_t Value[6]; 1776 } DW40_45; 1777 union { 1778 //!< DWORD 46 1779 struct { 1780 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1781 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1782 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1783 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1784 }; 1785 uint32_t Value; 1786 } DW46; 1787 union { 1788 //!< DWORD 47..52 1789 struct { 1790 uint8_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex[24]; //!< SIC Forward Transform Coeff Threshold Matrix2 Array Index[n] 1791 }; 1792 uint32_t Value[6]; 1793 } DW47_52; 1794 union { 1795 //!< DWORD 53 1796 struct { 1797 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1798 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1799 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1800 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1801 }; 1802 uint32_t Value; 1803 } DW53; 1804 union { 1805 //!< DWORD 54..59 1806 struct { 1807 uint8_t SicForwardTransformCoeffThresholdMatrix46ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix4/6 Array Index[n] 1808 }; 1809 uint32_t Value[6]; 1810 } DW54_59; 1811 union { 1812 //!< DWORD 60 1813 struct { 1814 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1815 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1816 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1817 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1818 }; 1819 uint32_t Value; 1820 } DW60; 1821 1822 //! \name Local enumerations 1823 1824 enum SUBOPB 1825 { 1826 SUBOPB_VDENCCONSTQPTSTATE = 6, //!< No additional details 1827 }; 1828 1829 enum SUBOPA 1830 { 1831 SUBOPA_UNNAMED0 = 0, //!< No additional details 1832 }; 1833 1834 enum OPCODE 1835 { 1836 OPCODE_VDENCPIPE = 1, //!< No additional details 1837 }; 1838 1839 enum PIPELINE 1840 { 1841 PIPELINE_MFXCOMMON = 2, //!< No additional details 1842 }; 1843 1844 enum COMMAND_TYPE 1845 { 1846 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1847 }; 1848 1849 //! \name Initializations 1850 1851 //! \brief Explicit member initialization function 1852 VDENC_CONST_QPT_STATE_CMD(); 1853 1854 static const size_t dwSize = 61; 1855 static const size_t byteSize = 244; 1856 }; 1857 1858 //! 1859 //! \brief VDENC_DS_REF_SURFACE_STATE 1860 //! \details 1861 //! This command specifies the surface state parameters for the downscaled 1862 //! reference surfaces. 1863 //! 1864 struct VDENC_DS_REF_SURFACE_STATE_CMD 1865 { 1866 union 1867 { 1868 //!< DWORD 0 1869 struct 1870 { 1871 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1872 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1873 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1874 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1875 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1876 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1877 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1878 }; 1879 uint32_t Value; 1880 } DW0; 1881 union 1882 { 1883 //!< DWORD 1 1884 struct 1885 { 1886 uint32_t Reserved32 ; //!< Reserved 1887 }; 1888 uint32_t Value; 1889 } DW1; 1890 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 1891 VDENC_Surface_State_Fields_CMD Dwords69 ; //!< Dwords 6..9 1892 1893 //! \name Local enumerations 1894 1895 enum SUBOPB 1896 { 1897 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 1898 }; 1899 1900 enum SUBOPA 1901 { 1902 SUBOPA_UNNAMED0 = 0, //!< No additional details 1903 }; 1904 1905 enum OPCODE 1906 { 1907 OPCODE_VDENCPIPE = 1, //!< No additional details 1908 }; 1909 1910 enum PIPELINE 1911 { 1912 PIPELINE_MFXCOMMON = 2, //!< No additional details 1913 }; 1914 1915 enum COMMAND_TYPE 1916 { 1917 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1918 }; 1919 1920 //! \name Initializations 1921 1922 //! \brief Explicit member initialization function 1923 VDENC_DS_REF_SURFACE_STATE_CMD(); 1924 1925 static const size_t dwSize = 10; 1926 static const size_t byteSize = 40; 1927 }; 1928 1929 //! 1930 //! \brief VDENC_IMG_STATE 1931 //! \details 1932 //! This command programs the frame level parameters required by the VDEnc 1933 //! pipeline. 1934 //! 1935 struct VDENC_IMG_STATE_CMD 1936 { 1937 union 1938 { 1939 //!< DWORD 0 1940 struct 1941 { 1942 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1943 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1944 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1945 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1946 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1947 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1948 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1949 }; 1950 uint32_t Value; 1951 } DW0; 1952 union 1953 { 1954 //!< DWORD 1 1955 struct 1956 { 1957 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1958 uint32_t BidirectionalMixDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< BIDIRECTIONAL_MIX_DISABLE 1959 uint32_t VdencPerfmode : __CODEGEN_BITFIELD( 3, 3) ; //!< VDENC_PERFMODE 1960 uint32_t TimeBudgetOverflowCheck : __CODEGEN_BITFIELD( 4, 4) ; //!< TIME_BUDGET_OVERFLOW_CHECK 1961 uint32_t VdencUltraMode : __CODEGEN_BITFIELD( 5, 5) ; //!< VDEnc_UltraMode 1962 uint32_t VdencExtendedPakObjCmdEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1963 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 7, 7) ; //!< TRANSFORM_8X8_FLAG 1964 uint32_t VdencL1CachePriority : __CODEGEN_BITFIELD( 8, 9) ; //!< VDENC_L1_CACHE_PRIORITY 1965 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1966 uint32_t LambdaValueForTrellis : __CODEGEN_BITFIELD(16, 31) ; //!< Lambda value for Trellis 1967 }; 1968 uint32_t Value; 1969 } DW1; 1970 union 1971 { 1972 //!< DWORD 2 1973 struct 1974 { 1975 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1976 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(16, 21) ; //!< BIDIRECTIONAL_WEIGHT 1977 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 27) ; //!< Reserved 1978 uint32_t UnidirectionalMixDisable : __CODEGEN_BITFIELD(28, 28) ; //!< Unidirectional Mix Disable 1979 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1980 }; 1981 uint32_t Value; 1982 } DW2; 1983 union 1984 { 1985 //!< DWORD 3 1986 struct 1987 { 1988 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1989 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31) ; //!< Picture Width 1990 }; 1991 uint32_t Value; 1992 } DW3; 1993 union 1994 { 1995 //!< DWORD 4 1996 struct 1997 { 1998 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1999 uint32_t SubPelMode : __CODEGEN_BITFIELD(12, 13) ; //!< SUB_PEL_MODE 2000 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 16) ; //!< Reserved 2001 uint32_t ForwardTransformSkipCheckEnable : __CODEGEN_BITFIELD(17, 17) ; //!< FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2002 uint32_t BmeDisableForFbrMessage : __CODEGEN_BITFIELD(18, 18) ; //!< BME_DISABLE_FOR_FBR_MESSAGE 2003 uint32_t BlockBasedSkipEnabled : __CODEGEN_BITFIELD(19, 19) ; //!< BLOCK_BASED_SKIP_ENABLED 2004 uint32_t InterSadMeasureAdjustment : __CODEGEN_BITFIELD(20, 21) ; //!< INTER_SAD_MEASURE_ADJUSTMENT 2005 uint32_t IntraSadMeasureAdjustment : __CODEGEN_BITFIELD(22, 23) ; //!< INTRA_SAD_MEASURE_ADJUSTMENT 2006 uint32_t SubMacroblockSubPartitionMask : __CODEGEN_BITFIELD(24, 30) ; //!< SUB_MACROBLOCK_SUB_PARTITION_MASK 2007 uint32_t BlockBasedSkipType : __CODEGEN_BITFIELD(31, 31) ; //!< BLOCK_BASED_SKIP_TYPE 2008 }; 2009 uint32_t Value; 2010 } DW4; 2011 union 2012 { 2013 //!< DWORD 5 2014 struct 2015 { 2016 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Picture Height Minus One 2017 uint32_t CrePrefetchEnable : __CODEGEN_BITFIELD(16, 16) ; //!< CRE_PREFETCH_ENABLE 2018 uint32_t HmeRef1Disable : __CODEGEN_BITFIELD(17, 17) ; //!< HME_REF1_DISABLE 2019 uint32_t MbSliceThresholdValue : __CODEGEN_BITFIELD(18, 21) ; //!< MB Slice Threshold Value 2020 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 2021 uint32_t ConstrainedIntraPredictionFlag : __CODEGEN_BITFIELD(26, 26) ; //!< CONSTRAINED_INTRA_PREDICTION_FLAG 2022 uint32_t Reserved187 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 2023 uint32_t PictureType : __CODEGEN_BITFIELD(29, 30) ; //!< PICTURE_TYPE 2024 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2025 }; 2026 uint32_t Value; 2027 } DW5; 2028 union 2029 { 2030 //!< DWORD 6 2031 struct 2032 { 2033 uint32_t SliceMacroblockHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Macroblock Height Minus One 2034 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2035 }; 2036 uint32_t Value; 2037 } DW6; 2038 union 2039 { 2040 //!< DWORD 7 2041 struct 2042 { 2043 uint32_t Hme0XOffset : __CODEGEN_BITFIELD( 0, 7) ; //!< HME0 X Offset 2044 uint32_t Hme0YOffset : __CODEGEN_BITFIELD( 8, 15) ; //!< HME0 Y Offset 2045 uint32_t Hme1XOffset : __CODEGEN_BITFIELD(16, 23) ; //!< HME1 X Offset 2046 uint32_t Hme1YOffset : __CODEGEN_BITFIELD(24, 31) ; //!< HME1 Y Offset 2047 }; 2048 uint32_t Value; 2049 } DW7; 2050 union 2051 { 2052 //!< DWORD 8 2053 struct 2054 { 2055 uint32_t LumaIntraPartitionMask : __CODEGEN_BITFIELD( 0, 4) ; //!< LUMA_INTRA_PARTITION_MASK 2056 uint32_t NonSkipZeroMvCostAdded : __CODEGEN_BITFIELD( 5, 5) ; //!< Non Skip Zero MV Cost Added 2057 uint32_t NonSkipMbModeCostAdded : __CODEGEN_BITFIELD( 6, 6) ; //!< Non Skip MB Mode Cost Added 2058 uint32_t Reserved263 : __CODEGEN_BITFIELD( 7, 15) ; //!< Reserved 2059 uint32_t MvCostScalingFactor : __CODEGEN_BITFIELD(16, 17) ; //!< MV_COST_SCALING_FACTOR 2060 uint32_t BilinearFilterEnable : __CODEGEN_BITFIELD(18, 18) ; //!< BiLinear Filter Enable 2061 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 21) ; //!< Reserved 2062 uint32_t RefidCostModeSelect : __CODEGEN_BITFIELD(22, 22) ; //!< REFID_COST_MODE_SELECT 2063 uint32_t Reserved279 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2064 }; 2065 uint32_t Value; 2066 } DW8; 2067 union 2068 { 2069 //!< DWORD 9 2070 struct 2071 { 2072 uint32_t Mode0Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 0 Cost 2073 uint32_t Mode1Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 1 Cost 2074 uint32_t Mode2Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 2 Cost 2075 uint32_t Mode3Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 3 Cost 2076 }; 2077 uint32_t Value; 2078 } DW9; 2079 union 2080 { 2081 //!< DWORD 10 2082 struct 2083 { 2084 uint32_t Mode4Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 4 Cost 2085 uint32_t Mode5Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 5 Cost 2086 uint32_t Mode6Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 6 Cost 2087 uint32_t Mode7Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 7 Cost 2088 }; 2089 uint32_t Value; 2090 } DW10; 2091 union 2092 { 2093 //!< DWORD 11 2094 struct 2095 { 2096 uint32_t Mode8Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 8 Cost 2097 uint32_t Mode9Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 9 Cost 2098 uint32_t RefIdCost : __CODEGEN_BITFIELD(16, 23) ; //!< RefID Cost 2099 uint32_t ChromaIntraModeCost : __CODEGEN_BITFIELD(24, 31) ; //!< Chroma Intra Mode Cost 2100 }; 2101 uint32_t Value; 2102 } DW11; 2103 union 2104 { 2105 //!< DWORD 12 2106 struct 2107 { 2108 uint32_t MvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 0 2109 uint32_t MvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 1 2110 uint32_t MvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 2 2111 uint32_t MvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 3 2112 }; 2113 uint32_t Value; 2114 } DW12; 2115 union 2116 { 2117 //!< DWORD 13 2118 struct 2119 { 2120 uint32_t MvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 4 2121 uint32_t MvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 5 2122 uint32_t MvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 6 2123 uint32_t MvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 7 2124 }; 2125 uint32_t Value; 2126 } DW13; 2127 union 2128 { 2129 //!< DWORD 14 2130 struct 2131 { 2132 uint32_t QpPrimeY : __CODEGEN_BITFIELD( 0, 7) ; //!< QpPrimeY 2133 uint32_t Reserved456 : __CODEGEN_BITFIELD( 8, 23) ; //!< Reserved 2134 uint32_t TargetSizeInWord : __CODEGEN_BITFIELD(24, 31) ; //!< TargetSizeInWord 2135 }; 2136 uint32_t Value; 2137 } DW14; 2138 union 2139 { 2140 //!< DWORD 15 2141 struct 2142 { 2143 uint32_t Reserved480 ; //!< Reserved 2144 }; 2145 uint32_t Value; 2146 } DW15; 2147 union 2148 { 2149 //!< DWORD 16 2150 struct 2151 { 2152 uint32_t Reserved512 ; //!< Reserved 2153 }; 2154 uint32_t Value; 2155 } DW16; 2156 union 2157 { 2158 //!< DWORD 17 2159 struct 2160 { 2161 uint32_t AvcIntra4X4ModeMask : __CODEGEN_BITFIELD( 0, 8) ; //!< AVC Intra 4x4 Mode Mask 2162 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2163 uint32_t AvcIntra8X8ModeMask : __CODEGEN_BITFIELD(16, 24) ; //!< AVC Intra 8x8 Mode Mask 2164 uint32_t Reserved569 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2165 }; 2166 uint32_t Value; 2167 } DW17; 2168 union 2169 { 2170 //!< DWORD 18 2171 struct 2172 { 2173 uint32_t AvcIntra16X16ModeMask : __CODEGEN_BITFIELD( 0, 3) ; //!< AVC_INTRA_16X16_MODE_MASK 2174 uint32_t AvcIntraChromaModeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AVC_INTRA_CHROMA_MODE_MASK 2175 uint32_t IntraComputeTypeIntracomputetype : __CODEGEN_BITFIELD( 8, 9) ; //!< INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2176 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2177 }; 2178 uint32_t Value; 2179 } DW18; 2180 union 2181 { 2182 //!< DWORD 19 2183 struct 2184 { 2185 uint32_t Reserved608 ; //!< Reserved 2186 }; 2187 uint32_t Value; 2188 } DW19; 2189 union 2190 { 2191 //!< DWORD 20 2192 struct 2193 { 2194 uint32_t PenaltyForIntra16X16NondcPrediction : __CODEGEN_BITFIELD( 0, 7) ; //!< Penalty for Intra16x16 NonDC Prediction. 2195 uint32_t PenaltyForIntra8X8NondcPrediction : __CODEGEN_BITFIELD( 8, 15) ; //!< Penalty for Intra8x8 NonDC Prediction. 2196 uint32_t PenaltyForIntra4X4NondcPrediction : __CODEGEN_BITFIELD(16, 23) ; //!< Penalty for Intra4x4 NonDC Prediction. 2197 uint32_t Reserved664 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2198 }; 2199 uint32_t Value; 2200 } DW20; 2201 union 2202 { 2203 //!< DWORD 21 2204 struct 2205 { 2206 uint32_t IntraRefreshMBPos : __CODEGEN_BITFIELD( 0, 7) ; //!< IntraRefreshMBPos 2207 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD( 8, 15) ; //!< IntraRefreshMBSizeMinusOne 2208 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16) ; //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 2209 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17) ; //!< INTRAREFRESHMODE 2210 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 23) ; //!< Reserved 2211 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31) ; //!< QP adjustment for Rolling-I 2212 }; 2213 uint32_t Value; 2214 } DW21; 2215 union 2216 { 2217 //!< DWORD 22 2218 struct 2219 { 2220 uint32_t Panicmodembthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeMBThreshold 2221 uint32_t Smallmbsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< SmallMbSizeInWord 2222 uint32_t Largembsizeinword : __CODEGEN_BITFIELD(24, 31) ; //!< LargeMbSizeInWord 2223 }; 2224 uint32_t Value; 2225 } DW22; 2226 union 2227 { 2228 //!< DWORD 23 2229 struct 2230 { 2231 uint32_t L0NumberOfReferencesMinusOne : __CODEGEN_BITFIELD( 0, 7) ; //!< L0 number of references Minus one 2232 uint32_t Reserved744 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2233 uint32_t L1NumberOfReferencesMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< L1 number of references Minus One 2234 uint32_t Reserved760 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2235 }; 2236 uint32_t Value; 2237 } DW23; 2238 union 2239 { 2240 //!< DWORD 24 2241 struct 2242 { 2243 uint32_t MacroblockBudget : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Budget 2244 uint32_t InitialTime : __CODEGEN_BITFIELD(16, 31) ; //!< Initial Time 2245 }; 2246 uint32_t Value; 2247 } DW24; 2248 union 2249 { 2250 //!< DWORD 25 2251 struct 2252 { 2253 uint32_t Reserved800 ; //!< Reserved 2254 }; 2255 uint32_t Value; 2256 } DW25; 2257 union 2258 { 2259 //!< DWORD 26 2260 struct 2261 { 2262 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 2263 uint32_t HmeRefWindowsCombiningThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< HME_REF_WINDOWS_COMBINING_THRESHOLD 2264 uint32_t Reserved848 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2265 }; 2266 uint32_t Value; 2267 } DW26; 2268 union 2269 { 2270 //!< DWORD 27 2271 struct 2272 { 2273 uint32_t MaxHmvR : __CODEGEN_BITFIELD( 0, 15) ; //!< MAXHMVR 2274 uint32_t MaxVmvR : __CODEGEN_BITFIELD(16, 31) ; //!< MAXVMVR 2275 }; 2276 uint32_t Value; 2277 } DW27; 2278 union 2279 { 2280 //!< DWORD 28 2281 struct 2282 { 2283 uint32_t HmeMvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 0 2284 uint32_t HmeMvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 1 2285 uint32_t HmeMvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 2 2286 uint32_t HmeMvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 3 2287 }; 2288 uint32_t Value; 2289 } DW28; 2290 union 2291 { 2292 //!< DWORD 29 2293 struct 2294 { 2295 uint32_t HmeMvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 4 2296 uint32_t HmeMvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 5 2297 uint32_t HmeMvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 6 2298 uint32_t HmeMvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 7 2299 }; 2300 uint32_t Value; 2301 } DW29; 2302 union 2303 { 2304 //!< DWORD 30 2305 struct 2306 { 2307 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< ROI QP adjustment for Zone0 2308 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 2309 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 2310 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 2311 uint32_t QpAdjustmentForShapeBestIntra4X4Winner : __CODEGEN_BITFIELD(16, 19) ; //!< QP adjustment for shape best intra 4x4 winner 2312 uint32_t QpAdjustmentForShapeBestIntra8X8Winner : __CODEGEN_BITFIELD(20, 23) ; //!< QP adjustment for shape best intra 8x8 winner 2313 uint32_t QpAdjustmentForShapeBestIntra16X16Winner : __CODEGEN_BITFIELD(24, 27) ; //!< QP adjustment for shape best intra 16x16 winner 2314 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2315 }; 2316 uint32_t Value; 2317 } DW30; 2318 union 2319 { 2320 //!< DWORD 31 2321 struct 2322 { 2323 uint32_t BestdistortionQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< BestDistortion QP adjustment for Zone0 2324 uint32_t BestdistortionQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< BestDistortion QP adjustment for Zone1 2325 uint32_t BestdistortionQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< BestDistortion QP adjustment for Zone2 2326 uint32_t BestdistortionQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< BestDistortion QP adjustment for Zone3 2327 uint32_t SadHaarThreshold0 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_0 2328 }; 2329 uint32_t Value; 2330 } DW31; 2331 union 2332 { 2333 //!< DWORD 32 2334 struct 2335 { 2336 uint32_t SadHaarThreshold1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Sad/Haar_Threshold_1 2337 uint32_t SadHaarThreshold2 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_2 2338 }; 2339 uint32_t Value; 2340 } DW32; 2341 union 2342 { 2343 //!< DWORD 33 2344 struct 2345 { 2346 uint32_t MaxQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MaxQP 2347 uint32_t MinQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MinQP 2348 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2349 uint32_t Maxdeltaqp : __CODEGEN_BITFIELD(24, 27) ; //!< MaxDeltaQP 2350 uint32_t Reserved1084 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2351 }; 2352 uint32_t Value; 2353 } DW33; 2354 union 2355 { 2356 //!< DWORD 34 2357 struct 2358 { 2359 uint32_t RoiEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ROI_Enable 2360 uint32_t FwdPredictor0MvEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Fwd/Predictor0 MV Enable 2361 uint32_t BwdPredictor1MvEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Bwd/Predictor1 MV Enable 2362 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< MB Level QP Enable 2363 uint32_t TargetsizeinwordsmbMaxsizeinwordsmbEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< TargetSizeinWordsMB/MaxSizeinWordsMB Enable 2364 uint32_t Reserverd : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserverd 2365 uint32_t PpmvDisable : __CODEGEN_BITFIELD( 8, 8) ; //!< PPMV_DISABLE 2366 uint32_t CoefficientClampEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Coefficient Clamp Enable 2367 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10) ; //!< LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2368 uint32_t LongtermReferenceFrameFwdRef2Indicator : __CODEGEN_BITFIELD(11, 11) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2369 uint32_t LongtermReferenceFrameFwdRef1Indicator : __CODEGEN_BITFIELD(12, 12) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2370 uint32_t LongtermReferenceFrameFwdRef0Indicator : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2371 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2372 uint32_t MidpointSadHaar : __CODEGEN_BITFIELD(16, 31) ; //!< Midpoint sad/haar 2373 }; 2374 uint32_t Value; 2375 } DW34; 2376 2377 //! \name Local enumerations 2378 2379 enum SUBOPB 2380 { 2381 SUBOPB_VDENCIMGSTATE = 5, //!< No additional details 2382 }; 2383 2384 enum SUBOPA 2385 { 2386 SUBOPA_UNNAMED0 = 0, //!< No additional details 2387 }; 2388 2389 enum OPCODE 2390 { 2391 OPCODE_VDENCPIPE = 1, //!< No additional details 2392 }; 2393 2394 enum PIPELINE 2395 { 2396 PIPELINE_MFXCOMMON = 2, //!< No additional details 2397 }; 2398 2399 enum COMMAND_TYPE 2400 { 2401 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2402 }; 2403 2404 enum BIDIRECTIONAL_MIX_DISABLE 2405 { 2406 BIDIRECTIONAL_MIX_DISABLE_SUBBLOCKENABLED = 0, //!< Bidirectional decision on subblock level that bidirectional mode is enabled. 2407 BIDIRECTIONAL_MIX_DISABLE_WHOLEMACROBLOCKENABLED = 1, //!< Bidirectional decision on whole macroblock. 2408 }; 2409 2410 //! \brief VDENC_PERFMODE 2411 //! \details 2412 //! This bit indicates if VDEnc is configured for normal or speed mode of 2413 //! operation. 2414 enum VDENC_PERFMODE 2415 { 2416 VDENC_PERFMODE_NORMAL = 0, //!< VDEnc is running in normal mode. IME Search: 3x3 SU per each reference. HME Search: 88x92 search window per HME instance (0 & 1). 2417 VDENC_PERFMODE_SPEED = 1, //!< VDEnc is configured for speed mode. IME Search: 2x2 SU per each reference. HME Search: 48x92 search window per HME instance (0 & 1). 2418 }; 2419 2420 //! \brief TIME_BUDGET_OVERFLOW_CHECK 2421 //! \details 2422 //! <p>This bit enables the frame time budget detection in VDEnc.</p> 2423 //! <p>To detect if a Time Budget Overflow happened in a frame, SW 2424 //! can read "PAK_Stream-Out Report (Errors)" register in MFX. When Time 2425 //! budget overflow condition happens in the frame, this register bits 15:8 2426 //! indicate MB y position and bits 7:0 indicate MB x position where Time 2427 //! budget overflow occured. When there is no time budget overflow in a 2428 //! frame, "<span style="line-height: 20.7999992370605px;">PAK_Stream-Out 2429 //! Report (Errors)" register reads zero.</span></p> 2430 enum TIME_BUDGET_OVERFLOW_CHECK 2431 { 2432 TIME_BUDGET_OVERFLOW_CHECK_DISABLED = 0, //!< No additional details 2433 TIME_BUDGET_OVERFLOW_CHECK_ENABLED = 1, //!< No additional details 2434 }; 2435 2436 //! \brief VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2437 //! \details 2438 //! This bit enables the distortion data to be populated in the VDenc PAK 2439 //! Obj inline data. 2440 enum VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2441 { 2442 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_DISABLE = 0, //!< The extra two DWS from VDEnc (MDC) to PAK will be Zero. 2443 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_ENABLE = 1, //!< The last two DWs from VDEnc (MDC) to PAK will be populated with distortion data. (Defined in the PAK Object command DW 22,23.) 2444 }; 2445 2446 //! \brief TRANSFORM_8X8_FLAG 2447 //! \details 2448 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flag specifies 8x8 IDCT 2449 //! transform may be used in this picture. It is set to the value of the 2450 //! syntax element in the current active PPS. 2451 enum TRANSFORM_8X8_FLAG 2452 { 2453 TRANSFORM_8X8_FLAG_DISABLED = 0, //!< No 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present. 2454 TRANSFORM_8X8_FLAG_ENABLED = 1, //!< 8x8 Transform is allowed. 2455 }; 2456 2457 //! \brief VDENC_L1_CACHE_PRIORITY 2458 //! \details 2459 //! L1 Cache inside VDEnc has 3 clients - IME, CRE and VMC. 2460 //! These bits indicate the priority order for L1 cache to 2461 //! service the client requests. 2462 enum VDENC_L1_CACHE_PRIORITY 2463 { 2464 VDENC_L1_CACHE_PRIORITY_UNNAMED0 = 0, //!< CRE High Priority, VMC and IME round robin. 2465 VDENC_L1_CACHE_PRIORITY_UNNAMED1 = 1, //!< CRE and VMC round robin, IME low priority. 2466 VDENC_L1_CACHE_PRIORITY_UNNAMED2 = 2, //!< CRE High Priority, IME Medium, VMC Low. 2467 VDENC_L1_CACHE_PRIORITY_UNNAMED3 = 3, //!< VMC High Priority, CRE Medium, IME low. 2468 }; 2469 2470 //! \brief BIDIRECTIONAL_WEIGHT 2471 //! \details 2472 //! Default value: Depends on the distance between the B and reference 2473 //! pictures. 2474 enum BIDIRECTIONAL_WEIGHT 2475 { 2476 BIDIRECTIONAL_WEIGHT_UNNAMED16 = 16, //!< No additional details 2477 BIDIRECTIONAL_WEIGHT_UNNAMED21 = 21, //!< No additional details 2478 BIDIRECTIONAL_WEIGHT_UNNAMED32 = 32, //!< No additional details 2479 BIDIRECTIONAL_WEIGHT_UNNAMED43 = 43, //!< No additional details 2480 BIDIRECTIONAL_WEIGHT_UNNAMED48 = 48, //!< No additional details 2481 }; 2482 2483 //! \brief SUB_PEL_MODE 2484 //! \details 2485 //! This field defines the half/quarter pel modes. The mode is inclusive, 2486 //! i.e., higher precision mode samples lower precision locations. 2487 enum SUB_PEL_MODE 2488 { 2489 SUB_PEL_MODE_UNNAMED0 = 0, //!< Integer mode searching. 2490 SUB_PEL_MODE_UNNAMED1 = 1, //!< Half-pel mode searching. 2491 SUB_PEL_MODE_UNNAMED3 = 3, //!< Quarter-pel mode searching. 2492 }; 2493 2494 //! \brief FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2495 //! \details 2496 //! This field enables the forward transform calculation for skip check. 2497 //! It does not override the other skip calculations but it does decrease 2498 //! the performance marginally so don't enable it unless the transform 2499 //! is necessary. 2500 enum FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2501 { 2502 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTDISABLED = 0, //!< No additional details 2503 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTENABLED = 1, //!< No additional details 2504 }; 2505 2506 //! \brief BME_DISABLE_FOR_FBR_MESSAGE 2507 //! \details 2508 //! FBR messages that do not want bidirectional motion estimation 2509 //! performed will set this bit and VME will only perform 2510 //! fractional refinement on the shapes identified by subpredmode. 2511 //! Note: only the LSB of the subpredmode for each shape will be 2512 //! considered in FBR (a shape iseither FWD or BWD as input of FBR, 2513 //! output however could change toBI if BME is enabled). 2514 enum BME_DISABLE_FOR_FBR_MESSAGE 2515 { 2516 BME_DISABLE_FOR_FBR_MESSAGE_BMEENABLED = 0, //!< No additional details 2517 BME_DISABLE_FOR_FBR_MESSAGE_BMEDISABLED = 1, //!< No additional details 2518 }; 2519 2520 //! \brief BLOCK_BASED_SKIP_ENABLED 2521 //! \details 2522 //! When this field is set on the skip thresholding passing criterion will 2523 //! be based on the maximal distortion of individual blocks (8x8's or 4x4's) 2524 //! instead of their sum (i.e. the distortion of 16x16). 2525 enum BLOCK_BASED_SKIP_ENABLED 2526 { 2527 BLOCK_BASED_SKIP_ENABLED_UNNAMED0 = 0, //!< 16x16 Block Based Skip threshold check. 2528 BLOCK_BASED_SKIP_ENABLED_BLOCK_BASEDSKIPTYPE = 1, //!< Parameter indicates 8x8 vs. 4x4 based check. 2529 }; 2530 2531 //! \brief INTER_SAD_MEASURE_ADJUSTMENT 2532 //! \details 2533 //! This field specifies distortion measure adjustments used 2534 //! for the motion search SAD comparison. This field applies 2535 //! to both luma and chroma inter measurement. 2536 enum INTER_SAD_MEASURE_ADJUSTMENT 2537 { 2538 INTER_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2539 INTER_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2540 }; 2541 2542 //! \brief INTRA_SAD_MEASURE_ADJUSTMENT 2543 //! \details 2544 //! This field specifies distortion measure adjustments used for the motion 2545 //! search SAD comparison. This field applies to both luma and chroma 2546 //! intra measurement. 2547 enum INTRA_SAD_MEASURE_ADJUSTMENT 2548 { 2549 INTRA_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2550 INTRA_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2551 }; 2552 2553 //! \brief SUB_MACROBLOCK_SUB_PARTITION_MASK 2554 //! \details 2555 //! This field defines the bit-mask for disabling 2556 //! <ul> 2557 //! <li>sub-partition (minor partition [30:28]) modes</li> 2558 //! <li>sub-macroblock (major partition [27:24]) modes</li> 2559 //! </ul> 2560 enum SUB_MACROBLOCK_SUB_PARTITION_MASK 2561 { 2562 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED113 = 113, //!< 16x16 sub-macroblock disabled 2563 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED114 = 114, //!< 2x(16x8) sub-macroblock within 16x16 disabled 2564 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED116 = 116, //!< 2x(8x16) sub-macroblock within 16x16 disabled 2565 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED120 = 120, //!< 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled 2566 }; 2567 2568 //! \brief BLOCK_BASED_SKIP_TYPE 2569 //! \details 2570 //! The skip thresholding passing criterion will be based on the maximal 2571 //! distortion of individual blocks (8x8's or 4x4's) instead of 2572 //! their sum (i.e. the distortion of 16x16). This field is only valid 2573 //! when <b>Block-Based Skip Enabled</b> = 1. 2574 enum BLOCK_BASED_SKIP_TYPE 2575 { 2576 BLOCK_BASED_SKIP_TYPE_UNNAMED0 = 0, //!< 4x4 block-based skip threshold check. 2577 BLOCK_BASED_SKIP_TYPE_UNNAMED1 = 1, //!< 8x8 block-based skip threshold check. 2578 }; 2579 2580 //! \brief CRE_PREFETCH_ENABLE 2581 //! \details 2582 //! This field determines if IME will prefetch the fractional CLs that are 2583 //! required by CRE ahead of time while fetching the reference windows around 2584 //! the IME predictors. The recommendation for driver is to always program 2585 //! this bit to 1 unless some usages restrict SubPelMode to be "<i>Integer 2586 //! mode searching</i>". 2587 enum CRE_PREFETCH_ENABLE 2588 { 2589 CRE_PREFETCH_ENABLE_UNNAMED0 = 0, //!< Disable 2590 CRE_PREFETCH_ENABLE_UNNAMED1 = 1, //!< Enable 2591 }; 2592 2593 //! \brief HME_REF1_DISABLE 2594 //! \details 2595 //! This field indicates if HME is disabled for reference 1 (second forward 2596 //! reference). 2597 enum HME_REF1_DISABLE 2598 { 2599 HME_REF1_DISABLE_UNNAMED0 = 0, //!< HME search is performed on forward reference 1. 2600 HME_REF1_DISABLE_UNNAMED1 = 1, //!< HME search is disabled on forward reference 1. 2601 }; 2602 2603 enum CONSTRAINED_INTRA_PREDICTION_FLAG 2604 { 2605 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED0 = 0, //!< Allows both intra and inter neighboring MB to be used in the intra-prediction decoding of the current MB. 2606 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED1 = 1, //!< Allows only to use neighboring Intra MBs in the intra-prediction decoding of the current MB.If the neighbor is an inter MB, it is considered as not available. 2607 }; 2608 2609 //! \brief PICTURE_TYPE 2610 //! \details 2611 //! This field specifies how the current picture is predicted. (It might be 2612 //! redundant from the kernel type.) 2613 enum PICTURE_TYPE 2614 { 2615 PICTURE_TYPE_I = 0, //!< No additional details 2616 PICTURE_TYPE_P = 1, //!< No additional details 2617 }; 2618 2619 //! \brief LUMA_INTRA_PARTITION_MASK 2620 //! \details 2621 //! This field specifies which Luma Intra partition is enabled/disabled for 2622 //! intra mode decision. 2623 enum LUMA_INTRA_PARTITION_MASK 2624 { 2625 LUMA_INTRA_PARTITION_MASK_UNNAMED1 = 1, //!< luma_intra_16x16 disabled 2626 LUMA_INTRA_PARTITION_MASK_UNNAMED2 = 2, //!< luma_intra_8x8 disabled 2627 LUMA_INTRA_PARTITION_MASK_UNNAMED4 = 4, //!< luma_intra_4x4 disabled 2628 }; 2629 2630 enum MV_COST_SCALING_FACTOR 2631 { 2632 MV_COST_SCALING_FACTOR_QPEL = 0, //!< Qpel difference between MV and cost center: eff cost range 0-15pel 2633 MV_COST_SCALING_FACTOR_HPEL = 1, //!< Hpel difference between MV and cost center: eff cost range 0-31pel 2634 MV_COST_SCALING_FACTOR_PEL = 2, //!< Pel difference between MV and cost center: eff cost range 0-63pel 2635 MV_COST_SCALING_FACTOR_2PEL = 3, //!< 2Pel difference between MV and cost center: eff cost range 0-127pel 2636 }; 2637 2638 enum REFID_COST_MODE_SELECT 2639 { 2640 REFID_COST_MODE_SELECT_MODE0 = 0, //!< AVC 2641 REFID_COST_MODE_SELECT_MODE1 = 1, //!< Linear 2642 }; 2643 2644 enum AVC_INTRA_16X16_MODE_MASK 2645 { 2646 AVC_INTRA_16X16_MODE_MASK_VERT = 1, //!< No additional details 2647 AVC_INTRA_16X16_MODE_MASK_HORZ = 2, //!< No additional details 2648 AVC_INTRA_16X16_MODE_MASK_DC = 4, //!< No additional details 2649 AVC_INTRA_16X16_MODE_MASK_PLANAR = 8, //!< No additional details 2650 }; 2651 2652 enum AVC_INTRA_CHROMA_MODE_MASK 2653 { 2654 AVC_INTRA_CHROMA_MODE_MASK_VERT = 1, //!< No additional details 2655 AVC_INTRA_CHROMA_MODE_MASK_HORZ = 2, //!< No additional details 2656 AVC_INTRA_CHROMA_MODE_MASK_DC = 4, //!< No additional details 2657 AVC_INTRA_CHROMA_MODE_MASK_PLANAR = 8, //!< No additional details 2658 }; 2659 2660 //! \brief INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2661 //! \details 2662 //! This field specifies the pixel components measured for Intra prediction. 2663 enum INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2664 { 2665 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED0 = 0, //!< Luma+Chroma enabled. 2666 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED1 = 1, //!< Luma Only. 2667 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED2 = 2, //!< Intra Disabled. 2668 }; 2669 2670 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 2671 //! \details 2672 //! <p>This parameter indicates if the IntraRefresh is enabled or 2673 //! disabled.</p> 2674 //! 2675 //! <p>This must be disabled on I-Frames.</p> 2676 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 2677 { 2678 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 2679 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 2680 }; 2681 2682 //! \brief INTRAREFRESHMODE 2683 //! \details 2684 //! This parameter indicates if the IntraRefresh is row based or column 2685 //! based. 2686 enum INTRAREFRESHMODE 2687 { 2688 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 2689 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 2690 }; 2691 2692 //! \brief HME_REF_WINDOWS_COMBINING_THRESHOLD 2693 //! \details 2694 //! When the reference windows of the HME refinement VME call and the 2695 //! regular VME call are overlapped and the difference of the locations 2696 //! is within this threshold in quarter pixel unit, the two calls 2697 //! are merged to a single call. 2698 enum HME_REF_WINDOWS_COMBINING_THRESHOLD 2699 { 2700 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED0 = 0, //!< No additional details 2701 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED255 = 255, //!< No additional details 2702 }; 2703 2704 //! \brief MAXHMVR 2705 //! \details 2706 //! Horizontal MV component range. The MV range is restricted to 2707 //! [-MaxHmvR+1, MaxHmvR-1] in luma quarter pel unit, 2708 //! which corresponds to [-MaxHmvR/4 + 0.25, MaxHmvR/4-0.25] in luma 2709 //! integer pel unit. 2710 enum MAXHMVR 2711 { 2712 MAXHMVR_UNNAMED256 = 256, //!< No additional details 2713 MAXHMVR_UNNAMED512 = 512, //!< No additional details 2714 MAXHMVR_UNNAMED1024 = 1024, //!< No additional details 2715 MAXHMVR_UNNAMED2048 = 2048, //!< No additional details 2716 MAXHMVR_UNNAMED4096 = 4096, //!< No additional details 2717 MAXHMVR_UNNAMED8192 = 8192, //!< No additional details 2718 }; 2719 2720 //! \brief MAXVMVR 2721 //! \details 2722 //! Vertical MV component range defined in the AVC Spec Annex A. 2723 //! The MV range is restricted to [-MaxVmvR+1, MaxVmvR-1] 2724 //! in luma quarter pel unit, which corresponds to 2725 //! [-MaxVmvR/4 + 0.25, MaxVmvR/4-0.25] in luma integer pel unit. 2726 enum MAXVMVR 2727 { 2728 MAXVMVR_UNNAMED256 = 256, //!< No additional details 2729 MAXVMVR_UNNAMED512 = 512, //!< No additional details 2730 MAXVMVR_UNNAMED1024 = 1024, //!< No additional details 2731 MAXVMVR_UNNAMED2048 = 2048, //!< No additional details 2732 }; 2733 2734 //! \brief PPMV_DISABLE 2735 //! \details 2736 //! This bit forces the IME to use the actual PMV predictor for the IME 2737 //! search. 2738 enum PPMV_DISABLE 2739 { 2740 PPMV_DISABLE_UNNAMED0 = 0, //!< Use PPMV based IME search. 2741 PPMV_DISABLE_UNNAMED1 = 1, //!< Use PMV based IME search. 2742 }; 2743 2744 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2745 //! \details 2746 //! Indicates whether the reference frame is a long or short term reference. 2747 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2748 { 2749 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2750 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2751 }; 2752 2753 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2754 //! \details 2755 //! Indicates whether the reference frame is a long or short term reference. 2756 enum LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2757 { 2758 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2759 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2760 }; 2761 2762 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2763 //! \details 2764 //! Indicates whether the reference frame is a long or short term reference. 2765 enum LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2766 { 2767 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2768 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2769 }; 2770 2771 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2772 //! \details 2773 //! Indicates whether the reference frame is a long or short term reference. 2774 enum LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2775 { 2776 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2777 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2778 }; 2779 2780 //! \name Initializations 2781 2782 //! \brief Explicit member initialization function 2783 VDENC_IMG_STATE_CMD(); 2784 2785 static const size_t dwSize = 35; 2786 static const size_t byteSize = 140; 2787 }; 2788 2789 //! 2790 //! \brief VDENC_PIPE_BUF_ADDR_STATE 2791 //! \details 2792 //! This state command provides the memory base addresses for all row 2793 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 2794 //! source, reference pictures and downscaled reference pictures required by 2795 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 2796 //! programmed with the same surface state (NV12 and TileY format), except 2797 //! each has its own frame buffer base address. Same holds true for the 2798 //! down-scaled reference pictures too. In the tile format, there is no need 2799 //! to provide buffer offset for each slice; since from each MB address, the 2800 //! hardware can calculated the corresponding memory location within the 2801 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 2802 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 2803 //! will sort out the base address from the DPB table and populate the base 2804 //! addresses that map to the corresponding reference index for both DS 2805 //! references and normal reference frames. Each of the individual DS ref/ 2806 //! Normal ref frames have their own MOCS DW that corresponds to the 2807 //! respective base address. The only thing that is different in the MOCS DW 2808 //! amongst the DS reference frames is the MMCD controls (specified in bits 2809 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 2810 //! to be the same across the different DS ref frames. The same is 2811 //! applicable for the normal reference frames. 2812 //! 2813 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 2814 { 2815 union 2816 { 2817 //!< DWORD 0 2818 struct 2819 { 2820 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2821 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2822 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2823 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2824 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2825 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2826 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2827 }; 2828 uint32_t Value; 2829 } DW0; 2830 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0 ; //!< DS FWD REF0 2831 union 2832 { 2833 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1; //!< DS FWD REF1 2834 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0; //!< DS BWD REF0 2835 }; 2836 VDENC_Down_Scaled_Reference_Picture_CMD Reserved; //!< Reserved 2837 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture ; //!< Original Uncompressed Picture 2838 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture ; //!< Streamin Data Picture 2839 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer ; //!< Row Store Scratch Buffer 2840 VDENC_Colocated_MV_Picture_CMD ColocatedMv ; //!< Colocated MV 2841 VDENC_Reference_Picture_CMD FwdRef0 ; //!< FWD REF0 2842 VDENC_Reference_Picture_CMD FwdRef1 ; //!< FWD REF1 2843 VDENC_Reference_Picture_CMD FwdRef2 ; //!< FWD REF2 2844 VDENC_Reference_Picture_CMD BwdRef0 ; //!< BWD REF0 2845 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout ; //!< VDEnc Statistics Streamout 2846 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X ; //!< DS FWD REF0 4X 2847 union 2848 { 2849 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X ; //!< DS FWD REF1 4X 2850 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef04X ; //!< DS BWD REF1 4X 2851 }; 2852 VDENC_Colocated_MV_Picture_CMD VdencCuRecordStreamOutBuffer ; //!< VDEnc CuRecord stream-out buffer 2853 VDENC_Colocated_MV_Picture_CMD VdencLcuPakObjCmdBuffer ; //!< VDEnc LCU PAK OBJ CMD Buffer 2854 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface8X ; //!< Scaled Reference Surface 8X 2855 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface4X ; //!< Scaled Reference Surface 4X 2856 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer ; //!< VP9 Segmentation Map Streamin Buffer 2857 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreamoutBuffer ; //!< VP9 Segmentation Map Streamout Buffer 2858 union 2859 { 2860 //!< DWORD 61 2861 struct 2862 { 2863 uint32_t WeightsHistogramStreamoutOffset ; //!< Weights Histogram Streamout offset 2864 }; 2865 uint32_t Value; 2866 } DW61; 2867 VDENC_Row_Store_Scratch_Buffer_Picture_CMD VdencTileRowStoreBuffer ; //!< VDENC Tile Row store Buffer 2868 VDENC_Statistics_Streamout_CMD VdencCumulativeCuCountStreamoutSurface ; //!< VDENC Cumulative CU count streamout surface 2869 VDENC_Statistics_Streamout_CMD VdencPaletteModeStreamoutSurface ; //!< VDENC Palette Mode streamout surface 2870 2871 //! \name Local enumerations 2872 2873 enum SUBOPB 2874 { 2875 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 2876 }; 2877 2878 enum SUBOPA 2879 { 2880 SUBOPA_UNNAMED0 = 0, //!< No additional details 2881 }; 2882 2883 enum OPCODE 2884 { 2885 OPCODE_VDENCPIPE = 1, //!< No additional details 2886 }; 2887 2888 enum PIPELINE 2889 { 2890 PIPELINE_MFXCOMMON = 2, //!< No additional details 2891 }; 2892 2893 enum COMMAND_TYPE 2894 { 2895 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2896 }; 2897 2898 //! \name Initializations 2899 2900 //! \brief Explicit member initialization function 2901 VDENC_PIPE_BUF_ADDR_STATE_CMD(); 2902 2903 static const size_t dwSize = 71; 2904 static const size_t byteSize = 284; 2905 }; 2906 2907 //! 2908 //! \brief VDENC_PIPE_MODE_SELECT 2909 //! \details 2910 //! Specifies which codec and hardware module is being used to encode/decode 2911 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 2912 //! specifies which codec and hardware module is being used to encode/decode 2913 //! the video data, on a per-frame basis. It also configures the hardware 2914 //! pipeline according to the active encoder/decoder operating mode for 2915 //! encoding/decoding the current picture. 2916 //! 2917 struct VDENC_PIPE_MODE_SELECT_CMD 2918 { 2919 union 2920 { 2921 //!< DWORD 0 2922 struct 2923 { 2924 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2925 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2926 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2927 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2928 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2929 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2930 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2931 }; 2932 uint32_t Value; 2933 } DW0; 2934 union 2935 { 2936 //!< DWORD 1 2937 struct 2938 { 2939 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 2940 uint32_t ScalabilityMode : __CODEGEN_BITFIELD( 4, 4) ; //!< Scalability Mode 2941 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 2942 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 2943 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TLB_PREFETCH_ENABLE 2944 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< PAK_THRESHOLD_CHECK_ENABLE 2945 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC_STREAM_IN_ENABLE 2946 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10) ; //!< DownScaled 8x write Disable 2947 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11) ; //!< DownScaled 4x write Disable 2948 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14) ; //!< BIT_DEPTH 2949 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16) ; //!< PAK_CHROMA_SUB_SAMPLING_TYPE 2950 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17) ; //!< output range control after color space conversion 2951 uint32_t IsRandomAccess : __CODEGEN_BITFIELD(18, 18) ; //!< Is random access B frame or not 2952 uint32_t Reserved50 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 2953 uint32_t RgbEncodingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< RGB encoding enable 2954 uint32_t PrimaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(21, 22) ; //!< PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 2955 uint32_t FirstSecondaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(23, 24) ; //!< FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 2956 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Tile replay enable 2957 uint32_t StreamingBufferConfig : __CODEGEN_BITFIELD(26, 27) ; //!< Streaming buffer config 2958 uint32_t Reserved58 : __CODEGEN_BITFIELD(28, 30) ; //!< Reserved 2959 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31) ; //!< Disable Speed Mode fetch optimization 2960 }; 2961 uint32_t Value; 2962 } DW1; 2963 union 2964 { 2965 //!< DWORD 2 2966 struct 2967 { 2968 uint32_t HmeRegionPreFetchenable : __CODEGEN_BITFIELD( 0, 0) ; //!< HME_REGION_PRE_FETCHENABLE 2969 uint32_t Topprefetchenablemode : __CODEGEN_BITFIELD( 1, 2) ; //!< TOPPREFETCHENABLEMODE 2970 uint32_t LeftpreFetchatwraparound : __CODEGEN_BITFIELD( 3, 3) ; //!< LEFTPRE_FETCHATWRAPAROUND 2971 uint32_t Verticalshift32Minus1 : __CODEGEN_BITFIELD( 4, 7) ; //!< VERTICALSHIFT32MINUS1 2972 uint32_t Hzshift32Minus1 : __CODEGEN_BITFIELD( 8, 11) ; //!< HZSHIFT32MINUS1 2973 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2974 uint32_t NumVerticalReqMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< NUMVERTICALREQMINUS1 2975 uint32_t Numhzreqminus1 : __CODEGEN_BITFIELD(20, 23) ; //!< NUMHZREQMINUS1 2976 uint32_t PreFetchOffsetForReferenceIn16PixelIncrement : __CODEGEN_BITFIELD(24, 27) ; //!< PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 2977 uint32_t Reserved92 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2978 }; 2979 uint32_t Value; 2980 } DW2; 2981 union 2982 { 2983 //!< DWORD 3 2984 struct 2985 { 2986 uint32_t SourceLumaPackedDataTlbPreFetchenable : __CODEGEN_BITFIELD( 0, 0) ; //!< SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 2987 uint32_t SourceChromaTlbPreFetchenable : __CODEGEN_BITFIELD( 1, 1) ; //!< SOURCE_CHROMA_TLB_PRE_FETCHENABLE 2988 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2989 uint32_t Verticalshift32Minus1Src : __CODEGEN_BITFIELD( 4, 7) ; //!< VERTICALSHIFT32MINUS1SRC 2990 uint32_t Hzshift32Minus1Src : __CODEGEN_BITFIELD( 8, 11) ; //!< HZSHIFT32MINUS1SRC 2991 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2992 uint32_t Numverticalreqminus1Src : __CODEGEN_BITFIELD(16, 19) ; //!< NUMVERTICALREQMINUS1SRC 2993 uint32_t Numhzreqminus1Src : __CODEGEN_BITFIELD(20, 23) ; //!< NUMHZREQMINUS1SRC 2994 uint32_t PreFetchoffsetforsource : __CODEGEN_BITFIELD(24, 27) ; //!< PRE_FETCHOFFSETFORSOURCE 2995 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2996 }; 2997 uint32_t Value; 2998 } DW3; 2999 union 3000 { 3001 struct 3002 { 3003 uint32_t Debugtilepassnum : __CODEGEN_BITFIELD( 0, 3) ; //!< DebugTilePassNum 3004 uint32_t Debugtilenum : __CODEGEN_BITFIELD( 4, 11) ; //!< DebugTileNum 3005 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 3006 }; 3007 uint32_t Value; 3008 } DW4; 3009 union 3010 { 3011 struct 3012 { 3013 uint32_t FrameNumber : __CODEGEN_BITFIELD( 0, 3) ; //!< Frame Number 3014 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 9) ; //!< Reserved 3015 uint32_t HeadPointerUpdateAuto : __CODEGEN_BITFIELD(10, 10) ; //!< Head Pointer Update Auto 3016 uint32_t CaptureMode : __CODEGEN_BITFIELD(11, 12) ; //!< CAPTURE_MODE 3017 uint32_t ParallelCaptureAndEncodeSessionId : __CODEGEN_BITFIELD(13, 15) ; //!< PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 3018 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 3019 uint32_t TailPointerReadFrequency : __CODEGEN_BITFIELD(24, 31) ; //!< Tail pointer read frequency 3020 }; 3021 uint32_t Value; 3022 } DW5; 3023 3024 //! \name Local enumerations 3025 3026 enum SUBOPB 3027 { 3028 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 3029 }; 3030 3031 enum SUBOPA 3032 { 3033 SUBOPA_UNNAMED0 = 0, //!< No additional details 3034 }; 3035 3036 enum OPCODE 3037 { 3038 OPCODE_VDENCPIPE = 1, //!< No additional details 3039 }; 3040 3041 enum PIPELINE 3042 { 3043 PIPELINE_MFXCOMMON = 2, //!< No additional details 3044 }; 3045 3046 enum COMMAND_TYPE 3047 { 3048 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3049 }; 3050 3051 enum STANDARD_SELECT 3052 { 3053 STANDARD_SELECT_AVC = 2, //!< No additional details 3054 }; 3055 3056 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 3057 //! \details 3058 //! This field controls whether the frame statistics stream-out is enabled. 3059 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 3060 { 3061 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 3062 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 3063 }; 3064 3065 //! \brief TLB_PREFETCH_ENABLE 3066 //! \details 3067 //! This field controls whether TLB prefetching is enabled. 3068 enum TLB_PREFETCH_ENABLE 3069 { 3070 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 3071 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 3072 }; 3073 3074 //! \brief PAK_THRESHOLD_CHECK_ENABLE 3075 //! \details 3076 //! For AVC standard: This field controls whether VDEnc will check the 3077 //! PAK indicator for bits overflow and terminates the slice. This mode is 3078 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 3079 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 3080 //! Minus One to terminate the slice. This feature is also referred to as 3081 //! slice size conformance. 3082 //! For HEVC standard: This bit is used to enable dynamic slice size 3083 //! control. 3084 enum PAK_THRESHOLD_CHECK_ENABLE 3085 { 3086 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 3087 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 3088 }; 3089 3090 //! \brief VDENC_STREAM_IN_ENABLE 3091 //! \details 3092 //! This field controls whether VDEnc will read the stream-in surface 3093 //! that is programmed. Currently the stream-in surface has MB level QP, 3094 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 3095 //! individual enables for each of the fields is programmed in the 3096 //! VDENC_IMG_STATE. 3097 //! (ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 3098 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable). 3099 //! This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 3100 //! reserved and should be set to zero. 3101 enum VDENC_STREAM_IN_ENABLE 3102 { 3103 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 3104 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 3105 }; 3106 3107 //! \brief BIT_DEPTH 3108 //! \details 3109 //! This parameter indicates the PAK bit depth. The valid values for this 3110 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 3111 //! set to 0. 3112 enum BIT_DEPTH 3113 { 3114 BIT_DEPTH_8BIT = 0, //!< No additional details 3115 BIT_DEPTH_10BIT = 2, //!< No additional details 3116 BIT_DEPTH_12BIT = 3, //!< No additional details 3117 }; 3118 3119 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 3120 //! \details 3121 //! This field is applicable only in HEVC and VP9. In AVC, this field is ignored. 3122 enum PAK_CHROMA_SUB_SAMPLING_TYPE 3123 { 3124 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 3125 PAK_CHROMA_SUB_SAMPLING_TYPE_4_4_4 = 3, //!< HEVC RExt 444, VP9 444 profiles. 3126 }; 3127 3128 //! \brief PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3129 //! \details 3130 //! In RGB encoding, any one of the channel could be primary. This field is 3131 //! used for selcting primary channel 3132 enum PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3133 { 3134 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is primary channel 3135 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is primary channel. 3136 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is primary channel 3137 }; 3138 3139 //! \brief FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3140 //! \details 3141 //! In RGB encoding, any one of the channel could be primary. This field is 3142 //! used for selcting primary channel 3143 enum FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3144 { 3145 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is first secondary channel 3146 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is first secondary channel 3147 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is first secondary channel. 3148 }; 3149 3150 //! \brief HME_REGION_PRE_FETCHENABLE 3151 //! \details 3152 //! When this bit is set, for all reference frames HME region pages are pre-fetched. 3153 enum HME_REGION_PRE_FETCHENABLE 3154 { 3155 HME_REGION_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3156 HME_REGION_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3157 }; 3158 3159 //! \brief TOPPREFETCHENABLEMODE 3160 //! \details 3161 //! Top Pre-fetch enable Mode 3162 enum TOPPREFETCHENABLEMODE 3163 { 3164 TOPPREFETCHENABLEMODE_UNNAMED1 = 1, //!< No additional details 3165 }; 3166 3167 //! \brief LEFTPRE_FETCHATWRAPAROUND 3168 //! \details 3169 //! Left pre-fetch enabled on wraparound 3170 enum LEFTPRE_FETCHATWRAPAROUND 3171 { 3172 LEFTPRE_FETCHATWRAPAROUND_UNNAMED1 = 1, //!< No additional details 3173 }; 3174 3175 enum VERTICALSHIFT32MINUS1 3176 { 3177 VERTICALSHIFT32MINUS1_UNNAMED0 = 0, //!< No additional details 3178 }; 3179 3180 //! \brief HZSHIFT32MINUS1 3181 //! \details 3182 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 3183 enum HZSHIFT32MINUS1 3184 { 3185 HZSHIFT32MINUS1_UNNAMED3 = 3, //!< No additional details 3186 }; 3187 3188 //! \brief NUMHZREQMINUS1 3189 //! \details 3190 //! Number of Vertical requests in each region for a constant horizontal position. 3191 enum NUMVERTICALREQMINUS1 3192 { 3193 NUMVERTICALREQMINUS1_UNNAMED11 = 11, //!< No additional details 3194 }; 3195 3196 //! \brief NUMHZREQMINUS1 3197 //! \details 3198 //! Number of Horizontal Requests minus 1 at row begining. 3199 enum NUMHZREQMINUS1 3200 { 3201 NUMHZREQMINUS1_UNNAMED2 = 2, //!< No additional details 3202 }; 3203 3204 enum PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 3205 { 3206 PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0 = 0, //!< No additional details 3207 }; 3208 3209 //! \brief SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 3210 //! \details 3211 //! When this bit is set, Souce Luma / Packed data TLB pre-fetches are 3212 //! performed. 3213 enum SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 3214 { 3215 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3216 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3217 }; 3218 3219 //! \brief SOURCE_CHROMA_TLB_PRE_FETCHENABLE 3220 //! \details 3221 //! When this bit is set, Souce Chroma TLB pre-fetches are performed. 3222 enum SOURCE_CHROMA_TLB_PRE_FETCHENABLE 3223 { 3224 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3225 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3226 }; 3227 3228 enum VERTICALSHIFT32MINUS1SRC 3229 { 3230 VERTICALSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 3231 }; 3232 3233 //! \brief HZSHIFT32MINUS1SRC 3234 //! \details 3235 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 3236 enum HZSHIFT32MINUS1SRC 3237 { 3238 HZSHIFT32MINUS1SRC_UNNAMED3 = 3, //!< No additional details 3239 }; 3240 3241 //! \brief NUMVERTICALREQMINUS1SRC 3242 //! \details 3243 //! Number of Horizontal requests Minus 1 for source 3244 enum NUMVERTICALREQMINUS1SRC 3245 { 3246 NUMVERTICALREQMINUS1SRC_UNNAMED0 = 0, //!< This is the valid for AVC 3247 NUMVERTICALREQMINUS1SRC_UNNAMED1 = 1, //!< This is the valid value for HEVC 3248 }; 3249 3250 //! \brief NUMHZREQMINUS1SRC 3251 //! \details 3252 //! Number of Horizontal requests Minus 1 for source 3253 enum NUMHZREQMINUS1SRC 3254 { 3255 NUMHZREQMINUS1SRC_UNNAMED0 = 0, //!< No additional details 3256 }; 3257 3258 //! \brief PRE_FETCHOFFSETFORSOURCE 3259 //! \details 3260 //! Pre-fetch offset for Reference in 16 pixel increment. 3261 enum PRE_FETCHOFFSETFORSOURCE 3262 { 3263 PRE_FETCHOFFSETFORSOURCE_UNNAMED_4 = 4, //!< This value is applicable in HEVC mode 3264 PRE_FETCHOFFSETFORSOURCE_UNNAMED7 = 7, //!< This Value is applicable in AVC mode 3265 }; 3266 3267 enum CAPTURE_MODE 3268 { 3269 CAPTURE_MODE_UNNAMED0 = 0, //!< No Parallel capture 3270 CAPTURE_MODE_UNNAMED1 = 1, //!< Parallel encode from Display overlay 3271 CAPTURE_MODE_CAMERA = 2, //!< Parallel encode from Camera Pipe 3272 CAPTURE_MODE_UNNAMED3 = 3, //!< Reserved 3273 }; 3274 3275 enum STREAMING_BUFFER_CONFIG 3276 { 3277 STREAMING_BUFFER_UNSUPPORTED = 0, 3278 STREAMING_BUFFER_64 = 1, 3279 STREAMING_BUFFER_128 = 2, 3280 STREAMING_BUFFER_256 = 3, 3281 }; 3282 3283 enum PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 3284 { 3285 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0 = 0, //!< Display tailpointer address location 00ED0h-00ED3h 3286 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED1 = 1, //!< Display tailpointer address location 00ED4h-00ED7h 3287 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED2 = 2, //!< Display tailpointer address location 00ED8h-00EDBh 3288 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED3 = 3, //!< Display tailpointer address location 00EDCh-00EDFh 3289 }; 3290 3291 //! \name Initializations 3292 3293 //! \brief Explicit member initialization function 3294 VDENC_PIPE_MODE_SELECT_CMD(); 3295 3296 static const size_t dwSize = 6; 3297 static const size_t byteSize = 24; 3298 }; 3299 3300 //! 3301 //! \brief VDENC_REF_SURFACE_STATE 3302 //! \details 3303 //! This command specifies the surface state parameters for the normal 3304 //! reference surfaces. 3305 //! 3306 struct VDENC_REF_SURFACE_STATE_CMD 3307 { 3308 union 3309 { 3310 //!< DWORD 0 3311 struct 3312 { 3313 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3314 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3315 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3316 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3317 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3318 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3319 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3320 }; 3321 uint32_t Value; 3322 } DW0; 3323 union 3324 { 3325 //!< DWORD 1 3326 struct 3327 { 3328 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 2) ; //!< Surface ID 3329 uint32_t Reserved : __CODEGEN_BITFIELD(3, 31) ; //!< Reserved 3330 }; 3331 uint32_t Value; 3332 } DW1; 3333 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3334 3335 //! \name Local enumerations 3336 3337 enum SUBOPB 3338 { 3339 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 3340 }; 3341 3342 enum SUBOPA 3343 { 3344 SUBOPA_UNNAMED0 = 0, //!< No additional details 3345 }; 3346 3347 enum OPCODE 3348 { 3349 OPCODE_VDENCPIPE = 1, //!< No additional details 3350 }; 3351 3352 enum PIPELINE 3353 { 3354 PIPELINE_MFXCOMMON = 2, //!< No additional details 3355 }; 3356 3357 enum COMMAND_TYPE 3358 { 3359 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3360 }; 3361 3362 //! \name Initializations 3363 3364 //! \brief Explicit member initialization function 3365 VDENC_REF_SURFACE_STATE_CMD(); 3366 3367 static const size_t dwSize = 6; 3368 static const size_t byteSize = 24; 3369 }; 3370 3371 //! 3372 //! \brief VDENC_SRC_SURFACE_STATE 3373 //! \details 3374 //! This command specifies the uncompressed original input picture to be 3375 //! encoded. The actual base address is defined in the 3376 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 3377 //! pixels and garbage will be there at the end of each line. The following 3378 //! describes all the different formats that are supported in WLV+ VDEnc: 3379 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 3380 //! 0 (the only format supported for video codec); vertical UV offset is MB 3381 //! aligned; UV xoffsets = 0. 3382 //! This surface state here is identical to the Surface State for 3383 //! deinterlace and sample_8x8 messages described in the Shared Function 3384 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 3385 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 3386 //! is designed to guarantee legal memory accesses (read and write). For the 3387 //! remaining cases, indirect object base address, indirect object address 3388 //! upper bound, object data start address (offset) and object data length 3389 //! are used to fully specified their corresponding buffer. This mechanism 3390 //! is chosen over the pixel surface type because of their variable record 3391 //! sizes. All row store surfaces are linear surface. Their addresses are 3392 //! programmed in VDEnc_Pipe_Buf_Base_State. 3393 //! 3394 struct VDENC_SRC_SURFACE_STATE_CMD 3395 { 3396 union 3397 { 3398 //!< DWORD 0 3399 struct 3400 { 3401 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3402 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3403 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3404 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3405 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3406 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3407 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3408 }; 3409 uint32_t Value; 3410 } DW0; 3411 union 3412 { 3413 //!< DWORD 1 3414 struct 3415 { 3416 uint32_t Reserved32 ; //!< Reserved 3417 }; 3418 uint32_t Value; 3419 } DW1; 3420 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3421 3422 //! \name Local enumerations 3423 3424 enum SUBOPB 3425 { 3426 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 3427 }; 3428 3429 enum SUBOPA 3430 { 3431 SUBOPA_UNNAMED0 = 0, //!< No additional details 3432 }; 3433 3434 enum OPCODE 3435 { 3436 OPCODE_VDENCPIPE = 1, //!< No additional details 3437 }; 3438 3439 enum PIPELINE 3440 { 3441 PIPELINE_MFXCOMMON = 2, //!< No additional details 3442 }; 3443 3444 enum COMMAND_TYPE 3445 { 3446 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3447 }; 3448 3449 //! \name Initializations 3450 3451 //! \brief Explicit member initialization function 3452 VDENC_SRC_SURFACE_STATE_CMD(); 3453 3454 static const size_t dwSize = 6; 3455 static const size_t byteSize = 24; 3456 }; 3457 3458 //! 3459 //! \brief VDENC_WALKER_STATE 3460 //! \details 3461 //! This command provides the macroblock start location for the VDEnc 3462 //! walker. Current programming to always have this command at the frame 3463 //! level, hence the macroblock X,Y location need to be programmed to 0,0 to 3464 //! always start at frame origin. Once the hardware receives this command 3465 //! packet, it internally starts the VDEnc pipeline. This should be the last 3466 //! command that is programmed for the VDEnc pipeline. 3467 //! 3468 //! This command is programmed per super-slice. The X location always needs 3469 //! to be programmed to 0. The Y location needs to be programmed to the 3470 //! starting point of the current super-slice. The programming needs to 3471 //! ensure that all super-slices are contiguous. It is illegal to have gaps 3472 //! between the super-slices. 3473 //! 3474 struct VDENC_WALKER_STATE_CMD 3475 { 3476 union 3477 { 3478 //!< DWORD 0 3479 struct 3480 { 3481 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3482 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3483 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3484 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3485 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3486 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3487 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3488 }; 3489 uint32_t Value; 3490 } DW0; 3491 union 3492 { 3493 //!< DWORD 1 3494 struct 3495 { 3496 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< MB/LCU Start Y Position 3497 uint32_t Reserved41 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3498 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24) ; //!< MB/LCU Start X Position 3499 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 3500 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28) ; //!< First Super Slice 3501 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3502 }; 3503 uint32_t Value; 3504 } DW1; 3505 union 3506 { 3507 //!< DWORD 2 3508 struct 3509 { 3510 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSlice MB Start Y Position 3511 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 3512 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25) ; //!< NextSlice MB/LCU Start X Position 3513 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3514 }; 3515 uint32_t Value; 3516 } DW2; 3517 union 3518 { 3519 //!< DWORD 3 3520 struct 3521 { 3522 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 3523 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 3524 uint32_t HevcLog2WeightDemonLuma : __CODEGEN_BITFIELD( 4, 6) ; //!< HevcLog2WeightDemonLuma 3525 uint32_t Reserved78 : __CODEGEN_BITFIELD( 7, 8) ; //!< Reserved 3526 uint32_t NumParEngine : __CODEGEN_BITFIELD( 9, 10) ; //!< NUM_PAR_ENGINE 3527 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 3528 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD(16, 16) ; //!< TileRowStoreSelect 3529 uint32_t Reserved108 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 3530 uint32_t TileNumber : __CODEGEN_BITFIELD(24, 31) ; //!< Tile number 3531 }; 3532 uint32_t Value; 3533 } DW3; 3534 union 3535 { 3536 //!< DWORD 4 3537 struct 3538 { 3539 uint32_t TileStartCtbY : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Start CTB-Y 3540 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Start CTB-X 3541 }; 3542 uint32_t Value; 3543 } DW4; 3544 union 3545 { 3546 //!< DWORD 5 3547 struct 3548 { 3549 uint32_t TileWidth : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Width 3550 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Height 3551 }; 3552 uint32_t Value; 3553 } DW5; 3554 union 3555 { 3556 //!< DWORD 6 3557 struct 3558 { 3559 uint32_t StreaminOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Streamin Offset enable 3560 uint32_t Reserved193 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3561 uint32_t TileStreaminOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Streamin Offset 3562 }; 3563 uint32_t Value; 3564 } DW6; 3565 union 3566 { 3567 //!< DWORD 7 3568 struct 3569 { 3570 uint32_t RowStoreOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Row store Offset enable 3571 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3572 uint32_t TileRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Rowstore Offset 3573 }; 3574 uint32_t Value; 3575 } DW7; 3576 union 3577 { 3578 //!< DWORD 8 3579 struct 3580 { 3581 uint32_t TileStreamoutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Tile streamout offset enable 3582 uint32_t Reserved257 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3583 uint32_t TileStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile streamout offset 3584 }; 3585 uint32_t Value; 3586 } DW8; 3587 union 3588 { 3589 //!< DWORD 9 3590 struct 3591 { 3592 uint32_t LcuStreamOutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< LCU stream out offset enable 3593 uint32_t Reserved289 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3594 uint32_t TileLcuStreamOutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile LCU stream out offset 3595 }; 3596 uint32_t Value; 3597 } DW9; 3598 uint32_t DW_Reserved_10 = {0}; //!< Reserved 3599 union 3600 { 3601 //!< DWORD 11 3602 struct 3603 { 3604 uint32_t Reserved290 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3605 }; 3606 uint32_t Value; 3607 } DW11; 3608 union 3609 { 3610 //!< DWORD 12 3611 struct 3612 { 3613 uint32_t Reserved291 : __CODEGEN_BITFIELD(0, 25) ; //!< Reserved 3614 uint32_t PaletteModeEnable : __CODEGEN_BITFIELD(26, 26) ; //!< PALETTE_MODE_ENABLE 3615 uint32_t IbcControl : __CODEGEN_BITFIELD(27, 28) ; //!< IBC_CONTROL 3616 uint32_t Reserved292 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3617 }; 3618 uint32_t Value; 3619 } DW12; 3620 union 3621 { 3622 //!< DWORD 13 3623 struct 3624 { 3625 uint32_t Reserved293 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3626 }; 3627 uint32_t Value; 3628 } DW13; 3629 union 3630 { 3631 //!< DWORD 14 3632 struct 3633 { 3634 uint32_t Reserved294 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3635 }; 3636 uint32_t Value; 3637 } DW14; 3638 union 3639 { 3640 //!< DWORD 15 3641 struct 3642 { 3643 uint32_t Reserved295 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3644 }; 3645 uint32_t Value; 3646 } DW15; 3647 union 3648 { 3649 //!< DWORD 16 3650 struct 3651 { 3652 uint32_t Reserved518 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 3653 uint32_t AdaptiveChannelThreshold : __CODEGEN_BITFIELD(24, 28) ; //!< Adaptive Channel Threshold 3654 uint32_t Reserved520 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3655 }; 3656 uint32_t Value; 3657 } DW16; 3658 uint32_t DW_Reserved_17_26[10] = {0}; //!< Reserved 3659 3660 //! \name Local enumerations 3661 3662 enum SUBOPB 3663 { 3664 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 3665 }; 3666 3667 enum SUBOPA 3668 { 3669 SUBOPA_UNNAMED0 = 0, //!< No additional details 3670 }; 3671 3672 enum OPCODE 3673 { 3674 OPCODE_VDENCPIPE = 1, //!< No additional details 3675 }; 3676 3677 enum PIPELINE 3678 { 3679 PIPELINE_MFXCOMMON = 2, //!< No additional details 3680 }; 3681 3682 enum COMMAND_TYPE 3683 { 3684 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3685 }; 3686 3687 //! \name Initializations 3688 3689 //! \brief Explicit member initialization function 3690 VDENC_WALKER_STATE_CMD(); 3691 3692 static const size_t dwSize = 27; 3693 static const size_t byteSize = 108; 3694 }; 3695 3696 //! 3697 //! \brief VDENC_CONTROL_STATE 3698 //! \details 3699 //! 3700 //! 3701 struct VDENC_CONTROL_STATE_CMD 3702 { 3703 union 3704 { 3705 //!< DWORD 0 3706 struct 3707 { 3708 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3709 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3710 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< Media Instruction Command 3711 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< Media Instruction Opcode 3712 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< Pipeline Type 3713 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< Command Type 3714 }; 3715 uint32_t Value; 3716 } DW0; 3717 union 3718 { 3719 //!< DWORD 1 3720 struct 3721 { 3722 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3723 uint32_t VdencInitialization : __CODEGEN_BITFIELD( 1, 1) ; //!< VDenc Initialization 3724 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3725 }; 3726 uint32_t Value; 3727 } DW1; 3728 3729 //! \name Local enumerations 3730 3731 //! \name Initializations 3732 3733 //! \brief Explicit member initialization function 3734 VDENC_CONTROL_STATE_CMD(); 3735 3736 static const size_t dwSize = 2; 3737 static const size_t byteSize = 8; 3738 }; 3739 3740 //! 3741 //! \brief VDENC_CMD1_CMD 3742 //! \details 3743 //! 3744 //! 3745 struct VDENC_CMD1_CMD 3746 { 3747 union 3748 { 3749 //!< DWORD 0 3750 struct 3751 { 3752 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWord Length 3753 uint32_t Reserved13 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3754 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3755 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3756 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3757 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3758 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3759 }; 3760 uint32_t Value; 3761 } DW0; 3762 union 3763 { 3764 //!< DWORD 1 3765 struct 3766 { 3767 uint32_t Reserved30 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3768 }; 3769 uint32_t Value; 3770 } DW1; 3771 union 3772 { 3773 //!< DWORD 2 3774 struct 3775 { 3776 uint32_t Reserved42 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3777 }; 3778 uint32_t Value; 3779 } DW2; 3780 union 3781 { 3782 //!< DWORD 3 3783 struct 3784 { 3785 uint32_t Reserved54 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3786 }; 3787 uint32_t Value; 3788 } DW3; 3789 union 3790 { 3791 //!< DWORD 4 3792 struct 3793 { 3794 uint32_t Reserved66 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3795 }; 3796 uint32_t Value; 3797 } DW4; 3798 union 3799 { 3800 //!< DWORD 5 3801 struct 3802 { 3803 uint32_t Reserved78 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3804 }; 3805 uint32_t Value; 3806 } DW5; 3807 union 3808 { 3809 //!< DWORD 6 3810 struct 3811 { 3812 uint32_t Reserved90 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3813 }; 3814 uint32_t Value; 3815 } DW6; 3816 union 3817 { 3818 //!< DWORD 7 3819 struct 3820 { 3821 uint32_t Reserved102 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3822 }; 3823 uint32_t Value; 3824 } DW7; 3825 union 3826 { 3827 //!< DWORD 8 3828 struct 3829 { 3830 uint32_t Reserved114 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3831 }; 3832 uint32_t Value; 3833 } DW8; 3834 union 3835 { 3836 //!< DWORD 9 3837 struct 3838 { 3839 uint32_t Reserved126 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3840 }; 3841 uint32_t Value; 3842 } DW9; 3843 union 3844 { 3845 //!< DWORD 10 3846 struct 3847 { 3848 uint32_t Reserved138 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3849 }; 3850 uint32_t Value; 3851 } DW10; 3852 union 3853 { 3854 //!< DWORD 11 3855 struct 3856 { 3857 uint32_t Reserved150 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3858 }; 3859 uint32_t Value; 3860 } DW11; 3861 union 3862 { 3863 //!< DWORD 12 3864 struct 3865 { 3866 uint32_t Reserved162 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3867 }; 3868 uint32_t Value; 3869 } DW12; 3870 union 3871 { 3872 //!< DWORD 13 3873 struct 3874 { 3875 uint32_t Reserved174 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3876 }; 3877 uint32_t Value; 3878 } DW13; 3879 union 3880 { 3881 //!< DWORD 14 3882 struct 3883 { 3884 uint32_t Reserved184 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3885 }; 3886 uint32_t Value; 3887 } DW14; 3888 union 3889 { 3890 //!< DWORD 15 3891 struct 3892 { 3893 uint32_t Reserved198 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3894 }; 3895 uint32_t Value; 3896 } DW15; 3897 union 3898 { 3899 //!< DWORD 16 3900 struct 3901 { 3902 uint32_t Reserved210 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3903 }; 3904 uint32_t Value; 3905 } DW16; 3906 union 3907 { 3908 //!< DWORD 17 3909 struct 3910 { 3911 uint32_t Reserved222 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3912 }; 3913 uint32_t Value; 3914 } DW17; 3915 union 3916 { 3917 //!< DWORD 18 3918 struct 3919 { 3920 uint32_t Reserved231 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3921 }; 3922 uint32_t Value; 3923 } DW18; 3924 union 3925 { 3926 //!< DWORD 19 3927 struct 3928 { 3929 uint32_t Reserved246 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3930 }; 3931 uint32_t Value; 3932 } DW19; 3933 union 3934 { 3935 //!< DWORD 20 3936 struct 3937 { 3938 uint32_t Reserved258 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3939 }; 3940 uint32_t Value; 3941 } DW20; 3942 union 3943 { 3944 //!< DWORD 21 3945 struct 3946 { 3947 uint32_t Reserved270 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3948 }; 3949 uint32_t Value; 3950 } DW21; 3951 union 3952 { 3953 //!< DWORD 22 3954 struct 3955 { 3956 uint32_t Reserved282 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3957 }; 3958 uint32_t Value; 3959 } DW22; 3960 union 3961 { 3962 //!< DWORD 23 3963 struct 3964 { 3965 uint32_t Reserved294 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3966 }; 3967 uint32_t Value; 3968 } DW23; 3969 union 3970 { 3971 //!< DWORD 24 3972 struct 3973 { 3974 uint32_t Reserved306 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3975 }; 3976 uint32_t Value; 3977 } DW24; 3978 union 3979 { 3980 //!< DWORD 25 3981 struct 3982 { 3983 uint32_t Reserved318 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3984 }; 3985 uint32_t Value; 3986 } DW25; 3987 union 3988 { 3989 //!< DWORD 26 3990 struct 3991 { 3992 uint32_t Reserved330 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3993 }; 3994 uint32_t Value; 3995 } DW26; 3996 union 3997 { 3998 //!< DWORD 27 3999 struct 4000 { 4001 uint32_t Reserved342 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4002 }; 4003 uint32_t Value; 4004 } DW27; 4005 union 4006 { 4007 //!< DWORD 28 4008 struct 4009 { 4010 uint32_t Reserved354 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4011 }; 4012 uint32_t Value; 4013 } DW28; 4014 union 4015 { 4016 //!< DWORD 29 4017 struct 4018 { 4019 uint32_t Reserved366 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4020 }; 4021 uint32_t Value; 4022 } DW29; 4023 union 4024 { 4025 //!< DWORD 30 4026 struct 4027 { 4028 uint32_t Reserved378 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4029 }; 4030 uint32_t Value; 4031 } DW30; 4032 4033 //! \name Local enumerations 4034 4035 enum SUBOPB 4036 { 4037 SUBOPB_VDENCCMD1CMD = 10, //!< No additional details 4038 }; 4039 4040 enum SUBOPA 4041 { 4042 SUBOPA_UNNAMED0 = 0, //!< No additional details 4043 }; 4044 4045 enum OPCODE 4046 { 4047 OPCODE_VDENCPIPE = 1, //!< No additional details 4048 }; 4049 4050 enum PIPELINE 4051 { 4052 PIPELINE_MFXCOMMON = 2, //!< No additional details 4053 }; 4054 4055 enum COMMAND_TYPE 4056 { 4057 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4058 }; 4059 4060 //! \name Initializations 4061 4062 //! \brief Explicit member initialization function 4063 VDENC_CMD1_CMD(); 4064 4065 static const size_t dwSize = 31; 4066 static const size_t byteSize = 124; 4067 }; 4068 4069 //! 4070 //! \brief VDENC_CMD2_STATE 4071 //! \details 4072 //! 4073 //! 4074 struct VDENC_CMD2_CMD 4075 { 4076 union 4077 { 4078 //!< DWORD 0 4079 struct 4080 { 4081 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWord Length 4082 uint32_t Reserved13 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4083 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 4084 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 4085 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 4086 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4087 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4088 }; 4089 uint32_t Value; 4090 } DW0; 4091 union 4092 { 4093 //!< DWORD 1 4094 struct 4095 { 4096 uint32_t FrameWidthInPixelsMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< FrameWidthInPixelsMinusOne 4097 uint32_t FrameHeightInPixelsMinusOne : __CODEGEN_BITFIELD(16, 31) ; //!< FrameHeightInPixelsMinusOne 4098 }; 4099 uint32_t Value; 4100 } DW1; 4101 union 4102 { 4103 //!< DWORD 2 4104 struct 4105 { 4106 uint32_t Reserved46 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 4107 uint32_t PictureType : __CODEGEN_BITFIELD(20, 21) ; //!< Picture Type 4108 uint32_t TemporalMvpEnableFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TemporalMvpEnableFlag 4109 uint32_t Reserved49 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 4110 uint32_t LongTermReferenceFlagsL0 : __CODEGEN_BITFIELD(24, 26) ; //!< LongTermReferenceFlags_L0 4111 uint32_t LongTermReferenceFlagsL1 : __CODEGEN_BITFIELD(27, 27) ; //!< LongTermReferenceFlags_L1 4112 uint32_t Reserved53 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 4113 uint32_t TransformSkip : __CODEGEN_BITFIELD(30, 30) ; //!< TransformSkip 4114 uint32_t Reserved55 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4115 }; 4116 uint32_t Value; 4117 } DW2; 4118 union 4119 { 4120 //!< DWORD 3 4121 struct 4122 { 4123 uint32_t PocNumberForRefid0InL0 : __CODEGEN_BITFIELD( 0, 7) ; //!< FWD_POC_NUMBER_FOR_REFID_0_IN_L0 4124 uint32_t PocNumberForRefid0InL1 : __CODEGEN_BITFIELD( 8, 15) ; //!< BWD_POC_NUMBER_FOR_REFID_0_IN_L1 4125 uint32_t PocNumberForRefid1InL0 : __CODEGEN_BITFIELD(16, 23) ; //!< POC_NUMBER_FOR_REFID_1_IN_L0 4126 uint32_t PocNumberForRefid1InL1 : __CODEGEN_BITFIELD(24, 31) ; //!< POC_NUMBER_FOR_REFID_1_IN_L1 4127 }; 4128 uint32_t Value; 4129 } DW3; 4130 union 4131 { 4132 //!< DWORD 4 4133 struct 4134 { 4135 uint32_t PocNumberForRefid2InL0 : __CODEGEN_BITFIELD( 0, 7) ; //!< FWD_POC_NUMBER_FOR_REFID_2_IN_L0 4136 uint32_t PocNumberForRefid2InL1 : __CODEGEN_BITFIELD( 8, 15) ; //!< BWD_POC_NUMBER_FOR_REFID_2_IN_L1 4137 uint32_t Reserved79 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4138 }; 4139 uint32_t Value; 4140 } DW4; 4141 union 4142 { 4143 //!< DWORD 5 4144 struct 4145 { 4146 uint32_t Reserved89 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4147 uint32_t StreaminRoiEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< StreamIn ROI Enable 4148 uint32_t Reserved98 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 4149 uint32_t NumRefIdxL0Minus1 : __CODEGEN_BITFIELD(24, 27) ; //!< NumRefIdxL0_minus1 4150 uint32_t NumRefIdxL1Minus1 : __CODEGEN_BITFIELD(28, 31) ; //!< NumRefIdxL1_minus1 4151 }; 4152 uint32_t Value; 4153 } DW5; 4154 union 4155 { 4156 //!< DWORD 6 4157 struct 4158 { 4159 uint32_t Reserved112 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4160 }; 4161 uint32_t Value; 4162 } DW6; 4163 union 4164 { 4165 //!< DWORD 7 4166 struct 4167 { 4168 uint32_t Reserved121 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 4169 uint32_t SegmentationEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< Segmentation Enable 4170 uint32_t SegmentationMapTemporalPredictionEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< Segmentation map temporal prediction enable 4171 uint32_t Reserved124 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 4172 uint32_t TilingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Tiling enable 4173 uint32_t Reserved126 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 4174 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC Stream IN 4175 uint32_t Reserved130 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 4176 uint32_t PakOnlyMultiPassEnable : __CODEGEN_BITFIELD(16, 16) ; //!< PAK-Only Multi-Pass Enable 4177 uint32_t Reserved139 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4178 }; 4179 uint32_t Value; 4180 } DW7; 4181 union 4182 { 4183 //!< DWORD 8 4184 struct 4185 { 4186 uint32_t Reserved155 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4187 }; 4188 uint32_t Value; 4189 } DW8; 4190 union 4191 { 4192 //!< DWORD 9 4193 struct 4194 { 4195 uint32_t Reserved170 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4196 }; 4197 uint32_t Value; 4198 } DW9; 4199 union 4200 { 4201 //!< DWORD 10 4202 struct 4203 { 4204 uint32_t Reserved182 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4205 }; 4206 uint32_t Value; 4207 } DW10; 4208 union 4209 { 4210 //!< DWORD 11 4211 struct 4212 { 4213 uint32_t Reserved199 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4214 }; 4215 uint32_t Value; 4216 } DW11; 4217 union 4218 { 4219 //!< DWORD 12 4220 struct 4221 { 4222 uint32_t Reserved209 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4223 }; 4224 uint32_t Value; 4225 } DW12; 4226 union 4227 { 4228 //!< DWORD 13 4229 struct 4230 { 4231 uint32_t Reserved218 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 4232 uint32_t RoiQpAdjustmentForZone1Stage3 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 (stage3) 4233 uint32_t RoiQpAdjustmentForZone2Stage3 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 (stage3) 4234 uint32_t RoiQpAdjustmentForZone3Stage3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 (stage3) 4235 uint32_t Reserved225 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4236 }; 4237 uint32_t Value; 4238 } DW13; 4239 union 4240 { 4241 //!< DWORD 14 4242 struct 4243 { 4244 uint32_t Reserved238 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4245 }; 4246 uint32_t Value; 4247 } DW14; 4248 union 4249 { 4250 //!< DWORD 15 4251 struct 4252 { 4253 uint32_t Reserved248 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4254 }; 4255 uint32_t Value; 4256 } DW15; 4257 union 4258 { 4259 //!< DWORD 16 4260 struct 4261 { 4262 uint32_t MinQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MINQP 4263 uint32_t MaxQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MAXQP 4264 uint32_t Reserved262 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4265 }; 4266 uint32_t Value; 4267 } DW16; 4268 union 4269 { 4270 //!< DWORD 17 4271 struct 4272 { 4273 uint32_t Reserved271 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 4274 uint32_t TemporalMVEnableForIntegerSearch : __CODEGEN_BITFIELD(20, 20) ; //!< Temporal MV disable for Integer Search 4275 uint32_t Reserved273 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 4276 }; 4277 uint32_t Value; 4278 } DW17; 4279 union 4280 { 4281 //!< DWORD 18 4282 struct 4283 { 4284 uint32_t Reserved286 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4285 }; 4286 uint32_t Value; 4287 } DW18; 4288 union 4289 { 4290 //!< DWORD 19 4291 struct 4292 { 4293 uint32_t Reserved298 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4294 }; 4295 uint32_t Value; 4296 } DW19; 4297 union 4298 { 4299 //!< DWORD 20 4300 struct 4301 { 4302 uint32_t Reserved312 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4303 }; 4304 uint32_t Value; 4305 } DW20; 4306 union 4307 { 4308 //!< DWORD 21 4309 struct 4310 { 4311 uint32_t IntraRefreshPos : __CODEGEN_BITFIELD( 0, 8) ; //!< IntraRefreshPos 4312 uint32_t Reserved322 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 4313 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< IntraRefreshMBSizeMinusOne 4314 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(24, 24) ; //!< IntraRefreshMode 4315 uint32_t Reserved326 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 4316 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(28, 31) ; //!< QP_ADJUSTMENT_FOR_ROLLING_I 4317 }; 4318 uint32_t Value; 4319 } DW21; 4320 union 4321 { 4322 //!< DWORD 22 4323 struct 4324 { 4325 uint32_t Reserved343 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4326 }; 4327 uint32_t Value; 4328 } DW22; 4329 union 4330 { 4331 //!< DWORD 23 4332 struct 4333 { 4334 uint32_t Reserved357 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4335 }; 4336 uint32_t Value; 4337 } DW23; 4338 union 4339 { 4340 //!< DWORD 24 4341 struct 4342 { 4343 uint32_t QpForSeg0 : __CODEGEN_BITFIELD( 0, 7) ; //!< QP for Seg0 4344 uint32_t QpForSeg1 : __CODEGEN_BITFIELD( 8, 15) ; //!< QP for Seg1 4345 uint32_t QpForSeg2 : __CODEGEN_BITFIELD(16, 23) ; //!< QP for Seg2 4346 uint32_t QpForSeg3 : __CODEGEN_BITFIELD(24, 31) ; //!< QP for Seg3 4347 }; 4348 uint32_t Value; 4349 } DW24; 4350 union 4351 { 4352 //!< DWORD 25 4353 struct 4354 { 4355 uint32_t QpForSeg4 : __CODEGEN_BITFIELD( 0, 7) ; //!< QP for Seg4 4356 uint32_t QpForSeg5 : __CODEGEN_BITFIELD( 8, 15) ; //!< QP for Seg5 4357 uint32_t QpForSeg6 : __CODEGEN_BITFIELD(16, 23) ; //!< QP for Seg6 4358 uint32_t QpForSeg7 : __CODEGEN_BITFIELD(24, 31) ; //!< QP for Seg7 4359 }; 4360 uint32_t Value; 4361 } DW25; 4362 union 4363 { 4364 //!< DWORD 26 4365 struct 4366 { 4367 uint32_t RdQpLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< RD QP Lambda 4368 uint32_t SadQpLambda : __CODEGEN_BITFIELD(16, 24) ; //!< SAD QP Lambda 4369 uint32_t Vp9DynamicSliceEnable : __CODEGEN_BITFIELD(25, 25) ; //!< VP9 Dynamic slice enable 4370 uint32_t Reserved394 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 4371 }; 4372 uint32_t Value; 4373 } DW26; 4374 union 4375 { 4376 //!< DWORD 27 4377 struct 4378 { 4379 uint32_t QpPrimeYDc : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY_DC 4380 uint32_t QpPrimeYAc : __CODEGEN_BITFIELD( 8, 15) ; //!< QPPRIMEY_AC 4381 uint32_t Reserved405 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4382 }; 4383 uint32_t Value; 4384 } DW27; 4385 union 4386 { 4387 //!< DWORD 28 4388 struct 4389 { 4390 uint32_t Reserved415 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4391 }; 4392 uint32_t Value; 4393 } DW28; 4394 union 4395 { 4396 //!< DWORD 29 4397 struct 4398 { 4399 uint32_t Reserved425 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4400 }; 4401 uint32_t Value; 4402 } DW29; 4403 union 4404 { 4405 //!< DWORD 30 4406 struct 4407 { 4408 uint32_t Reserved435 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4409 }; 4410 uint32_t Value; 4411 } DW30; 4412 union 4413 { 4414 //!< DWORD 31 4415 struct 4416 { 4417 uint32_t Reserved445 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4418 }; 4419 uint32_t Value; 4420 } DW31; 4421 union 4422 { 4423 //!< DWORD 32 4424 struct 4425 { 4426 uint32_t Reserved454 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4427 }; 4428 uint32_t Value; 4429 } DW32; 4430 union 4431 { 4432 //!< DWORD 33 4433 struct 4434 { 4435 uint32_t Reserved474 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4436 }; 4437 uint32_t Value; 4438 } DW33; 4439 union 4440 { 4441 //!< DWORD 34 4442 struct 4443 { 4444 uint32_t Reserved490 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4445 }; 4446 uint32_t Value; 4447 } DW34; 4448 union 4449 { 4450 //!< DWORD 35 4451 struct 4452 { 4453 uint32_t Reserved503 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4454 }; 4455 uint32_t Value; 4456 } DW35; 4457 union 4458 { 4459 //!< DWORD 36 4460 struct 4461 { 4462 uint32_t IntraRefreshBoundaryRef0 : __CODEGEN_BITFIELD( 0, 8) ; //!< IntraRefreshBoundary Ref0 4463 uint32_t Reserved513 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 4464 uint32_t IntraRefreshBoundaryRef1 : __CODEGEN_BITFIELD(10, 18) ; //!< IntraRefreshBoundary Ref1 4465 uint32_t Reserved515 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 4466 uint32_t IntraRefreshBoundaryRef2 : __CODEGEN_BITFIELD(20, 28) ; //!< IntraRefreshBoundary Ref2 4467 uint32_t Reserved517 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4468 }; 4469 uint32_t Value; 4470 } DW36; 4471 union 4472 { 4473 //!< DWORD 37 4474 struct 4475 { 4476 uint32_t Reserved530 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 4477 uint32_t Reserved533 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 4478 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Tile Replay enable 4479 uint32_t Reserved536 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4480 }; 4481 uint32_t Value; 4482 } DW37; 4483 union 4484 { 4485 //!< DWORD 38 4486 struct 4487 { 4488 uint32_t Reserved551 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4489 }; 4490 uint32_t Value; 4491 } DW38; 4492 union 4493 { 4494 //!< DWORD 39 4495 struct 4496 { 4497 uint32_t Reserved561 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4498 }; 4499 uint32_t Value; 4500 } DW39; 4501 union 4502 { 4503 //!< DWORD 40 4504 struct 4505 { 4506 uint32_t Reserved571 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4507 }; 4508 uint32_t Value; 4509 } DW40; 4510 union 4511 { 4512 //!< DWORD 41 4513 struct 4514 { 4515 uint32_t Reserved581 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4516 }; 4517 uint32_t Value; 4518 } DW41; 4519 union 4520 { 4521 //!< DWORD 42 4522 struct 4523 { 4524 uint32_t Reserved591 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4525 }; 4526 uint32_t Value; 4527 } DW42; 4528 union 4529 { 4530 //!< DWORD 43 4531 struct 4532 { 4533 uint32_t Reserved601 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4534 }; 4535 uint32_t Value; 4536 } DW43; 4537 union 4538 { 4539 //!< DWORD 44 4540 struct 4541 { 4542 uint32_t Reserved611 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4543 }; 4544 uint32_t Value; 4545 } DW44; 4546 union 4547 { 4548 //!< DWORD 45 4549 struct 4550 { 4551 uint32_t Reserved621 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4552 }; 4553 uint32_t Value; 4554 } DW45; 4555 union 4556 { 4557 //!< DWORD 46 4558 struct 4559 { 4560 uint32_t Reserved631 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4561 }; 4562 uint32_t Value; 4563 } DW46; 4564 union 4565 { 4566 //!< DWORD 47 4567 struct 4568 { 4569 uint32_t Reserved641 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4570 }; 4571 uint32_t Value; 4572 } DW47; 4573 union 4574 { 4575 //!< DWORD 48 4576 struct 4577 { 4578 uint32_t Reserved651 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4579 }; 4580 uint32_t Value; 4581 } DW48; 4582 union 4583 { 4584 //!< DWORD 49 4585 struct 4586 { 4587 uint32_t Reserved661 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4588 }; 4589 uint32_t Value; 4590 } DW49; 4591 union 4592 { 4593 //!< DWORD 50 4594 struct 4595 { 4596 uint32_t Reserved671 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4597 }; 4598 uint32_t Value; 4599 } DW50; 4600 4601 4602 //! \name Local enumerations 4603 4604 enum SUBOPB 4605 { 4606 SUBOPB_VDENCCMD2CMD = 9, //!< No additional details 4607 }; 4608 4609 enum SUBOPA 4610 { 4611 SUBOPA_UNNAMED0 = 0, //!< No additional details 4612 }; 4613 4614 enum OPCODE 4615 { 4616 OPCODE_VDENCPIPE = 1, //!< No additional details 4617 }; 4618 4619 enum PIPELINE 4620 { 4621 PIPELINE_MFXCOMMON = 2, //!< No additional details 4622 }; 4623 4624 enum COMMAND_TYPE 4625 { 4626 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4627 }; 4628 4629 //! \brief Explicit member initialization function 4630 VDENC_CMD2_CMD(); 4631 4632 static const size_t dwSize = 51; 4633 static const size_t byteSize = 204; 4634 }; 4635 }; 4636 4637 #pragma pack() 4638 4639 #endif // __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 4640