1 /** 2 * 3 * Copyright (C) 2018, Marvell International Ltd. and its affiliates 4 * 5 * SPDX-License-Identifier: BSD-2-Clause-Patent 6 * 7 **/ 8 #ifndef __ARMADA_BOARD_DESC_LIB_H__ 9 #define __ARMADA_BOARD_DESC_LIB_H__ 10 11 #include <Library/ArmadaSoCDescLib.h> 12 #include <Library/MvGpioLib.h> 13 14 // 15 // COMPHY controllers per-board description 16 // 17 typedef struct { 18 MV_SOC_COMPHY_DESC *SoC; 19 UINTN ComPhyDevCount; 20 } MV_BOARD_COMPHY_DESC; 21 22 // 23 // GPIO devices per-board description 24 // 25 typedef struct { 26 UINTN ChipId; 27 UINTN I2cAddress; 28 UINTN I2cBus; 29 } MV_GPIO_EXPANDER; 30 31 typedef struct { 32 GPIO_CONTROLLER *SoCGpio; 33 UINTN GpioDeviceCount; 34 MV_GPIO_EXPANDER *GpioExpanders; 35 UINTN GpioExpanderCount; 36 } MV_BOARD_GPIO_DESCRIPTION; 37 38 EFI_STATUS 39 EFIAPI 40 ArmadaBoardGpioExpanderGet ( 41 IN OUT MV_GPIO_EXPANDER **GpioExpanders, 42 IN OUT UINTN *GpioExpanderCount 43 ); 44 45 // 46 // I2C devices per-board description 47 // 48 typedef struct { 49 MV_SOC_I2C_DESC *SoC; 50 UINTN I2cDevCount; 51 } MV_BOARD_I2C_DESC; 52 53 // 54 // MDIO devices per-board description 55 // 56 typedef struct { 57 MV_SOC_MDIO_DESC *SoC; 58 UINTN MdioDevCount; 59 } MV_BOARD_MDIO_DESC; 60 61 // 62 // NonDiscoverableDevices per-board description 63 // 64 65 // 66 // AHCI devices per-board description 67 // 68 typedef struct { 69 MV_SOC_AHCI_DESC *SoC; 70 UINTN AhciDevCount; 71 } MV_BOARD_AHCI_DESC; 72 73 // 74 // SDMMC devices per-board description 75 // 76 typedef enum { 77 RemovableSlot, 78 EmbeddedSlot, 79 SharedBusSlot, 80 UnknownSlot 81 } MV_SDMMC_SLOT_TYPE; 82 83 typedef struct { 84 MV_SOC_SDMMC_DESC *SoC; 85 UINTN SdMmcDevCount; 86 BOOLEAN Xenon1v8Enabled; 87 BOOLEAN Xenon8BitBusEnabled; 88 BOOLEAN XenonSlowModeEnabled; 89 UINT8 XenonTuningStepDivisor; 90 MV_SDMMC_SLOT_TYPE SlotType; 91 } MV_BOARD_SDMMC_DESC; 92 93 EFI_STATUS 94 EFIAPI 95 ArmadaBoardDescSdMmcGet ( 96 OUT UINTN *SdMmcDevCount, 97 OUT MV_BOARD_SDMMC_DESC **SdMmcDesc 98 ); 99 100 // 101 // XHCI devices per-board description 102 // 103 typedef struct { 104 MV_SOC_XHCI_DESC *SoC; 105 UINTN XhciDevCount; 106 } MV_BOARD_XHCI_DESC; 107 108 // 109 // PCIE controllers description 110 // 111 typedef struct { 112 EFI_PHYSICAL_ADDRESS PcieDbiAddress; 113 EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; 114 BOOLEAN HaveResetGpio; 115 MV_GPIO_PIN PcieResetGpio; 116 UINT64 PcieBusMin; 117 UINT64 PcieBusMax; 118 UINT64 PcieIoTranslation; 119 UINT64 PcieIoWinBase; 120 UINT64 PcieIoWinSize; 121 UINT64 PcieMmio32Translation; 122 UINT64 PcieMmio32WinBase; 123 UINT64 PcieMmio32WinSize; 124 UINT64 PcieMmio64Translation; 125 UINT64 PcieMmio64WinBase; 126 UINT64 PcieMmio64WinSize; 127 } MV_PCIE_CONTROLLER; 128 129 typedef struct { 130 MV_PCIE_CONTROLLER CONST *PcieControllers; 131 UINTN PcieControllerCount; 132 } MV_BOARD_PCIE_DESCRIPTION; 133 134 /** 135 Return the number and description of PCIE controllers used on the platform. 136 137 @param[in out] **PcieControllers Array containing PCIE controllers' 138 description. 139 @param[in out] *PcieControllerCount Amount of used PCIE controllers. 140 141 @retval EFI_SUCCESS The data were obtained successfully. 142 @retval EFI_NOT_FOUND None of the controllers is used. 143 @retval other Return error status. 144 145 **/ 146 EFI_STATUS 147 EFIAPI 148 ArmadaBoardPcieControllerGet ( 149 IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, 150 IN OUT UINTN *PcieControllerCount 151 ); 152 153 // 154 // PP2 NIC devices per-board description 155 // 156 typedef struct { 157 MV_SOC_PP2_DESC *SoC; 158 UINT8 Pp2DevCount; 159 } MV_BOARD_PP2_DESC; 160 161 // 162 // UTMI PHY devices per-board description 163 // 164 typedef struct { 165 MV_SOC_UTMI_DESC *SoC; 166 UINTN UtmiDevCount; 167 UINTN UtmiPortType; 168 } MV_BOARD_UTMI_DESC; 169 #endif /* __ARMADA_SOC_DESC_LIB_H__ */ 170