1 /* 2 * extractInt.h -- 3 * 4 * Defines things shared internally by the extract module of Magic, 5 * but not generally needed outside the extract module. 6 * 7 * rcsid "$Header: /usr/cvsroot/magic-8.0/extract/extractInt.h,v 1.7 2010/08/10 00:18:46 tim Exp $" 8 * 9 * ********************************************************************* 10 * * Copyright (C) 1985, 1990 Regents of the University of California. * 11 * * Permission to use, copy, modify, and distribute this * 12 * * software and its documentation for any purpose and without * 13 * * fee is hereby granted, provided that the above copyright * 14 * * notice appear in all copies. The University of California * 15 * * makes no representations about the suitability of this * 16 * * software for any purpose. It is provided "as is" without * 17 * * express or implied warranty. Export of this software outside * 18 * * of the United States of America may require an export license. * 19 * ********************************************************************* 20 * 21 * This module has been modified at DEC/WRL and Stanford University. 22 * The above disclaimers apply. 23 * 24 */ 25 26 #ifndef _EXTRACTINT_H 27 #define _EXTRACTINT_H 28 29 #include "database/database.h" 30 31 #undef NT 32 #define NT TT_MAXTYPES 33 #undef NP 34 #define NP PL_MAXTYPES 35 36 /* ------------------------ Capacitance Values ------------------------- */ 37 38 typedef double CapValue; /* No longer allowed to define back to integer, 39 * as this touches too many parts of the code. 40 */ 41 42 /* Procs to manipulate capacitance hash tables. */ 43 extern CapValue extGetCapValue(); 44 extern void extSetCapValue(); 45 extern void extCapHashKill(); 46 47 typedef int ResValue; /* Warning: in some places resistances are stored 48 * as ints. This is here for documentation only. 49 */ 50 51 typedef struct { 52 char areaType; /* ANTENNAMODEL_SURFACE or ANTENNAMODEL_SIDEWALL */ 53 float ratioGate; 54 float ratioDiffA; /* Proportional */ 55 float ratioDiffB; /* Constant */ 56 } RatioValues; 57 58 /* Antenna models */ 59 #define ANTENNAMODEL_PARTIAL 0x01 60 #define ANTENNAMODEL_CUMULATIVE 0x02 61 #define ANTENNAMODEL_SURFACE 0x04 62 #define ANTENNAMODEL_SIDEWALL 0x08 63 64 /* ------------------------ Parameter lists --------------------------- */ 65 66 /* These lists keep track of what parameter names subcircuit definitions 67 * use for parameters that magic knows how to generate. Valid pl_param 68 * values are a (area), p (perimeter), w (width), l (length), s (substrate), 69 * x (position), and y (position). Values "a" and "p" may be followed by 70 * an additional integer indicating the terminal from which the value is 71 * used (e.g., source area, drain perimeter, etc.). An integer "0" 72 * indicates the device identifier region (e.g., gate) and is equivalent 73 * to having no integer at all. Integers "1" and up indicate terminals, 74 * in order. 75 */ 76 77 typedef struct pl 78 { 79 int pl_count; /* Share this list. . . */ 80 char pl_param[2]; /* Default character for parameter */ 81 char *pl_name; /* Full name for parameter */ 82 double pl_scale; /* Scaling of parameter, if specified */ 83 struct pl *pl_next; /* Next parameter in list */ 84 } ParamList; 85 86 /* -------------------------- Label lists ----------------------------- */ 87 88 /* 89 * List of labels for a node. 90 * We keep around pointers to the entire labels for 91 * later figuring out which are attached to the gates, 92 * sources, or drains of transistors. 93 */ 94 typedef struct ll 95 { 96 Label *ll_label; /* Actual Label in the source CellDef */ 97 struct ll *ll_next; /* Next LabelList in this region */ 98 int ll_attr; /* Which terminal of a transistor this is 99 * an attribute of. 100 */ 101 } LabelList; 102 103 #define LL_NOATTR -1 /* Value for ll_attr above if the label is 104 * not a transistor attribute. 105 */ 106 #define LL_GATEATTR -2 /* Value for ll_attr if the label is a gate 107 * attribute, rather than one of the diffusion 108 * terminals' attributes. 109 */ 110 #define LL_SORTATTR -3 /* value for ll_attr used in 111 * ExtBasic.c/ExtSortTerminals() to swap 112 * the attributes as well as the regions 113 * -- Stefanos 5/96 114 */ 115 #define LL_PORTATTR -4 /* value for ll_attr used to declare 116 * the label to be a subcircuit port 117 * -- Tim 5/02 118 */ 119 /* 120 * Types of labels. 121 * These can be or'd into a mask and passed to extLabType(). 122 */ 123 #define LABTYPE_NAME 0x01 /* Normal node name */ 124 #define LABTYPE_NODEATTR 0x02 /* Node attribute */ 125 #define LABTYPE_GATEATTR 0x04 /* Transistor gate attribute */ 126 #define LABTYPE_TERMATTR 0x08 /* Transistor terminal (source/drain) 127 * attribute. 128 */ 129 #define LABTYPE_PORTATTR 0x10 /* Subcircuit port */ 130 131 /* ----------------------------- Regions ------------------------------ */ 132 133 /* 134 * The following are the structures built up by the various 135 * clients of ExtFindRegions. The general rule for these 136 * structures is that their initial fields must be identical 137 * to those in a Region, but subsequent fields are up to 138 * the individual client. 139 * 140 * Regions marked as GENERIC are the types accepted by 141 * procedures in ExtRegion.c. 142 */ 143 144 /* 145 * GENERIC Region struct. 146 * All this provides is a pointer to the next Region. 147 * This is the type passed to functions like ExtFreeRegions, 148 * and is the type returned by ExtFindRegions. Clients should 149 * cast pointers of this type to their own, client type. 150 */ 151 typedef struct reg 152 { 153 struct reg *reg_next; /* Next region in list */ 154 } Region; 155 156 /* 157 * GENERIC region with labels. 158 * Any other structure that wants to reference node names 159 * must include the same fields as this one as its first part. 160 */ 161 typedef struct lreg 162 { 163 struct lreg *lreg_next; /* Next region in list */ 164 int lreg_pnum; /* Lowest numbered plane in this region */ 165 int lreg_type; /* Type of tile that contains lreg_ll */ 166 Point lreg_ll; /* Lower-leftmost point in this region on 167 * plane lreg_pnum. We take the min first 168 * in X, then in Y. 169 */ 170 LabelList *lreg_labels; /* List of labels for this region. These are 171 * any labels connected to the geometry making 172 * up this region. If the list is empty, make 173 * up a name from lreg_pnum and lreg_ll. 174 */ 175 } LabRegion; 176 177 /* 178 * Node region: labelled region with resistance and capacitance. 179 * Used for each node in the flat extraction of a cell. 180 */ 181 182 typedef struct 183 { 184 int pa_perim; 185 dlong pa_area; 186 } PerimArea; 187 188 typedef struct nreg 189 { 190 struct nreg *nreg_next; /* Next region in list */ 191 int nreg_pnum; /* Lowest numbered plane in this region */ 192 int nreg_type; /* Type of tile that contains nreg_ll */ 193 Point nreg_ll; /* Lower-leftmost point in this region on 194 * plane nreg_pnum. We take the min first 195 * in X, then in Y. 196 */ 197 LabelList *nreg_labels; /* See LabRegion for description */ 198 CapValue nreg_cap; /* Capacitance to ground */ 199 ResValue nreg_resist; /* Resistance estimate */ 200 PerimArea nreg_pa[1]; /* Dummy; each node actually has 201 * ExtCurStyle->exts_numResistClasses 202 * array elements allocated to it. 203 */ 204 } NodeRegion; 205 206 /* 207 * Transistor region: labelled region with perimeter and area. 208 * Used for each transistor in the flat extraction of a cell. 209 */ 210 typedef struct treg 211 { 212 struct treg *treg_next; /* Next region in list */ 213 int treg_pnum; /* UNUSED */ 214 int treg_type; /* Type of tile that contains treg_ll */ 215 Point treg_ll; /* UNUSED */ 216 LabelList *treg_labels; /* Attribute list */ 217 Tile *treg_tile; /* Some tile in the channel */ 218 int treg_area; /* Area of channel */ 219 } TransRegion; 220 221 typedef struct { /* Maintain plane information when pushing */ 222 Rect area; /* tiles on the node stack. For use with */ 223 int plane; /* function extNbrPushFunc(). */ 224 } PlaneAndArea; 225 226 /* Structure to be kept in a hash table of node regions for the current */ 227 /* extract cell. It tracks the original substrate cap calculated for */ 228 /* each region used in the "node" line output, the final substrate cap */ 229 /* calculated after taking all subcircuits into account, and a running */ 230 /* total of all corrections to the node's substrate cap generated in */ 231 /* "merge" lines by extSubtree() and extArray(). After both routines */ 232 /* have run, any unaccounted capacitance is output to the .ext file as */ 233 /* a "subcap" line. */ 234 235 typedef struct { 236 NodeRegion *subcap_reg; 237 CapValue subcap_orig; 238 CapValue subcap_final; 239 CapValue subcap_adjust; 240 } SubCapAdjust; 241 242 /* 243 * Argument passed to filter functions for finding regions. 244 */ 245 typedef struct 246 { 247 TileTypeBitMask *fra_connectsTo; /* Array of TileTypeBitMasks. The 248 * element fra_connectsTo[t] has a 249 * bit set for each type that 250 * connects to 't'. 251 */ 252 CellDef *fra_def; /* Def being searched */ 253 int fra_pNum; /* Plane currently searching */ 254 ClientData fra_uninit; /* This value appears in the ti_client 255 * field of a tile if it's not yet 256 * been visited. 257 */ 258 Region *(*fra_first)(); /* Function to init new region */ 259 int (*fra_each)(); /* Function for each tile in region */ 260 Region *fra_region; /* Ptr to Region struct for current 261 * region. May be set by fra_first 262 * and used by fra_each. 263 */ 264 } FindRegion; 265 266 #define TILEAREA(tp) ((TOP(tp) - BOTTOM(tp)) * (RIGHT(tp) - LEFT(tp))) 267 268 /* -------------------- Perimeter of a region ------------------------- */ 269 270 /* 271 * Segment of the boundary of a region whose perimeter 272 * is being traced by ExtTracePerimeter() and extEnumTilePerim(). 273 */ 274 typedef struct 275 { 276 Tile *b_inside; /* Pointer to tile just inside segment */ 277 Tile *b_outside; /* Pointer to tile just outside segment */ 278 Rect b_segment; /* Actual coordinates of segment */ 279 unsigned char b_direction; /* Direction following segment (see below) */ 280 int b_plane; /* extract argument for extSideOverlap */ 281 } Boundary; 282 283 #define BoundaryLength(bp) \ 284 ((bp)->b_segment.r_xtop - (bp)->b_segment.r_xbot \ 285 + (bp)->b_segment.r_ytop - (bp)->b_segment.r_ybot) 286 287 /* Directions in which we can be following the boundary of a perimeter */ 288 289 #define BD_LEFT 1 /* Inside is to right */ 290 #define BD_TOP 2 /* Inside is below */ 291 #define BD_RIGHT 4 /* Inside is to left */ 292 #define BD_BOTTOM 8 /* Inside is above */ 293 294 /* -------- Yank buffers for hierarchical and array extraction -------- */ 295 296 extern CellUse *extYuseCum; 297 extern CellDef *extYdefCum; 298 299 /* --------------- Argument passed to extHierYankFunc ----------------- */ 300 301 typedef struct 302 { 303 Rect *hy_area; /* Area (in parent coordinates) to be yanked */ 304 CellUse *hy_target; /* Yank into this use */ 305 bool hy_prefix; /* If TRUE, prefix labels with use id */ 306 } HierYank; 307 308 /* ----- Arguments to filter functions in hierarchical extraction ---- */ 309 310 /* 311 * The following defines an extracted subtree. 312 * The CellUse et_use will be either a cell we are extracting, 313 * or a flattened subtree. If et_lookNames is non-NULL, it 314 * points to a CellDef that we should look in for node names. 315 */ 316 typedef struct extTree 317 { 318 CellUse *et_use; /* Extracted cell, usually flattened */ 319 CellUse *et_realuse; /* If et_use is flattened, et_realuse 320 * points to the unflattened subtree's 321 * root use; otherwise it is NULL. 322 */ 323 CellDef *et_lookNames; /* See above */ 324 NodeRegion *et_nodes; /* List of nodes */ 325 HashTable et_coupleHash; /* Table for coupling capacitance. 326 * key is type CoupleKey 327 * value is pointer to type CapValue 328 */ 329 struct extTree *et_next; /* Next one in list */ 330 } ExtTree; 331 332 /* 333 * The following structure contains information passed down 334 * through several levels of filter functions during hierarchical 335 * extraction. 336 * 337 * The procedure ha_nodename is used to map from a tile into the 338 * name of the node to which that tile belongs. It should be of 339 * the following format: 340 * 341 * char * 342 * proc(tp, et, ha) 343 * Tile *tp; 344 * ExtTree *et; 345 * HierExtractArg *ha; 346 * { 347 * } 348 * 349 * It should always return a non-NULL string; if the name of a 350 * node can't be determined, the string can be "(none)". 351 */ 352 typedef struct 353 { 354 FILE *ha_outf; /* The .ext file being written */ 355 CellUse *ha_parentUse; /* Use pointing to the def being extracted */ 356 char *(*ha_nodename)(); /* Map (tp, et, ha) into nodename; see above */ 357 ExtTree ha_cumFlat; /* Cumulative yank buffer */ 358 NodeRegion *ha_parentReg; /* Node region list from parent def */ 359 HashTable ha_connHash; /* Connections made during hier processing */ 360 361 /* All areas are in parent coordinates */ 362 363 Rect ha_interArea; /* Area of whole interaction being considered */ 364 Rect ha_clipArea; /* Only consider capacitance, perimeter, and 365 * area that come from inside this area. This 366 * rectangle is contained within ha_interArea. 367 */ 368 CellUse *ha_subUse; /* Root of the subtree being processed now */ 369 Rect ha_subArea; /* Area of ha_subUse inside the interaction 370 * area, i.e, contained within ha_interArea. 371 */ 372 Tile *hierOneTile; /* Used in ExtHier.c, tile from extHierOneFlat */ 373 int hierPNum; /* Used in ExtHier.c, plane of tile above */ 374 TileType hierType; /* Used in ExtHier.c, type of tile above */ 375 int hierPNumBelow; /* Used in ExtHier.c, plane of tile below */ 376 } HierExtractArg; 377 378 /* 379 * Normally, nodes in overlapping subcells are expected to have labels 380 * in the area of overlap. When this is not the case, we have to use 381 * a much more expensive algorithm for finding the labels attached to 382 * the subcells' geometry in the overlap area. The following structure 383 * is used to hold information about the search in progress for such 384 * labels. 385 */ 386 typedef struct 387 { 388 HierExtractArg *hw_ha; /* Describes context of search */ 389 Label *hw_label; /* We update hw_label with a ptr to a 390 * newly allocated label if successful. 391 */ 392 Rect hw_area; /* Area in parent coordinates of the 393 * area where we're searching. 394 */ 395 bool hw_autogen; /* If TRUE, we trace out all geometry 396 * in the first node in the first cell 397 * found to overlap the search area, 398 * and use the internal name for that 399 * node. 400 */ 401 TerminalPath hw_tpath; /* Hierarchical path down to label 402 * we are searching for, rooted at 403 * the parent being extracted. 404 */ 405 TileTypeBitMask hw_mask; /* Mask of tile types that connect to 406 * the tile whose node is to be found, 407 * and which are on the same plane. 408 * Used when calling ExtFindRegions. 409 */ 410 bool hw_prefix; /* If FALSE, we skip the initial 411 * use identifier when building 412 * hierarchical labels (as when 413 * extracting arrays; see hy_prefix 414 * in the HierYank struct). 415 */ 416 int (*hw_proc)(); 417 } HardWay; 418 419 /* --------------------- Coupling capacitance ------------------------- */ 420 421 /* 422 * The following structure is the hash key used for computing 423 * internodal coupling capacitance. Each word is a pointer to 424 * one of the nodes being coupled. By convention, the first 425 * word is the lesser of the two NodeRegion pointers. 426 */ 427 typedef struct 428 { 429 NodeRegion *ck_1, *ck_2; 430 } CoupleKey; 431 432 extern void extCoupleHashZero(); /* Clears out all pointers to data in table */ 433 434 /* ------------------ Interface to debugging module ------------------- */ 435 436 extern ClientData extDebugID; /* Identifier returned by the debug module */ 437 438 /* ----------------- Technology-specific information ------------------ */ 439 440 /* 441 * Structure used to define sidewall coupling capacitances. 442 */ 443 typedef struct edgecap 444 { 445 struct edgecap *ec_next; /* Next edge capacitance rule in list */ 446 CapValue ec_cap; /* Capacitance (attofarads) */ 447 TileTypeBitMask ec_near; /* Types closest to causing edge, or in 448 * the case of sideOverlaps, the 449 * types we are overlapping. 450 */ 451 TileTypeBitMask ec_far; /* Types farthest from causing edge, or 452 * in the case of sideOverlaps, the 453 * types that shield the edge from 454 * the overlaped tile. 455 */ 456 int ec_pmask; /* specifies which planes are to be */ 457 /* used. */ 458 } EdgeCap; 459 460 461 /* A type used to determine if current style needs planeorder or not */ 462 typedef enum { noPlaneOrder, needPlaneOrder, seenPlaneOrder } planeOrderStatus ; 463 464 /* 465 * Because a large TT_MAXTYPES value quickly generates huge extract section 466 * structures, we want to keep around only the style names, and dynamically 467 * load and destroy the extract section values as needed, when doing an 468 * extraction command. 469 */ 470 471 typedef struct extkeep 472 { 473 struct extkeep *exts_next; 474 char *exts_name; 475 } ExtKeep; 476 477 /* 478 * Structure used to define transistors and other extracted devices 479 * One of these records is kept per tile type. However, the record 480 * can link to additional records through the "exts_next" record, 481 * so that multiple extraction devices can be defined for the same 482 * tile type, provided that each definition has a unique combination 483 * of exts_deviceSDTypes and exts_deviceSubstrateTypes. 484 */ 485 486 typedef struct extDevice 487 { 488 /* Name of each transistor type as output in .ext file */ 489 char *exts_deviceName; 490 491 /* List of parameter names for each subcircuit type */ 492 ParamList *exts_deviceParams; 493 494 /* Device class for each layer type */ 495 char exts_deviceClass; 496 497 /* 498 * Per-square resistances for each possible transistor type, 499 * in the various regions that such a type might operate. 500 * The only operating region currently used is "linear", 501 * which the resistance extractor uses in its thresholding 502 * operation. NOTE: resistances in this table are in OHMS 503 * per square, not MILLIOHMS! 504 */ 505 506 HashTable exts_deviceResist; 507 ResValue exts_linearResist; 508 509 /* 510 * Mask of the types of tiles that connect to the channel terminals 511 * of a transistor type. The intent is that these will be the 512 * diffusion terminals of a transistor, ie, its source and drain. 513 * UPDATED May, 2008: Record is a list of type masks, allowing 514 * multiple terminal types in the case of, e.g., high-voltage 515 * or other asymmetric devices. The last entry in the list should 516 * be equal to DBSpaceBits. 517 */ 518 TileTypeBitMask *exts_deviceSDTypes; 519 520 /* 521 * Maximum number of terminals (source/drains) per transistor type. 522 * This table exists to allow the possibility of transistors with 523 * more than two diffusion terminals at some point in the future. 524 */ 525 int exts_deviceSDCount; 526 527 /* Currently unused: gate-source capacitance per unit perimeter */ 528 CapValue exts_deviceSDCap; 529 530 /* Currently unused: gate-channel capacitance per unit area */ 531 CapValue exts_deviceGateCap; 532 533 /* 534 * Each type of transistor has a substrate node. By default, 535 * it is the one given by exts_deviceSubstrateName[t]. However, 536 * if the mask exts_deviceSubstrateTypes is non-zero, and if 537 * the transistor overlaps material of one of the types in the 538 * mask, then the transistor substrate node is the node of the 539 * material it overlaps. 540 */ 541 char *exts_deviceSubstrateName; 542 TileTypeBitMask exts_deviceSubstrateTypes; 543 544 /* 545 * Each device type can have any number of extract models based 546 * on identifier layers (such as thickox, esd, etc.) 547 */ 548 TileTypeBitMask exts_deviceIdentifierTypes; 549 550 struct extDevice *exts_next; 551 } ExtDevice; 552 553 /* 554 * Parameters for the process being extracted. 555 * We try to use use integers here, rather than floats, to be nice to 556 * machines like Sun workstations that don't have hardware 557 * floating point. 558 * 559 * In the case of capacitances, though, we may have to use floats, depending 560 * upon the type CapValue. In some newer processes the capacitance per 561 * lambda^2 is less than 1 attofarad. 562 */ 563 564 typedef struct extstyle 565 { 566 char exts_status; /* Loaded, not loaded, or pending */ 567 char *exts_name; /* Name of this style */ 568 569 /* 570 * Connectivity tables. 571 * Each table is an array of TileTypeBitMasks indexed by TileType. 572 * The i-th element of each array is a mask of those TileTypes 573 * to which type 'i' connects. 574 */ 575 576 /* Everything is connected to everything else in this table */ 577 TileTypeBitMask exts_allConn[NT]; 578 579 /* 580 * Connectivity for determining electrical nodes. 581 * This should be essentially the same as DBConnectTbl[]. 582 */ 583 TileTypeBitMask exts_nodeConn[NT]; 584 585 /* 586 * Connectivity for determining resistive regions. 587 * Two types should be marked as connected here if 588 * they are both connected in exts_nodeConnect[], and 589 * if they both have the same resistance per square. 590 */ 591 TileTypeBitMask exts_resistConn[NT]; 592 593 /* 594 * Connectivity for determining devices. 595 * Each devices type should connect only to itself. 596 * Nothing else should connect to anything else. 597 */ 598 TileTypeBitMask exts_deviceConn[NT]; 599 600 /* 601 * Set of types to be considered for extraction. Types not in 602 * this list cannot be nodes (e.g., implant layers) 603 */ 604 TileTypeBitMask exts_activeTypes; 605 606 /* 607 * Sheet resistivity for each tile type, in milli-ohms per square. 608 * For types that are transistors or capacitors, this corresponds 609 * to the sheet resistivity of the gate. 610 */ 611 612 /* Maps from a tile type to the index of its sheet resistance entry */ 613 int exts_typeToResistClass[NT]; 614 615 /* Gives a mask of neighbors of a type with different resistivity */ 616 TileTypeBitMask exts_typesResistChanged[NT]; 617 618 /* 619 * Resistance information is also provided by the following tables: 620 * exts_typesByResistClass[] is an array of masks of those types 621 * having the same sheet resistivity, for each different value 622 * of sheet resistivity; exts_resistByResistClass[] is a parallel array 623 * giving the actual value of sheet resistivity. Both are indexed 624 * from 0 up to (but not including) exts_numResistClasses. 625 */ 626 TileTypeBitMask exts_typesByResistClass[NT]; 627 ResValue exts_resistByResistClass[NT]; 628 int exts_numResistClasses; 629 630 /* Resistance per type */ 631 ResValue exts_sheetResist[NT]; 632 633 /* 634 * Resistances for via holes, given in milliohms. Number of 635 * cuts is determined by the "cifoutput" style "squares" 636 * parameters. 637 */ 638 ResValue exts_viaResist[NT]; 639 640 /* 641 * Amount to scale resistance of a material on a corner. 642 * Defauts to 1.0. Often set to 0.5. 643 */ 644 float exts_cornerChop[NT]; 645 646 /* Layer height and thickness used by the geometry extractor */ 647 float exts_height[NT]; 648 float exts_thick[NT]; 649 650 char exts_antennaModel; 651 652 /* Antenna area ratio for each layer */ 653 RatioValues exts_antennaRatio[NT]; 654 655 /* Mask of types that tie down antennas */ 656 TileTypeBitMask exts_antennaTieTypes; 657 658 /* 659 * Capacitance to substrate for each tile type, in units of 660 * attofarads per square lambda. 661 */ 662 663 /* 664 * Capacitance per unit area. This is zero for explicit capacitor 665 * types, which handle gate-channel capacitance specially. For 666 * transistor types, this is at best an approximation that is 667 * truly valid only when the transistor is switched off. 668 */ 669 CapValue exts_areaCap[NT]; 670 671 /* 672 * Capacitance per unit perimeter. Sidewall capacitance depends both 673 * on the type inside the perimeter as well as the type outside it, 674 * so the table is doubly indexed by TileType. 675 * 676 * The mask exts_perimCapMask[t] contains bits for all those TileTypes 677 * 's' such that exts_perimCap[t][s] is nonzero. 678 */ 679 CapValue exts_perimCap[NT][NT]; 680 TileTypeBitMask exts_perimCapMask[NT]; 681 682 /* 683 * Overlap coupling capacitance for each pair of tile types, in units 684 * of attofarads per square lambda of overlap. 685 * Internodal capacitance due to overlap only occurs between tile 686 * types on different tile planes that are not shielded by intervening 687 * tiles. 688 */ 689 690 /* 691 * The mask exts_overlapPlanes is a mask of those planes that must 692 * be searched for tiles having overlap capacitance, and the mask 693 * exts_overlapTypes[p] is those types having overlap capacitance 694 * on each plane p. The intent is that exts_overlapTypes[p] lists 695 * only those types t for which some entry of exts_overlapCap[t][s] 696 * is non-zero. 697 */ 698 PlaneMask exts_overlapPlanes; 699 TileTypeBitMask exts_overlapTypes[NP]; 700 701 /* 702 * The mask exts_overlapOtherPlanes[t] is a mask of the planes that 703 * must be searched for tiles having overlap capacitance with tiles 704 * of type 't', and exts_overlapOtherTypes[t] is a mask of the types 705 * with which our overlap capacitance is non-zero. 706 */ 707 TileTypeBitMask exts_overlapOtherTypes[NT]; 708 PlaneMask exts_overlapOtherPlanes[NT]; 709 710 /* 711 * Both exts_overlapShieldTypes[][] and exts_overlapShieldPlanes[][] 712 * are indexed by the same pair of types used to index the table 713 * exts_overlapCap[][]; they identify the types and planes that 714 * shield capacitance between their index types. 715 */ 716 TileTypeBitMask exts_overlapShieldTypes[NT][NT]; 717 PlaneMask exts_overlapShieldPlanes[NT][NT]; 718 719 /* 720 * The table extOverlapCap[][] is indexed by two types to give the 721 * overlap coupling capacitance between them, per unit area. Only 722 * one of extOverlapCap[i][j] and extOverlapCap[j][i] should be 723 * nonzero. The capacitance to substrate of the tile of type 'i' 724 * is deducted when an overlap between i and j is detected, if 725 * extOverlapCap[i][j] is nonzero. This is only done, however, if 726 * tile i is below tile j in exts_planeOrder; 727 */ 728 CapValue exts_overlapCap[NT][NT]; 729 730 /* Specifies an ordering of the planes, so we can determine which 731 * tile is above another one. This is used only when determining 732 * if we should subtract capacitance to substrate for overlap and 733 * sideoverlap rules. If no planeorder is specified and the style 734 * does not contain a noplaneordering command a warning is issued 735 * and the default planeorder is used for the style. 736 */ 737 int exts_planeOrder[NP]; 738 /* set/reset with planeorder commands to determine whether 739 * we will warn if no planeorder is specified. This is done 740 * because at Stanford we use a lot of diagnostic extraction 741 * styles (for floating wells etc.) and we don't want to specify 742 * the planeorder for each and every one of them. 743 */ 744 planeOrderStatus exts_planeOrderStatus; 745 746 747 /* 748 * Sidewall coupling capacitance. This capacitance is between edges 749 * on the same plane, and is in units of attofarads. It is multiplied 750 * by the value interpolated from a fringing-field table indexed by the 751 * common length of the pair of edges divided by their separation: 752 * 753 * | | 754 * E1 +----------------------------+ 755 * ^ 756 * +--- distance between edges 757 * v 758 * +-----------------------------------+ E2 759 * | | 760 * 761 * <-----------------------> length in common 762 */ 763 764 /* 765 * The entry exts_sideCoupleCap[i][j] is a list of the coupling 766 * capacitance info between edges with type 'i' on the inside 767 * and 'j' on the outside, and other kinds of edges. 768 */ 769 EdgeCap *exts_sideCoupleCap[NT][NT]; 770 771 /* 772 * exts_sideCoupleOtherEdges[i][j] is a mask of those types on the 773 * far sides of edges to which an edge with 'i' on the inside and 774 * 'j' on the outside has coupling capacitance. 775 */ 776 TileTypeBitMask exts_sideCoupleOtherEdges[NT][NT]; 777 778 /* 779 * We search out a distance exts_sideCoupleHalo from each edge 780 * for other types with which we have coupling capacitance. 781 * This value determines how much extra gets yanked when 782 * computing hierarchical adjustments, so should be kept 783 * small to insure reasonable performance. 784 */ 785 int exts_sideCoupleHalo; 786 787 /* 788 * Sidewall-overlap coupling capacitance. 789 * This is between an edge on one plane and a type on another plane 790 * that overlaps the edge (from the outside of the edge), and is in 791 * units of attofarads per lambda. 792 * 793 * When an edge with sidewall capacitance to substrate is found to 794 * overlap a type to which it has sidewall overlap capacitance, the 795 * original capacitance to substrate is replaced with the overlap 796 * capacitance to the tile overlapped, if the edge is above the tile 797 * being overlapped (according to ext_planeOrder). If the tiles are 798 * the other way around, then this replacement is not done. 799 */ 800 801 /* 802 * The entry exts_sideOverlapCap[i][j] is a list of the coupling 803 * capacitance info between edges with type 'i' on the inside 804 * and 'j' on the outside, and other kinds of tiles on other 805 * planes. The ec_near mask in the EdgeCap record identifies the 806 * types to which we have sidewall overlap capacitance, and the 807 * ec_far mask identifies the types that shield the tiles preventing 808 * a capacitance. 809 */ 810 EdgeCap *exts_sideOverlapCap[NT][NT]; 811 812 /* 813 * extSideOverlapOtherTypes[i][j] is a mask of those types to which 814 * an edge with 'i' on the inside and 'j' on the outside has coupling 815 * capacitance. extSideOverlapOtherPlanes[i][j] is a mask of those 816 * planes to which edge [i][j] has overlap coupling capacitance. 817 * exts_sideOverlapShieldPlanes[s][t] is a list of the planes that 818 * need to be examined for shielding material when we are considering 819 * a sidewall overlap capacitor between types s and t. This may 820 * be the "or" of the planes needed by several sideoverlap rules, 821 * since there can be several types of edges in which type s is 822 * the "intype" member and the "outtype" member varies. Note that 823 * sideOverlapShieldPlanes is indexed like overlapShieldPlanes, not 824 * like sideOverlapOtherPlanes. 825 */ 826 PlaneMask exts_sideOverlapOtherPlanes[NT][NT]; 827 TileTypeBitMask exts_sideOverlapOtherTypes[NT][NT]; 828 PlaneMask exts_sideOverlapShieldPlanes[NT][NT]; 829 830 /* 831 * Both exts_overlapShieldTypes[][] and exts_overlapShieldPlanes[][] 832 * are indexed by the same pair of types used to index the table 833 * exts_overlapCap[][]; they identify the types and planes that 834 * shield capacitance between their index types. 835 */ 836 837 838 /* Common to both sidewall coupling and sidewall overlap */ 839 840 /* 841 * exts_sideTypes[p] is a mask of those types 't' having sidewall 842 * coupling or sidewall overlap capacitance on plane p (i.e, for 843 * which a bin in exts_sideCoupleCap[t][] or exts_sideOverlapCap[t][] 844 * is non-empty), and exts_sidePlanes a mask of those planes containing 845 * tiles in exts_sideTypes[]. 846 */ 847 PlaneMask exts_sidePlanes; 848 TileTypeBitMask exts_sideTypes[NP]; 849 850 /* 851 * The mask exts_sideEdges[i] is just a mask of those types j for 852 * which either exts_sideCoupleCap[i][j] or exts_sideOverlapCap[i][j] 853 * is non-empty. 854 */ 855 TileTypeBitMask exts_sideEdges[NT]; 856 857 /* Devices */ 858 859 /* Contains one for each type of device, zero for all other tile types */ 860 TileTypeBitMask exts_deviceMask; 861 862 /* All information about a device goes in this record (see above) */ 863 ExtDevice *exts_device[NT]; 864 865 #ifdef ARIEL 866 TileTypeBitMask exts_subsTransistorTypes[NT]; 867 #endif /* ARIEL */ 868 869 /* 870 * There is a single name for global substrate, and a list of 871 * types that connect to the substrate. Since for non-SOI 872 * processes, this generally is used to specify that space on 873 * the well plane is the substrate, the plane number for the 874 * well plane is given, too. The "shield types" mask is a 875 * mask of types that prevent any types in exts_globSubstrateTypes 876 * from contacting the substrate (e.g., deep nwell might be a 877 * shielding type, or it could be a special marker layer like 878 * "not_substrate"). 879 */ 880 char *exts_globSubstrateName; 881 TileTypeBitMask exts_globSubstrateTypes; 882 int exts_globSubstratePlane; 883 TileTypeBitMask exts_globSubstrateShieldTypes; 884 885 /* Scaling */ 886 /* 887 * Step size used when breaking up a large cell for interaction 888 * checks during hierarchical extraction. We check exts_stepSize 889 * by exts_stepSize chunks for interactions one at a time. 890 */ 891 int exts_stepSize; 892 893 /* 894 * Number of linear units per lambda. All perimeter dimensions 895 * that we output to the .ext file should be multiplied by 896 * exts_unitsPerLambda; we produce a "scale" line in the .ext file 897 * indicating this. All area dimensions should be multiplied 898 * by exts_unitsPerLambda**2. 899 * (changed to type float May 11, 2006 to accommodate, e.g., 90 900 * and 130 nm technologies) 901 */ 902 float exts_unitsPerLambda; 903 904 /* 905 * Scaling for resistance and capacitance. 906 * All resistances in the .ext file should be multiplied by 907 * exts_resistScale to get milliohms, and all capacitances by 908 * exts_capScale to get attofarads. These numbers appear in 909 * the "scale" line in the .ext file. 910 */ 911 int exts_capScale; 912 int exts_resistScale; 913 } ExtStyle; 914 915 #define EXT_PLUG_GND 1 916 #define EXT_PLUG_VDD 2 917 918 extern ExtStyle *ExtCurStyle; 919 920 /* ------------------- Hierarchical node merging ---------------------- */ 921 922 /* 923 * Table used to hold all merged nodes during hierarchical extraction. 924 * Used for duplicate suppression. 925 */ 926 extern HashTable extHierMergeTable; 927 928 /* 929 * Each hash entry in the above table points to a NodeName struct. 930 * Each NodeName points to the Node corresponding to that name. 931 * Each Node points back to a list of NodeNames that point to that 932 * Node, and which are linked together along their nn_next fields. 933 */ 934 typedef struct nn 935 { 936 struct node *nn_node; /* Node for which this is a name */ 937 char *nn_name; /* Text of name */ 938 struct nn *nn_next; /* Other names of nn_node */ 939 } NodeName; 940 941 typedef struct node 942 { 943 NodeName *node_names; /* List of names for this node. The first name 944 * in the list is the "official" node name. 945 */ 946 int node_len; /* Number of entries in node_names */ 947 CapValue node_cap; /* Capacitance to substrate */ 948 PerimArea node_pa[1]; /* Dummy; each node actually has 949 * ExtCurStyle->exts_numResistClasses 950 * array elements allocated to it. 951 */ 952 } Node; 953 954 /* -------------------------------------------------------------------- */ 955 956 /* 957 * Value normally resident in the ti_client field of a tile, 958 * indicating that the tile has not yet been visited in a 959 * region search. 960 */ 961 extern ClientData extUnInit; 962 963 #define extGetRegion(tp) ( (tp)->ti_client ) 964 #define extHasRegion(tp,und) ( (tp)->ti_client != (und) ) 965 966 967 /* For non-recursive flooding algorithm */ 968 #define VISITPENDING ((ClientData) NULL) /* Marks tiles on stack */ 969 970 /* Note that this macro depends on MAXPLANES being small */ 971 /* compared to the bit position of TT_SIDE. Since tens of */ 972 /* thousands of planes is inconceivable, this should not be a */ 973 /* problem. It is necessary to push the tile's TT_SIDE bit */ 974 /* because the search algorithm can overwrite it between the */ 975 /* time the tile is pushed and the time that it is popped. */ 976 977 #define PUSHTILE(tp, pl) \ 978 (tp)->ti_client = VISITPENDING; \ 979 STACKPUSH((ClientData)(pointertype)(pl | \ 980 ((TileType)(spointertype)(tp)->ti_body & TT_SIDE)), extNodeStack); \ 981 STACKPUSH((ClientData)(pointertype)tp, extNodeStack) 982 983 #define POPTILE(tp, pl) \ 984 tp = (Tile *) STACKPOP(extNodeStack); \ 985 pl = (spointertype) STACKPOP(extNodeStack); \ 986 if (pl & TT_SIDE) { \ 987 TiSetBody((tp), TiGetTypeExact(tp) | TT_SIDE); \ 988 pl &= (~TT_SIDE); \ 989 } \ 990 else \ 991 TiSetBody((tp), TiGetTypeExact(tp) & (~TT_SIDE)) 992 993 /* Variations of "pushtile" to force a specific value on TT_SIDE */ 994 995 #define PUSHTILEBOTTOM(tp, pl) \ 996 (tp)->ti_client = VISITPENDING; \ 997 STACKPUSH((ClientData)(pointertype)(pl | \ 998 ((SplitDirection(tp)) ? 0 : TT_SIDE)), extNodeStack) ;\ 999 STACKPUSH((ClientData)(pointertype)tp, extNodeStack) 1000 1001 #define PUSHTILETOP(tp, pl) \ 1002 (tp)->ti_client = VISITPENDING; \ 1003 STACKPUSH((ClientData)(pointertype)(pl | \ 1004 ((SplitDirection(tp)) ? TT_SIDE : 0)), extNodeStack) ;\ 1005 STACKPUSH((ClientData)(pointertype)tp, extNodeStack) 1006 1007 #define PUSHTILELEFT(tp, pl) \ 1008 (tp)->ti_client = VISITPENDING; \ 1009 STACKPUSH((ClientData)(pointertype)(pl), extNodeStack); \ 1010 STACKPUSH((ClientData)(pointertype)tp, extNodeStack) 1011 1012 #define PUSHTILERIGHT(tp, pl) \ 1013 (tp)->ti_client = VISITPENDING; \ 1014 STACKPUSH((ClientData)(pointertype)(pl | TT_SIDE), extNodeStack); \ 1015 STACKPUSH((ClientData)(pointertype)tp, extNodeStack) 1016 1017 /* ------------------------- Region finding --------------------------- */ 1018 1019 extern Region *ExtFindRegions(); 1020 1021 /* Filter functions for ExtFindRegions() */ 1022 extern Region *extTransFirst(); extern int extTransEach(); 1023 extern Region *extResFirst(); extern int extResEach(); 1024 extern Region *extNodeFirst(); extern int extNodeEach(); 1025 extern Region *extHierLabFirst(); extern int extHierLabEach(); 1026 1027 extern Tile *extNodeToTile(); 1028 1029 /* -------- Search for matching node in another ExtTree ---------- */ 1030 1031 /* 1032 * NODETONODE(nold, et, nnew) 1033 * NodeRegion *nold; 1034 * ExtTree *et; 1035 * NodeRegion *nnew; 1036 * 1037 * Like extNodeToTile(), but leaves nnew pointing to the node associated 1038 * with the tile we find. 1039 */ 1040 #define NODETONODE(nold, et, nnew) \ 1041 if (1) { \ 1042 Tile *tp; \ 1043 \ 1044 (nnew) = (NodeRegion *) NULL; \ 1045 tp = extNodeToTile((nold), (et)); \ 1046 if (tp && extHasRegion(tp, extUnInit)) \ 1047 (nnew) = (NodeRegion *) extGetRegion(tp); \ 1048 } 1049 1050 /* -------------------- Miscellaneous procedures ---------------------- */ 1051 1052 extern char *extNodeName(); 1053 extern NodeRegion *extBasic(); 1054 extern NodeRegion *extFindNodes(); 1055 extern ExtTree *extHierNewOne(); 1056 extern int extNbrPushFunc(); 1057 extern TileType extGetDevType(); 1058 extern void extMakeNodeNumPrint(); 1059 1060 /* --------------------- Miscellaneous globals ------------------------ */ 1061 1062 extern int extNumFatal; /* Number fatal errors encountered so far */ 1063 extern int extNumWarnings; /* Number warning messages so far */ 1064 extern CellUse *extParentUse; /* Dummy use for def being extracted */ 1065 extern ClientData extNbrUn; /* Ditto */ 1066 1067 extern NodeRegion *glob_subsnode; /* Substrate node for cell def */ 1068 extern NodeRegion *temp_subsnode; /* Substrate connection to subcell */ 1069 1070 /* 1071 * This is really a (Stack *), but we use the struct tag to avoid 1072 * having to include stack.h in every .c file. Used in the non-recursive 1073 * flooding algorithm. 1074 */ 1075 extern struct stack *extNodeStack; 1076 1077 /* ------------------ Connectivity table management ------------------- */ 1078 1079 /* 1080 * The following is true if tile types 'r' and 's' are connected 1081 * according to the connectivity table 'tbl' 1082 */ 1083 #define extConnectsTo(r, s, tbl) ( TTMaskHasType(&(tbl)[(r)], (s)) ) 1084 1085 /* -------------------------------------------------------------------- */ 1086 1087 #include "extDebugInt.h" 1088 1089 #endif /* _EXTRACTINT_H */ 1090