1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6
7 #ifndef __QLA_NX2_H
8 #define __QLA_NX2_H
9
10 #define QSNT_ACK_TOV 30
11 #define INTENT_TO_RECOVER 0x01
12 #define PROCEED_TO_RECOVER 0x02
13 #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
14 #define IDC_LOCK_RECOVERY_STATE_MASK 0x3
15 #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
16
17 #define QLA8044_DRV_LOCK_MSLEEP 200
18 #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
19 #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
20
21 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
22 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
23 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
24 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
25
26 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
27 #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
28 #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
29 MIU_TA_CTL_START)
30 #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
31
32 /* Imbus address bit used to indicate a host address. This bit is
33 * eliminated by the pcie bar and bar select before presentation
34 * over pcie. */
35 /* host memory via IMBUS */
36 #define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
37 #define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
38 #define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
39 #define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
40 #define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
41 #define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
42 #define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
43 #define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
44 #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
45 #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
46 #define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
47 #define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
48 #define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
49 #define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
50 #define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
51 #define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
52 #define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
53 #define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
54
55 /* PCI Windowing for DDR regions. */
addr_in_range(u64 addr,u64 low,u64 high)56 static inline bool addr_in_range(u64 addr, u64 low, u64 high)
57 {
58 return addr <= high && addr >= low;
59 }
60
61 /* Indirectly Mapped Registers */
62 #define QLA8044_FLASH_SPI_STATUS 0x2808E010
63 #define QLA8044_FLASH_SPI_CONTROL 0x2808E014
64 #define QLA8044_FLASH_STATUS 0x42100004
65 #define QLA8044_FLASH_CONTROL 0x42110004
66 #define QLA8044_FLASH_ADDR 0x42110008
67 #define QLA8044_FLASH_WRDATA 0x4211000C
68 #define QLA8044_FLASH_RDDATA 0x42110018
69 #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
70 #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
71
72 /* Flash access regs */
73 #define QLA8044_FLASH_LOCK 0x3850
74 #define QLA8044_FLASH_UNLOCK 0x3854
75 #define QLA8044_FLASH_LOCK_ID 0x3500
76
77 /* Driver Lock regs */
78 #define QLA8044_DRV_LOCK 0x3868
79 #define QLA8044_DRV_UNLOCK 0x386C
80 #define QLA8044_DRV_LOCK_ID 0x3504
81 #define QLA8044_DRV_LOCKRECOVERY 0x379C
82
83 /* IDC version */
84 #define QLA8044_IDC_VER_MAJ_VALUE 0x1
85 #define QLA8044_IDC_VER_MIN_VALUE 0x0
86
87 /* IDC Registers : Driver Coexistence Defines */
88 #define QLA8044_CRB_IDC_VER_MAJOR 0x3780
89 #define QLA8044_CRB_IDC_VER_MINOR 0x3798
90 #define QLA8044_IDC_DRV_AUDIT 0x3794
91 #define QLA8044_SRE_SHIM_CONTROL 0x0D200284
92 #define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
93 #define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
94 #define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
95 #define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
96 #define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
97 #define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
98 #define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
99 #define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
100
101 /* set value to pause threshold value */
102 #define QLA8044_SET_PAUSE_VAL 0x0
103 #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
104 #define QLA8044_PEG_HALT_STATUS1 0x34A8
105 #define QLA8044_PEG_HALT_STATUS2 0x34AC
106 #define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
107 #define QLA8044_FW_CAPABILITIES 0x3528
108 #define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
109 #define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
110 #define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
111 #define QLA8044_CRB_DRV_SCRATCH 0x3548
112 #define QLA8044_CRB_DEV_PART_INFO1 0x37E0
113 #define QLA8044_CRB_DEV_PART_INFO2 0x37E4
114 #define QLA8044_FW_VER_MAJOR 0x3550
115 #define QLA8044_FW_VER_MINOR 0x3554
116 #define QLA8044_FW_VER_SUB 0x3558
117 #define QLA8044_NPAR_STATE 0x359C
118 #define QLA8044_FW_IMAGE_VALID 0x35FC
119 #define QLA8044_CMDPEG_STATE 0x3650
120 #define QLA8044_ASIC_TEMP 0x37B4
121 #define QLA8044_FW_API 0x356C
122 #define QLA8044_DRV_OP_MODE 0x3570
123 #define QLA8044_CRB_WIN_BASE 0x3800
124 #define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
125 #define QLA8044_SEM_LOCK_BASE 0x3840
126 #define QLA8044_SEM_UNLOCK_BASE 0x3844
127 #define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
128 #define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
129 #define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
130 #define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
131 #define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
132 #define QLA8044_LINK_SPEED_FACTOR 10
133 #define QLA8044_FUN7_ACTIVE_INDEX 0x80
134
135 /* FLASH API Defines */
136 #define QLA8044_FLASH_MAX_WAIT_USEC 100
137 #define QLA8044_FLASH_LOCK_TIMEOUT 10000
138 #define QLA8044_FLASH_SECTOR_SIZE 65536
139 #define QLA8044_DRV_LOCK_TIMEOUT 2000
140 #define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
141 #define QLA8044_FLASH_WRITE_CMD 0xdacdacda
142 #define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
143 #define QLA8044_FLASH_READ_RETRY_COUNT 2000
144 #define QLA8044_FLASH_STATUS_READY 0x6
145 #define QLA8044_FLASH_BUFFER_WRITE_MIN 2
146 #define QLA8044_FLASH_BUFFER_WRITE_MAX 64
147 #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
148 #define QLA8044_ERASE_MODE 1
149 #define QLA8044_WRITE_MODE 2
150 #define QLA8044_DWORD_WRITE_MODE 3
151 #define QLA8044_GLOBAL_RESET 0x38CC
152 #define QLA8044_WILDCARD 0x38F0
153 #define QLA8044_INFORMANT 0x38FC
154 #define QLA8044_HOST_MBX_CTRL 0x3038
155 #define QLA8044_FW_MBX_CTRL 0x303C
156 #define QLA8044_BOOTLOADER_ADDR 0x355C
157 #define QLA8044_BOOTLOADER_SIZE 0x3560
158 #define QLA8044_FW_IMAGE_ADDR 0x3564
159 #define QLA8044_MBX_INTR_ENABLE 0x1000
160 #define QLA8044_MBX_INTR_MASK 0x1200
161
162 /* IDC Control Register bit defines */
163 #define DONTRESET_BIT0 0x1
164 #define GRACEFUL_RESET_BIT1 0x2
165
166 /* ISP8044 PEG_HALT_STATUS1 bits */
167 #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
168 #define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
169 #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
170
171 /* Firmware image definitions */
172 #define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
173 #define QLA8044_BOOT_FROM_FLASH 0
174 #define QLA8044_IDC_PARAM_ADDR 0x3e8020
175
176 /* FLASH related definitions */
177 #define QLA8044_OPTROM_BURST_SIZE 0x100
178 #define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
179 #define QLA8044_MIN_OPTROM_BURST_DWORDS 2
180 #define QLA8044_SECTOR_SIZE (64 * 1024)
181
182 #define QLA8044_FLASH_SPI_CTL 0x4
183 #define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
184 #define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
185 #define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
186 #define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
187 #define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
188 #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
189 #define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
190 #define QLA8044_FLASH_ERASE_SIG 0xFD0300
191 #define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
192
193 /* Reset template definitions */
194 #define QLA8044_MAX_RESET_SEQ_ENTRIES 16
195 #define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
196 #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
197 #define QLA8044_RESET_SEQ_VERSION 0x0101
198
199 /* Reset template entry opcodes */
200 #define OPCODE_NOP 0x0000
201 #define OPCODE_WRITE_LIST 0x0001
202 #define OPCODE_READ_WRITE_LIST 0x0002
203 #define OPCODE_POLL_LIST 0x0004
204 #define OPCODE_POLL_WRITE_LIST 0x0008
205 #define OPCODE_READ_MODIFY_WRITE 0x0010
206 #define OPCODE_SEQ_PAUSE 0x0020
207 #define OPCODE_SEQ_END 0x0040
208 #define OPCODE_TMPL_END 0x0080
209 #define OPCODE_POLL_READ_LIST 0x0100
210
211 /* Template Header */
212 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
213 #define QLA8044_IDC_DRV_CTRL 0x3790
214 #define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
215
216 #define MINIDUMP_SIZE_36K 36864
217
218 struct qla8044_reset_template_hdr {
219 uint16_t version;
220 uint16_t signature;
221 uint16_t size;
222 uint16_t entries;
223 uint16_t hdr_size;
224 uint16_t checksum;
225 uint16_t init_seq_offset;
226 uint16_t start_seq_offset;
227 } __packed;
228
229 /* Common Entry Header. */
230 struct qla8044_reset_entry_hdr {
231 uint16_t cmd;
232 uint16_t size;
233 uint16_t count;
234 uint16_t delay;
235 } __packed;
236
237 /* Generic poll entry type. */
238 struct qla8044_poll {
239 uint32_t test_mask;
240 uint32_t test_value;
241 } __packed;
242
243 /* Read modify write entry type. */
244 struct qla8044_rmw {
245 uint32_t test_mask;
246 uint32_t xor_value;
247 uint32_t or_value;
248 uint8_t shl;
249 uint8_t shr;
250 uint8_t index_a;
251 uint8_t rsvd;
252 } __packed;
253
254 /* Generic Entry Item with 2 DWords. */
255 struct qla8044_entry {
256 uint32_t arg1;
257 uint32_t arg2;
258 } __packed;
259
260 /* Generic Entry Item with 4 DWords.*/
261 struct qla8044_quad_entry {
262 uint32_t dr_addr;
263 uint32_t dr_value;
264 uint32_t ar_addr;
265 uint32_t ar_value;
266 } __packed;
267
268 struct qla8044_reset_template {
269 int seq_index;
270 int seq_error;
271 int array_index;
272 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
273 uint8_t *buff;
274 uint8_t *stop_offset;
275 uint8_t *start_offset;
276 uint8_t *init_offset;
277 struct qla8044_reset_template_hdr *hdr;
278 uint8_t seq_end;
279 uint8_t template_end;
280 };
281
282 /* Driver_code is for driver to write some info about the entry
283 * currently not used.
284 */
285 struct qla8044_minidump_entry_hdr {
286 uint32_t entry_type;
287 uint32_t entry_size;
288 uint32_t entry_capture_size;
289 struct {
290 uint8_t entry_capture_mask;
291 uint8_t entry_code;
292 uint8_t driver_code;
293 uint8_t driver_flags;
294 } d_ctrl;
295 } __packed;
296
297 /* Read CRB entry header */
298 struct qla8044_minidump_entry_crb {
299 struct qla8044_minidump_entry_hdr h;
300 uint32_t addr;
301 struct {
302 uint8_t addr_stride;
303 uint8_t state_index_a;
304 uint16_t poll_timeout;
305 } crb_strd;
306 uint32_t data_size;
307 uint32_t op_count;
308
309 struct {
310 uint8_t opcode;
311 uint8_t state_index_v;
312 uint8_t shl;
313 uint8_t shr;
314 } crb_ctrl;
315
316 uint32_t value_1;
317 uint32_t value_2;
318 uint32_t value_3;
319 } __packed;
320
321 struct qla8044_minidump_entry_cache {
322 struct qla8044_minidump_entry_hdr h;
323 uint32_t tag_reg_addr;
324 struct {
325 uint16_t tag_value_stride;
326 uint16_t init_tag_value;
327 } addr_ctrl;
328 uint32_t data_size;
329 uint32_t op_count;
330 uint32_t control_addr;
331 struct {
332 uint16_t write_value;
333 uint8_t poll_mask;
334 uint8_t poll_wait;
335 } cache_ctrl;
336 uint32_t read_addr;
337 struct {
338 uint8_t read_addr_stride;
339 uint8_t read_addr_cnt;
340 uint16_t rsvd_1;
341 } read_ctrl;
342 } __packed;
343
344 /* Read OCM */
345 struct qla8044_minidump_entry_rdocm {
346 struct qla8044_minidump_entry_hdr h;
347 uint32_t rsvd_0;
348 uint32_t rsvd_1;
349 uint32_t data_size;
350 uint32_t op_count;
351 uint32_t rsvd_2;
352 uint32_t rsvd_3;
353 uint32_t read_addr;
354 uint32_t read_addr_stride;
355 } __packed;
356
357 /* Read Memory */
358 struct qla8044_minidump_entry_rdmem {
359 struct qla8044_minidump_entry_hdr h;
360 uint32_t rsvd[6];
361 uint32_t read_addr;
362 uint32_t read_data_size;
363 };
364
365 /* Read Memory: For Pex-DMA */
366 struct qla8044_minidump_entry_rdmem_pex_dma {
367 struct qla8044_minidump_entry_hdr h;
368 uint32_t desc_card_addr;
369 uint16_t dma_desc_cmd;
370 uint8_t rsvd[2];
371 uint32_t start_dma_cmd;
372 uint8_t rsvd2[12];
373 uint32_t read_addr;
374 uint32_t read_data_size;
375 } __packed;
376
377 /* Read ROM */
378 struct qla8044_minidump_entry_rdrom {
379 struct qla8044_minidump_entry_hdr h;
380 uint32_t rsvd[6];
381 uint32_t read_addr;
382 uint32_t read_data_size;
383 } __packed;
384
385 /* Mux entry */
386 struct qla8044_minidump_entry_mux {
387 struct qla8044_minidump_entry_hdr h;
388 uint32_t select_addr;
389 uint32_t rsvd_0;
390 uint32_t data_size;
391 uint32_t op_count;
392 uint32_t select_value;
393 uint32_t select_value_stride;
394 uint32_t read_addr;
395 uint32_t rsvd_1;
396 } __packed;
397
398 /* Queue entry */
399 struct qla8044_minidump_entry_queue {
400 struct qla8044_minidump_entry_hdr h;
401 uint32_t select_addr;
402 struct {
403 uint16_t queue_id_stride;
404 uint16_t rsvd_0;
405 } q_strd;
406 uint32_t data_size;
407 uint32_t op_count;
408 uint32_t rsvd_1;
409 uint32_t rsvd_2;
410 uint32_t read_addr;
411 struct {
412 uint8_t read_addr_stride;
413 uint8_t read_addr_cnt;
414 uint16_t rsvd_3;
415 } rd_strd;
416 } __packed;
417
418 /* POLLRD Entry */
419 struct qla8044_minidump_entry_pollrd {
420 struct qla8044_minidump_entry_hdr h;
421 uint32_t select_addr;
422 uint32_t read_addr;
423 uint32_t select_value;
424 uint16_t select_value_stride;
425 uint16_t op_count;
426 uint32_t poll_wait;
427 uint32_t poll_mask;
428 uint32_t data_size;
429 uint32_t rsvd_1;
430 } __packed;
431
432 struct qla8044_minidump_entry_rddfe {
433 struct qla8044_minidump_entry_hdr h;
434 uint32_t addr_1;
435 uint32_t value;
436 uint8_t stride;
437 uint8_t stride2;
438 uint16_t count;
439 uint32_t poll;
440 uint32_t mask;
441 uint32_t modify_mask;
442 uint32_t data_size;
443 uint32_t rsvd;
444
445 } __packed;
446
447 struct qla8044_minidump_entry_rdmdio {
448 struct qla8044_minidump_entry_hdr h;
449
450 uint32_t addr_1;
451 uint32_t addr_2;
452 uint32_t value_1;
453 uint8_t stride_1;
454 uint8_t stride_2;
455 uint16_t count;
456 uint32_t poll;
457 uint32_t mask;
458 uint32_t value_2;
459 uint32_t data_size;
460
461 } __packed;
462
463 struct qla8044_minidump_entry_pollwr {
464 struct qla8044_minidump_entry_hdr h;
465 uint32_t addr_1;
466 uint32_t addr_2;
467 uint32_t value_1;
468 uint32_t value_2;
469 uint32_t poll;
470 uint32_t mask;
471 uint32_t data_size;
472 uint32_t rsvd;
473
474 } __packed;
475
476 /* RDMUX2 Entry */
477 struct qla8044_minidump_entry_rdmux2 {
478 struct qla8044_minidump_entry_hdr h;
479 uint32_t select_addr_1;
480 uint32_t select_addr_2;
481 uint32_t select_value_1;
482 uint32_t select_value_2;
483 uint32_t op_count;
484 uint32_t select_value_mask;
485 uint32_t read_addr;
486 uint8_t select_value_stride;
487 uint8_t data_size;
488 uint8_t rsvd[2];
489 } __packed;
490
491 /* POLLRDMWR Entry */
492 struct qla8044_minidump_entry_pollrdmwr {
493 struct qla8044_minidump_entry_hdr h;
494 uint32_t addr_1;
495 uint32_t addr_2;
496 uint32_t value_1;
497 uint32_t value_2;
498 uint32_t poll_wait;
499 uint32_t poll_mask;
500 uint32_t modify_mask;
501 uint32_t data_size;
502 } __packed;
503
504 /* IDC additional information */
505 struct qla8044_idc_information {
506 uint32_t request_desc; /* IDC request descriptor */
507 uint32_t info1; /* IDC additional info */
508 uint32_t info2; /* IDC additional info */
509 uint32_t info3; /* IDC additional info */
510 } __packed;
511
512 enum qla_regs {
513 QLA8044_PEG_HALT_STATUS1_INDEX = 0,
514 QLA8044_PEG_HALT_STATUS2_INDEX,
515 QLA8044_PEG_ALIVE_COUNTER_INDEX,
516 QLA8044_CRB_DRV_ACTIVE_INDEX,
517 QLA8044_CRB_DEV_STATE_INDEX,
518 QLA8044_CRB_DRV_STATE_INDEX,
519 QLA8044_CRB_DRV_SCRATCH_INDEX,
520 QLA8044_CRB_DEV_PART_INFO_INDEX,
521 QLA8044_CRB_DRV_IDC_VERSION_INDEX,
522 QLA8044_FW_VERSION_MAJOR_INDEX,
523 QLA8044_FW_VERSION_MINOR_INDEX,
524 QLA8044_FW_VERSION_SUB_INDEX,
525 QLA8044_CRB_CMDPEG_STATE_INDEX,
526 QLA8044_CRB_TEMP_STATE_INDEX,
527 } __packed;
528
529 #define CRB_REG_INDEX_MAX 14
530 #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
531 #define CRB_CMDPEG_CHECK_DELAY 500
532
533 /* MiniDump Structures */
534
535 /* Driver_code is for driver to write some info about the entry
536 * currently not used.
537 */
538 #define QLA8044_SS_OCM_WNDREG_INDEX 3
539 #define QLA8044_DBG_STATE_ARRAY_LEN 16
540 #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
541 #define QLA8044_DBG_RSVD_ARRAY_LEN 8
542 #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
543 #define QLA8044_SS_PCI_INDEX 0
544 #define QLA8044_RDDFE 38
545 #define QLA8044_RDMDIO 39
546 #define QLA8044_POLLWR 40
547
548 struct qla8044_minidump_template_hdr {
549 uint32_t entry_type;
550 uint32_t first_entry_offset;
551 uint32_t size_of_template;
552 uint32_t capture_debug_level;
553 uint32_t num_of_entries;
554 uint32_t version;
555 uint32_t driver_timestamp;
556 uint32_t checksum;
557
558 uint32_t driver_capture_mask;
559 uint32_t driver_info_word2;
560 uint32_t driver_info_word3;
561 uint32_t driver_info_word4;
562
563 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
564 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
565 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
566 };
567
568 struct qla8044_pex_dma_descriptor {
569 struct {
570 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
571 uint8_t rsvd[2];
572 uint16_t dma_desc_cmd;
573 } cmd;
574 uint64_t src_addr;
575 uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
576 uint8_t rsvd[24];
577 } __packed;
578
579 #endif
580