1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_RCC_EX_H 22 #define STM32H7xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PLL2 Clock structure definition 46 */ 47 typedef struct 48 { 49 50 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 51 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 52 53 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 54 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 55 56 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 57 This parameter must be a number between Min_Data = 2 and Max_Data = 128 58 odd division factors are not allowed */ 59 60 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 61 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 62 63 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 66 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 67 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 68 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 69 70 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 71 PLL2 VCO It should be a value between 0 and 8191 */ 72 }RCC_PLL2InitTypeDef; 73 74 75 /** 76 * @brief PLL3 Clock structure definition 77 */ 78 typedef struct 79 { 80 81 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 82 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 83 84 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 85 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 86 87 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 88 This parameter must be a number between Min_Data = 2 and Max_Data = 128 89 odd division factors are not allowed */ 90 91 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 92 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 93 94 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 95 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 96 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 97 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 98 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 99 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 100 101 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 102 PLL3 VCO It should be a value between 0 and 8191 */ 103 }RCC_PLL3InitTypeDef; 104 105 /** 106 * @brief RCC PLL1 Clocks structure definition 107 */ 108 typedef struct 109 { 110 uint32_t PLL1_P_Frequency; 111 uint32_t PLL1_Q_Frequency; 112 uint32_t PLL1_R_Frequency; 113 }PLL1_ClocksTypeDef; 114 115 /** 116 * @brief RCC PLL2 Clocks structure definition 117 */ 118 typedef struct 119 { 120 uint32_t PLL2_P_Frequency; 121 uint32_t PLL2_Q_Frequency; 122 uint32_t PLL2_R_Frequency; 123 }PLL2_ClocksTypeDef; 124 125 /** 126 * @brief RCC PLL3 Clocks structure definition 127 */ 128 typedef struct 129 { 130 uint32_t PLL3_P_Frequency; 131 uint32_t PLL3_Q_Frequency; 132 uint32_t PLL3_R_Frequency; 133 }PLL3_ClocksTypeDef; 134 135 136 /** 137 * @brief RCC extended clocks structure definition 138 */ 139 typedef struct 140 { 141 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 142 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 143 144 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 145 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 146 147 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 148 This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */ 149 150 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 151 This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ 152 153 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 154 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 155 #if defined(DSI) 156 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 157 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 158 #endif /*DSI*/ 159 160 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source 161 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 162 163 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 164 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 165 166 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 167 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 168 169 uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source 170 This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ 171 172 uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source 173 This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */ 174 175 uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source 176 This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ 177 178 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 179 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 180 181 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source 182 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 183 #if defined(FDCAN1) || defined(FDCAN2) 184 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 185 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 186 #endif /*FDCAN1 || FDCAN2*/ 187 188 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source 189 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 190 191 uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source 192 This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ 193 194 uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source 195 This parameter can be a value of @ref RCCEx_USART16_Clock_Source */ 196 197 uint32_t RngClockSelection; /*!< Specifies RNG clock source 198 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 199 200 uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source 201 This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */ 202 203 uint32_t UsbClockSelection; /*!< Specifies USB clock source 204 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 205 206 uint32_t CecClockSelection; /*!< Specifies CEC clock source 207 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 208 209 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 210 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 211 212 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source 213 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 214 215 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source 216 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 217 218 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source 219 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 220 221 uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source 222 This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */ 223 224 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 225 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 226 227 uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source 228 This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */ 229 230 uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source 231 This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */ 232 233 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 234 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 235 236 uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source 237 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 238 239 uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source 240 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ 241 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 242 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 243 }RCC_PeriphCLKInitTypeDef; 244 245 246 /** 247 * @brief RCC_CRS Init structure definition 248 */ 249 typedef struct 250 { 251 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 252 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 253 254 uint32_t Source; /*!< Specifies the SYNC signal source. 255 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 256 257 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 258 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 259 260 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 261 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 262 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 263 264 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 265 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 266 267 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 268 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 269 270 }RCC_CRSInitTypeDef; 271 272 /** 273 * @brief RCC_CRS Synchronization structure definition 274 */ 275 typedef struct 276 { 277 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 278 This parameter must be a number between 0 and 0xFFFF */ 279 280 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 281 This parameter must be a number between 0 and 0x3F */ 282 283 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 284 value latched in the time of the last SYNC event. 285 This parameter must be a number between 0 and 0xFFFF */ 286 287 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 288 frequency error counter latched in the time of the last SYNC event. 289 It shows whether the actual frequency is below or above the target. 290 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 291 292 }RCC_CRSSynchroInfoTypeDef; 293 294 /** 295 * @} 296 */ 297 298 299 /* Exported constants --------------------------------------------------------*/ 300 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 301 * @{ 302 */ 303 304 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 305 * @{ 306 */ 307 308 #define RCC_PERIPHCLK_USART16 (0x00000001U) 309 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 310 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 311 #define RCC_PERIPHCLK_USART234578 (0x00000002U) 312 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 313 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 314 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578 315 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578 316 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 317 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 318 #define RCC_PERIPHCLK_LPUART1 (0x00000004U) 319 #define RCC_PERIPHCLK_I2C123 (0x00000008U) 320 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 321 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 322 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 323 #define RCC_PERIPHCLK_I2C4 (0x00000010U) 324 #define RCC_PERIPHCLK_LPTIM1 (0x00000020U) 325 #define RCC_PERIPHCLK_LPTIM2 (0x00000040U) 326 #define RCC_PERIPHCLK_LPTIM345 (0x00000080U) 327 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 328 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 329 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 330 #define RCC_PERIPHCLK_SAI1 (0x00000100U) 331 #define RCC_PERIPHCLK_SAI23 (0x00000200U) 332 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 333 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 334 #define RCC_PERIPHCLK_SAI4A (0x00000400U) 335 #define RCC_PERIPHCLK_SAI4B (0x00000800U) 336 #define RCC_PERIPHCLK_SPI123 (0x00001000U) 337 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 338 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 339 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123 340 #define RCC_PERIPHCLK_SPI45 (0x00002000U) 341 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45 342 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45 343 #define RCC_PERIPHCLK_SPI6 (0x00004000U) 344 #define RCC_PERIPHCLK_FDCAN (0x00008000U) 345 #define RCC_PERIPHCLK_SDMMC (0x00010000U) 346 #define RCC_PERIPHCLK_RNG (0x00020000U) 347 #define RCC_PERIPHCLK_USB (0x00040000U) 348 #define RCC_PERIPHCLK_ADC (0x00080000U) 349 #define RCC_PERIPHCLK_SWPMI1 (0x00100000U) 350 #define RCC_PERIPHCLK_DFSDM1 (0x00200000U) 351 #define RCC_PERIPHCLK_RTC (0x00400000U) 352 #define RCC_PERIPHCLK_CEC (0x00800000U) 353 #define RCC_PERIPHCLK_FMC (0x01000000U) 354 #define RCC_PERIPHCLK_QSPI (0x02000000U) 355 #define RCC_PERIPHCLK_DSI (0x04000000U) 356 #define RCC_PERIPHCLK_SPDIFRX (0x08000000U) 357 #define RCC_PERIPHCLK_HRTIM1 (0x10000000U) 358 359 #if defined(LTDC) 360 #define RCC_PERIPHCLK_LTDC (0x20000000U) 361 #endif /* LTDC */ 362 363 #define RCC_PERIPHCLK_TIM (0x40000000U) 364 #define RCC_PERIPHCLK_CKPER (0x80000000U) 365 366 /** 367 * @} 368 */ 369 370 371 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 372 * @{ 373 */ 374 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN 375 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN 376 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN 377 378 /** 379 * @} 380 */ 381 382 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 383 * @{ 384 */ 385 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN 386 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN 387 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN 388 389 /** 390 * @} 391 */ 392 393 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 394 * @{ 395 */ 396 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 397 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 398 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 399 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 400 401 /** 402 * @} 403 */ 404 405 406 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 407 * @{ 408 */ 409 #define RCC_PLL2VCOWIDE (0x00000000U) 410 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL 411 412 /** 413 * @} 414 */ 415 416 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 417 * @{ 418 */ 419 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 420 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 421 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 422 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 423 424 /** 425 * @} 426 */ 427 428 429 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 430 * @{ 431 */ 432 #define RCC_PLL3VCOWIDE (0x00000000U) 433 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL 434 435 /** 436 * @} 437 */ 438 439 /** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source 440 * @{ 441 */ 442 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) 443 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 444 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 445 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) 446 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 447 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 453 * @{ 454 */ 455 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 456 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 457 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 458 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 459 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 460 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 461 /** 462 * @} 463 */ 464 465 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source 466 * @{ 467 */ 468 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 469 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 470 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 471 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI 472 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI 473 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE 474 475 /** 476 * @} 477 */ 478 479 /** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source 480 * @{ 481 */ 482 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) 483 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 484 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 485 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) 486 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 487 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) 488 489 /** 490 * @} 491 */ 492 493 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 494 * @{ 495 */ 496 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 497 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 498 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 499 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 500 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 501 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 502 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 508 * @{ 509 */ 510 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 511 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 512 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 513 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 514 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 515 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 516 517 /** 518 * @} 519 */ 520 521 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source 522 * @{ 523 */ 524 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 525 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 526 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 527 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 528 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 529 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 530 531 /** 532 * @} 533 */ 534 535 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source 536 * @{ 537 */ 538 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 539 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 540 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 541 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 542 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 543 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 544 545 /** 546 * @} 547 */ 548 549 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source 550 * @{ 551 */ 552 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 553 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 554 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 555 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 556 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 557 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 558 559 /** 560 * @} 561 */ 562 563 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source 564 * @{ 565 */ 566 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 567 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2 568 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3 569 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI 570 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI 571 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE 572 573 /** 574 * @} 575 */ 576 577 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 578 * @{ 579 */ 580 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) 581 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 582 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 583 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) 584 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 585 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) 586 587 /** 588 * @} 589 */ 590 591 /** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source 592 * @{ 593 */ 594 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) 595 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 596 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 597 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) 598 599 /** 600 * @} 601 */ 602 603 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 604 * @{ 605 */ 606 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 607 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 608 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 609 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 610 611 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source 617 * @{ 618 */ 619 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 620 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 621 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 622 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 623 624 /** 625 * @} 626 */ 627 628 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 629 * @{ 630 */ 631 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 632 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 633 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI 634 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI 635 636 /** 637 * @} 638 */ 639 640 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source 641 * @{ 642 */ 643 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) 644 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 645 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 646 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) 647 648 649 /** 650 * @} 651 */ 652 653 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 654 * @{ 655 */ 656 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) 657 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 658 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 659 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL 660 661 662 /** 663 * @} 664 */ 665 666 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source 667 * @{ 668 */ 669 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U) 670 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL 671 672 /** 673 * @} 674 */ 675 676 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 677 * @{ 678 */ 679 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 680 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 681 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL 682 683 /** 684 * @} 685 */ 686 687 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 688 * @{ 689 */ 690 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) 691 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 692 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 693 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) 694 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 695 696 /** 697 * @} 698 */ 699 700 701 702 /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source 703 * @{ 704 */ 705 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U) 706 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0 707 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 708 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) 709 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 710 711 /** 712 * @} 713 */ 714 715 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 716 * @{ 717 */ 718 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 719 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 720 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 721 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 722 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 723 724 /** 725 * @} 726 */ 727 728 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 729 * @{ 730 */ 731 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL 732 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2 733 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 734 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN 735 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP 736 737 /** 738 * @} 739 */ 740 741 /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source 742 * @{ 743 */ 744 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) 745 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 746 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 747 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) 748 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 749 750 /** 751 * @} 752 */ 753 754 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 755 * @{ 756 */ 757 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 758 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 759 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 760 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 761 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 762 763 /** 764 * @} 765 */ 766 767 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 768 * @{ 769 */ 770 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 771 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 772 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 773 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 774 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 775 776 /** 777 * @} 778 */ 779 780 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 781 * @{ 782 */ 783 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL 784 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2 785 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3 786 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN 787 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP 788 789 /** 790 * @} 791 */ 792 793 /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source 794 * @{ 795 */ 796 #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U) 797 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 798 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 799 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) 800 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 801 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) 802 803 /** 804 * @} 805 */ 806 807 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 808 * @{ 809 */ 810 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 811 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 812 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 813 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 814 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 815 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 816 817 /** 818 * @} 819 */ 820 821 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 822 * @{ 823 */ 824 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 825 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2 826 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3 827 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI 828 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI 829 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE 830 831 /** 832 * @} 833 */ 834 835 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 836 * @{ 837 */ 838 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) 839 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 840 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 841 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) 842 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 843 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) 844 845 846 /** 847 * @} 848 */ 849 850 851 /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source 852 * @{ 853 */ 854 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U) 855 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0 856 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 857 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) 858 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 859 860 861 /** 862 * @} 863 */ 864 865 866 /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source 867 * @{ 868 */ 869 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U) 870 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0 871 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 872 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) 873 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 874 875 /** 876 * @} 877 */ 878 879 880 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 881 * @{ 882 */ 883 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) 884 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 885 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 886 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) 887 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 888 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) 889 890 891 /** 892 * @} 893 */ 894 895 /** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source 896 * @{ 897 */ 898 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) 899 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 900 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 901 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) 902 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 903 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) 904 905 /** 906 * @} 907 */ 908 909 /** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source 910 * @{ 911 */ 912 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U) 913 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0 914 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1 915 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) 916 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 917 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) 918 919 /** 920 * @} 921 */ 922 923 /** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source 924 * @{ 925 */ 926 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 927 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 928 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 929 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 930 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 931 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 932 933 /** 934 * @} 935 */ 936 937 /** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source 938 * @{ 939 */ 940 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 941 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 942 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 943 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 944 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 945 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 946 947 /** 948 * @} 949 */ 950 951 /** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source 952 * @{ 953 */ 954 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1 955 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2 956 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3 957 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE 958 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI 959 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP 960 961 /** 962 * @} 963 */ 964 965 /** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source 966 * @{ 967 */ 968 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U) 969 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0 970 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 971 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL 972 973 974 975 /** 976 * @} 977 */ 978 #if defined(DSI) 979 /** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source 980 * @{ 981 */ 982 #define RCC_DSICLKSOURCE_PHY (0x00000000U) 983 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL 984 985 /** 986 * @} 987 */ 988 #endif /*DSI*/ 989 990 /** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source 991 * @{ 992 */ 993 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) 994 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 995 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 996 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL 997 998 /** 999 * @} 1000 */ 1001 1002 #if defined(FDCAN1) || defined(FDCAN2) 1003 /** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source 1004 * @{ 1005 */ 1006 1007 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) 1008 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 1009 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 1010 1011 /** 1012 * @} 1013 */ 1014 #endif /*FDCAN1 || FDCAN2*/ 1015 1016 1017 /** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source 1018 * @{ 1019 */ 1020 1021 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) 1022 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL 1023 1024 /** 1025 * @} 1026 */ 1027 1028 1029 /** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source 1030 * @{ 1031 */ 1032 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) 1033 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 1034 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 1035 1036 /** 1037 * @} 1038 */ 1039 1040 1041 1042 1043 1044 /** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source 1045 * @{ 1046 */ 1047 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) 1048 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL 1049 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source 1055 * @{ 1056 */ 1057 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) 1058 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL 1059 1060 1061 /** 1062 * @} 1063 */ 1064 1065 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source 1066 * @{ 1067 */ 1068 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) 1069 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 1070 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 1071 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL 1072 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 1078 * @{ 1079 */ 1080 #define RCC_CECCLKSOURCE_LSE (0x00000000U) 1081 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 1082 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 1083 1084 /** 1085 * @} 1086 */ 1087 1088 1089 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1090 * @{ 1091 */ 1092 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1093 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 1094 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 1095 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1101 * @{ 1102 */ 1103 #define RCC_TIMPRES_DESACTIVATED (0x00000000U) 1104 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE 1105 1106 /** 1107 * @} 1108 */ 1109 1110 #if defined(DUAL_CORE) 1111 1112 /** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx 1113 * @{ 1114 */ 1115 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1 1116 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2 1117 1118 /** 1119 * @} 1120 */ 1121 #endif /*DUAL_CORE*/ 1122 1123 #if defined(DUAL_CORE) 1124 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1125 * @{ 1126 */ 1127 #define RCC_WWDG1 RCC_GCR_WW1RSC 1128 #define RCC_WWDG2 RCC_GCR_WW2RSC 1129 1130 /** 1131 * @} 1132 */ 1133 1134 #else 1135 1136 /** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx 1137 * @{ 1138 */ 1139 #define RCC_WWDG1 RCC_GCR_WW1RSC 1140 1141 /** 1142 * @} 1143 */ 1144 1145 #endif /*DUAL_CORE*/ 1146 1147 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1148 * @{ 1149 */ 1150 #define RCC_CRS_NONE (0x00000000U) 1151 #define RCC_CRS_TIMEOUT (0x00000001U) 1152 #define RCC_CRS_SYNCOK (0x00000002U) 1153 #define RCC_CRS_SYNCWARN (0x00000004U) 1154 #define RCC_CRS_SYNCERR (0x00000008U) 1155 #define RCC_CRS_SYNCMISS (0x00000010U) 1156 #define RCC_CRS_TRIMOVF (0x00000020U) 1157 /** 1158 * @} 1159 */ 1160 1161 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1162 * @{ 1163 */ 1164 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and abobe devices only */ 1165 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1166 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */ 1167 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */ 1168 1169 1170 /** 1171 * @} 1172 */ 1173 1174 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1175 * @{ 1176 */ 1177 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 1178 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1179 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1180 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1181 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1182 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1183 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1184 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1185 /** 1186 * @} 1187 */ 1188 1189 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1190 * @{ 1191 */ 1192 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 1193 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1194 /** 1195 * @} 1196 */ 1197 1198 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1199 * @{ 1200 */ 1201 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1202 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 1203 /** 1204 * @} 1205 */ 1206 1207 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1208 * @{ 1209 */ 1210 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 1211 /** 1212 * @} 1213 */ 1214 1215 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1216 * @{ 1217 */ 1218 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 1219 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 1220 corresponds to a higher output frequency */ 1221 /** 1222 * @} 1223 */ 1224 1225 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1226 * @{ 1227 */ 1228 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1229 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1230 /** 1231 * @} 1232 */ 1233 1234 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1235 * @{ 1236 */ 1237 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1238 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1239 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1240 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1241 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1242 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1243 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1244 1245 /** 1246 * @} 1247 */ 1248 1249 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1250 * @{ 1251 */ 1252 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1253 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1254 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1255 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1256 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1257 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1258 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1259 1260 /** 1261 * @} 1262 */ 1263 1264 /** 1265 * @} 1266 */ 1267 1268 1269 1270 /* Exported macro ------------------------------------------------------------*/ 1271 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1272 * @{ 1273 */ 1274 1275 /** @brief Macros to enable or disable PLL2. 1276 * @note After enabling PLL2, the application software should wait on 1277 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1278 * be used as kernel clock source. 1279 * @note PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1280 */ 1281 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1282 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1283 1284 /** 1285 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1286 * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, 1287 * This is mainly used to save Power. 1288 * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted 1289 * This parameter can be one of the following values: 1290 * @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ) 1291 * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) 1292 * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) 1293 * @retval None 1294 */ 1295 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1296 1297 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) 1298 1299 /** 1300 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1301 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 1302 * @retval None 1303 */ 1304 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1305 1306 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 1307 1308 /** 1309 * @brief Macro to configures the PLL2 multiplication and division factors. 1310 * @note This function must be used only when PLL2 is disabled. 1311 * 1312 * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock 1313 * This parameter must be a number between 1 and 63. 1314 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1315 * frequency ranges from 1 to 16 MHz. 1316 * 1317 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock 1318 * This parameter must be a number between 4 and 512. 1319 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1320 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1321 * between 192 and 836 MHZ (when in wide VCO range) 1322 * 1323 * @param __PLL2P__ specifies the division factor for peripheral kernel clocks 1324 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 1325 * 1326 * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks 1327 * This parameter must be a number between 1 and 128 1328 * 1329 * @param __PLL2R__ specifies the division factor for peripheral kernel clocks 1330 * This parameter must be a number between 1 and 128 1331 * 1332 * @retval None 1333 */ 1334 1335 1336 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ 1337 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ 1338 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ 1339 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ 1340 } while(0) 1341 /** 1342 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1343 * 1344 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1345 * 1346 * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1347 * It should be a value between 0 and 8191 1348 * @note Warning: the software has to set correctly these bits to insure that the VCO 1349 * output frequency is between its valid frequency range, which is: 1350 * 192 to 836 MHz if PLL2VCOSEL = 0 1351 * 150 to 420 MHz if PLL2VCOSEL = 1. 1352 * 1353 * 1354 * @retval None 1355 */ 1356 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos) 1357 1358 /** @brief Macro to select the PLL2 reference frequency range. 1359 * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range 1360 * This parameter can be one of the following values: 1361 * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz 1362 * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz 1363 * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz 1364 * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz 1365 * @retval None 1366 */ 1367 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ 1368 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) 1369 1370 1371 /** @brief Macro to select the PLL2 reference frequency range. 1372 * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range 1373 * This parameter can be one of the following values: 1374 * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz 1375 * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz 1376 * @retval None 1377 */ 1378 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1379 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1380 1381 /** @brief Macros to enable or disable the main PLL3. 1382 * @note After enabling PLL3, the application software should wait on 1383 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1384 * be used as kernel clock source. 1385 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1386 */ 1387 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1388 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1389 1390 /** 1391 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1392 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 1393 * @retval None 1394 */ 1395 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1396 1397 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 1398 1399 /** 1400 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1401 * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, 1402 * This is mainly used to save Power. 1403 * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted 1404 * This parameter can be one of the following values: 1405 * @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ) 1406 * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) 1407 * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) 1408 * @retval None 1409 */ 1410 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1411 1412 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) 1413 1414 /** 1415 * @brief Macro to configures the PLL3 multiplication and division factors. 1416 * @note This function must be used only when PLL3 is disabled. 1417 * 1418 * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock 1419 * This parameter must be a number between 1 and 63. 1420 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1421 * frequency ranges from 1 to 16 MHz. 1422 * 1423 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock 1424 * This parameter must be a number between 4 and 512. 1425 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1426 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 1427 * between 192 and 836 MHZ (when in wide VCO range) 1428 * 1429 * @param __PLL3P__ specifies the division factor for peripheral kernel clocks 1430 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 1431 * 1432 * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks 1433 * This parameter must be a number between 1 and 128 1434 * 1435 * @param __PLL3R__ specifies the division factor for peripheral kernel clocks 1436 * This parameter must be a number between 1 and 128 1437 * 1438 * @retval None 1439 */ 1440 1441 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ 1442 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ 1443 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ 1444 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ 1445 } while(0) 1446 1447 1448 1449 /** 1450 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1451 * 1452 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1453 * 1454 * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1455 * It should be a value between 0 and 8191 1456 * @note Warning: the software has to set correctly these bits to insure that the VCO 1457 * output frequency is between its valid frequency range, which is: 1458 * 192 to 836 MHz if PLL3VCOSEL = 0 1459 * 150 to 420 MHz if PLL3VCOSEL = 1. 1460 * 1461 * 1462 * @retval None 1463 */ 1464 #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) 1465 1466 /** @brief Macro to select the PLL3 reference frequency range. 1467 * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range 1468 * This parameter can be one of the following values: 1469 * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz 1470 * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz 1471 * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz 1472 * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz 1473 * @retval None 1474 */ 1475 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ 1476 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) 1477 1478 1479 /** @brief Macro to select the PLL3 reference frequency range. 1480 * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range 1481 * This parameter can be one of the following values: 1482 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz 1483 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 1484 * @retval None 1485 */ 1486 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 1487 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 1488 /** 1489 * @brief Macro to Configure the SAI1 clock source. 1490 * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived 1491 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1492 * This parameter can be one of the following values: 1493 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 1494 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 1495 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 1496 * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC 1497 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 1498 * @retval None 1499 */ 1500 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ 1501 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) 1502 1503 /** @brief Macro to get the SAI1 clock source. 1504 * @retval The clock source can be one of the following values: 1505 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL 1506 * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 1507 * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 1508 * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP 1509 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock 1510 */ 1511 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) 1512 1513 /** 1514 * @brief Macro to Configure the SPDIFRX clock source. 1515 * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived 1516 * from system PLL, PLL2, PLL3, or internal OSC clock 1517 * This parameter can be one of the following values: 1518 * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL 1519 * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 1520 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 1521 * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI 1522 * @retval None 1523 */ 1524 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ 1525 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) 1526 /** 1527 * @brief Macro to get the SPDIFRX clock source. 1528 * @retval None 1529 */ 1530 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) 1531 1532 /** 1533 * @brief Macro to Configure the SAI2/3 clock source. 1534 * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived 1535 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1536 * This parameter can be one of the following values: 1537 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 1538 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 1539 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 1540 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 1541 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 1542 * @retval None 1543 */ 1544 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ 1545 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) 1546 1547 /** @brief Macro to get the SAI2/3 clock source. 1548 * @retval The clock source can be one of the following values: 1549 * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL 1550 * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 1551 * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 1552 * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP 1553 * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock 1554 */ 1555 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 1556 1557 /** 1558 * @brief Macro to Configure the SAI2 clock source. 1559 * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived 1560 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1561 * This parameter can be one of the following values: 1562 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 1563 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 1564 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 1565 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 1566 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 1567 * @retval None 1568 */ 1569 #define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\ 1570 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__)) 1571 1572 /** @brief Macro to get the SAI2 clock source. 1573 * @retval The clock source can be one of the following values: 1574 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL 1575 * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 1576 * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 1577 * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP 1578 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock 1579 */ 1580 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 1581 1582 /** 1583 * @brief Macro to Configure the SAI3 clock source. 1584 * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived 1585 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1586 * This parameter can be one of the following values: 1587 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 1588 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 1589 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 1590 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 1591 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 1592 * @retval None 1593 */ 1594 #define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\ 1595 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__)) 1596 1597 /** @brief Macro to get the SAI3 clock source. 1598 * @retval The clock source can be one of the following values: 1599 * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL 1600 * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 1601 * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 1602 * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP 1603 * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock 1604 */ 1605 #define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) 1606 1607 /** 1608 * @brief Macro to Configure the SAI4A clock source. 1609 * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived 1610 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1611 * This parameter can be one of the following values: 1612 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL 1613 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 1614 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 1615 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP 1616 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock 1617 * @retval None 1618 */ 1619 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ 1620 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) 1621 1622 /** @brief Macro to get the SAI4A clock source. 1623 * @retval The clock source can be one of the following values: 1624 * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL 1625 * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 1626 * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 1627 * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP 1628 * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock 1629 */ 1630 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) 1631 1632 /** 1633 * @brief Macro to Configure the SAI4B clock source. 1634 * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived 1635 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 1636 * This parameter can be one of the following values: 1637 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 1638 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 1639 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 1640 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 1641 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 1642 * @retval None 1643 */ 1644 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ 1645 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) 1646 1647 /** @brief Macro to get the SAI4B clock source. 1648 * @retval The clock source can be one of the following values: 1649 * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL 1650 * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 1651 * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 1652 * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP 1653 * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock 1654 */ 1655 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) 1656 1657 /** @brief macro to configure the I2C1/2/3 clock (I2C123CLK). 1658 * 1659 * @param __I2C123CLKSource__ specifies the I2C1/2/3 clock source. 1660 * This parameter can be one of the following values: 1661 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock 1662 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock 1663 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock 1664 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock 1665 */ 1666 #define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \ 1667 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__)) 1668 1669 /** @brief macro to get the I2C1/2/3 clock source. 1670 * @retval The clock source can be one of the following values: 1671 * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock 1672 * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock 1673 * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock 1674 * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock 1675 */ 1676 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 1677 1678 /** @brief macro to configure the I2C1 clock (I2C1CLK). 1679 * 1680 * @param __I2C1CLKSource__ specifies the I2C1 clock source. 1681 * This parameter can be one of the following values: 1682 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 1683 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 1684 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 1685 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 1686 */ 1687 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ 1688 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__)) 1689 1690 /** @brief macro to get the I2C1 clock source. 1691 * @retval The clock source can be one of the following values: 1692 * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock 1693 * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock 1694 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 1695 * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock 1696 */ 1697 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 1698 1699 /** @brief macro to configure the I2C2 clock (I2C2CLK). 1700 * 1701 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 1702 * This parameter can be one of the following values: 1703 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 1704 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 1705 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 1706 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 1707 */ 1708 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ 1709 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__)) 1710 1711 /** @brief macro to get the I2C2 clock source. 1712 * @retval The clock source can be one of the following values: 1713 * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock 1714 * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock 1715 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 1716 * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock 1717 */ 1718 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 1719 1720 /** @brief macro to configure the I2C3 clock (I2C3CLK). 1721 * 1722 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 1723 * This parameter can be one of the following values: 1724 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 1725 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 1726 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 1727 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 1728 */ 1729 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ 1730 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__)) 1731 1732 /** @brief macro to get the I2C3 clock source. 1733 * @retval The clock source can be one of the following values: 1734 * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock 1735 * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock 1736 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 1737 * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock 1738 */ 1739 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) 1740 1741 /** @brief macro to configure the I2C4 clock (I2C4CLK). 1742 * 1743 * @param __I2C4CLKSource__ specifies the I2C4 clock source. 1744 * This parameter can be one of the following values: 1745 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 1746 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 1747 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 1748 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 1749 */ 1750 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ 1751 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) 1752 1753 /** @brief macro to get the I2C4 clock source. 1754 * @retval The clock source can be one of the following values: 1755 * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock 1756 * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock 1757 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 1758 * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock 1759 */ 1760 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) 1761 1762 /** @brief macro to configure the USART1/6 clock (USART16CLK). 1763 * 1764 * @param __USART16CLKSource__ specifies the USART1/6 clock source. 1765 * This parameter can be one of the following values: 1766 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock 1767 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock 1768 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock 1769 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock 1770 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock 1771 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock 1772 */ 1773 #define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \ 1774 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__)) 1775 1776 /** @brief macro to get the USART1/6 clock source. 1777 * @retval The clock source can be one of the following values: 1778 * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock 1779 * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock 1780 * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock 1781 * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock 1782 * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock 1783 * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock 1784 */ 1785 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 1786 1787 /** @brief macro to configure the USART234578 clock (USART234578CLK). 1788 * 1789 * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. 1790 * This parameter can be one of the following values: 1791 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 1792 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 1793 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 1794 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 1795 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 1796 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 1797 */ 1798 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ 1799 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) 1800 1801 /** @brief macro to get the USART2/3/4/5/7/8 clock source. 1802 * @retval The clock source can be one of the following values: 1803 * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock 1804 * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock 1805 * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock 1806 * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock 1807 * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock 1808 * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock 1809 */ 1810 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1811 1812 /** @brief macro to configure the USART1 clock (USART1CLK). 1813 * 1814 * @param __USART1CLKSource__ specifies the USART1 clock source. 1815 * This parameter can be one of the following values: 1816 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 1817 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 1818 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 1819 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 1820 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 1821 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 1822 */ 1823 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ 1824 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__)) 1825 1826 /** @brief macro to get the USART1 clock source. 1827 * @retval The clock source can be one of the following values: 1828 * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock 1829 * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock 1830 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 1831 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 1832 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 1833 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 1834 */ 1835 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 1836 1837 /** @brief macro to configure the USART2 clock (USART2CLK). 1838 * 1839 * @param __USART2CLKSource__ specifies the USART2 clock source. 1840 * This parameter can be one of the following values: 1841 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 1842 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 1843 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 1844 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 1845 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 1846 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 1847 */ 1848 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ 1849 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__)) 1850 1851 /** @brief macro to get the USART2 clock source. 1852 * @retval The clock source can be one of the following values: 1853 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock 1854 * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock 1855 * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock 1856 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 1857 * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock 1858 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 1859 */ 1860 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1861 1862 /** @brief macro to configure the USART3 clock (USART3CLK). 1863 * 1864 * @param __USART3CLKSource__ specifies the USART3 clock source. 1865 * This parameter can be one of the following values: 1866 * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 1867 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 1868 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 1869 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 1870 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 1871 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 1872 */ 1873 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \ 1874 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__)) 1875 1876 /** @brief macro to get the USART3 clock source. 1877 * @retval The clock source can be one of the following values: 1878 * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock 1879 * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock 1880 * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock 1881 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 1882 * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock 1883 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 1884 */ 1885 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1886 1887 /** @brief macro to configure the UART4 clock (UART4CLK). 1888 * 1889 * @param __UART4CLKSource__ specifies the UART4 clock source. 1890 * This parameter can be one of the following values: 1891 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 1892 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 1893 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 1894 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 1895 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 1896 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 1897 */ 1898 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ 1899 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__)) 1900 1901 /** @brief macro to get the UART4 clock source. 1902 * @retval The clock source can be one of the following values: 1903 * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock 1904 * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock 1905 * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock 1906 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 1907 * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock 1908 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 1909 */ 1910 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1911 1912 /** @brief macro to configure the UART5 clock (UART5CLK). 1913 * 1914 * @param __UART5CLKSource__ specifies the UART5 clock source. 1915 * This parameter can be one of the following values: 1916 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 1917 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 1918 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 1919 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 1920 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 1921 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 1922 */ 1923 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ 1924 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__)) 1925 1926 /** @brief macro to get the UART5 clock source. 1927 * @retval The clock source can be one of the following values: 1928 * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock 1929 * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock 1930 * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock 1931 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 1932 * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock 1933 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 1934 */ 1935 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1936 1937 /** @brief macro to configure the USART6 clock (USART6CLK). 1938 * 1939 * @param __USART6CLKSource__ specifies the USART6 clock source. 1940 * This parameter can be one of the following values: 1941 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 1942 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 1943 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 1944 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1945 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1946 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 1947 */ 1948 #define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \ 1949 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__)) 1950 1951 /** @brief macro to get the USART6 clock source. 1952 * @retval The clock source can be one of the following values: 1953 * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock 1954 * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock 1955 * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock 1956 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1957 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1958 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 1959 */ 1960 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) 1961 1962 /** @brief macro to configure the UART5 clock (UART7CLK). 1963 * 1964 * @param __UART7CLKSource__ specifies the UART7 clock source. 1965 * This parameter can be one of the following values: 1966 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 1967 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 1968 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 1969 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 1970 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 1971 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 1972 */ 1973 #define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \ 1974 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__)) 1975 1976 /** @brief macro to get the UART7 clock source. 1977 * @retval The clock source can be one of the following values: 1978 * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock 1979 * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock 1980 * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock 1981 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 1982 * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock 1983 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 1984 */ 1985 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 1986 1987 /** @brief macro to configure the UART8 clock (UART8CLK). 1988 * 1989 * @param __UART8CLKSource__ specifies the UART8 clock source. 1990 * This parameter can be one of the following values: 1991 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 1992 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 1993 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 1994 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 1995 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 1996 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 1997 */ 1998 #define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \ 1999 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__)) 2000 2001 /** @brief macro to get the UART8 clock source. 2002 * @retval The clock source can be one of the following values: 2003 * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock 2004 * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock 2005 * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock 2006 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 2007 * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock 2008 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 2009 */ 2010 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) 2011 2012 /** @brief macro to configure the LPUART1 clock (LPUART1CLK). 2013 * 2014 * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. 2015 * This parameter can be one of the following values: 2016 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2017 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2018 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2019 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2020 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2021 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2022 */ 2023 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ 2024 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) 2025 2026 /** @brief macro to get the LPUART1 clock source. 2027 * @retval The clock source can be one of the following values: 2028 * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock 2029 * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock 2030 * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock 2031 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock 2032 * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock 2033 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock 2034 */ 2035 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) 2036 2037 /** @brief macro to configure the LPTIM1 clock source. 2038 * 2039 * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. 2040 * This parameter can be one of the following values: 2041 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2042 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2043 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2044 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2045 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2046 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2047 */ 2048 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 2049 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) 2050 2051 2052 /** @brief macro to get the LPTIM1 clock source. 2053 * @retval The clock source can be one of the following values: 2054 * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock 2055 * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock 2056 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock 2057 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 2058 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 2059 * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock 2060 */ 2061 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) 2062 2063 /** @brief macro to configure the LPTIM2 clock source. 2064 * 2065 * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. 2066 * This parameter can be one of the following values: 2067 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2068 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2069 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2070 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2071 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2072 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2073 */ 2074 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ 2075 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) 2076 2077 2078 /** @brief macro to get the LPTIM2 clock source. 2079 * @retval The clock source can be one of the following values: 2080 * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock 2081 * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock 2082 * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock 2083 * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock 2084 * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock 2085 * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock 2086 */ 2087 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) 2088 2089 /** @brief macro to configure the LPTIM3/4/5 clock source. 2090 * 2091 * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. 2092 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2093 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2094 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2095 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2096 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2097 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2098 */ 2099 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ 2100 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) 2101 2102 2103 /** @brief macro to get the LPTIM3/4/5 clock source. 2104 * @retval The clock source can be one of the following values: 2105 * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock 2106 * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock 2107 * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock 2108 * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock 2109 * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock 2110 * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock 2111 */ 2112 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2113 2114 /** @brief macro to configure the LPTIM3 clock source. 2115 * 2116 * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. 2117 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2118 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2119 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2120 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2121 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2122 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2123 */ 2124 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \ 2125 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__)) 2126 2127 2128 /** @brief macro to get the LPTIM3 clock source. 2129 * @retval The clock source can be one of the following values: 2130 * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock 2131 * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock 2132 * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock 2133 * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock 2134 * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock 2135 * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock 2136 */ 2137 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2138 2139 /** @brief macro to configure the LPTIM4 clock source. 2140 * 2141 * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. 2142 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2143 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2144 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2145 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2146 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2147 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2148 */ 2149 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \ 2150 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__)) 2151 2152 2153 /** @brief macro to get the LPTIM4 clock source. 2154 * @retval The clock source can be one of the following values: 2155 * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock 2156 * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock 2157 * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock 2158 * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock 2159 * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock 2160 * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock 2161 */ 2162 #define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2163 2164 /** @brief macro to configure the LPTIM5 clock source. 2165 * 2166 * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. 2167 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2168 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2169 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2170 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2171 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2172 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2173 */ 2174 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \ 2175 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__)) 2176 2177 2178 /** @brief macro to get the LPTIM5 clock source. 2179 * @retval The clock source can be one of the following values: 2180 * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock 2181 * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock 2182 * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock 2183 * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock 2184 * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock 2185 * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock 2186 */ 2187 #define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) 2188 2189 /** @brief macro to configure the QSPI clock source. 2190 * 2191 * @param __QSPICLKSource__ specifies the QSPI clock source. 2192 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2193 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2194 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2195 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2196 */ 2197 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 2198 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) 2199 2200 2201 /** @brief macro to get the QSPI clock source. 2202 * @retval The clock source can be one of the following values: 2203 * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock 2204 * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock 2205 * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock 2206 * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock 2207 */ 2208 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) 2209 2210 #if defined(DSI) 2211 /** @brief macro to configure the DSI clock source. 2212 * 2213 * @param __DSICLKSource__ specifies the DSI clock source. 2214 * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock 2215 * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock 2216 */ 2217 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 2218 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) 2219 2220 2221 /** @brief macro to get the DSI clock source. 2222 * @retval The clock source can be one of the following values: 2223 * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock 2224 * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock 2225 */ 2226 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) 2227 #endif /*DSI*/ 2228 2229 /** @brief macro to configure the FMC clock source. 2230 * 2231 * @param __FMCCLKSource__ specifies the FMC clock source. 2232 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 2233 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 2234 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 2235 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 2236 */ 2237 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 2238 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) 2239 2240 2241 /** @brief macro to get the FMC clock source. 2242 * @retval The clock source can be one of the following values: 2243 * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock 2244 * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock 2245 * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock 2246 * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock 2247 */ 2248 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) 2249 2250 /** @brief Macro to configure the USB clock (USBCLK). 2251 * @param __USBCLKSource__ specifies the USB clock source. 2252 * This parameter can be one of the following values: 2253 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 2254 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 2255 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 2256 */ 2257 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 2258 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) 2259 2260 /** @brief Macro to get the USB clock source. 2261 * @retval The clock source can be one of the following values: 2262 * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock 2263 * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock 2264 * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock 2265 */ 2266 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) 2267 2268 2269 /** @brief Macro to configure the ADC clock 2270 * @param __ADCCLKSource__ specifies the ADC digital interface clock source. 2271 * This parameter can be one of the following values: 2272 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 2273 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 2274 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 2275 */ 2276 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 2277 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) 2278 2279 /** @brief Macro to get the ADC clock source. 2280 * @retval The clock source can be one of the following values: 2281 * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock 2282 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock 2283 * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock 2284 */ 2285 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) 2286 2287 /** @brief Macro to configure the SWPMI1 clock 2288 * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. 2289 * This parameter can be one of the following values: 2290 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 2291 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 2292 */ 2293 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ 2294 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) 2295 2296 /** @brief Macro to get the SWPMI1 clock source. 2297 * @retval The clock source can be one of the following values: 2298 * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock 2299 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock 2300 */ 2301 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) 2302 2303 /** @brief Macro to configure the DFSDM1 clock 2304 * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. 2305 * This parameter can be one of the following values: 2306 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 2307 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 2308 */ 2309 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ 2310 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) 2311 2312 /** @brief Macro to get the DFSDM1 clock source. 2313 * @retval The clock source can be one of the following values: 2314 * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock 2315 * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock 2316 */ 2317 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) 2318 2319 /** @brief macro to configure the CEC clock (CECCLK). 2320 * 2321 * @param __CECCLKSource__ specifies the CEC clock source. 2322 * This parameter can be one of the following values: 2323 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 2324 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 2325 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 2326 */ 2327 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 2328 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) 2329 2330 /** @brief macro to get the CEC clock source. 2331 * @retval The clock source can be one of the following values: 2332 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 2333 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 2334 * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock 2335 */ 2336 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) 2337 2338 2339 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 2340 * @param __CLKPSource__ specifies Oscillator clock for peripheral 2341 * This parameter can be one of the following values: 2342 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 2343 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 2344 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 2345 */ 2346 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 2347 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) 2348 2349 /** @brief Macro to get the Oscillator clock for peripheral source. 2350 * @retval The clock source can be one of the following values: 2351 * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral 2352 * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral 2353 * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral 2354 */ 2355 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) 2356 2357 #if defined(FDCAN1) || defined(FDCAN2) 2358 /** @brief Macro to configure the FDCAN clock 2359 * @param __FDCANCLKSource__ specifies clock source for FDCAN 2360 * This parameter can be one of the following values: 2361 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 2362 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 2363 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 2364 */ 2365 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 2366 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) 2367 2368 /** @brief Macro to get the FDCAN clock 2369 * @retval The clock source can be one of the following values: 2370 * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock 2371 * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock 2372 * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock 2373 */ 2374 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) 2375 #endif /*FDCAN1 || FDCAN2*/ 2376 /** 2377 * @brief Macro to Configure the SPI1/2/3 clock source. 2378 * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived 2379 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2380 * This parameter can be one of the following values: 2381 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 2382 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 2383 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 2384 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 2385 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 2386 * @retval None 2387 */ 2388 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ 2389 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) 2390 2391 /** @brief Macro to get the SPI1/2/3 clock source. 2392 * @retval The clock source can be one of the following values: 2393 * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL 2394 * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 2395 * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 2396 * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP 2397 * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock 2398 */ 2399 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 2400 2401 /** 2402 * @brief Macro to Configure the SPI1 clock source. 2403 * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived 2404 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2405 * This parameter can be one of the following values: 2406 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 2407 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 2408 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 2409 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 2410 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 2411 * @retval None 2412 */ 2413 #define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\ 2414 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__)) 2415 2416 /** @brief Macro to get the SPI1 clock source. 2417 * @retval The clock source can be one of the following values: 2418 * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL 2419 * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 2420 * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 2421 * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP 2422 * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock 2423 */ 2424 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 2425 2426 /** 2427 * @brief Macro to Configure the SPI2 clock source. 2428 * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived 2429 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2430 * This parameter can be one of the following values: 2431 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 2432 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 2433 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 2434 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 2435 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 2436 * @retval None 2437 */ 2438 #define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\ 2439 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__)) 2440 2441 /** @brief Macro to get the SPI2 clock source. 2442 * @retval The clock source can be one of the following values: 2443 * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL 2444 * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 2445 * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 2446 * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP 2447 * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock 2448 */ 2449 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 2450 2451 /** 2452 * @brief Macro to Configure the SPI3 clock source. 2453 * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived 2454 * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) 2455 * This parameter can be one of the following values: 2456 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 2457 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 2458 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 2459 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 2460 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 2461 * @retval None 2462 */ 2463 #define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\ 2464 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__)) 2465 2466 /** @brief Macro to get the SPI3 clock source. 2467 * @retval The clock source can be one of the following values: 2468 * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL 2469 * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 2470 * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 2471 * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP 2472 * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock 2473 */ 2474 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) 2475 2476 /** 2477 * @brief Macro to Configure the SPI4/5 clock source. 2478 * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived 2479 * from system PCLK, PLL2, PLL3, OSC 2480 * This parameter can be one of the following values: 2481 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 2482 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 2483 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 2484 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 2485 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 2486 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 2487 * @retval None 2488 */ 2489 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ 2490 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) 2491 2492 /** @brief Macro to get the SPI4/5 clock source. 2493 * @retval The clock source can be one of the following values: 2494 * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 2495 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 2496 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 2497 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI 2498 * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI 2499 * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE 2500 */ 2501 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 2502 2503 /** 2504 * @brief Macro to Configure the SPI4 clock source. 2505 * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived 2506 * from system PCLK, PLL2, PLL3, OSC 2507 * This parameter can be one of the following values: 2508 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 2509 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 2510 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 2511 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 2512 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 2513 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 2514 * @retval None 2515 */ 2516 #define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\ 2517 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__)) 2518 2519 /** @brief Macro to get the SPI4 clock source. 2520 * @retval The clock source can be one of the following values: 2521 * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 2522 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 2523 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 2524 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI 2525 * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI 2526 * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE 2527 */ 2528 #define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 2529 2530 /** 2531 * @brief Macro to Configure the SPI5 clock source. 2532 * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived 2533 * from system PCLK, PLL2, PLL3, OSC 2534 * This parameter can be one of the following values: 2535 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 2536 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 2537 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 2538 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 2539 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 2540 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 2541 * @retval None 2542 */ 2543 #define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\ 2544 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__)) 2545 2546 /** @brief Macro to get the SPI5 clock source. 2547 * @retval The clock source can be one of the following values: 2548 * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 2549 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 2550 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 2551 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI 2552 * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI 2553 * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE 2554 */ 2555 #define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) 2556 2557 /** 2558 * @brief Macro to Configure the SPI6 clock source. 2559 * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived 2560 * from system PCLK, PLL2, PLL3, OSC 2561 * This parameter can be one of the following values: 2562 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 2563 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 2564 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 2565 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 2566 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 2567 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 2568 * @retval None 2569 */ 2570 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ 2571 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) 2572 2573 /** @brief Macro to get the SPI6 clock source. 2574 * @retval The clock source can be one of the following values: 2575 * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 2576 * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 2577 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 2578 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 2579 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 2580 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 2581 */ 2582 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) 2583 2584 /** @brief Macro to configure the SDMMC clock 2585 * @param __SDMMCCLKSource__ specifies clock source for SDMMC 2586 * This parameter can be one of the following values: 2587 * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock 2588 * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock 2589 */ 2590 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ 2591 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) 2592 2593 /** @brief Macro to get the SDMMC clock 2594 */ 2595 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) 2596 2597 /** @brief macro to configure the RNG clock (RNGCLK). 2598 * 2599 * @param __RNGCLKSource__ specifies the RNG clock source. 2600 * This parameter can be one of the following values: 2601 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2602 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 2603 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2604 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2605 */ 2606 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 2607 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) 2608 2609 /** @brief macro to get the RNG clock source. 2610 * @retval The clock source can be one of the following values: 2611 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2612 * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock 2613 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2614 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2615 */ 2616 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) 2617 2618 2619 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config 2620 * @{ 2621 */ 2622 /** @brief Macro to configure the HRTIM1 prescaler clock source. 2623 * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. 2624 * This parameter can be one of the following values: 2625 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 2626 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 2627 */ 2628 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ 2629 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) 2630 2631 /** @brief Macro to get the HRTIM1 clock source. 2632 * @retval The clock source can be one of the following values: 2633 * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock 2634 * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock 2635 */ 2636 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) 2637 2638 /** @brief Macro to configure the Timers clocks prescalers 2639 * @param __PRESC__ specifies the Timers clocks prescalers selection 2640 * This parameter can be one of the following values: 2641 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 2642 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, 2643 * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) 2644 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 2645 * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, 2646 * else it is equal to 4 x Frcc_pclkx_d2 2647 */ 2648 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ 2649 RCC->CFGR |= (__PRESC__); \ 2650 }while(0) 2651 2652 /** 2653 * @} 2654 */ 2655 /** 2656 * @brief Enable the specified CRS interrupts. 2657 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2658 * This parameter can be any combination of the following values: 2659 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2660 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2661 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2662 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2663 * @retval None 2664 */ 2665 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 2666 2667 /** 2668 * @brief Disable the specified CRS interrupts. 2669 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 2670 * This parameter can be any combination of the following values: 2671 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2672 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2673 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2674 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2675 * @retval None 2676 */ 2677 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 2678 2679 /** @brief Check whether the CRS interrupt has occurred or not. 2680 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 2681 * This parameter can be one of the following values: 2682 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2683 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2684 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2685 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2686 * @retval The new state of __INTERRUPT__ (SET or RESET). 2687 */ 2688 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 2689 2690 /** @brief Clear the CRS interrupt pending bits 2691 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2692 * This parameter can be any combination of the following values: 2693 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2694 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2695 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2696 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2697 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 2698 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 2699 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 2700 */ 2701 /* CRS IT Error Mask */ 2702 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 2703 2704 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 2705 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 2706 { \ 2707 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 2708 } \ 2709 else \ 2710 { \ 2711 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 2712 } \ 2713 } while(0) 2714 2715 /** 2716 * @brief Check whether the specified CRS flag is set or not. 2717 * @param __FLAG__ specifies the flag to check. 2718 * This parameter can be one of the following values: 2719 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2720 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2721 * @arg @ref RCC_CRS_FLAG_ERR Error 2722 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2723 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2724 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2725 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2726 * @retval The new state of _FLAG_ (TRUE or FALSE). 2727 */ 2728 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 2729 2730 /** 2731 * @brief Clear the CRS specified FLAG. 2732 * @param __FLAG__ specifies the flag to clear. 2733 * This parameter can be one of the following values: 2734 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2735 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2736 * @arg @ref RCC_CRS_FLAG_ERR Error 2737 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2738 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2739 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2740 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2741 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 2742 * @retval None 2743 */ 2744 2745 /* CRS Flag Error Mask */ 2746 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 2747 2748 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 2749 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 2750 { \ 2751 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 2752 } \ 2753 else \ 2754 { \ 2755 WRITE_REG(CRS->ICR, (__FLAG__)); \ 2756 } \ 2757 } while(0) 2758 2759 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 2760 * @{ 2761 */ 2762 /** 2763 * @brief Enable the oscillator clock for frequency error counter. 2764 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 2765 * @retval None 2766 */ 2767 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 2768 2769 /** 2770 * @brief Disable the oscillator clock for frequency error counter. 2771 * @retval None 2772 */ 2773 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 2774 2775 /** 2776 * @brief Enable the automatic hardware adjustment of TRIM bits. 2777 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 2778 * @retval None 2779 */ 2780 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2781 2782 /** 2783 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 2784 * @retval None 2785 */ 2786 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2787 2788 /** 2789 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 2790 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 2791 * of the synchronization source after pre-scaling. It is then decreased by one in order to 2792 * reach the expected synchronization on the zero value. The formula is the following: 2793 * RELOAD = (fTARGET / fSYNC) -1 2794 * @param __FTARGET__ Target frequency (value in Hz) 2795 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 2796 * @retval None 2797 */ 2798 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 2799 2800 2801 /** 2802 * @} 2803 */ 2804 2805 2806 /** 2807 * @} 2808 */ 2809 2810 2811 /* Exported functions --------------------------------------------------------*/ 2812 /** @addtogroup RCCEx_Exported_Functions_Group1 2813 * @{ 2814 */ 2815 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2816 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2817 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 2818 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); 2819 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); 2820 uint32_t HAL_RCCEx_GetD1SysClockFreq(void); 2821 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks); 2822 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks); 2823 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks); 2824 /** 2825 * @} 2826 */ 2827 2828 /** @addtogroup RCCEx_Exported_Functions_Group2 2829 * @{ 2830 */ 2831 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 2832 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 2833 void HAL_RCCEx_EnableLSECSS(void); 2834 void HAL_RCCEx_DisableLSECSS(void); 2835 #if defined(DUAL_CORE) 2836 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 2837 #endif /*DUAL_CORE*/ 2838 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); 2839 /** 2840 * @} 2841 */ 2842 2843 2844 /** @addtogroup RCCEx_Exported_Functions_Group3 2845 * @{ 2846 */ 2847 2848 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 2849 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 2850 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 2851 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 2852 void HAL_RCCEx_CRS_IRQHandler(void); 2853 void HAL_RCCEx_CRS_SyncOkCallback(void); 2854 void HAL_RCCEx_CRS_SyncWarnCallback(void); 2855 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 2856 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 2857 2858 /** 2859 * @} 2860 */ 2861 2862 /* Private macros ------------------------------------------------------------*/ 2863 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros 2864 * @{ 2865 */ 2866 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 2867 * @{ 2868 */ 2869 2870 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ 2871 ((VALUE) == RCC_PLL2_DIVQ) || \ 2872 ((VALUE) == RCC_PLL2_DIVR)) 2873 2874 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 2875 ((VALUE) == RCC_PLL3_DIVQ) || \ 2876 ((VALUE) == RCC_PLL3_DIVR)) 2877 2878 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ 2879 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ 2880 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ 2881 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ 2882 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ 2883 ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) 2884 2885 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ 2886 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ 2887 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ 2888 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ 2889 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ 2890 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) 2891 2892 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ 2893 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ 2894 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 2895 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 2896 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 2897 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 2898 2899 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ 2900 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ 2901 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ 2902 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ 2903 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 2904 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 2905 2906 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ 2907 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ 2908 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ 2909 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ 2910 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 2911 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 2912 2913 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ 2914 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ 2915 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ 2916 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ 2917 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 2918 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 2919 2920 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ 2921 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ 2922 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ 2923 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ 2924 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 2925 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 2926 2927 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ 2928 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ 2929 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ 2930 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 2931 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ 2932 ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 2933 2934 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \ 2935 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ 2936 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ 2937 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ 2938 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ 2939 ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 2940 2941 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \ 2942 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ 2943 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ 2944 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ 2945 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ 2946 ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 2947 2948 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ 2949 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ 2950 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ 2951 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ 2952 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ 2953 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) 2954 2955 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ 2956 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ 2957 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ 2958 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) 2959 2960 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ 2961 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ 2962 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ 2963 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) 2964 2965 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ 2966 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 2967 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ 2968 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) 2969 2970 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ 2971 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 2972 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ 2973 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 2974 2975 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ 2976 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ 2977 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ 2978 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) 2979 2980 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ 2981 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ 2982 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ 2983 ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) 2984 2985 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ 2986 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) 2987 2988 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ 2989 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ 2990 ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) 2991 2992 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2993 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2994 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ 2995 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ 2996 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ 2997 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 2998 2999 #define IS_RCC_SAI23CLK(__SOURCE__) \ 3000 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ 3001 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ 3002 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ 3003 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ 3004 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) 3005 3006 #define IS_RCC_SAI2CLK(__SOURCE__) \ 3007 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 3008 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ 3009 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ 3010 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ 3011 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 3012 3013 #define IS_RCC_SAI3CLK(__SOURCE__) \ 3014 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ 3015 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ 3016 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ 3017 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ 3018 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) 3019 3020 #define IS_RCC_SPI123CLK(__SOURCE__) \ 3021 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ 3022 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ 3023 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ 3024 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ 3025 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) 3026 3027 #define IS_RCC_SPI1CLK(__SOURCE__) \ 3028 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ 3029 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ 3030 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ 3031 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ 3032 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) 3033 3034 #define IS_RCC_SPI2CLK(__SOURCE__) \ 3035 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ 3036 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ 3037 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ 3038 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ 3039 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) 3040 3041 #define IS_RCC_SPI3CLK(__SOURCE__) \ 3042 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ 3043 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ 3044 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ 3045 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ 3046 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) 3047 3048 #define IS_RCC_SPI45CLK(__SOURCE__) \ 3049 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \ 3050 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ 3051 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ 3052 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 3053 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 3054 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 3055 3056 #define IS_RCC_SPI4CLK(__SOURCE__) \ 3057 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \ 3058 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ 3059 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ 3060 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 3061 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 3062 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 3063 3064 #define IS_RCC_SPI5CLK(__SOURCE__) \ 3065 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \ 3066 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ 3067 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ 3068 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 3069 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 3070 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 3071 3072 #define IS_RCC_SPI6CLK(__SOURCE__) \ 3073 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ 3074 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ 3075 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ 3076 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 3077 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 3078 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 3079 3080 #define IS_RCC_SAI4ACLK(__SOURCE__) \ 3081 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ 3082 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ 3083 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ 3084 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ 3085 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) 3086 3087 #define IS_RCC_SAI4BCLK(__SOURCE__) \ 3088 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ 3089 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ 3090 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ 3091 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ 3092 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) 3093 3094 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3095 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3096 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3097 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3098 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3099 3100 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3101 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3102 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3103 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3104 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3105 3106 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ 3107 ((VALUE) == RCC_PLL2VCIRANGE_1) || \ 3108 ((VALUE) == RCC_PLL2VCIRANGE_2) || \ 3109 ((VALUE) == RCC_PLL2VCIRANGE_3)) 3110 3111 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ 3112 ((VALUE) == RCC_PLL3VCIRANGE_1) || \ 3113 ((VALUE) == RCC_PLL3VCIRANGE_2) || \ 3114 ((VALUE) == RCC_PLL3VCIRANGE_3)) 3115 3116 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ 3117 ((VALUE) == RCC_PLL2VCOMEDIUM)) 3118 3119 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ 3120 ((VALUE) == RCC_PLL3VCOMEDIUM)) 3121 3122 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U) 3123 3124 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ 3125 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ 3126 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 3127 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3128 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3129 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) 3130 3131 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ 3132 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ 3133 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ 3134 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3135 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3136 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) 3137 3138 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ 3139 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ 3140 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ 3141 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ 3142 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ 3143 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) 3144 3145 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \ 3146 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ 3147 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ 3148 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ 3149 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ 3150 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) 3151 3152 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ 3153 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ 3154 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ 3155 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ 3156 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ 3157 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) 3158 3159 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ 3160 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ 3161 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ 3162 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ 3163 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ 3164 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) 3165 3166 #define IS_RCC_QSPICLK(__SOURCE__) \ 3167 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ 3168 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ 3169 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ 3170 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) 3171 3172 #if defined(DSI) 3173 #define IS_RCC_DSICLK(__SOURCE__) \ 3174 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 3175 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) 3176 #endif /*DSI*/ 3177 3178 #define IS_RCC_FMCCLK(__SOURCE__) \ 3179 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ 3180 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ 3181 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ 3182 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) 3183 3184 #if defined(FDCAN1) || defined(FDCAN2) 3185 #define IS_RCC_FDCANCLK(__SOURCE__) \ 3186 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 3187 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 3188 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) 3189 #endif /*FDCAN1 || FDCAN2*/ 3190 3191 #define IS_RCC_SDMMC(__SOURCE__) \ 3192 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ 3193 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) 3194 3195 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ 3196 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ 3197 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) 3198 3199 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ 3200 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) 3201 3202 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ 3203 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) 3204 3205 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ 3206 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ 3207 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 3208 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 3209 3210 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 3211 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 3212 ((SOURCE) == RCC_CECCLKSOURCE_CSI)) 3213 3214 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 3215 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 3216 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 3217 #define IS_RCC_TIMPRES(VALUE) \ 3218 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ 3219 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 3220 3221 #if defined(DUAL_CORE) 3222 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 3223 ((CORE) == RCC_BOOT_C2)) 3224 #endif /*DUAL_CORE*/ 3225 3226 #if defined(DUAL_CORE) 3227 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ 3228 ((WWDG) == RCC_WWDG2)) 3229 #else 3230 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) 3231 3232 #endif /*DUAL_CORE*/ 3233 3234 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ 3235 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3236 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ 3237 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) 3238 3239 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3240 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3241 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3242 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3243 3244 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3245 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3246 3247 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3248 3249 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3250 3251 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 3252 3253 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3254 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3255 /** 3256 * @} 3257 */ 3258 3259 /** 3260 * @} 3261 */ 3262 /** 3263 * @} 3264 */ 3265 3266 /** 3267 * @} 3268 */ 3269 3270 #ifdef __cplusplus 3271 } 3272 #endif 3273 3274 #endif /* STM32H7xx_HAL_RCC_EX_H */ 3275 3276 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3277