1 /*- 2 * This code is derived from software copyrighted by the Free Software 3 * Foundation. 4 * 5 * Modified 1991 by Donn Seeley at UUNET Technologies, Inc. 6 * 7 * @(#)i386-opcode.h 6.3 (Berkeley) 05/08/91 8 */ 9 10 /* i386-opcode.h -- Intel 80386 opcode table 11 Copyright (C) 1989, Free Software Foundation. 12 13 This file is part of GAS, the GNU Assembler. 14 15 GAS is free software; you can redistribute it and/or modify 16 it under the terms of the GNU General Public License as published by 17 the Free Software Foundation; either version 1, or (at your option) 18 any later version. 19 20 GAS is distributed in the hope that it will be useful, 21 but WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 GNU General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with GAS; see the file COPYING. If not, write to 27 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 28 29 template i386_optab[] = { 30 31 #define _ None 32 /* move instructions */ 33 { "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 }, 34 { "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 }, 35 { "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 }, 36 { "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 }, 37 { "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 }, 38 /* move to/from control debug registers */ 39 { "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0}, 40 { "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0}, 41 { "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0}, 42 43 /* move with sign extend */ 44 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 45 conflict with the "movs" string move instruction. Thus, 46 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, 47 is not kosher; we must seperate the two instructions. */ 48 {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0}, 49 {"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0}, 50 {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, 51 52 /* move with zero extend */ 53 {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, 54 {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, 55 56 /* push instructions */ 57 {"push", 1, 0x50, _, ShortForm, WordReg,0,0 }, 58 {"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 }, 59 {"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0}, 60 {"push", 1, 0x68, _, NoModrm, Imm32, 0, 0}, 61 {"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 }, 62 {"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 }, 63 /* push all */ 64 {"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 }, 65 66 /* pop instructions */ 67 {"pop", 1, 0x58, _, ShortForm, WordReg,0,0 }, 68 {"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 }, 69 #define POP_SEG_SHORT 0x7 70 {"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 }, 71 {"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 }, 72 /* pop all */ 73 {"popa", 0, 0x61, _, NoModrm, 0, 0, 0 }, 74 75 /* xchg exchange instructions 76 xchg commutes: we allow both operand orders */ 77 {"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 }, 78 {"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 }, 79 {"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 }, 80 {"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 }, 81 82 /* in/out from ports */ 83 {"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 }, 84 {"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 }, 85 {"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 }, 86 {"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 }, 87 88 /* load effective address */ 89 {"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 }, 90 91 /* load segment registers from memory */ 92 {"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0}, 93 {"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0}, 94 {"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0}, 95 {"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0}, 96 {"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0}, 97 98 /* flags register instructions */ 99 {"clc", 0, 0xf8, _, NoModrm, 0, 0, 0}, 100 {"cld", 0, 0xfc, _, NoModrm, 0, 0, 0}, 101 {"cli", 0, 0xfa, _, NoModrm, 0, 0, 0}, 102 {"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0}, 103 {"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0}, 104 {"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0}, 105 {"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0}, 106 {"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0}, 107 {"popf", 0, 0x9d, _, NoModrm, 0, 0, 0}, 108 {"stc", 0, 0xf9, _, NoModrm, 0, 0, 0}, 109 {"std", 0, 0xfd, _, NoModrm, 0, 0, 0}, 110 {"sti", 0, 0xfb, _, NoModrm, 0, 0, 0}, 111 112 {"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0}, 113 {"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0}, 114 {"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0}, 115 {"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0}, 116 117 {"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0}, 118 {"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0}, 119 120 {"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0}, 121 {"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0}, 122 {"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0}, 123 {"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0}, 124 125 {"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0}, 126 {"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0}, 127 128 {"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0}, 129 {"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0}, 130 {"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0}, 131 {"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0}, 132 133 {"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0}, 134 {"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0}, 135 {"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0}, 136 {"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0}, 137 138 {"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0}, 139 {"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0}, 140 {"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0}, 141 {"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0}, 142 143 {"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0}, 144 {"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0}, 145 {"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0}, 146 {"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0}, 147 148 {"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0}, 149 {"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0}, 150 {"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0}, 151 {"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0}, 152 153 {"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0}, 154 {"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0}, 155 {"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0}, 156 {"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0}, 157 158 {"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0}, 159 {"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0}, 160 {"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0}, 161 {"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0}, 162 163 {"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0}, 164 {"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0}, 165 166 {"aaa", 0, 0x37, _, NoModrm, 0, 0, 0}, 167 {"aas", 0, 0x3f, _, NoModrm, 0, 0, 0}, 168 {"daa", 0, 0x27, _, NoModrm, 0, 0, 0}, 169 {"das", 0, 0x2f, _, NoModrm, 0, 0, 0}, 170 {"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0}, 171 {"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0}, 172 173 /* conversion insns */ 174 /* conversion: intel naming */ 175 {"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0}, 176 {"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0}, 177 {"cwde", 0, 0x98, _, NoModrm, 0, 0, 0}, 178 {"cdq", 0, 0x99, _, NoModrm, 0, 0, 0}, 179 /* att naming */ 180 {"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0}, 181 {"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0}, 182 {"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0}, 183 {"cltd", 0, 0x99, _, NoModrm, 0, 0, 0}, 184 185 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 186 expanding 64-bit multiplies, and *cannot* be selected to accomplish 187 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 188 These multiplies can only be selected with single opearnd forms. */ 189 {"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0}, 190 {"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0}, 191 192 193 194 195 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. 196 These instructions are exceptions: 'imul $2, %eax, %ecx' would put 197 '%eax' in the reg field and '%ecx' in the regmem field if we did not 198 switch them. */ 199 {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 200 {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg}, 201 {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg}, 202 /* 203 imul with 2 operands mimicks imul with 3 by puting register both 204 in i.rm.reg & i.rm.regmem fields 205 */ 206 {"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0}, 207 {"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0}, 208 {"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0}, 209 {"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0}, 210 {"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0}, 211 {"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0}, 212 213 {"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0}, 214 {"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0}, 215 {"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0}, 216 {"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0}, 217 218 {"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0}, 219 {"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0}, 220 {"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0}, 221 {"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0}, 222 223 {"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0}, 224 {"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0}, 225 {"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0}, 226 {"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0}, 227 228 {"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0}, 229 {"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0}, 230 {"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0}, 231 {"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0}, 232 233 {"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, 234 {"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, 235 {"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, 236 {"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, 237 {"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, 238 {"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, 239 {"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, 240 {"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, 241 242 {"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem}, 243 {"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, 244 245 {"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0}, 246 {"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0}, 247 {"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0}, 248 {"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0}, 249 250 {"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem}, 251 {"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, 252 253 {"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0}, 254 {"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0}, 255 {"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0}, 256 {"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0}, 257 258 /* control transfer instructions */ 259 #define CALL_PC_RELATIVE 0xe8 260 {"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0}, 261 {"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0}, 262 #define CALL_FAR_IMMEDIATE 0x9a 263 {"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Imm32, 0}, 264 {"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0}, 265 266 #define JUMP_PC_RELATIVE 0xeb 267 {"jmp", 1, 0xeb, _, Jump, Disp, 0, 0}, 268 {"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0}, 269 #define JUMP_FAR_IMMEDIATE 0xea 270 {"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0}, 271 {"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0}, 272 273 {"ret", 0, 0xc3, _, NoModrm, 0, 0, 0}, 274 {"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0}, 275 {"lret", 0, 0xcb, _, NoModrm, 0, 0, 0}, 276 {"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0}, 277 {"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0}, 278 {"leave", 0, 0xc9, _, NoModrm, 0, 0, 0}, 279 280 /* conditional jumps */ 281 {"jo", 1, 0x70, _, Jump, Disp, 0, 0}, 282 283 {"jno", 1, 0x71, _, Jump, Disp, 0, 0}, 284 285 {"jb", 1, 0x72, _, Jump, Disp, 0, 0}, 286 {"jc", 1, 0x72, _, Jump, Disp, 0, 0}, 287 {"jnae", 1, 0x72, _, Jump, Disp, 0, 0}, 288 289 {"jnb", 1, 0x73, _, Jump, Disp, 0, 0}, 290 {"jnc", 1, 0x73, _, Jump, Disp, 0, 0}, 291 {"jae", 1, 0x73, _, Jump, Disp, 0, 0}, 292 293 {"je", 1, 0x74, _, Jump, Disp, 0, 0}, 294 {"jz", 1, 0x74, _, Jump, Disp, 0, 0}, 295 296 {"jne", 1, 0x75, _, Jump, Disp, 0, 0}, 297 {"jnz", 1, 0x75, _, Jump, Disp, 0, 0}, 298 299 {"jbe", 1, 0x76, _, Jump, Disp, 0, 0}, 300 {"jna", 1, 0x76, _, Jump, Disp, 0, 0}, 301 302 {"jnbe", 1, 0x77, _, Jump, Disp, 0, 0}, 303 {"ja", 1, 0x77, _, Jump, Disp, 0, 0}, 304 305 {"js", 1, 0x78, _, Jump, Disp, 0, 0}, 306 307 {"jns", 1, 0x79, _, Jump, Disp, 0, 0}, 308 309 {"jp", 1, 0x7a, _, Jump, Disp, 0, 0}, 310 {"jpe", 1, 0x7a, _, Jump, Disp, 0, 0}, 311 312 {"jnp", 1, 0x7b, _, Jump, Disp, 0, 0}, 313 {"jpo", 1, 0x7b, _, Jump, Disp, 0, 0}, 314 315 {"jl", 1, 0x7c, _, Jump, Disp, 0, 0}, 316 {"jnge", 1, 0x7c, _, Jump, Disp, 0, 0}, 317 318 {"jnl", 1, 0x7d, _, Jump, Disp, 0, 0}, 319 {"jge", 1, 0x7d, _, Jump, Disp, 0, 0}, 320 321 {"jle", 1, 0x7e, _, Jump, Disp, 0, 0}, 322 {"jng", 1, 0x7e, _, Jump, Disp, 0, 0}, 323 324 {"jnle", 1, 0x7f, _, Jump, Disp, 0, 0}, 325 {"jg", 1, 0x7f, _, Jump, Disp, 0, 0}, 326 327 /* these turn into pseudo operations when disp is larger than 8 bits */ 328 #define IS_JUMP_ON_CX_ZERO(o) \ 329 (o == 0x67e3) 330 #define IS_JUMP_ON_ECX_ZERO(o) \ 331 (o == 0xe3) 332 333 {"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0}, 334 {"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0}, 335 336 #define IS_LOOP_ECX_TIMES(o) \ 337 (o == 0xe2 || o == 0xe1 || o == 0xe0) 338 339 {"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0}, 340 341 {"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0}, 342 {"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0}, 343 344 {"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0}, 345 {"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0}, 346 347 /* set byte on flag instructions */ 348 {"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0}, 349 350 {"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0}, 351 352 {"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, 353 {"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, 354 355 {"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, 356 {"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, 357 358 {"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, 359 {"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, 360 361 {"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, 362 {"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, 363 364 {"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, 365 {"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, 366 367 {"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, 368 {"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, 369 370 {"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0}, 371 372 {"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0}, 373 374 {"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, 375 {"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, 376 377 {"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, 378 {"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, 379 380 {"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, 381 {"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, 382 383 {"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, 384 {"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, 385 386 {"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, 387 {"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, 388 389 {"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, 390 {"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, 391 392 #define IS_STRING_INSTRUCTION(o) \ 393 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ 394 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ 395 (o) == 0xd7) 396 397 /* string manipulation */ 398 {"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0}, 399 {"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0}, 400 {"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0}, 401 {"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0}, 402 {"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0}, 403 {"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0}, 404 {"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0}, 405 {"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0}, 406 407 /* bit manipulation */ 408 {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, 409 {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, 410 {"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0}, 411 {"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0}, 412 {"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0}, 413 {"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0}, 414 {"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0}, 415 {"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0}, 416 {"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0}, 417 {"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0}, 418 419 /* interrupts & op. sys insns */ 420 /* See i386.c for conversion of 'int $3' into the special int 3 insn. */ 421 #define INT_OPCODE 0xcd 422 #define INT3_OPCODE 0xcc 423 {"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0}, 424 {"int3", 0, 0xcc, _, NoModrm, 0, 0, 0}, 425 {"into", 0, 0xce, _, NoModrm, 0, 0, 0}, 426 {"iret", 0, 0xcf, _, NoModrm, 0, 0, 0}, 427 428 {"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0}, 429 {"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0}, 430 431 {"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0}, 432 {"wait", 0, 0x9b, _, NoModrm, 0, 0, 0}, 433 /* nop is actually 'xchgl %eax, %eax' */ 434 {"nop", 0, 0x90, _, NoModrm, 0, 0, 0}, 435 436 /* protection control */ 437 {"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0}, 438 {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 439 {"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0}, 440 {"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0}, 441 {"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0}, 442 {"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0}, 443 {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 444 {"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0}, 445 446 {"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0}, 447 {"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0}, 448 {"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0}, 449 {"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0}, 450 {"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0}, 451 452 {"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0}, 453 {"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0}, 454 455 /* floating point instructions */ 456 457 /* load */ 458 {"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ 459 {"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */ 460 {"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */ 461 {"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */ 462 {"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ 463 {"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */ 464 {"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */ 465 {"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */ 466 {"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */ 467 468 /* store (no pop) */ 469 {"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ 470 {"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ 471 {"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ 472 {"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ 473 {"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ 474 {"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ 475 476 /* store (with pop) */ 477 {"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ 478 {"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ 479 {"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ 480 {"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ 481 {"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ 482 {"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ 483 {"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */ 484 {"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */ 485 {"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */ 486 487 /* exchange %st<n> with %st0 */ 488 {"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0}, 489 490 /* comparison (without pop) */ 491 {"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, 492 {"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ 493 {"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ 494 {"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ 495 {"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, 496 {"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ 497 498 /* comparison (with pop) */ 499 {"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, 500 {"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ 501 {"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ 502 {"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ 503 {"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, 504 {"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ 505 {"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */ 506 507 /* unordered comparison (with pop) */ 508 {"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0}, 509 {"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0}, 510 {"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */ 511 512 {"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */ 513 {"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */ 514 515 /* load constants into %st0 */ 516 {"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */ 517 {"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */ 518 {"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */ 519 {"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */ 520 {"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */ 521 {"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */ 522 {"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */ 523 524 /* arithmetic */ 525 526 /* add */ 527 {"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0}, 528 {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 529 {"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */ 530 {"faddp", 1, 0xdac0, _, ShortForm, FloatReg, 0, 0}, 531 {"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 532 {"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */ 533 {"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0}, 534 {"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0}, 535 {"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0}, 536 {"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0}, 537 538 /* sub */ 539 /* Note: intel has decided that certain of these operations are reversed 540 in assembler syntax. */ 541 {"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0}, 542 {"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0}, 543 #ifdef NON_BROKEN_OPCODES 544 {"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, 545 #else 546 {"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, 547 #endif 548 {"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0}, 549 {"fsubp", 1, 0xdae0, _, ShortForm, FloatReg, 0, 0}, 550 {"fsubp", 2, 0xdae0, _, ShortForm, FloatReg, FloatAcc, 0}, 551 #ifdef NON_BROKEN_OPCODES 552 {"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, 553 #else 554 {"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, 555 #endif 556 {"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0}, 557 {"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0}, 558 {"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0}, 559 {"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0}, 560 {"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0}, 561 562 /* sub reverse */ 563 {"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0}, 564 {"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0}, 565 #ifdef NON_BROKEN_OPCODES 566 {"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, 567 #else 568 {"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, 569 #endif 570 {"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0}, 571 {"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0}, 572 {"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0}, 573 #ifdef NON_BROKEN_OPCODES 574 {"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, 575 #else 576 {"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, 577 #endif 578 {"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0}, 579 {"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0}, 580 {"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0}, 581 {"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0}, 582 {"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0}, 583 584 /* mul */ 585 {"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0}, 586 {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 587 {"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0}, 588 {"fmulp", 1, 0xdac8, _, ShortForm, FloatReg, 0, 0}, 589 {"fmulp", 2, 0xdac8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 590 {"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0}, 591 {"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0}, 592 {"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0}, 593 {"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0}, 594 {"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0}, 595 596 /* div */ 597 /* Note: intel has decided that certain of these operations are reversed 598 in assembler syntax. */ 599 {"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0}, 600 {"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0}, 601 #ifdef NON_BROKEN_OPCODES 602 {"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, 603 #else 604 {"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, 605 #endif 606 {"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0}, 607 {"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0}, 608 {"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0}, 609 #ifdef NON_BROKEN_OPCODES 610 {"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, 611 #else 612 {"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, 613 #endif 614 {"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0}, 615 {"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0}, 616 {"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0}, 617 {"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0}, 618 {"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0}, 619 620 /* div reverse */ 621 {"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0}, 622 {"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0}, 623 #ifdef NON_BROKEN_OPCODES 624 {"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, 625 #else 626 {"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, 627 #endif 628 {"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0}, 629 {"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0}, 630 {"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0}, 631 #ifdef NON_BROKEN_OPCODES 632 {"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, 633 #else 634 {"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, 635 #endif 636 {"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0}, 637 {"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0}, 638 {"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0}, 639 {"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0}, 640 {"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0}, 641 642 {"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0}, 643 {"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0}, 644 {"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0}, 645 {"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0}, 646 {"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0}, 647 {"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0}, 648 {"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0}, 649 {"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0}, 650 {"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0}, 651 {"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0}, 652 {"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0}, 653 {"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0}, 654 {"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0}, 655 {"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0}, 656 {"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0}, 657 {"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0}, 658 659 {"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0}, 660 {"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0}, 661 662 /* processor control */ 663 {"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0}, 664 {"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0}, 665 {"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0}, 666 {"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0}, 667 {"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0}, 668 {"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0}, 669 {"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, 670 {"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0}, 671 {"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0}, 672 {"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, 673 {"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0}, 674 {"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0}, 675 {"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0}, 676 /* 677 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor 678 instructions; i'm not sure how to add them or how they are different. 679 My 386/387 book offers no details about this. 680 */ 681 {"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0}, 682 {"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0}, 683 {"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0}, 684 {"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0}, 685 {"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0}, 686 {"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0}, 687 688 {"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0}, 689 {"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0}, 690 {"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0}, 691 692 /* 693 opcode prefixes; we allow them as seperate insns too 694 (see prefix table below) 695 */ 696 {"aword", 0, 0x67, _, NoModrm, 0, 0, 0}, 697 {"word", 0, 0x66, _, NoModrm, 0, 0, 0}, 698 {"lock", 0, 0xf0, _, NoModrm, 0, 0, 0}, 699 {"cs", 0, 0x2e, _, NoModrm, 0, 0, 0}, 700 {"ds", 0, 0x3e, _, NoModrm, 0, 0, 0}, 701 {"es", 0, 0x26, _, NoModrm, 0, 0, 0}, 702 {"fs", 0, 0x64, _, NoModrm, 0, 0, 0}, 703 {"gs", 0, 0x65, _, NoModrm, 0, 0, 0}, 704 {"ss", 0, 0x36, _, NoModrm, 0, 0, 0}, 705 {"rep", 0, 0xf3, _, NoModrm, 0, 0, 0}, 706 {"repe", 0, 0xf3, _, NoModrm, 0, 0, 0}, 707 { "repne", 0, 0xf2, _, NoModrm, 0, 0, 0}, 708 709 {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */ 710 }; 711 #undef _ 712 713 template *i386_optab_end 714 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); 715 716 /* 386 register table */ 717 718 reg_entry i386_regtab[] = { 719 /* 8 bit regs */ 720 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, 721 {"bl", Reg8, 3}, 722 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, 723 /* 16 bit regs */ 724 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, 725 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, 726 /* 32 bit regs */ 727 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, 728 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, 729 /* segment registers */ 730 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, 731 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, 732 /* control registers */ 733 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, 734 /* debug registers */ 735 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, 736 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, 737 /* test registers */ 738 {"tr6", Test, 6}, {"tr7", Test, 7}, 739 /* float registers */ 740 {"st(0)", FloatReg|FloatAcc, 0}, 741 {"st", FloatReg|FloatAcc, 0}, 742 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 743 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 744 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7} 745 }; 746 747 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 748 749 reg_entry *i386_regtab_end 750 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); 751 752 /* segment stuff */ 753 seg_entry cs = { "cs", 0x2e }; 754 seg_entry ds = { "ds", 0x3e }; 755 seg_entry ss = { "ss", 0x36 }; 756 seg_entry es = { "es", 0x26 }; 757 seg_entry fs = { "fs", 0x64 }; 758 seg_entry gs = { "gs", 0x65 }; 759 seg_entry null = { "", 0x0 }; 760 761 /* 762 This table is used to store the default segment register implied by all 763 possible memory addressing modes. 764 It is indexed by the mode & modrm entries of the modrm byte as follows: 765 index = (mode<<3) | modrm; 766 */ 767 seg_entry *one_byte_segment_defaults[] = { 768 /* mode 0 */ 769 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, 770 /* mode 1 */ 771 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 772 /* mode 2 */ 773 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 774 /* mode 3 --- not a memory reference; never referenced */ 775 }; 776 777 seg_entry *two_byte_segment_defaults[] = { 778 /* mode 0 */ 779 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 780 /* mode 1 */ 781 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 782 /* mode 2 */ 783 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 784 /* mode 3 --- not a memory reference; never referenced */ 785 }; 786 787 prefix_entry i386_prefixtab[] = { 788 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing 789 * (How is this useful?) */ 790 #define WORD_PREFIX_OPCODE 0x66 791 { "data16", 0x66 }, /* operand size prefix */ 792 { "lock", 0xf0 }, /* bus lock prefix */ 793 { "wait", 0x9b }, /* wait for coprocessor */ 794 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ 795 { "es", 0x26 }, { "fs", 0x64 }, 796 { "gs", 0x65 }, { "ss", 0x36 }, 797 /* REPE & REPNE used to detect rep/repne with a non-string instruction */ 798 #define REPNE 0xf2 799 #define REPE 0xf3 800 { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */ 801 { "repne", 0xf2 } 802 }; 803 804 prefix_entry *i386_prefixtab_end 805 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); 806 807