1 /* Target-dependent header for the RISC-V architecture, for GDB, the 2 GNU Debugger. 3 4 Copyright (C) 2018-2021 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef RISCV_TDEP_H 22 #define RISCV_TDEP_H 23 24 #include "arch/riscv.h" 25 26 /* RiscV register numbers. */ 27 enum 28 { 29 RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */ 30 RISCV_RA_REGNUM = 1, /* Return Address. */ 31 RISCV_SP_REGNUM = 2, /* Stack Pointer. */ 32 RISCV_GP_REGNUM = 3, /* Global Pointer. */ 33 RISCV_TP_REGNUM = 4, /* Thread Pointer. */ 34 RISCV_FP_REGNUM = 8, /* Frame Pointer. */ 35 RISCV_A0_REGNUM = 10, /* First argument. */ 36 RISCV_A1_REGNUM = 11, /* Second argument. */ 37 RISCV_PC_REGNUM = 32, /* Program Counter. */ 38 39 RISCV_NUM_INTEGER_REGS = 32, 40 41 RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */ 42 RISCV_FA0_REGNUM = 43, 43 RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1, 44 RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ 45 46 RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ 47 #define DECLARE_CSR(name, num, class, define_version, abort_version) \ 48 RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, 49 #include "opcode/riscv-opc.h" 50 #undef DECLARE_CSR 51 RISCV_LAST_CSR_REGNUM = 4160, 52 RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM, 53 54 RISCV_PRIV_REGNUM = 4161, 55 56 RISCV_V0_REGNUM, 57 58 RISCV_V31_REGNUM = RISCV_V0_REGNUM + 31, 59 60 RISCV_LAST_REGNUM = RISCV_V31_REGNUM 61 }; 62 63 /* RiscV DWARF register numbers. */ 64 enum 65 { 66 RISCV_DWARF_REGNUM_X0 = 0, 67 RISCV_DWARF_REGNUM_X31 = 31, 68 RISCV_DWARF_REGNUM_F0 = 32, 69 RISCV_DWARF_REGNUM_F31 = 63, 70 RISCV_DWARF_REGNUM_V0 = 96, 71 RISCV_DWARF_REGNUM_V31 = 127, 72 RISCV_DWARF_FIRST_CSR = 4096, 73 RISCV_DWARF_LAST_CSR = 8191, 74 }; 75 76 /* RISC-V specific per-architecture information. */ 77 struct gdbarch_tdep 78 { 79 /* Features about the target hardware that impact how the gdbarch is 80 configured. Two gdbarch instances are compatible only if this field 81 matches. */ 82 struct riscv_gdbarch_features isa_features; 83 84 /* Features about the abi that impact how the gdbarch is configured. Two 85 gdbarch instances are compatible only if this field matches. */ 86 struct riscv_gdbarch_features abi_features; 87 88 /* ISA-specific data types. */ 89 struct type *riscv_fpreg_d_type = nullptr; 90 91 /* Use for tracking unknown CSRs in the target description. 92 UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown 93 CSR. All other unknown CSRs will be assigned sequential numbers after 94 this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs. */ 95 int unknown_csrs_first_regnum = -1; 96 int unknown_csrs_count = 0; 97 98 /* Some targets (QEMU) are reporting three registers twice in the target 99 description they send. These three register numbers, when not set to 100 -1, are for the duplicate copies of these registers. */ 101 int duplicate_fflags_regnum = -1; 102 int duplicate_frm_regnum = -1; 103 int duplicate_fcsr_regnum = -1; 104 105 }; 106 107 108 /* Return the width in bytes of the general purpose registers for GDBARCH. 109 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or 110 RV128. */ 111 extern int riscv_isa_xlen (struct gdbarch *gdbarch); 112 113 /* Return the width in bytes of the hardware floating point registers for 114 GDBARCH. If this architecture has no floating point registers, then 115 return 0. Possible values are 4, 8, or 16 for depending on which of 116 single, double or quad floating point support is available. */ 117 extern int riscv_isa_flen (struct gdbarch *gdbarch); 118 119 /* Return the width in bytes of the general purpose register abi for 120 GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects 121 how the binary was compiled rather than the hardware that is available. 122 It is possible that a binary compiled for RV32 is being run on an RV64 123 target, in which case the isa xlen is 8-bytes, and the abi xlen is 124 4-bytes. This will impact how inferior functions are called. */ 125 extern int riscv_abi_xlen (struct gdbarch *gdbarch); 126 127 /* Return the width in bytes of the floating point register abi for 128 GDBARCH. This reflects how the binary was compiled rather than the 129 hardware that is available. It is possible that a binary is compiled 130 for single precision floating point, and then run on a target with 131 double precision floating point. A return value of 0 indicates that no 132 floating point abi is in use (floating point arguments will be passed 133 in integer registers) other possible return value are 4, 8, or 16 as 134 with RISCV_ISA_FLEN. */ 135 extern int riscv_abi_flen (struct gdbarch *gdbarch); 136 137 /* Return true if GDBARCH is using the embedded x-regs abi, that is the 138 target only has 16 x-registers, which includes a reduced number of 139 argument registers. */ 140 extern bool riscv_abi_embedded (struct gdbarch *gdbarch); 141 142 /* Single step based on where the current instruction will take us. */ 143 extern std::vector<CORE_ADDR> riscv_software_single_step 144 (struct regcache *regcache); 145 146 /* Supply register REGNUM from the buffer REGS (length LEN) into 147 REGCACHE. REGSET describes the layout of the buffer. If REGNUM is -1 148 then all registers described by REGSET are supplied. 149 150 The register RISCV_ZERO_REGNUM should not be described by REGSET, 151 however, this register (which always has the value 0) will be supplied 152 by this function if requested. 153 154 The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should 155 not be described by REGSET, however, these register will be provided if 156 requested assuming either: 157 (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or 158 (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS 159 buffer. 160 161 This function can be used as the supply function for either x-regs or 162 f-regs when loading corefiles, and doesn't care which abi is currently 163 in use. */ 164 165 extern void riscv_supply_regset (const struct regset *regset, 166 struct regcache *regcache, int regnum, 167 const void *regs, size_t len); 168 169 /* The names of the RISC-V target description features. */ 170 extern const char *riscv_feature_name_csr; 171 172 #endif /* RISCV_TDEP_H */ 173