1 /* $OpenBSD: rt2661reg.h,v 1.13 2013/11/26 20:33:16 deraadt Exp $ */
2
3 /*-
4 * Copyright (c) 2006
5 * Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #define RT2661_TX_RING_COUNT 32
21 #define RT2661_MGT_RING_COUNT 32
22 #define RT2661_RX_RING_COUNT 64
23
24 #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc))
25 #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4)
26 #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc))
27 #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4)
28
29 #define RT2661_MAX_SCATTER 5
30
31 /*
32 * Control and status registers.
33 */
34 #define RT2661_HOST_CMD_CSR 0x0008
35 #define RT2661_MCU_CNTL_CSR 0x000c
36 #define RT2661_SOFT_RESET_CSR 0x0010
37 #define RT2661_MCU_INT_SOURCE_CSR 0x0014
38 #define RT2661_MCU_INT_MASK_CSR 0x0018
39 #define RT2661_PCI_USEC_CSR 0x001c
40 #define RT2661_H2M_MAILBOX_CSR 0x2100
41 #define RT2661_M2H_CMD_DONE_CSR 0x2104
42 #define RT2661_HW_BEACON_BASE0 0x2c00
43 #define RT2661_HW_BEACON_BASE1 0x2d00
44 #define RT2661_HW_BEACON_BASE2 0x2e00
45 #define RT2661_HW_BEACON_BASE3 0x2f00
46 #define RT2661_MAC_CSR0 0x3000
47 #define RT2661_MAC_CSR1 0x3004
48 #define RT2661_MAC_CSR2 0x3008
49 #define RT2661_MAC_CSR3 0x300c
50 #define RT2661_MAC_CSR4 0x3010
51 #define RT2661_MAC_CSR5 0x3014
52 #define RT2661_MAC_CSR6 0x3018
53 #define RT2661_MAC_CSR7 0x301c
54 #define RT2661_MAC_CSR8 0x3020
55 #define RT2661_MAC_CSR9 0x3024
56 #define RT2661_MAC_CSR10 0x3028
57 #define RT2661_MAC_CSR11 0x302c
58 #define RT2661_MAC_CSR12 0x3030
59 #define RT2661_MAC_CSR13 0x3034
60 #define RT2661_MAC_CSR14 0x3038
61 #define RT2661_MAC_CSR15 0x303c
62 #define RT2661_TXRX_CSR0 0x3040
63 #define RT2661_TXRX_CSR1 0x3044
64 #define RT2661_TXRX_CSR2 0x3048
65 #define RT2661_TXRX_CSR3 0x304c
66 #define RT2661_TXRX_CSR4 0x3050
67 #define RT2661_TXRX_CSR5 0x3054
68 #define RT2661_TXRX_CSR6 0x3058
69 #define RT2661_TXRX_CSR7 0x305c
70 #define RT2661_TXRX_CSR8 0x3060
71 #define RT2661_TXRX_CSR9 0x3064
72 #define RT2661_TXRX_CSR10 0x3068
73 #define RT2661_TXRX_CSR11 0x306c
74 #define RT2661_TXRX_CSR12 0x3070
75 #define RT2661_TXRX_CSR13 0x3074
76 #define RT2661_TXRX_CSR14 0x3078
77 #define RT2661_TXRX_CSR15 0x307c
78 #define RT2661_PHY_CSR0 0x3080
79 #define RT2661_PHY_CSR1 0x3084
80 #define RT2661_PHY_CSR2 0x3088
81 #define RT2661_PHY_CSR3 0x308c
82 #define RT2661_PHY_CSR4 0x3090
83 #define RT2661_PHY_CSR5 0x3094
84 #define RT2661_PHY_CSR6 0x3098
85 #define RT2661_PHY_CSR7 0x309c
86 #define RT2661_SEC_CSR0 0x30a0
87 #define RT2661_SEC_CSR1 0x30a4
88 #define RT2661_SEC_CSR2 0x30a8
89 #define RT2661_SEC_CSR3 0x30ac
90 #define RT2661_SEC_CSR4 0x30b0
91 #define RT2661_SEC_CSR5 0x30b4
92 #define RT2661_STA_CSR0 0x30c0
93 #define RT2661_STA_CSR1 0x30c4
94 #define RT2661_STA_CSR2 0x30c8
95 #define RT2661_STA_CSR3 0x30cc
96 #define RT2661_STA_CSR4 0x30d0
97 #define RT2661_AC0_BASE_CSR 0x3400
98 #define RT2661_AC1_BASE_CSR 0x3404
99 #define RT2661_AC2_BASE_CSR 0x3408
100 #define RT2661_AC3_BASE_CSR 0x340c
101 #define RT2661_MGT_BASE_CSR 0x3410
102 #define RT2661_TX_RING_CSR0 0x3418
103 #define RT2661_TX_RING_CSR1 0x341c
104 #define RT2661_AIFSN_CSR 0x3420
105 #define RT2661_CWMIN_CSR 0x3424
106 #define RT2661_CWMAX_CSR 0x3428
107 #define RT2661_TX_DMA_DST_CSR 0x342c
108 #define RT2661_TX_CNTL_CSR 0x3430
109 #define RT2661_LOAD_TX_RING_CSR 0x3434
110 #define RT2661_RX_BASE_CSR 0x3450
111 #define RT2661_RX_RING_CSR 0x3454
112 #define RT2661_RX_CNTL_CSR 0x3458
113 #define RT2661_PCI_CFG_CSR 0x3460
114 #define RT2661_INT_SOURCE_CSR 0x3468
115 #define RT2661_INT_MASK_CSR 0x346c
116 #define RT2661_E2PROM_CSR 0x3470
117 #define RT2661_AC_TXOP_CSR0 0x3474
118 #define RT2661_AC_TXOP_CSR1 0x3478
119 #define RT2661_TEST_MODE_CSR 0x3484
120 #define RT2661_IO_CNTL_CSR 0x3498
121 #define RT2661_MCU_CODE_BASE 0x4000
122
123
124 /* possible flags for register HOST_CMD_CSR */
125 #define RT2661_KICK_CMD (1 << 7)
126 /* Host to MCU (8051) command identifiers */
127 #define RT2661_MCU_CMD_SLEEP 0x30
128 #define RT2661_MCU_CMD_WAKEUP 0x31
129 #define RT2661_MCU_SET_LED 0x50
130 #define RT2661_MCU_SET_RSSI_LED 0x52
131
132 /* possible flags for register MCU_CNTL_CSR */
133 #define RT2661_MCU_SEL (1 << 0)
134 #define RT2661_MCU_RESET (1 << 1)
135 #define RT2661_MCU_READY (1 << 2)
136
137 /* possible flags for register MCU_INT_SOURCE_CSR */
138 #define RT2661_MCU_CMD_DONE 0xff
139 #define RT2661_MCU_WAKEUP (1 << 8)
140 #define RT2661_MCU_BEACON_EXPIRE (1 << 9)
141
142 /* possible flags for register H2M_MAILBOX_CSR */
143 #define RT2661_H2M_BUSY (1 << 24)
144 #define RT2661_TOKEN_NO_INTR 0xff
145
146 /* possible flags for register MAC_CSR5 */
147 #define RT2661_ONE_BSSID 3
148
149 /* possible flags for register TXRX_CSR0 */
150 /* Tx filter flags are in the low 16 bits */
151 #define RT2661_AUTO_TX_SEQ (1 << 15)
152 /* Rx filter flags are in the high 16 bits */
153 #define RT2661_DISABLE_RX (1 << 16)
154 #define RT2661_DROP_CRC_ERROR (1 << 17)
155 #define RT2661_DROP_PHY_ERROR (1 << 18)
156 #define RT2661_DROP_CTL (1 << 19)
157 #define RT2661_DROP_NOT_TO_ME (1 << 20)
158 #define RT2661_DROP_TODS (1 << 21)
159 #define RT2661_DROP_VER_ERROR (1 << 22)
160 #define RT2661_DROP_MULTICAST (1 << 23)
161 #define RT2661_DROP_BROADCAST (1 << 24)
162 #define RT2661_DROP_ACKCTS (1 << 25)
163
164 /* possible flags for register TXRX_CSR4 */
165 #define RT2661_SHORT_PREAMBLE (1 << 18)
166 #define RT2661_MRR_ENABLED (1 << 19)
167 #define RT2661_MRR_CCK_FALLBACK (1 << 22)
168
169 /* possible flags for register TXRX_CSR9 */
170 #define RT2661_TSF_TICKING (1 << 16)
171 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17)
172 /* TBTT stands for Target Beacon Transmission Time */
173 #define RT2661_ENABLE_TBTT (1 << 19)
174 #define RT2661_GENERATE_BEACON (1 << 20)
175
176 /* possible flags for register PHY_CSR0 */
177 #define RT2661_PA_PE_2GHZ (1 << 16)
178 #define RT2661_PA_PE_5GHZ (1 << 17)
179
180 /* possible flags for register PHY_CSR3 */
181 #define RT2661_BBP_READ (1 << 15)
182 #define RT2661_BBP_BUSY (1 << 16)
183
184 /* possible flags for register PHY_CSR4 */
185 #define RT2661_RF_21BIT (21U << 24)
186 #define RT2661_RF_BUSY (1U << 31)
187
188 /* possible values for register STA_CSR4 */
189 #define RT2661_TX_STAT_VALID (1 << 0)
190 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7)
191 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf)
192 /* Driver-private data written before TX and read back when TX completes.
193 * We store the driver-private ID of an AMRR node in here. */
194 #define RT2661_TX_PRIV_DATA(v) (((v) >> 8) & 0xff)
195 #define RT2661_TX_SUCCESS 0
196 #define RT2661_TX_RETRY_FAIL 6
197
198 /* possible flags for register TX_CNTL_CSR */
199 #define RT2661_KICK_MGT (1 << 4)
200
201 /* possible flags for register INT_SOURCE_CSR */
202 #define RT2661_TX_DONE (1 << 0)
203 #define RT2661_RX_DONE (1 << 1)
204 #define RT2661_TX0_DMA_DONE (1 << 16)
205 #define RT2661_TX1_DMA_DONE (1 << 17)
206 #define RT2661_TX2_DMA_DONE (1 << 18)
207 #define RT2661_TX3_DMA_DONE (1 << 19)
208 #define RT2661_MGT_DONE (1 << 20)
209
210 /* possible flags for register E2PROM_CSR */
211 #define RT2661_C (1 << 1)
212 #define RT2661_S (1 << 2)
213 #define RT2661_D (1 << 3)
214 #define RT2661_Q (1 << 4)
215 #define RT2661_93C46 (1 << 5)
216
217 /* Tx descriptor */
218 struct rt2661_tx_desc {
219 uint32_t flags;
220 #define RT2661_TX_BUSY (1 << 0)
221 #define RT2661_TX_VALID (1 << 1)
222 #define RT2661_TX_MORE_FRAG (1 << 2)
223 #define RT2661_TX_NEED_ACK (1 << 3)
224 #define RT2661_TX_TIMESTAMP (1 << 4)
225 #define RT2661_TX_OFDM (1 << 5)
226 #define RT2661_TX_IFS_SIFS (1 << 6)
227 #define RT2661_TX_LONG_RETRY (1 << 7)
228 #define RT2661_TX_BURST (1 << 28)
229
230 uint16_t wme;
231 #define RT2661_QID(v) (v)
232 #define RT2661_AIFSN(v) ((v) << 4)
233 #define RT2661_LOGCWMIN(v) ((v) << 8)
234 #define RT2661_LOGCWMAX(v) ((v) << 12)
235
236 uint16_t xflags;
237 #define RT2661_TX_HWSEQ (1 << 12)
238
239 uint8_t plcp_signal;
240 uint8_t plcp_service;
241 #define RT2661_PLCP_LENGEXT 0x80
242
243 uint8_t plcp_length_lo;
244 uint8_t plcp_length_hi;
245
246 uint32_t iv;
247 uint32_t eiv;
248
249 uint8_t offset;
250 uint8_t priv_data;
251 #define RT2661_QID_MGT 13
252
253 uint8_t txpower;
254 #define RT2661_DEFAULT_TXPOWER 0
255
256 uint8_t reserved1;
257
258 uint32_t addr[RT2661_MAX_SCATTER];
259 uint16_t len[RT2661_MAX_SCATTER];
260
261 uint16_t reserved2;
262 } __packed;
263
264 /* Rx descriptor */
265 struct rt2661_rx_desc {
266 uint32_t flags;
267 #define RT2661_RX_BUSY (1 << 0)
268 #define RT2661_RX_DROP (1 << 1)
269 #define RT2661_RX_CRC_ERROR (1 << 6)
270 #define RT2661_RX_OFDM (1 << 7)
271 #define RT2661_RX_PHY_ERROR (1 << 8)
272 #define RT2661_RX_CIPHER_MASK 0x00000600
273
274 uint8_t rate;
275 uint8_t rssi;
276 uint8_t reserved1;
277 uint8_t offset;
278 uint32_t iv;
279 uint32_t eiv;
280 uint32_t reserved2;
281 uint32_t physaddr;
282 uint32_t reserved3[10];
283 } __packed;
284
285 #define RAL_RF1 0
286 #define RAL_RF2 2
287 #define RAL_RF3 1
288 #define RAL_RF4 3
289
290 /* dual-band RF */
291 #define RT2661_RF_5225 1
292 #define RT2661_RF_5325 2
293 /* single-band RF */
294 #define RT2661_RF_2527 3
295 #define RT2661_RF_2529 4
296
297 #define RT2661_RX_DESC_BACK 4
298
299 #define RT2661_SMART_MODE (1 << 0)
300
301 #define RT2661_BBPR94_DEFAULT 6
302
303 #define RT2661_SHIFT_D 3
304 #define RT2661_SHIFT_Q 4
305
306 #define RT2661_EEPROM_MAC01 0x02
307 #define RT2661_EEPROM_MAC23 0x03
308 #define RT2661_EEPROM_MAC45 0x04
309 #define RT2661_EEPROM_ANTENNA 0x10
310 #define RT2661_EEPROM_CONFIG2 0x11
311 #define RT2661_EEPROM_BBP_BASE 0x13
312 #define RT2661_EEPROM_TXPOWER 0x23
313 #define RT2661_EEPROM_FREQ_OFFSET 0x2f
314 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d
315 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e
316
317 #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
318
319 /*-
320 * Control and status registers access functions.
321 * The ASIC does not like PCI bursts on registers because of a silicon bug.
322 * To prevent PCI read or write bursts, we issue a read to a non-contiguous
323 * register before accessing a register. This problem does not show up on
324 * x86 architectures since the memory model makes it almost impossible to
325 * generate PCI bursts without doing DMA.
326 * This makes the RT2561S chip on the Gdium (loongson) work.
327 */
328 static __inline uint32_t
RAL_READ(struct rt2661_softc * sc,bus_size_t reg)329 RAL_READ(struct rt2661_softc *sc, bus_size_t reg)
330 {
331 bus_space_read_4(sc->sc_st, sc->sc_sh, RT2661_MAC_CSR0);
332 return bus_space_read_4(sc->sc_st, sc->sc_sh, reg);
333 }
334
335 static __inline void
RAL_READ_REGION_4(struct rt2661_softc * sc,bus_size_t offset,uint32_t * datap,bus_size_t count)336 RAL_READ_REGION_4(struct rt2661_softc *sc, bus_size_t offset,
337 uint32_t *datap, bus_size_t count)
338 {
339 /* NB: do not use bus_space_read_region_4 to prevent PCI bursts. */
340 for (; count > 0; count--, datap++, offset += 4)
341 *datap = RAL_READ(sc, offset);
342 }
343
344 static __inline void
RAL_WRITE(struct rt2661_softc * sc,bus_size_t reg,uint32_t val)345 RAL_WRITE(struct rt2661_softc *sc, bus_size_t reg, uint32_t val)
346 {
347 bus_space_read_4(sc->sc_st, sc->sc_sh, RT2661_MAC_CSR0);
348 bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
349 }
350
351 static __inline void
RAL_WRITE_1(struct rt2661_softc * sc,bus_size_t reg,uint8_t val)352 RAL_WRITE_1(struct rt2661_softc *sc, bus_size_t reg, uint8_t val)
353 {
354 bus_space_read_4(sc->sc_st, sc->sc_sh, RT2661_MAC_CSR0);
355 bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val);
356 }
357
358 static __inline void
RAL_WRITE_REGION_1(struct rt2661_softc * sc,bus_size_t offset,const uint8_t * datap,bus_size_t count)359 RAL_WRITE_REGION_1(struct rt2661_softc *sc, bus_size_t offset,
360 const uint8_t *datap, bus_size_t count)
361 {
362 /* NB: do not use bus_space_write_region_1 to prevent PCI bursts. */
363 for (; count > 0; count--, datap++, offset++)
364 RAL_WRITE_1(sc, offset, *datap);
365 }
366
367 #define RAL_RW_BARRIER_1(sc, reg) \
368 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, (reg), 1, \
369 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
370
371 /*
372 * EEPROM access macro
373 */
374 #define RT2661_EEPROM_CTL(sc, val) do { \
375 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
376 DELAY(RT2661_EEPROM_DELAY); \
377 } while (/* CONSTCOND */0)
378
379
380 /*
381 * Default values for MAC registers; values taken from the reference driver.
382 */
383 #define RT2661_DEF_MAC \
384 { RT2661_TXRX_CSR0, 0x0000b032 }, \
385 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \
386 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \
387 { RT2661_TXRX_CSR3, 0x00858687 }, \
388 { RT2661_TXRX_CSR7, 0x2e31353b }, \
389 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \
390 { RT2661_TXRX_CSR15, 0x0000000f }, \
391 { RT2661_MAC_CSR6, 0x00000fff }, \
392 { RT2661_MAC_CSR8, 0x016c030a }, \
393 { RT2661_MAC_CSR10, 0x00000718 }, \
394 { RT2661_MAC_CSR12, 0x00000004 }, \
395 { RT2661_MAC_CSR13, 0x0000e000 }, \
396 { RT2661_SEC_CSR0, 0x00000000 }, \
397 { RT2661_SEC_CSR1, 0x00000000 }, \
398 { RT2661_SEC_CSR5, 0x00000000 }, \
399 { RT2661_PHY_CSR1, 0x000023b0 }, \
400 { RT2661_PHY_CSR5, 0x060a100c }, \
401 { RT2661_PHY_CSR6, 0x00080606 }, \
402 { RT2661_PHY_CSR7, 0x00000a08 }, \
403 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \
404 { RT2661_AIFSN_CSR, 0x00002273 }, \
405 { RT2661_CWMIN_CSR, 0x00002344 }, \
406 { RT2661_CWMAX_CSR, 0x000034aa }, \
407 { RT2661_TEST_MODE_CSR, 0x00000200 }, \
408 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff }, \
409 { RT2661_HW_BEACON_BASE0, 0x00000000 }, \
410 { RT2661_HW_BEACON_BASE1, 0x00000000 }, \
411 { RT2661_HW_BEACON_BASE2, 0x00000000 }, \
412 { RT2661_HW_BEACON_BASE3, 0x00000000 }
413
414 /*
415 * Default values for BBP registers; values taken from the reference driver.
416 */
417 #define RT2661_DEF_BBP \
418 { 3, 0x00 }, \
419 { 15, 0x30 }, \
420 { 17, 0x20 }, \
421 { 21, 0xc8 }, \
422 { 22, 0x38 }, \
423 { 23, 0x06 }, \
424 { 24, 0xfe }, \
425 { 25, 0x0a }, \
426 { 26, 0x0d }, \
427 { 34, 0x12 }, \
428 { 37, 0x07 }, \
429 { 39, 0xf8 }, \
430 { 41, 0x60 }, \
431 { 53, 0x10 }, \
432 { 54, 0x18 }, \
433 { 60, 0x10 }, \
434 { 61, 0x04 }, \
435 { 62, 0x04 }, \
436 { 75, 0xfe }, \
437 { 86, 0xfe }, \
438 { 88, 0xfe }, \
439 { 90, 0x0f }, \
440 { 99, 0x00 }, \
441 { 102, 0x16 }, \
442 { 107, 0x04 }
443
444 /*
445 * Default settings for RF registers; values taken from the reference driver.
446 */
447 #define RT2661_RF5225_1 \
448 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
449 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
450 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
451 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
452 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
453 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
454 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
455 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
456 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
457 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
458 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
459 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
460 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
461 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
462 \
463 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \
464 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \
465 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \
466 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \
467 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \
468 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \
469 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \
470 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \
471 \
472 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \
473 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \
474 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \
475 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \
476 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \
477 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \
478 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \
479 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \
480 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \
481 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \
482 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \
483 \
484 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \
485 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \
486 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \
487 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \
488 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
489
490 #define RT2661_RF5225_2 \
491 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
492 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
493 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
494 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
495 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
496 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
497 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
498 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
499 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
500 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
501 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
502 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
503 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
504 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
505 \
506 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \
507 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \
508 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \
509 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \
510 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \
511 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \
512 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \
513 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \
514 \
515 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \
516 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \
517 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \
518 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \
519 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \
520 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \
521 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \
522 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \
523 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \
524 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \
525 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \
526 \
527 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \
528 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \
529 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \
530 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \
531 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }
532