1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * Copyright (c) 2004, 2005 David Young. All rights reserved. 7 * 8 * Programmed for NetBSD by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of David Young may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 * OF SUCH DAMAGE. 34 */ 35 /* Macros for bit twiddling. */ 36 37 #ifndef _RTW_REG_H_ 38 #define _RTW_REG_H_ 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #ifndef _BIT_TWIDDLE 45 #define _BIT_TWIDDLE 46 /* 47 * nth bit, BIT(0) == 0x1. 48 */ 49 #define BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n))) 50 51 /* 52 * bits m through n, m < n. 53 */ 54 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 55 56 /* 57 * find least significant bit that is set 58 */ 59 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 60 61 /* 62 * for x a power of two and p a non-negative integer, is x a greater 63 * power than 2**p? 64 */ 65 #define GTEQ_POWER(x, p) (((ulong_t)(x) >> (p)) != 0) 66 67 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 68 69 #define MASK_TO_SHIFT4(m) \ 70 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 71 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 72 : MASK_TO_SHIFT2((m))) 73 74 #define MASK_TO_SHIFT8(m) \ 75 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 76 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 77 : MASK_TO_SHIFT4((m))) 78 79 #define MASK_TO_SHIFT16(m) \ 80 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 81 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 82 : MASK_TO_SHIFT8((m))) 83 84 #define MASK_TO_SHIFT(m) \ 85 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 86 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 87 : MASK_TO_SHIFT16((m))) 88 89 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 90 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 91 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 92 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 93 94 #endif /* _BIT_TWIDDLE */ 95 96 /* RTL8180L Host Control and Status Registers */ 97 98 /* 99 * ID Register: MAC addr, 6 bytes. 100 * Auto-loaded from EEPROM. Read by byte, by word, or by double word, 101 * but write only by double word. 102 */ 103 #define RTW_IDR0 0x00 104 #define RTW_IDR1 0x04 105 106 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 107 #define RTW_MAR1 0x0c 108 109 /* 110 * Timing Synchronization Function Timer Register, 111 * low word, 32b, read-only. 112 */ 113 #define RTW_TSFTRL 0x18 114 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 115 /* 116 * Transmit Low Priority Descriptors Start Address, 117 * 32b, 256-byte alignment. 118 */ 119 #define RTW_TLPDA 0x20 120 /* 121 * Transmit Normal Priority Descriptors Start Address, 122 * 32b, 256-byte alignment. 123 */ 124 #define RTW_TNPDA 0x24 125 /* 126 * Transmit High Priority Descriptors Start Address, 127 * 32b, 256-byte alignment. 128 */ 129 #define RTW_THPDA 0x28 130 131 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 132 /* 133 * 1: use short PLCP header for CTS/ACK packet, 134 * 0: use long PLCP header 135 */ 136 #define RTW_BRSR_BPLCP BIT(8) 137 #define RTW_BRSR_MBR8180_MASK BITS(1, 0) /* Maximum Basic Service Rate */ 138 #define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR8180_MASK) 139 #define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR8180_MASK) 140 #define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR8180_MASK) 141 #define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR8180_MASK) 142 143 /* 144 * 8181 and 8180 docs conflict! 145 */ 146 #define RTW_BRSR_MBR8181_1MBPS BIT(0) 147 #define RTW_BRSR_MBR8181_2MBPS BIT(1) 148 #define RTW_BRSR_MBR8181_5MBPS BIT(2) 149 #define RTW_BRSR_MBR8181_11MBPS BIT(3) 150 151 #define RTW_BSSID 0x2e 152 /* 153 * BSSID, 6 bytes 154 */ 155 #define RTW_BSSID16 0x2e /* first two bytes */ 156 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 157 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 158 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 159 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 160 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 161 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 162 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 163 164 #define RTW_CR 0x37 /* Command Register, 8b */ 165 /* 166 * Reset: host sets to 1 to disable 167 * transmitter & receiver, reinitialize FIFO. 168 * RTL8180L sets to 0 to signal completion. 169 */ 170 #define RTW_CR_RST BIT(4) 171 /* 172 * Receiver Enable: host enables receiver 173 * by writing 1. RTL8180L indicates receiver 174 * is active with 1. After power-up, host 175 * must wait for reset before writing. 176 */ 177 #define RTW_CR_RE BIT(3) 178 /* 179 * Transmitter Enable: host enables transmitter 180 * by writing 1. RTL8180L indicates transmitter 181 * is active with 1. After power-up, host 182 * must wait for reset before writing. 183 */ 184 #define RTW_CR_TE BIT(2) 185 /* 186 * PCI Multiple Read/Write enable: 187 * 1 enables, 188 * 0 disables. XXX RTL8180, only? 189 */ 190 #define RTW_CR_MULRW BIT(0) 191 192 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 193 #define RTW_ISR 0x3e /* Interrupt status register, 16b */ 194 195 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ 196 /* 197 * Time Out: 1 indicates RTW_TSFTR[0:31] = RTW_TINT 198 */ 199 #define RTW_INTR_TIMEOUT BIT(14) 200 /* 201 * Beacon Time Out: time for host to prepare beacon: 202 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 203 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 204 */ 205 #define RTW_INTR_BCNINT BIT(13) 206 /* 207 * ATIM Time Out: ATIM interval will pass, 208 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 209 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 210 */ 211 #define RTW_INTR_ATIMINT BIT(12) 212 /* 213 * Tx Beacon Descriptor Error: 214 * beacon transmission aborted because 215 * frame Rx'd 216 */ 217 #define RTW_INTR_TBDER BIT(11) 218 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 219 /* 220 * Tx High Priority Descriptor Error: 221 * reached short/long retry limit 222 */ 223 #define RTW_INTR_THPDER BIT(9) 224 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 225 /* 226 * Tx Normal Priority Descriptor Error: 227 * reached short/long retry limit 228 */ 229 #define RTW_INTR_TNPDER BIT(7) 230 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 231 /* 232 * Rx FIFO Overflow: either RDU (see below) 233 * or PCI bus too slow/busy 234 */ 235 #define RTW_INTR_RXFOVW BIT(5) 236 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 237 /* 238 * Tx Low Priority Descriptor Error 239 * reached short/long retry limit 240 */ 241 #define RTW_INTR_TLPDER BIT(3) 242 #define RTW_INTR_TLPDOK BIT(2) /* Tx Low Priority Descriptor OK */ 243 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 244 #define RTW_INTR_ROK BIT(0) /* Rx OK */ 245 246 /* 247 * Convenient interrupt conjunctions. 248 */ 249 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK | \ 250 RTW_INTR_RDU |RTW_INTR_RXFOVW) 251 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 252 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\ 253 RTW_INTR_TBDER|RTW_INTR_TBDOK) 254 #define RTW_INTR_BEACON (RTW_INTR_BCNINT) 255 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 256 257 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 258 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 259 /* 260 * 1: host assigns 802.11 sequence number, 261 * 0: hardware assigns sequence number 262 */ 263 #define RTW_TCR_SWSEQ BIT(30) 264 /* Hardware version ID, read-only */ 265 #define RTW_TCR_HWVERID_MASK BITS(29, 25) 266 #define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK) 267 #define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK) 268 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 269 270 /* 271 * Set ACK/CTS Timeout (EIFS). 272 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 273 * 0: ACK rate = 1Mbps 274 */ 275 #define RTW_TCR_SAT BIT(24) 276 /* Max DMA Burst Size per Tx DMA Burst */ 277 #define RTW_TCR_MXDMA_MASK BITS(23, 21) 278 #define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 279 #define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 280 #define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 281 #define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 282 #define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 283 #define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 284 #define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 285 #define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 286 287 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 288 289 /* 290 * host lets RTL8180 append ICV to WEP packets 291 */ 292 #define RTW_TCR_ICV BIT(19) 293 294 /* 295 * Loopback Test: disables TXI/TXQ outputs. 296 */ 297 #define RTW_TCR_LBK_MASK BITS(18, 17) 298 #define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 299 #define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 300 #define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 301 #define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 302 303 /* 304 * 0: RTL8180 appends CRC32 305 * 1: host appends CRC32 306 * 307 * (I *think* this is right. The docs have a mysterious 308 * description in the passive voice.) 309 */ 310 #define RTW_TCR_CRC BIT(16) 311 #define RTW_TCR_SRL_MASK BITS(15, 8) /* Short Retry Limit */ 312 #define RTW_TCR_LRL_MASK BITS(7, 0) /* Long Retry Limit */ 313 314 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 315 /* 316 * only do Early Rx on packets longer than 1536 bytes 317 */ 318 #define RTW_RCR_ONLYERLPKT BIT(31) 319 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 320 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 321 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 322 /* 323 * Check BSSID/ToDS/FromDS: set "Link On" when received BSSID 324 * matches RTW_BSSID and received ToDS/FromDS are appropriate 325 * according to RTW_MSR_NETYPE. 326 */ 327 #define RTW_RCR_CBSSID BIT(23) 328 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 329 /* 330 * when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept 331 * broadcast/multicast packets whose 3rd address matches RTL8180's MAC. 332 */ 333 #define RTW_RCR_ADD3 BIT(21) 334 #define RTW_RCR_AMF BIT(20) /* accept management frames */ 335 #define RTW_RCR_ACF BIT(19) /* accept control frames */ 336 #define RTW_RCR_ADF BIT(18) /* accept data frames */ 337 /* 338 * Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 339 * bytes are received 340 */ 341 #define RTW_RCR_RXFTH_MASK BITS(15, 13) 342 #define RTW_RCR_RXFTH_64 LSHIFT(2, RTW_RCR_RXFTH_MASK) 343 #define RTW_RCR_RXFTH_128 LSHIFT(3, RTW_RCR_RXFTH_MASK) 344 #define RTW_RCR_RXFTH_256 LSHIFT(4, RTW_RCR_RXFTH_MASK) 345 #define RTW_RCR_RXFTH_512 LSHIFT(5, RTW_RCR_RXFTH_MASK) 346 #define RTW_RCR_RXFTH_1024 LSHIFT(6, RTW_RCR_RXFTH_MASK) 347 #define RTW_RCR_RXFTH_WHOLE LSHIFT(7, RTW_RCR_RXFTH_MASK) 348 349 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 350 351 /* 352 * Max DMA Burst Size per Rx DMA Burst 353 */ 354 #define RTW_RCR_MXDMA_MASK BITS(10, 8) 355 #define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 356 #define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 357 #define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 358 #define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 359 #define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 360 #define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 361 #define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 362 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 363 364 /* 365 * EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 366 */ 367 #define RTW_RCR_9356SEL BIT(6) 368 369 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 370 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 371 #define RTW_RCR_AM BIT(2) /* accept multicast frames */ 372 /* 373 * accept physical match frames. XXX means PLCP header ok? 374 */ 375 #define RTW_RCR_APM BIT(1) 376 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 377 378 /* 379 * Additional bits to set in monitor mode. 380 */ 381 #define RTW_RCR_MONITOR ( \ 382 RTW_RCR_AAP | \ 383 RTW_RCR_ACF | \ 384 RTW_RCR_ACRC32 | \ 385 RTW_RCR_AICV | \ 386 0) 387 388 /* 389 * The packet filter bits. 390 */ 391 #define RTW_RCR_PKTFILTER_MASK (\ 392 RTW_RCR_ENCS1|RTW_RCR_ENCS2|\ 393 RTW_RCR_AAP | \ 394 RTW_RCR_AB | \ 395 RTW_RCR_ACF | \ 396 RTW_RCR_ACRC32 | \ 397 RTW_RCR_ADD3 | \ 398 RTW_RCR_ADF | \ 399 RTW_RCR_AICV | \ 400 RTW_RCR_AM | \ 401 RTW_RCR_AMF | \ 402 RTW_RCR_APM | \ 403 RTW_RCR_APWRMGT | \ 404 0) 405 406 /* 407 * Receive power-management frames and mgmt/ctrl/data frames. 408 */ 409 #define RTW_RCR_PKTFILTER_DEFAULT ( \ 410 RTW_RCR_ONLYERLPKT | \ 411 RTW_RCR_ENCS1 | \ 412 RTW_RCR_CBSSID | \ 413 RTW_RCR_ADF | \ 414 RTW_RCR_AMF | \ 415 RTW_RCR_APM | \ 416 RTW_RCR_AM | \ 417 RTW_RCR_AB | \ 418 0) 419 #define RTW_RCR_PROMIC ( \ 420 RTW_RCR_AAP | \ 421 0) 422 423 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 424 /* 425 * Transmit Beacon Descriptor Start Address, 426 * 32b, 256-byte alignment 427 */ 428 #define RTW_TBDA 0x4c 429 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 430 #define RTW_9346CR_EEM_MASK BITS(7, 6) /* Operating Mode */ 431 #define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 432 /* 433 * Load the EEPROM. Reset registers to defaults. 434 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 435 * XXX RTL8180 only? 436 */ 437 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 438 /* 439 * Disable network & bus-master operations and enable 440 * _EECS, _EESK, _EEDI, _EEDO. 441 * XXX RTL8180 only? 442 */ 443 #define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 444 /* Enable RTW_CONFIG[0123] registers. */ 445 #define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 446 /* 447 * EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 448 * XXX RTL8180 only? 449 */ 450 #define RTW_9346CR_EECS BIT(3) 451 #define RTW_9346CR_EESK BIT(2) 452 #define RTW_9346CR_EEDI BIT(1) 453 #define RTW_9346CR_EEDO BIT(0) /* read-only */ 454 455 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 456 /* 457 * implements 40-bit WEP, XXX RTL8180 only? 458 */ 459 #define RTW_CONFIG0_WEP40 BIT(7) 460 /* 461 * implements 104-bit WEP, from EEPROM, read-only XXX RTL8180 only? 462 */ 463 #define RTW_CONFIG0_WEP104 BIT(6) 464 /* 465 * 1: RTW_PSR_LEDGPO[01] control LED[01] pins. 466 * 0: LED behavior defined by RTW_CONFIG1_LEDS10_MASK 467 * XXX RTL8180 only? 468 */ 469 #define RTW_CONFIG0_LEDGPOEN BIT(4) 470 /* 471 * auxiliary power is present, read-only 472 */ 473 #define RTW_CONFIG0_AUXPWR BIT(3) 474 /* 475 * Geographic Location, read-only 476 */ 477 #define RTW_CONFIG0_GL_MASK BITS(1, 0) 478 /* 479 * _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 480 * work. 481 */ 482 #define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK) 483 #define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK) 484 #define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK) 485 #define RTW_CONFIG0_GL_USA LSHIFT(0, RTW_CONFIG0_GL_MASK) 486 /* 487 * RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. 488 */ 489 490 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 491 492 /* 493 * LED configuration. From EEPROM. Read/write. 494 * 495 * Setting LED0 LED1 496 * ------- ---- ---- 497 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 498 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 499 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 500 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 501 */ 502 #define RTW_CONFIG1_LEDS_MASK BITS(7, 6) 503 #define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 504 #define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 505 #define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 506 #define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 507 508 /* 509 * LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 510 * 511 * RTW_CONFIG1_LWACT 512 * 0 1 513 * RTW_CONFIG4_LWPTN 0 active high active low 514 * 1 positive pulse negative pulse 515 */ 516 #define RTW_CONFIG1_LWACT BIT(4) 517 518 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 519 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 520 /* 521 * if set, VPD from offsets 0x40-0x7f in EEPROM are at 522 * registers 0x60-0x67 of PCI Configuration Space ( XXX huh? ) 523 */ 524 #define RTW_CONFIG1_VPD BIT(1) 525 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 526 527 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 528 /* 529 * clocks are locked, read-only: 530 * Tx frequency & symbol clocks are derived from the same OSC 531 */ 532 #define RTW_CONFIG2_LCK BIT(7) 533 #define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 534 /* 535 * Descriptor Polling State: enable test mode. 536 */ 537 #define RTW_CONFIG2_DPS BIT(3) 538 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 539 #define RTW_CONFIG2_PAPETIME_MASK BITS(1, 0) /* TBD, from EEPROM */ 540 541 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 542 /* 543 * undocumented bits which appear to control the power state of the RF 544 * components 545 */ 546 #define RTW_ANAPARM_RFPOW0_MASK BITS(30, 28) 547 #define RTW_ANAPARM_RFPOW_MASK \ 548 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 549 550 /* 551 * 1: disable Tx DAC, 552 * 0: enable 553 */ 554 #define RTW_ANAPARM_TXDACOFF BIT(27) 555 /* 556 * undocumented bits which appear to control the power state of the RF 557 * components 558 */ 559 #define RTW_ANAPARM_RFPOW1_MASK BITS(26, 20) 560 561 /* 562 * Maxim On/Sleep/Off control 563 */ 564 #define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 565 566 /* 567 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 568 */ 569 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 570 571 /* 572 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 573 */ 574 #define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 575 576 /* 577 * RFMD On/Sleep/Off control 578 */ 579 #define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK) 580 581 /* 582 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 583 */ 584 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 585 586 /* 587 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 588 */ 589 #define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 590 591 /* 592 * Philips On/Sleep/Off control 593 */ 594 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 595 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 596 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 597 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK) 598 599 /* 600 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 601 */ 602 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 603 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 604 605 /* 606 * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; 607 */ 608 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 609 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 610 611 #define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 612 613 /* 614 * undocumented card-specific bits from the EEPROM. 615 */ 616 #define RTW_ANAPARM_CARDSP_MASK BITS(19, 0) 617 618 #define RTW_MSR 0x58 /* Media Status Register, 8b */ 619 /* 620 * Network Type and Link Status 621 */ 622 #define RTW_MSR_NETYPE_MASK BITS(3, 2) 623 /* 624 * AP, XXX RTL8181 only? 625 */ 626 #define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 627 /* 628 * infrastructure link ok 629 */ 630 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 631 /* 632 * ad-hoc link ok 633 */ 634 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 635 /* 636 * no link 637 */ 638 #define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 639 640 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 641 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 642 /* 643 * Set RTW_CONFIG3_PARMEN and RTW_9346CR_EEM_CONFIG to 644 * allow RTW_ANAPARM writes. 645 */ 646 #define RTW_CONFIG3_PARMEN BIT(6) 647 /* 648 * Valid when RTW_CONFIG1_PMEN is set. If set, RTL8180 wakes up 649 * OS when Magic Packet is Rx'd. 650 */ 651 #define RTW_CONFIG3_MAGIC BIT(5) 652 /* 653 * Cardbus-related registers and functions are enabled, 654 * read-only. XXX RTL8180 only. 655 */ 656 #define RTW_CONFIG3_CARDBEN BIT(3) 657 /* 658 * CLKRUN enabled, read-only. XXX RTL8180 only. 659 */ 660 #define RTW_CONFIG3_CLKRUNEN BIT(2) 661 /* 662 * Function Registers Enabled, read-only. XXX RTL8180 only. 663 */ 664 #define RTW_CONFIG3_FUNCREGEN BIT(1) 665 /* 666 * Fast back-to-back enabled, read-only. 667 */ 668 #define RTW_CONFIG3_FBTBEN BIT(0) 669 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 670 /* 671 * VCO Power Down 672 * 0: normal operation 673 * (power-on default) 674 * 1: power-down VCO, RF front-end, 675 * and most RTL8180 components. 676 */ 677 #define RTW_CONFIG4_VCOPDN BIT(7) 678 /* 679 * Power Off 680 * 0: normal operation 681 * (power-on default) 682 * 1: power-down RF front-end, 683 * and most RTL8180 components, 684 * but leave VCO on. 685 * 686 * XXX RFMD front-end only? 687 */ 688 #define RTW_CONFIG4_PWROFF BIT(6) 689 /* 690 * Power Management 691 * 0: normal operation 692 * (power-on default) 693 * 1: set Tx packet's PWRMGMT bit. 694 */ 695 #define RTW_CONFIG4_PWRMGT BIT(5) 696 /* 697 * LANWAKE vs. PMEB: Cardbus-only 698 * 0: LWAKE & PMEB asserted 699 * simultaneously 700 * 1: LWAKE asserted only if 701 * both PMEB is asserted and 702 * ISOLATEB is low. 703 * XXX RTL8180 only. 704 */ 705 #define RTW_CONFIG4_LWPME BIT(4) 706 /* 707 * see RTW_CONFIG1_LWACT XXX RTL8180 only. 708 */ 709 #define RTW_CONFIG4_LWPTN BIT(2) 710 /* 711 * Radio Front-End Programming Method 712 */ 713 #define RTW_CONFIG4_RFTYPE_MASK BITS(1, 0) 714 #define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 715 #define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 716 #define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 717 718 #define RTW_TESTR 0x5B /* TEST mode register, 8b */ 719 720 #define RTW_PSR 0x5e /* Page Select Register, 8b */ 721 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 722 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 723 /* 724 * Status/control of LED1 pin if RTW_CONFIG0_LEDGPOEN is set. 725 */ 726 #define RTW_PSR_LEDGPO1 BIT(5) 727 /* 728 * Status/control of LED0 pin if RTW_CONFIG0_LEDGPOEN is set. 729 */ 730 #define RTW_PSR_LEDGPO0 BIT(4) 731 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 732 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 733 734 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 735 #define RTW_SCR_KM_MASK BITS(5, 4) /* Key Mode */ 736 #define RTW_SCR_KM_WEP104 LSHIFT(1, RTW_SCR_KM_MASK) 737 #define RTW_SCR_KM_WEP40 LSHIFT(0, RTW_SCR_KM_MASK) 738 /* 739 * Enable Tx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor 740 * RTW_CONFIG0_WEP104 is set. 741 */ 742 #define RTW_SCR_TXSECON BIT(1) 743 /* 744 * Enable Rx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor 745 * RTW_CONFIG0_WEP104 is set. 746 */ 747 #define RTW_SCR_RXSECON BIT(0) 748 749 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 750 /* 751 * TU between TBTT, written by host. 752 */ 753 #define RTW_BCNITV_BCNITV_MASK BITS(9, 0) 754 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 755 /* 756 * ATIM Window length in TU, written by host. 757 */ 758 #define RTW_ATIMWND_ATIMWND BITS(9, 0) 759 760 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 761 /* 762 * RTL8180 wakes host with RTW_INTR_BCNINT at BINTRITV 763 * microseconds before TBTT 764 */ 765 #define RTW_BINTRITV_BINTRITV BITS(9, 0) 766 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 767 /* 768 * RTL8180 wakes host with RTW_INTR_ATIMINT at ATIMTRITV 769 * microseconds before end of ATIM Window 770 */ 771 #define RTW_ATIMTRITV_ATIMTRITV BITS(9, 0) 772 773 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 774 /* 775 * Rev. C magic from reference driver 776 */ 777 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) 778 /* 779 * microsecond Tx delay between MAC and RF front-end 780 */ 781 #define RTW_PHYDELAY_PHYDELAY BITS(2, 0) 782 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 783 #define RTW_CRCOUNT_MAGIC 0x4c 784 785 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 786 787 #define RTW_BB 0x7c /* Baseband interface, 32b */ 788 /* 789 * used for writing RTL8180's integrated baseband processor 790 */ 791 #define RTW_BB_RD_MASK BITS(23, 16) /* data to read */ 792 #define RTW_BB_WR_MASK BITS(15, 8) /* data to write */ 793 #define RTW_BB_WREN BIT(7) /* write enable */ 794 #define RTW_BB_ADDR_MASK BITS(6, 0) /* address */ 795 796 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 797 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 798 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 799 800 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 801 /* 802 * if !RTW_PHYCFG_HST, host sets. MAC clears after banging bits. 803 */ 804 #define RTW_PHYCFG_MAC_POLL BIT(31) 805 /* 806 * 1: host bangs bits 807 * 0: MAC bangs bits 808 */ 809 #define RTW_PHYCFG_HST BIT(30) 810 #define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29, 28) 811 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 812 #define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 813 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 814 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 815 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27, 24) 816 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23, 0) 817 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27, 24) 818 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11, 8) 819 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7, 0) 820 #define RTW_PHYCFG_HST_EN BIT(2) 821 #define RTW_PHYCFG_HST_CLK BIT(1) 822 #define RTW_PHYCFG_HST_DATA BIT(0) 823 824 #define RTW_MAXIM_HIDATA_MASK BITS(11, 4) 825 #define RTW_MAXIM_LODATA_MASK BITS(3, 0) 826 827 /* 828 * 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 829 */ 830 831 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 832 #define RTW_WAKEUP0H 0x88 /* 32b */ 833 834 #define RTW_WAKEUP1L 0x8c 835 #define RTW_WAKEUP1H 0x90 836 837 #define RTW_WAKEUP2LL 0x94 838 #define RTW_WAKEUP2LH 0x98 839 840 #define RTW_WAKEUP2HL 0x9c 841 #define RTW_WAKEUP2HH 0xa0 842 843 #define RTW_WAKEUP3LL 0xa4 844 #define RTW_WAKEUP3LH 0xa8 845 846 #define RTW_WAKEUP3HL 0xac 847 #define RTW_WAKEUP3HH 0xb0 848 849 #define RTW_WAKEUP4LL 0xb4 850 #define RTW_WAKEUP4LH 0xb8 851 852 #define RTW_WAKEUP4HL 0xbc 853 #define RTW_WAKEUP4HH 0xc0 854 855 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 856 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 857 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 858 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 859 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 860 861 /* 862 * 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 863 */ 864 865 /* 866 * Default Key Registers, each 128b 867 * 868 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 869 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 870 */ 871 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 872 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 873 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 874 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 875 876 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 877 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 878 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 879 /* 880 * 1: start calibration cycle and raise AGCRESET pin. 881 * 0: lower AGCRESET pin 882 */ 883 #define RTW_CONFIG5_CALON BIT(5) 884 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 885 /* 886 * Enable LAN Wake signal, from EEPROM 887 */ 888 #define RTW_CONFIG5_LANWAKE BIT(1) 889 /* 890 * 1: both software & PCI Reset reset PME_Status 891 * 0: only software resets PME_Status 892 * 893 * From EEPROM. 894 */ 895 #define RTW_CONFIG5_PMESTS BIT(0) 896 897 /* 898 * Transmit Priority Polling Register, 8b, write-only. 899 */ 900 #define RTW_TPPOLL 0xd9 901 /* 902 * RTL8180 clears to notify host of a beacon 903 * Tx. Host writes have no effect. 904 */ 905 #define RTW_TPPOLL_BQ BIT(7) 906 /* 907 * Host writes 1 to notify RTL8180 of high-priority Tx packets, RTL8180 clears 908 * to after high-priority Tx is complete. 909 */ 910 #define RTW_TPPOLL_HPQ BIT(6) 911 /* 912 * If RTW_CONFIG2_DPS is set, host writes 1 to notify RTL8180 of 913 * normal-priority Tx packets, RTL8180 clears 914 * after normal-priority Tx is complete. 915 * 916 * If RTW_CONFIG2_DPS is clear, host writes have no effect. RTL8180 clears after 917 * normal-priority Tx is complete. 918 */ 919 #define RTW_TPPOLL_NPQ BIT(5) 920 /* 921 * Host writes 1 to notify RTL8180 of low-priority Tx packets, RTL8180 clears 922 * after low-priority Tx is complete. 923 */ 924 #define RTW_TPPOLL_LPQ BIT(4) 925 /* 926 * Host writes 1 to tell RTL8180 to stop beacon DMA. This bit is invalid 927 * when RTW_CONFIG2_DPS is set. 928 */ 929 #define RTW_TPPOLL_SBQ BIT(3) 930 /* 931 * Host writes 1 to tell RTL8180 to stop high-priority DMA. 932 */ 933 #define RTW_TPPOLL_SHPQ BIT(2) 934 /* 935 * Host writes 1 to tell RTL8180 to stop normal-priority DMA. 936 * This bit is invalid when RTW_CONFIG2_DPS is set. 937 */ 938 #define RTW_TPPOLL_SNPQ BIT(1) 939 /* 940 * Host writes 1 to tell RTL8180 to stop low-priority DMA. 941 */ 942 #define RTW_TPPOLL_SLPQ BIT(0) 943 944 /* Start all queues. */ 945 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \ 946 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 947 948 /* Start queues solaris required. */ 949 #define RTW_TPPOLL_LN (RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 950 951 /* Stop all queues. */ 952 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \ 953 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ) 954 955 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 956 /* 957 * Contention Window: indicates number of contention windows before Tx 958 */ 959 #define RTW_CWR_CW BITS(9, 0) 960 961 /* 962 * Retry Count Register, 16b, read-only 963 */ 964 #define RTW_RETRYCTR 0xde 965 /* 966 * Retry Count: indicates number of retries after Tx 967 */ 968 #define RTW_RETRYCTR_RETRYCT BITS(7, 0) 969 970 /* 971 * Receive descriptor Start Address Register, 972 * 32b, 256-byte alignment. 973 */ 974 #define RTW_RDSAR 0xe4 975 /* 976 * Function Event Register, 32b, Cardbus only. Only valid when 977 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 978 */ 979 #define RTW_FER 0xf0 980 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 981 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 982 /* 983 * Function Event Mask Register, 32b, Cardbus only. Only valid when 984 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 985 */ 986 #define RTW_FEMR 0xf4 987 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 988 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 989 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 990 /* 991 * Function Present State Register, 32b, read-only, Cardbus only. 992 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 993 * are set. 994 */ 995 #define RTW_FPSR 0xf8 996 #define RTW_FPSR_INTR BIT(15) /* TBD */ 997 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 998 /* 999 * Function Force Event Register, 32b, write-only, Cardbus only. 1000 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 1001 * are set. 1002 */ 1003 #define RTW_FFER 0xfc 1004 #define RTW_FFER_INTR BIT(15) /* TBD */ 1005 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 1006 1007 /* 1008 * Serial EEPROM offsets 1009 */ 1010 #define RTW_SR_ID 0x00 /* 16b */ 1011 #define RTW_SR_VID 0x02 /* 16b */ 1012 #define RTW_SR_DID 0x04 /* 16b */ 1013 #define RTW_SR_SVID 0x06 /* 16b */ 1014 #define RTW_SR_SMID 0x08 /* 16b */ 1015 #define RTW_SR_MNGNT 0x0a 1016 #define RTW_SR_MXLAT 0x0b 1017 #define RTW_SR_RFCHIPID 0x0c 1018 #define RTW_SR_CONFIG3 0x0d 1019 #define RTW_SR_MAC 0x0e /* 6 bytes */ 1020 #define RTW_SR_CONFIG0 0x14 1021 #define RTW_SR_CONFIG1 0x15 1022 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 1023 #define RTW_SR_CONFIG2 0x18 1024 #define RTW_SR_CONFIG4 0x19 1025 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 1026 #define RTW_SR_TESTR 0x1e 1027 #define RTW_SR_CONFIG5 0x1f 1028 #define RTW_SR_TXPOWER1 0x20 1029 #define RTW_SR_TXPOWER2 0x21 1030 #define RTW_SR_TXPOWER3 0x22 1031 #define RTW_SR_TXPOWER4 0x23 1032 #define RTW_SR_TXPOWER5 0x24 1033 #define RTW_SR_TXPOWER6 0x25 1034 #define RTW_SR_TXPOWER7 0x26 1035 #define RTW_SR_TXPOWER8 0x27 1036 #define RTW_SR_TXPOWER9 0x28 1037 #define RTW_SR_TXPOWER10 0x29 1038 #define RTW_SR_TXPOWER11 0x2a 1039 #define RTW_SR_TXPOWER12 0x2b 1040 #define RTW_SR_TXPOWER13 0x2c 1041 #define RTW_SR_TXPOWER14 0x2d 1042 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 1043 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 1044 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 1045 #define RTW_SR_CISPOINTER 0x30 /* 16b */ 1046 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 1047 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 1048 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 1049 #define RTW_SR_RFPARM_CS_MASK BITS(2, 3) /* carrier-sense type */ 1050 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 1051 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 1052 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 1053 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes */ 1054 1055 /* 1056 * RTL8180 Transmit/Receive Descriptors 1057 */ 1058 1059 /* 1060 * the first descriptor in each ring must be on a 256-byte boundary 1061 */ 1062 #define RTW_DESC_ALIGNMENT 256 1063 1064 /* 1065 * Tx descriptor 1066 */ 1067 struct rtw_txdesc { 1068 uint32_t td_ctl0; 1069 uint32_t td_ctl1; 1070 uint32_t td_buf; 1071 uint32_t td_len; 1072 uint32_t td_next; 1073 uint32_t td_rsvd[3]; 1074 }; 1075 1076 #define td_stat td_ctl0 1077 1078 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 1079 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 1080 #define RTW_TXCTL0_FS BIT(29) /* first segment */ 1081 #define RTW_TXCTL0_LS BIT(28) /* last segment */ 1082 1083 #define RTW_TXCTL0_RATE_MASK BITS(27, 24) /* Tx rate */ 1084 #define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK) 1085 #define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK) 1086 #define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK) 1087 #define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK) 1088 1089 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 1090 1091 #define RTW_TXCTL0_RTSRATE_MASK BITS(22, 19) /* Tx rate */ 1092 #define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK) 1093 #define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK) 1094 #define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK) 1095 #define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK) 1096 1097 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 1098 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 1099 /* 1100 * add short PLCP preamble and header 1101 */ 1102 #define RTW_TXCTL0_SPLCP BIT(16) 1103 #define RTW_TXCTL0_KEYID_MASK BITS(15, 14) /* default key id */ 1104 #define RTW_TXCTL0_RSVD1_MASK BITS(13, 12) /* reserved */ 1105 /* 1106 * Tx packet size in bytes 1107 */ 1108 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11, 0) 1109 1110 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 1111 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 1112 #define RTW_TXSTAT_FS RTW_TXCTL0_FS 1113 #define RTW_TXSTAT_LS RTW_TXCTL0_LS 1114 #define RTW_TXSTAT_RSVD1_MASK BITS(27, 16) 1115 #define RTW_TXSTAT_TOK BIT(15) 1116 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14, 8) /* RTS retry count */ 1117 #define RTW_TXSTAT_DRC_MASK BITS(7, 0) /* Data retry count */ 1118 1119 /* 1120 * supplements _LENGTH in packets sent 5.5Mb/s or faster 1121 */ 1122 #define RTW_TXCTL1_LENGEXT BIT(31) 1123 #define RTW_TXCTL1_LENGTH_MASK BITS(30, 16) /* PLCP length (microseconds) */ 1124 /* 1125 * RTS Duration (microseconds) 1126 */ 1127 #define RTW_TXCTL1_RTSDUR_MASK BITS(15, 0) 1128 1129 #define RTW_TXLEN_LENGTH_MASK BITS(11, 0) /* Tx buffer length in bytes */ 1130 1131 /* 1132 * Rx descriptor 1133 */ 1134 struct rtw_rxdesc { 1135 uint32_t rd_ctl; 1136 uint32_t rd_rsvd0; 1137 uint32_t rd_buf; 1138 uint32_t rd_rsvd1; 1139 }; 1140 1141 #define rd_stat rd_ctl 1142 #define rd_rssi rd_rsvd0 1143 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 1144 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 1145 1146 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 1147 #define RTW_RXCTL_EOR BIT(30) /* end of ring */ 1148 #define RTW_RXCTL_FS BIT(29) /* first segment */ 1149 #define RTW_RXCTL_LS BIT(28) /* last segment */ 1150 #define RTW_RXCTL_RSVD0_MASK BITS(29, 12) /* reserved */ 1151 #define RTW_RXCTL_LENGTH_MASK BITS(11, 0) /* Rx buffer length */ 1152 1153 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN 1154 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR 1155 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 1156 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 1157 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 1158 /* 1159 * buffer overflow XXX means FIFO exhausted? 1160 */ 1161 #define RTW_RXSTAT_BOVF BIT(26) 1162 /* 1163 * Rx'd with short preamble and PLCP header 1164 */ 1165 #define RTW_RXSTAT_SPLCP BIT(25) 1166 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 1167 #define RTW_RXSTAT_RATE_MASK BITS(23, 20) /* Rx rate */ 1168 #define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 1169 #define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 1170 #define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 1171 #define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 1172 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 1173 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 1174 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 1175 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 1176 /* 1177 * error summary. valid when RTW_RXSTAT_LS set. indicates 1178 * that either RTW_RXSTAT_CRC32 or RTW_RXSTAT_ICV is set. 1179 */ 1180 #define RTW_RXSTAT_RES BIT(15) 1181 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 1182 /* 1183 * XXX CRC16 error, from reference driver 1184 */ 1185 #define RTW_RXSTAT_CRC16 BIT(14) 1186 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 1187 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 1188 /* 1189 * frame length, including CRC32 1190 */ 1191 #define RTW_RXSTAT_LENGTH_MASK BITS(11, 0) 1192 1193 /* 1194 * Convenient status conjunction. 1195 */ 1196 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 1197 /* 1198 * Convenient status disjunctions. 1199 */ 1200 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 1201 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 1202 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 1203 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 1204 RTW_RXSTAT_ICV) 1205 1206 1207 #define RTW_RXRSSI_VLAN BITS(32, 16) /* XXX from reference driver */ 1208 /* 1209 * for Philips RF front-ends 1210 */ 1211 #define RTW_RXRSSI_RSSI BITS(15, 8) /* RF energy at the PHY */ 1212 /* 1213 * for RF front-ends by Intersil, Maxim, RFMD 1214 */ 1215 #define RTW_RXRSSI_IMR_RSSI BITS(15, 9) /* RF energy at the PHY */ 1216 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 1217 #define RTW_RXRSSI_SQ BITS(7, 0) /* Barker code-lock quality */ 1218 1219 #define RTW_READ8(regs, ofs) \ 1220 ddi_get8((regs)->r_handle, \ 1221 (uint8_t *)((regs)->r_base + (ofs))) 1222 1223 #define RTW_READ16(regs, ofs) \ 1224 ddi_get16((regs)->r_handle, \ 1225 (uint16_t *)((uintptr_t)(regs)->r_base + (ofs))) 1226 1227 #define RTW_READ(regs, ofs) \ 1228 ddi_get32((regs)->r_handle, \ 1229 (uint32_t *)((uintptr_t)(regs)->r_base + (ofs))) 1230 1231 #define RTW_WRITE8(regs, ofs, val) \ 1232 ddi_put8((regs)->r_handle, \ 1233 (uint8_t *)((regs)->r_base + (ofs)), val) 1234 1235 #define RTW_WRITE16(regs, ofs, val) \ 1236 ddi_put16((regs)->r_handle, \ 1237 (uint16_t *)((uintptr_t)(regs)->r_base + (ofs)), val) 1238 1239 #define RTW_WRITE(regs, ofs, val) \ 1240 ddi_put32((regs)->r_handle, \ 1241 (uint32_t *)((uintptr_t)(regs)->r_base + (ofs)), val) 1242 1243 #define RTW_ISSET(regs, reg, mask) \ 1244 (RTW_READ((regs), (reg)) & (mask)) 1245 1246 #define RTW_CLR(regs, reg, mask) \ 1247 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 1248 1249 /* 1250 * bus_space(9) lied? 1251 */ 1252 #ifndef BUS_SPACE_BARRIER_SYNC 1253 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1254 #endif 1255 1256 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1257 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1258 #endif 1259 1260 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1261 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1262 #endif 1263 1264 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1265 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1266 #endif 1267 1268 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1269 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1270 #endif 1271 1272 /* 1273 * Bus barrier 1274 * 1275 * Complete outstanding read and/or write ops on [reg0, reg1] 1276 * ([reg1, reg0]) before starting new ops on the same region. See 1277 * acceptable bus_space_barrier(9) for the flag definitions. 1278 */ 1279 #define RTW_BARRIER(regs, reg0, reg1, flags) 1280 /* 1281 * ***just define a dummy macro here in solaris*** 1282 * bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1283 * MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1284 */ 1285 /* 1286 * Barrier convenience macros. 1287 */ 1288 /* 1289 * sync 1290 */ 1291 #define RTW_SYNC(regs, reg0, reg1) \ 1292 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1293 1294 /* 1295 * write-before-write 1296 */ 1297 #define RTW_WBW(regs, reg0, reg1) \ 1298 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1299 1300 /* 1301 * write-before-read 1302 */ 1303 #define RTW_WBR(regs, reg0, reg1) \ 1304 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1305 1306 /* 1307 * read-before-read 1308 */ 1309 #define RTW_RBR(regs, reg0, reg1) \ 1310 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1311 1312 /* 1313 * read-before-read 1314 */ 1315 #define RTW_RBW(regs, reg0, reg1) \ 1316 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1317 1318 #define RTW_WBRW(regs, reg0, reg1) \ 1319 RTW_BARRIER(regs, reg0, reg1, \ 1320 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1321 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1322 1323 /* 1324 * Registers for RTL8180L's built-in baseband modem. 1325 */ 1326 #define RTW_BBP_SYS1 0x00 1327 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1328 /* 1329 * guess: low-noise amplifier activation threshold 1330 */ 1331 #define RTW_BBP_LNADET 0x04 1332 /* 1333 * guess: intermediate frequency (IF) 1334 * auto-gain control (AGC) initial value 1335 */ 1336 #define RTW_BBP_IFAGCINI 0x05 1337 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1338 /* 1339 * guess: activation threshold for IF AGC loop 1340 */ 1341 #define RTW_BBP_IFAGCDET 0x07 1342 1343 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1344 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1345 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1346 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1347 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1348 #define RTW_BBP_ANTATTEN_DFLANTB 0x40 1349 #define RTW_BBP_ANTATTEN_CHAN14 0x0c 1350 1351 /* 1352 * guess: transmit/receive switch latency 1353 */ 1354 #define RTW_BBP_TRL 0x11 1355 #define RTW_BBP_SYS2 0x12 1356 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1357 /* 1358 * loopback rate? 1359 * 0: 1Mbps 1360 * 1: 2Mbps 1361 * 2: 5.5Mbps 1362 * 3: 11Mbps 1363 */ 1364 #define RTW_BBP_SYS2_RATE_MASK BITS(5, 4) 1365 #define RTW_BBP_SYS3 0x13 1366 /* 1367 * carrier-sense threshold 1368 */ 1369 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0, 3) 1370 /* 1371 * guess: channel energy-detect threshold 1372 */ 1373 #define RTW_BBP_CHESTLIM 0x19 1374 /* 1375 * guess: channel signal-quality threshold 1376 */ 1377 #define RTW_BBP_CHSQLIM 0x1a 1378 1379 #define RTW_EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1380 #define RTW_EPROM_CMD_OPERATING_MODE_SHIFT 6 1381 #define RTW_EPROM_CS_SHIFT 3 1382 #define RTW_EPROM_CK_SHIFT 2 1383 #define RTW_EPROM_CMD_CONFIG 0x3 1384 #define RTW_EPROM_CMD_NORMAL 0 1385 #define RTW_EPROM_CMD_LOAD 1 1386 #define RTW_TX_DMA_POLLING_HIPRIORITY_SHIFT 6 1387 #define RTW_TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 1388 #define RTW_TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 1389 #define RTW_CONFIG2_DMA_POLLING_MODE_SHIFT 3 1390 1391 #define RTW_CMD_RST_SHIFT (4) 1392 #define RTW_TX_DMA_STOP_BEACON_SHIFT 3 1393 #ifdef __cplusplus 1394 } 1395 #endif 1396 1397 #endif /* _RTW_REG_H_ */ 1398