1 //===--  riscv.h  - Generic JITLink riscv edge kinds, utilities -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Generic utilities for graphs representing riscv objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_EXECUTIONENGINE_JITLINK_RISCV_H
14 #define LLVM_EXECUTIONENGINE_JITLINK_RISCV_H
15 
16 #include "llvm/ExecutionEngine/JITLink/JITLink.h"
17 
18 namespace llvm {
19 namespace jitlink {
20 namespace riscv {
21 
22 /// Represents riscv fixups. Ordered in the same way as the relocations in
23 /// include/llvm/BinaryFormat/ELFRelocs/RISCV.def.
24 enum EdgeKind_riscv : Edge::Kind {
25 
26   // TODO: Capture and replace to generic fixups
27   /// A plain 32-bit pointer value relocation
28   ///
29   /// Fixup expression:
30   ///   Fixup <= Target + Addend : uint32
31   ///
32   R_RISCV_32 = Edge::FirstRelocation,
33 
34   /// A plain 64-bit pointer value relocation
35   ///
36   /// Fixup expression:
37   ///   Fixup <- Target + Addend : uint32
38   ///
39   R_RISCV_64,
40 
41   /// PC-relative branch pointer value relocation
42   ///
43   /// Fixup expression:
44   ///   Fixup <- (Target - Fixup + Addend)
45   ///
46   R_RISCV_BRANCH,
47 
48   /// High 20 bits of PC-relative jump pointer value relocation
49   ///
50   /// Fixup expression:
51   ///   Fixup <- Target - Fixup + Addend
52   ///
53   R_RISCV_JAL,
54 
55   /// PC relative call
56   ///
57   /// Fixup expression:
58   ///   Fixup <- (Target - Fixup + Addend)
59   R_RISCV_CALL,
60 
61   /// PC relative call by PLT
62   ///
63   /// Fixup expression:
64   ///   Fixup <- (Target - Fixup + Addend)
65   R_RISCV_CALL_PLT,
66 
67   /// PC relative GOT offset
68   ///
69   /// Fixup expression:
70   ///   Fixup <- (GOT - Fixup + Addend) >> 12
71   R_RISCV_GOT_HI20,
72 
73   /// High 20 bits of PC relative relocation
74   ///
75   /// Fixup expression:
76   ///   Fixup <- (Target - Fixup + Addend + 0x800) >> 12
77   R_RISCV_PCREL_HI20,
78 
79   /// Low 12 bits of PC relative relocation, used by I type instruction format
80   ///
81   /// Fixup expression:
82   ///   Fixup <- (Target - Fixup + Addend) & 0xFFF
83   R_RISCV_PCREL_LO12_I,
84 
85   /// Low 12 bits of PC relative relocation, used by S type instruction format
86   ///
87   /// Fixup expression:
88   ///   Fixup <- (Target - Fixup + Addend) & 0xFFF
89   R_RISCV_PCREL_LO12_S,
90 
91   /// High 20 bits of 32-bit pointer value relocation
92   ///
93   /// Fixup expression
94   ///   Fixup <- (Target + Addend + 0x800) >> 12
95   R_RISCV_HI20,
96 
97   /// Low 12 bits of 32-bit pointer value relocation
98   ///
99   /// Fixup expression
100   ///   Fixup <- (Target + Addend) & 0xFFF
101   R_RISCV_LO12_I,
102 
103   /// Low 12 bits of 32-bit pointer value relocation, used by S type instruction
104   /// format
105   ///
106   /// Fixup expression
107   ///   Fixup <- (Target + Addend) & 0xFFF
108   R_RISCV_LO12_S,
109 
110   /// 8 bits label addition
111   ///
112   /// Fixup expression
113   ///   Fixup <- (Target - *{1}Fixup + Addend)
114   R_RISCV_ADD8,
115 
116   /// 16 bits label addition
117   ///
118   /// Fixup expression
119   ///   Fixup <- (Target - *{2}Fixup + Addend)
120   R_RISCV_ADD16,
121 
122   /// 32 bits label addition
123   ///
124   /// Fixup expression:
125   ///   Fixup <- (Target - *{4}Fixup + Addend)
126   R_RISCV_ADD32,
127 
128   /// 64 bits label addition
129   ///
130   /// Fixup expression:
131   ///   Fixup <- (Target - *{8}Fixup + Addend)
132   R_RISCV_ADD64,
133 
134   /// 8 bits label subtraction
135   ///
136   /// Fixup expression
137   ///   Fixup <- (Target - *{1}Fixup - Addend)
138   R_RISCV_SUB8,
139 
140   /// 16 bits label subtraction
141   ///
142   /// Fixup expression
143   ///   Fixup <- (Target - *{2}Fixup - Addend)
144   R_RISCV_SUB16,
145 
146   /// 32 bits label subtraction
147   ///
148   /// Fixup expression
149   ///   Fixup <- (Target - *{4}Fixup - Addend)
150   R_RISCV_SUB32,
151 
152   /// 64 bits label subtraction
153   ///
154   /// Fixup expression
155   ///   Fixup <- (Target - *{8}Fixup - Addend)
156   R_RISCV_SUB64,
157 
158   /// 8-bit PC-relative branch offset
159   ///
160   /// Fixup expression:
161   ///   Fixup <- (Target - Fixup + Addend)
162   R_RISCV_RVC_BRANCH,
163 
164   /// 11-bit PC-relative jump offset
165   ///
166   /// Fixup expression:
167   ///   Fixup <- (Target - Fixup + Addend)
168   R_RISCV_RVC_JUMP,
169 
170   /// 6 bits label subtraction
171   ///
172   /// Fixup expression
173   ///   Fixup <- (Target - *{1}Fixup - Addend)
174   R_RISCV_SUB6,
175 
176   /// Local label assignment
177   ///
178   /// Fixup expression:
179   ///   Fixup <- (Target + Addend)
180   R_RISCV_SET6,
181 
182   /// Local label assignment
183   ///
184   /// Fixup expression:
185   ///   Fixup <- (Target + Addend)
186   R_RISCV_SET8,
187 
188   /// Local label assignment
189   ///
190   /// Fixup expression:
191   ///   Fixup <- (Target + Addend)
192   R_RISCV_SET16,
193 
194   /// Local label assignment
195   ///
196   /// Fixup expression:
197   ///   Fixup <- (Target + Addend)
198   R_RISCV_SET32,
199 
200   /// 32 bits PC relative relocation
201   ///
202   /// Fixup expression:
203   ///   Fixup <- (Target - Fixup + Addend)
204   R_RISCV_32_PCREL,
205 };
206 
207 /// Returns a string name for the given riscv edge. For debugging purposes
208 /// only
209 const char *getEdgeKindName(Edge::Kind K);
210 } // namespace riscv
211 } // namespace jitlink
212 } // namespace llvm
213 
214 #endif
215