| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 169 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
178 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
188 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
220 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
226 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
239 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
245 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
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| H A D | MipsMCCodeEmitter.cpp | 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
501 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
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| H A D | X86InstrInfo.cpp | 5632 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2131 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2266 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2439 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2976 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
3169 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3217 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3239 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3260 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
4937 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
4948 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
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| H A D | Thumb2SizeReduction.cpp | 756 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
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| H A D | ARMAsmPrinter.cpp | 322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 237 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
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| H A D | HexagonBitTracker.cpp | 314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = in emitPrologue() local
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 759 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
772 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
810 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
821 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 747 uint16_t Reg0 = 0; variable
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1188 Register Reg0 = MO0.getReg(); in allocateInstruction() local
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| H A D | TargetInstrInfo.cpp | 184 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
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| H A D | RegisterCoalescer.cpp | 2606 Register Reg0; in valuesIdentical() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1169 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1199 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1473 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect()
|