| /dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/experiments/jit/ |
| H A D | reg.go | 26 RegHi Reg = 0x80000000 // last user-available register = 0x80000000 const
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1039 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1032 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1032 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1508 unsigned RegHi = RegLo + 1; in LowerReturn() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1665 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1654 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1750 case ISD::SUB:
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1665 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1654 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1839 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1665 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1610 unsigned RegHi = RegLo + 1; in LowerReturn() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2422 Register RegHi = RegLo + 1; in LowerReturn() local
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2308 unsigned RegHi = RegLo + 1; in LowerReturn() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 3887 Variable *RegHi, *RegLo; in lowerCast() local
3897 auto *RegHi = legalizeToReg(hiOperand(Var64On32)); in lowerCast() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2525 Register RegHi = RegLo + 1; in LowerReturn() local
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2456 Register RegHi = RegLo + 1; in LowerReturn() local
|