1 /* $OpenBSD: sdmmcvar.h,v 1.34 2020/08/14 14:49:04 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _SDMMCVAR_H_ 20 #define _SDMMCVAR_H_ 21 22 #include <sys/queue.h> 23 #include <sys/rwlock.h> 24 25 #include <machine/bus.h> 26 27 #include <scsi/scsi_all.h> 28 #include <scsi/scsiconf.h> 29 30 #include <dev/sdmmc/sdmmcchip.h> 31 #include <dev/sdmmc/sdmmcreg.h> 32 33 struct sdmmc_csd { 34 int csdver; /* CSD structure format */ 35 int mmcver; /* MMC version (for CID format) */ 36 int capacity; /* total number of sectors */ 37 int sector_size; /* sector size in bytes */ 38 int read_bl_len; /* block length for reads */ 39 int tran_speed; /* transfer speed (kbit/s) */ 40 int ccc; /* Card Command Class for SD */ 41 /* ... */ 42 }; 43 44 struct sdmmc_cid { 45 int mid; /* manufacturer identification number */ 46 int oid; /* OEM/product identification number */ 47 char pnm[8]; /* product name (MMC v1 has the longest) */ 48 int rev; /* product revision */ 49 int psn; /* product serial number */ 50 int mdt; /* manufacturing date */ 51 }; 52 53 struct sdmmc_scr { 54 int sd_spec; 55 int bus_width; 56 }; 57 58 typedef u_int32_t sdmmc_response[4]; 59 60 struct sdmmc_softc; 61 62 struct sdmmc_task { 63 void (*func)(void *arg); 64 void *arg; 65 int onqueue; 66 struct sdmmc_softc *sc; 67 TAILQ_ENTRY(sdmmc_task) next; 68 }; 69 70 #define sdmmc_init_task(xtask, xfunc, xarg) do { \ 71 (xtask)->func = (xfunc); \ 72 (xtask)->arg = (xarg); \ 73 (xtask)->onqueue = 0; \ 74 (xtask)->sc = NULL; \ 75 } while (0) 76 77 #define sdmmc_task_pending(xtask) ((xtask)->onqueue) 78 79 struct sdmmc_command { 80 struct sdmmc_task c_task; /* task queue entry */ 81 u_int16_t c_opcode; /* SD or MMC command index */ 82 u_int32_t c_arg; /* SD/MMC command argument */ 83 sdmmc_response c_resp; /* response buffer */ 84 bus_dmamap_t c_dmamap; 85 void *c_data; /* buffer to send or read into */ 86 int c_datalen; /* length of data buffer */ 87 int c_blklen; /* block length */ 88 int c_flags; /* see below */ 89 #define SCF_ITSDONE 0x0001 /* command is complete */ 90 #define SCF_CMD(flags) ((flags) & 0x00f0) 91 #define SCF_CMD_AC 0x0000 92 #define SCF_CMD_ADTC 0x0010 93 #define SCF_CMD_BC 0x0020 94 #define SCF_CMD_BCR 0x0030 95 #define SCF_CMD_READ 0x0040 /* read command (data expected) */ 96 #define SCF_RSP_BSY 0x0100 97 #define SCF_RSP_136 0x0200 98 #define SCF_RSP_CRC 0x0400 99 #define SCF_RSP_IDX 0x0800 100 #define SCF_RSP_PRESENT 0x1000 101 /* response types */ 102 #define SCF_RSP_R0 0 /* none */ 103 #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 104 #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 105 #define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136) 106 #define SCF_RSP_R3 (SCF_RSP_PRESENT) 107 #define SCF_RSP_R4 (SCF_RSP_PRESENT) 108 #define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 109 #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 110 #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 111 #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 112 int c_error; /* errno value on completion */ 113 114 /* Host controller owned fields for data xfer in progress */ 115 int c_resid; /* remaining I/O */ 116 u_char *c_buf; /* remaining data */ 117 }; 118 119 /* 120 * Decoded PC Card 16 based Card Information Structure (CIS), 121 * per card (function 0) and per function (1 and greater). 122 */ 123 struct sdmmc_cis { 124 u_int16_t manufacturer; 125 #define SDMMC_VENDOR_INVALID 0xffff 126 u_int16_t product; 127 #define SDMMC_PRODUCT_INVALID 0xffff 128 u_int8_t function; 129 #define SDMMC_FUNCTION_INVALID 0xff 130 u_char cis1_major; 131 u_char cis1_minor; 132 char cis1_info_buf[256]; 133 char *cis1_info[4]; 134 }; 135 136 /* 137 * Structure describing either an SD card I/O function or a SD/MMC 138 * memory card from a "stack of cards" that responded to CMD2. For a 139 * combo card with one I/O function and one memory card, there will be 140 * two of these structures allocated. Each card slot has such a list 141 * of sdmmc_function structures. 142 */ 143 struct sdmmc_function { 144 /* common members */ 145 struct sdmmc_softc *sc; /* card slot softc */ 146 u_int16_t rca; /* relative card address */ 147 int flags; 148 #define SFF_ERROR 0x0001 /* function is poo; ignore it */ 149 #define SFF_SDHC 0x0002 /* SD High Capacity card */ 150 void *cookie; /* pass extra info from bus to dev */ 151 SIMPLEQ_ENTRY(sdmmc_function) sf_list; 152 /* SD card I/O function members */ 153 int number; /* I/O function number or -1 */ 154 struct device *child; /* function driver */ 155 struct sdmmc_cis cis; /* decoded CIS */ 156 unsigned int cur_blklen; /* current block length */ 157 /* SD/MMC memory card members */ 158 struct sdmmc_csd csd; /* decoded CSD value */ 159 struct sdmmc_cid cid; /* decoded CID value */ 160 sdmmc_response raw_cid; /* temp. storage for decoding */ 161 struct sdmmc_scr scr; /* decoded SCR value */ 162 }; 163 164 /* 165 * Structure describing a single SD/MMC/SDIO card slot. 166 */ 167 struct sdmmc_softc { 168 struct device sc_dev; /* base device */ 169 #define DEVNAME(sc) ((sc)->sc_dev.dv_xname) 170 sdmmc_chipset_tag_t sct; /* host controller chipset tag */ 171 sdmmc_chipset_handle_t sch; /* host controller chipset handle */ 172 173 bus_dma_tag_t sc_dmat; 174 bus_dmamap_t sc_dmap; 175 #define SDMMC_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 176 177 int sc_flags; 178 #define SMF_SD_MODE 0x0001 /* host in SD mode (MMC otherwise) */ 179 #define SMF_IO_MODE 0x0002 /* host in I/O mode (SD mode only) */ 180 #define SMF_MEM_MODE 0x0004 /* host in memory mode (SD or MMC) */ 181 #define SMF_UHS_MODE 0x0010 /* host in UHS mode */ 182 #define SMF_CARD_PRESENT 0x0020 /* card presence noticed */ 183 #define SMF_CARD_ATTACHED 0x0040 /* card driver(s) attached */ 184 #define SMF_STOP_AFTER_MULTIPLE 0x0080 /* send a stop after a multiple cmd */ 185 #define SMF_CONFIG_PENDING 0x0100 /* config_pending_incr() called */ 186 187 uint32_t sc_caps; /* host capability */ 188 #define SMC_CAPS_AUTO_STOP 0x0001 /* send CMD12 automagically by host */ 189 #define SMC_CAPS_4BIT_MODE 0x0002 /* 4-bits data bus width */ 190 #define SMC_CAPS_DMA 0x0004 /* DMA transfer */ 191 #define SMC_CAPS_SPI_MODE 0x0008 /* SPI mode */ 192 #define SMC_CAPS_POLL_CARD_DET 0x0010 /* Polling card detect */ 193 #define SMC_CAPS_SINGLE_ONLY 0x0020 /* only single read/write */ 194 #define SMC_CAPS_8BIT_MODE 0x0040 /* 8-bits data bus width */ 195 #define SMC_CAPS_MULTI_SEG_DMA 0x0080 /* multiple segment DMA transfer */ 196 #define SMC_CAPS_SD_HIGHSPEED 0x0100 /* SD high-speed timing */ 197 #define SMC_CAPS_MMC_HIGHSPEED 0x0200 /* MMC high-speed timing */ 198 #define SMC_CAPS_UHS_SDR50 0x0400 /* UHS SDR50 timing */ 199 #define SMC_CAPS_UHS_SDR104 0x0800 /* UHS SDR104 timing */ 200 #define SMC_CAPS_UHS_DDR50 0x1000 /* UHS DDR50 timing */ 201 #define SMC_CAPS_UHS_MASK 0x1c00 202 #define SMC_CAPS_MMC_DDR52 0x2000 /* eMMC DDR52 timing */ 203 #define SMC_CAPS_MMC_HS200 0x4000 /* eMMC HS200 timing */ 204 #define SMC_CAPS_MMC_HS400 0x8000 /* eMMC HS400 timing */ 205 #define SMC_CAPS_NONREMOVABLE 0x10000 /* non-removable devices */ 206 207 int sc_function_count; /* number of I/O functions (SDIO) */ 208 struct sdmmc_function *sc_card; /* selected card */ 209 struct sdmmc_function *sc_fn0; /* function 0, the card itself */ 210 SIMPLEQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */ 211 int sc_dying; /* bus driver is shutting down */ 212 struct proc *sc_task_thread; /* asynchronous tasks */ 213 TAILQ_HEAD(, sdmmc_task) sc_tskq; /* task thread work queue */ 214 struct sdmmc_task sc_discover_task; /* card attach/detach task */ 215 struct sdmmc_task sc_intr_task; /* card interrupt task */ 216 struct rwlock sc_lock; /* lock around host controller */ 217 void *sc_scsibus; /* SCSI bus emulation softc */ 218 TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */ 219 long sc_max_seg; /* maximum segment size */ 220 long sc_max_xfer; /* maximum transfer size */ 221 void *sc_cookies[SDMMC_MAX_FUNCTIONS]; /* pass extra info from bus to dev */ 222 }; 223 224 /* 225 * Attach devices at the sdmmc bus. 226 */ 227 struct sdmmc_attach_args { 228 struct scsibus_attach_args saa; 229 struct sdmmc_function *sf; 230 }; 231 232 #define IPL_SDMMC IPL_BIO 233 #define splsdmmc() splbio() 234 235 #define SDMMC_ASSERT_LOCKED(sc) \ 236 rw_assert_wrlock(&(sc)->sc_lock) 237 238 void sdmmc_add_task(struct sdmmc_softc *, struct sdmmc_task *); 239 void sdmmc_del_task(struct sdmmc_task *); 240 241 struct sdmmc_function *sdmmc_function_alloc(struct sdmmc_softc *); 242 void sdmmc_function_free(struct sdmmc_function *); 243 int sdmmc_set_bus_power(struct sdmmc_softc *, u_int32_t, u_int32_t); 244 int sdmmc_mmc_command(struct sdmmc_softc *, struct sdmmc_command *); 245 int sdmmc_app_command(struct sdmmc_softc *, struct sdmmc_command *); 246 void sdmmc_go_idle_state(struct sdmmc_softc *); 247 int sdmmc_select_card(struct sdmmc_softc *, struct sdmmc_function *); 248 int sdmmc_set_relative_addr(struct sdmmc_softc *, 249 struct sdmmc_function *); 250 int sdmmc_send_if_cond(struct sdmmc_softc *, uint32_t); 251 252 void sdmmc_intr_enable(struct sdmmc_function *); 253 void sdmmc_intr_disable(struct sdmmc_function *); 254 void *sdmmc_intr_establish(struct device *, int (*)(void *), 255 void *, const char *); 256 void sdmmc_intr_disestablish(void *); 257 void sdmmc_intr_task(void *); 258 259 int sdmmc_io_enable(struct sdmmc_softc *); 260 void sdmmc_io_scan(struct sdmmc_softc *); 261 int sdmmc_io_init(struct sdmmc_softc *, struct sdmmc_function *); 262 void sdmmc_io_attach(struct sdmmc_softc *); 263 void sdmmc_io_detach(struct sdmmc_softc *); 264 u_int8_t sdmmc_io_read_1(struct sdmmc_function *, int); 265 u_int16_t sdmmc_io_read_2(struct sdmmc_function *, int); 266 u_int32_t sdmmc_io_read_4(struct sdmmc_function *, int); 267 int sdmmc_io_read_multi_1(struct sdmmc_function *, int, u_char *, int); 268 int sdmmc_io_read_region_1(struct sdmmc_function *, int, u_char *, int); 269 void sdmmc_io_write_1(struct sdmmc_function *, int, u_int8_t); 270 void sdmmc_io_write_2(struct sdmmc_function *, int, u_int16_t); 271 void sdmmc_io_write_4(struct sdmmc_function *, int, u_int32_t); 272 int sdmmc_io_write_multi_1(struct sdmmc_function *, int, u_char *, int); 273 int sdmmc_io_write_region_1(struct sdmmc_function *, int, u_char *, int); 274 int sdmmc_io_function_ready(struct sdmmc_function *); 275 int sdmmc_io_function_enable(struct sdmmc_function *); 276 void sdmmc_io_function_disable(struct sdmmc_function *); 277 void sdmmc_io_set_blocklen(struct sdmmc_function *, unsigned int); 278 279 int sdmmc_read_cis(struct sdmmc_function *, struct sdmmc_cis *); 280 void sdmmc_print_cis(struct sdmmc_function *); 281 void sdmmc_check_cis_quirks(struct sdmmc_function *); 282 283 int sdmmc_mem_enable(struct sdmmc_softc *); 284 void sdmmc_mem_scan(struct sdmmc_softc *); 285 int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *); 286 int sdmmc_mem_read_block(struct sdmmc_function *, int, u_char *, size_t); 287 int sdmmc_mem_write_block(struct sdmmc_function *, int, u_char *, size_t); 288 289 #ifdef HIBERNATE 290 int sdmmc_mem_hibernate_write(struct sdmmc_function *, daddr_t, u_char *, 291 size_t); 292 #endif 293 294 /* ioctls */ 295 296 #include <sys/ioccom.h> 297 298 struct bio_sdmmc_command { 299 void *cookie; 300 struct sdmmc_command cmd; 301 }; 302 303 struct bio_sdmmc_debug { 304 void *cookie; 305 int debug; 306 }; 307 308 #define SDIOCEXECMMC _IOWR('S',0, struct bio_sdmmc_command) 309 #define SDIOCEXECAPP _IOWR('S',1, struct bio_sdmmc_command) 310 #define SDIOCSETDEBUG _IOWR('S',2, struct bio_sdmmc_debug) 311 312 #endif 313