1 /* 2 * Copyright 2012 Michael Ossmann <mike@ossmann.com> 3 * Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com> 4 * Copyright 2012 Jared Boone <jared@sharebrained.com> 5 * 6 * This file is part of HackRF. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 51 Franklin Street, 21 * Boston, MA 02110-1301, USA. 22 */ 23 24 #ifndef __HACKRF_CORE_H 25 #define __HACKRF_CORE_H 26 27 #ifdef __cplusplus 28 extern "C" 29 { 30 #endif 31 32 #include <stdint.h> 33 #include <stdbool.h> 34 35 #include "si5351c.h" 36 #include "spi_ssp.h" 37 38 #include "max2837.h" 39 #include "max5864.h" 40 #include "mixer.h" 41 #include "w25q80bv.h" 42 #include "sgpio.h" 43 #include "rf_path.h" 44 #include "cpld_jtag.h" 45 46 /* hardware identification number */ 47 #define BOARD_ID_JAWBREAKER 1 48 #define BOARD_ID_HACKRF_ONE 2 49 #define BOARD_ID_RAD1O 3 50 51 #ifdef JAWBREAKER 52 #define BOARD_ID BOARD_ID_JAWBREAKER 53 #endif 54 55 #ifdef HACKRF_ONE 56 #define BOARD_ID BOARD_ID_HACKRF_ONE 57 #endif 58 59 #ifdef RAD1O 60 #define BOARD_ID BOARD_ID_RAD1O 61 #endif 62 63 /* 64 * SCU PinMux 65 */ 66 67 /* GPIO Output PinMux */ 68 #define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */ 69 #define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */ 70 #define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */ 71 #ifdef RAD1O 72 #define SCU_PINMUX_LED4 (PB_6) /* GPIO5[26] on PB_6 */ 73 #endif 74 75 #define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */ 76 77 /* GPIO Input PinMux */ 78 #define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */ 79 #define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */ 80 #ifndef HACKRF_ONE 81 #define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */ 82 #define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ 83 #endif 84 #define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */ 85 #define SCU_PINMUX_PP_LCD_RDX (P2_4) /* GPIO5[4] on P2_4 */ 86 #define SCU_PINMUX_PP_UNUSED (P2_8) /* GPIO5[7] on P2_8 */ 87 #define SCU_PINMUX_PP_LCD_WRX (P2_9) /* GPIO1[10] on P2_9 */ 88 #define SCU_PINMUX_PP_DIR (P2_13) /* GPIO1[13] on P2_13 */ 89 90 /* USB peripheral */ 91 #ifdef JAWBREAKER 92 #define SCU_PINMUX_USB_LED0 (P6_8) 93 #define SCU_PINMUX_USB_LED1 (P6_7) 94 #endif 95 96 /* SSP1 Peripheral PinMux */ 97 #define SCU_SSP1_CIPO (P1_3) /* P1_3 */ 98 #define SCU_SSP1_COPI (P1_4) /* P1_4 */ 99 #define SCU_SSP1_SCK (P1_19) /* P1_19 */ 100 #define SCU_SSP1_CS (P1_20) /* P1_20 */ 101 102 /* CPLD JTAG interface */ 103 #define SCU_PINMUX_CPLD_TDO (P9_5) /* GPIO5[18] */ 104 #define SCU_PINMUX_CPLD_TCK (P6_1) /* GPIO3[ 0] */ 105 #if (defined HACKRF_ONE || defined RAD1O) 106 #define SCU_PINMUX_CPLD_TMS (P6_5) /* GPIO3[ 4] */ 107 #define SCU_PINMUX_CPLD_TDI (P6_2) /* GPIO3[ 1] */ 108 #else 109 #define SCU_PINMUX_CPLD_TMS (P6_2) /* GPIO3[ 1] */ 110 #define SCU_PINMUX_CPLD_TDI (P6_5) /* GPIO3[ 4] */ 111 #endif 112 113 /* CPLD SGPIO interface */ 114 #define SCU_PINMUX_SGPIO0 (P0_0) 115 #define SCU_PINMUX_SGPIO1 (P0_1) 116 #define SCU_PINMUX_SGPIO2 (P1_15) 117 #define SCU_PINMUX_SGPIO3 (P1_16) 118 #define SCU_PINMUX_SGPIO4 (P6_3) 119 #define SCU_PINMUX_SGPIO5 (P6_6) 120 #define SCU_PINMUX_SGPIO6 (P2_2) 121 #define SCU_PINMUX_SGPIO7 (P1_0) 122 #if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O) 123 #define SCU_PINMUX_SGPIO8 (P9_6) 124 #endif 125 #define SCU_PINMUX_SGPIO9 (P4_3) 126 #define SCU_PINMUX_SGPIO10 (P1_14) 127 #define SCU_PINMUX_SGPIO11 (P1_17) 128 #define SCU_PINMUX_SGPIO12 (P1_18) 129 #define SCU_PINMUX_SGPIO13 (P4_8) 130 #define SCU_PINMUX_SGPIO14 (P4_9) 131 #define SCU_PINMUX_SGPIO15 (P4_10) 132 133 /* MAX2837 GPIO (XCVR_CTL) PinMux */ 134 #ifdef RAD1O 135 #define SCU_XCVR_RXHP (P8_1) /* GPIO[] on P8_1 */ 136 #define SCU_XCVR_B6 (P8_2) /* GPIO[] on P8_2 */ 137 #define SCU_XCVR_B7 (P9_3) /* GPIO[] on P8_3 */ 138 #endif 139 140 #define SCU_XCVR_ENABLE (P4_6) /* GPIO2[6] on P4_6 */ 141 #define SCU_XCVR_RXENABLE (P4_5) /* GPIO2[5] on P4_5 */ 142 #define SCU_XCVR_TXENABLE (P4_4) /* GPIO2[4] on P4_4 */ 143 #define SCU_XCVR_CS (P1_20) /* GPIO0[15] on P1_20 */ 144 145 /* MAX5864 SPI chip select (AD_CS) GPIO PinMux */ 146 #define SCU_AD_CS (P5_7) /* GPIO2[7] on P5_7 */ 147 148 /* RFFC5071 GPIO serial interface PinMux */ 149 #if (defined JAWBREAKER || defined HACKRF_ONE) 150 #define SCU_MIXER_ENX (P5_4) /* GPIO2[13] on P5_4 */ 151 #define SCU_MIXER_SCLK (P2_6) /* GPIO5[6] on P2_6 */ 152 #define SCU_MIXER_SDATA (P6_4) /* GPIO3[3] on P6_4 */ 153 #define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */ 154 #endif 155 #ifdef RAD1O 156 #define SCU_VCO_CE (P5_4) /* GPIO2[13] on P5_4 */ 157 #define SCU_VCO_SCLK (P2_6) /* GPIO5[6] on P2_6 */ 158 #define SCU_VCO_SDATA (P6_4) /* GPIO3[3] on P6_4 */ 159 #define SCU_VCO_LE (P5_5) /* GPIO2[14] on P5_5 */ 160 #define SCU_VCO_MUX (PB_5) /* GPIO5[25] on PB_5 */ 161 #define SCU_MIXER_EN (P6_8) /* GPIO5[16] on P6_8 */ 162 #define SCU_SYNT_RFOUT_EN (P6_9) /* GPIO3[5] on P6_9 */ 163 #endif 164 165 /* RF LDO control */ 166 #ifdef JAWBREAKER 167 #define SCU_RF_LDO_ENABLE (P5_0) /* GPIO2[9] on P5_0 */ 168 #endif 169 170 /* RF supply (VAA) control */ 171 #ifdef HACKRF_ONE 172 #define SCU_NO_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */ 173 #endif 174 #ifdef RAD1O 175 #define SCU_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */ 176 #endif 177 178 179 /* SPI flash */ 180 #define SCU_SSP0_CIPO (P3_6) 181 #define SCU_SSP0_COPI (P3_7) 182 #define SCU_SSP0_SCK (P3_3) 183 #define SCU_SSP0_CS (P3_8) /* GPIO5[11] on P3_8 */ 184 #define SCU_FLASH_HOLD (P3_4) /* GPIO1[14] on P3_4 */ 185 #define SCU_FLASH_WP (P3_5) /* GPIO1[15] on P3_5 */ 186 187 /* RF switch control */ 188 #ifdef HACKRF_ONE 189 #define SCU_HP (P4_0) /* GPIO2[0] on P4_0 */ 190 #define SCU_LP (P5_1) /* GPIO2[10] on P5_1 */ 191 #define SCU_TX_MIX_BP (P5_2) /* GPIO2[11] on P5_2 */ 192 #define SCU_NO_MIX_BYPASS (P1_7) /* GPIO1[0] on P1_7 */ 193 #define SCU_RX_MIX_BP (P5_3) /* GPIO2[12] on P5_3 */ 194 #define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */ 195 #define SCU_TX (P6_7) /* GPIO5[15] on P6_7 */ 196 #define SCU_MIX_BYPASS (P6_8) /* GPIO5[16] on P6_8 */ 197 #define SCU_RX (P2_5) /* GPIO5[5] on P2_5 */ 198 #define SCU_NO_TX_AMP_PWR (P6_9) /* GPIO3[5] on P6_9 */ 199 #define SCU_AMP_BYPASS (P2_10) /* GPIO0[14] on P2_10 */ 200 #define SCU_RX_AMP (P2_11) /* GPIO1[11] on P2_11 */ 201 #define SCU_NO_RX_AMP_PWR (P2_12) /* GPIO1[12] on P2_12 */ 202 #endif 203 #ifdef RAD1O 204 #define SCU_BY_AMP (P1_7) /* GPIO1[0] on P1_7 */ 205 #define SCU_BY_AMP_N (P2_5) /* GPIO5[5] on P2_5 */ 206 #define SCU_TX_RX (P2_10) /* GPIO0[14] on P2_10 */ 207 #define SCU_TX_RX_N (P2_11) /* GPIO1[11] on P2_11 */ 208 #define SCU_BY_MIX (P2_12) /* GPIO1[12] on P2_12 */ 209 #define SCU_BY_MIX_N (P5_1) /* GPIO2[10] on P5_1 */ 210 #define SCU_LOW_HIGH_FILT (P5_2) /* GPIO2[11] on P5_2 */ 211 #define SCU_LOW_HIGH_FILT_N (P5_3) /* GPIO2[12] on P5_3 */ 212 #define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */ 213 #define SCU_RX_LNA (P6_7) /* GPIO5[15] on P6_7 */ 214 #endif 215 216 #define SCU_PINMUX_PP_D0 (P7_0) /* GPIO3[8] */ 217 #define SCU_PINMUX_PP_D1 (P7_1) /* GPIO3[9] */ 218 #define SCU_PINMUX_PP_D2 (P7_2) /* GPIO3[10] */ 219 #define SCU_PINMUX_PP_D3 (P7_3) /* GPIO3[11] */ 220 #define SCU_PINMUX_PP_D4 (P7_4) /* GPIO3[12] */ 221 #define SCU_PINMUX_PP_D5 (P7_5) /* GPIO3[13] */ 222 #define SCU_PINMUX_PP_D6 (P7_6) /* GPIO3[14] */ 223 #define SCU_PINMUX_PP_D7 (P7_7) /* GPIO3[15] */ 224 /* TODO add other Pins */ 225 #define SCU_PINMUX_GPIO3_8 (P7_0) /* GPIO3[8] */ 226 #define SCU_PINMUX_GPIO3_9 (P7_1) /* GPIO3[9] */ 227 #define SCU_PINMUX_GPIO3_10 (P7_2) /* GPIO3[10] */ 228 #define SCU_PINMUX_GPIO3_11 (P7_3) /* GPIO3[11] */ 229 #define SCU_PINMUX_GPIO3_12 (P7_4) /* GPIO3[12] */ 230 #define SCU_PINMUX_GPIO3_13 (P7_5) /* GPIO3[13] */ 231 #define SCU_PINMUX_GPIO3_14 (P7_6) /* GPIO3[14] */ 232 #define SCU_PINMUX_GPIO3_15 (P7_7) /* GPIO3[15] */ 233 234 #define SCU_PINMUX_PP_TDO (P1_5) /* GPIO1[8] */ 235 #define SCU_PINMUX_SD_POW (P1_5) /* GPIO1[8] */ 236 #define SCU_PINMUX_SD_CMD (P1_6) /* GPIO1[9] */ 237 #define SCU_PINMUX_PP_TMS (P1_8) /* GPIO1[1] */ 238 #define SCU_PINMUX_SD_VOLT0 (P1_8) /* GPIO1[1] */ 239 #define SCU_PINMUX_SD_DAT0 (P1_9) /* GPIO1[2] */ 240 #define SCU_PINMUX_SD_DAT1 (P1_10) /* GPIO1[3] */ 241 #define SCU_PINMUX_SD_DAT2 (P1_11) /* GPIO1[4] */ 242 #define SCU_PINMUX_SD_DAT3 (P1_12) /* GPIO1[5] */ 243 #define SCU_PINMUX_SD_CD (P1_13) /* GPIO1[6] */ 244 245 #define SCU_PINMUX_PP_IO_STBX (P2_0) /* GPIO5[0] */ 246 #define SCU_PINMUX_PP_ADDR (P2_1) /* GPIO5[1] */ 247 #define SCU_PINMUX_U0_TXD (P2_0) /* GPIO5[0] */ 248 #define SCU_PINMUX_U0_RXD (P2_1) /* GPIO5[1] */ 249 250 #define SCU_PINMUX_ISP (P2_7) /* GPIO0[7] */ 251 252 #define SCU_PINMUX_GP_CLKIN (P4_7) 253 254 typedef enum { 255 TRANSCEIVER_MODE_OFF = 0, 256 TRANSCEIVER_MODE_RX = 1, 257 TRANSCEIVER_MODE_TX = 2, 258 TRANSCEIVER_MODE_SS = 3, 259 TRANSCEIVER_MODE_CPLD_UPDATE = 4, 260 TRANSCEIVER_MODE_RX_SWEEP = 5, 261 } transceiver_mode_t; 262 263 typedef enum { 264 HW_SYNC_MODE_OFF = 0, 265 HW_SYNC_MODE_ON = 1, 266 } hw_sync_mode_t; 267 268 typedef enum { 269 CLOCK_SOURCE_HACKRF = 0, 270 CLOCK_SOURCE_EXTERNAL = 1, 271 CLOCK_SOURCE_PORTAPACK = 2, 272 } clock_source_t; 273 274 void delay(uint32_t duration); 275 276 /* TODO: Hide these configurations */ 277 extern si5351c_driver_t clock_gen; 278 extern const ssp_config_t ssp_config_w25q80bv; 279 extern const ssp_config_t ssp_config_max2837; 280 extern const ssp_config_t ssp_config_max5864; 281 282 extern max2837_driver_t max2837; 283 extern max5864_driver_t max5864; 284 extern mixer_driver_t mixer; 285 extern w25q80bv_driver_t spi_flash; 286 extern sgpio_config_t sgpio_config; 287 extern rf_path_t rf_path; 288 extern jtag_t jtag_cpld; 289 extern i2c_bus_t i2c0; 290 291 void cpu_clock_init(void); 292 void ssp1_set_mode_max2837(void); 293 void ssp1_set_mode_max5864(void); 294 295 void pin_setup(void); 296 297 void enable_1v8_power(void); 298 void disable_1v8_power(void); 299 300 bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom); 301 bool sample_rate_set(const uint32_t sampling_rate_hz); 302 bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz); 303 304 clock_source_t activate_best_clock_source(void); 305 306 #if (defined HACKRF_ONE || defined RAD1O) 307 void enable_rf_power(void); 308 void disable_rf_power(void); 309 #endif 310 311 typedef enum { 312 LED1 = 0, 313 LED2 = 1, 314 LED3 = 2, 315 LED4 = 3, 316 } led_t; 317 318 void led_on(const led_t led); 319 void led_off(const led_t led); 320 void led_toggle(const led_t led); 321 322 void hw_sync_enable(const hw_sync_mode_t hw_sync_mode); 323 324 void halt_and_flash(const uint32_t duration); 325 326 #ifdef __cplusplus 327 } 328 #endif 329 330 #endif /* __HACKRF_CORE_H */ 331